From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955811401383.9133888799679; Tue, 13 Mar 2018 08:43:31 -0700 (PDT) Received: from localhost ([::1]:40604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm5K-0004UB-Jo for importer@patchew.org; Tue, 13 Mar 2018 11:43:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxP-0005Tz-Ht for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxL-0005pU-DZ for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:19 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxF-0005j0-Vu; Tue, 13 Mar 2018 11:35:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx7-0003EE-O2; Tue, 13 Mar 2018 15:35:01 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:50 +0000 Message-Id: <20180313153458.26822-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/9] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the rpi1 and 2 we want to boot the Linux kernel via some custom setup code that makes sure that the SMC instruction acts as a no-op, because it's used for cache maintenance. The rpi3 boots AArch64 kernels, which don't need SMC for cache maintenance and always expect to be booted non-secure. Don't fill in the aarch32-specific parts of the binfo struct. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/raspi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a37881433c..1ac0737149 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -82,10 +82,19 @@ static void setup_boot(MachineState *machine, int versi= on, size_t ram_size) binfo.board_id =3D raspi_boardid[version]; binfo.ram_size =3D ram_size; binfo.nb_cpus =3D smp_cpus; - binfo.board_setup_addr =3D BOARDSETUP_ADDR; - binfo.write_board_setup =3D write_board_setup; - binfo.secure_board_setup =3D true; - binfo.secure_boot =3D true; + + if (version <=3D 2) { + /* The rpi1 and 2 require some custom setup code to run in Secure + * mode before booting a kernel (to set up the SMC vectors so + * that we get a no-op SMC; this is used by Linux to call the + * firmware for some cache maintenance operations. + * The rpi3 doesn't need this. + */ + binfo.board_setup_addr =3D BOARDSETUP_ADDR; + binfo.write_board_setup =3D write_board_setup; + binfo.secure_board_setup =3D true; + binfo.secure_boot =3D true; + } =20 /* Pi2 and Pi3 requires SMP setup */ if (version >=3D 2) { --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955880900929.2911019037567; Tue, 13 Mar 2018 08:44:40 -0700 (PDT) Received: from localhost ([::1]:40607 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm6S-0005fO-27 for importer@patchew.org; Tue, 13 Mar 2018 11:44:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxb-0005qm-Qe for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxb-00067Z-61 for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxQ-0005j0-B8; Tue, 13 Mar 2018 11:35:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx8-0003ER-ER; Tue, 13 Mar 2018 15:35:02 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:51 +0000 Message-Id: <20180313153458.26822-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/9] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add some assertions that if we're about to boot an AArch64 kernel, the board code has not mistakenly set either secure_boot or secure_board_setup. It doesn't make sense to set secure_boot, because all AArch64 kernels must be booted in non-secure mode. It might in theory make sense to set secure_board_setup, but we don't currently support that, because only the AArch32 bootloader[] code calls this hook; bootloader_aarch64[] does not. Since we don't have a current need for this functionality, just assert that we don't try to use it. If it's needed we'll add it later. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/boot.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 196c7fb242..e21a92f972 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -720,6 +720,13 @@ static void do_cpu_reset(void *opaque) } else { env->pstate =3D PSTATE_MODE_EL1h; } + /* AArch64 kernels never boot in secure mode */ + assert(!info->secure_boot); + /* This hook is only supported for AArch32 currently: + * bootloader_aarch64[] will not call the hook, and + * the code above has already dropped us into EL2 or E= L1. + */ + assert(!info->secure_board_setup); } =20 /* Set to non-secure if not a secure boot */ --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955711185508.5022172296091; Tue, 13 Mar 2018 08:41:51 -0700 (PDT) Received: from localhost ([::1]:40590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm3i-00035o-7H for importer@patchew.org; Tue, 13 Mar 2018 11:41:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47176) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxX-0005lW-Uz for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxS-0005zT-E7 for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxO-0005j0-27; Tue, 13 Mar 2018 11:35:18 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx9-0003Em-46; Tue, 13 Mar 2018 15:35:03 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:52 +0000 Message-Id: <20180313153458.26822-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/9] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e21a92f972..9319b12fcd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } =20 + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to w= ork */ + env->cp15.scr_el3 |=3D SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs !=3D first_cpu || !info->secure_board_setup)) { --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955628280535.6972040790322; Tue, 13 Mar 2018 08:40:28 -0700 (PDT) Received: from localhost ([::1]:40578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm2N-0001qj-Cf for importer@patchew.org; Tue, 13 Mar 2018 11:40:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxV-0005bc-3L for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxS-0005zw-QU for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxM-0005j0-Rx; Tue, 13 Mar 2018 11:35:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx9-0003F5-S1; Tue, 13 Mar 2018 15:35:03 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:53 +0000 Message-Id: <20180313153458.26822-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/9] hw/arm/bcm2386: Fix parent type of bcm2386 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The TypeInfo and state struct for bcm2386 disagree about what the parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, but the BCM2386State struct only defines the parent_obj field as DeviceState. This would have caused problems if anything actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't need any of the additional functionality TYPE_SYS_BUS_DEVICE provides. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- I noticed this when I tried to make the type into one which has its own class struct, because we hit the assert that the child's class struct had better be bigger than the parent's. --- hw/arm/bcm2836.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 40e8b25a46..9266f27c14 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -165,7 +165,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *d= ata) =20 static const TypeInfo bcm2836_type_info =3D { .name =3D TYPE_BCM2836, - .parent =3D TYPE_SYS_BUS_DEVICE, + .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(BCM2836State), .instance_init =3D bcm2836_init, .class_init =3D bcm2836_class_init, --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520956278509936.491632928896; Tue, 13 Mar 2018 08:51:18 -0700 (PDT) Received: from localhost ([::1]:40664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evmCr-0002ml-KV for importer@patchew.org; Tue, 13 Mar 2018 11:51:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxZ-0005oC-PE for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxV-000637-OS for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxL-0005j0-RD; Tue, 13 Mar 2018 11:35:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxA-0003FQ-IQ; Tue, 13 Mar 2018 15:35:04 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:54 +0000 Message-Id: <20180313153458.26822-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/9] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Our BCM2836 type is really a generic one that can be any of the bcm283x family. Rename it accordingly. We change only the names which are visible via the header file to the rest of the QEMU code, leaving private function names in bcm2836.c as they are. This is a preliminary to making bcm283x be an abstract parent class to specific types for the bcm2836 and bcm2837. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/bcm2836.h | 12 ++++++------ hw/arm/bcm2836.c | 17 +++++++++-------- hw/arm/raspi.c | 16 ++++++++-------- 3 files changed, 23 insertions(+), 22 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 4758b4ae54..9a10a76631 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -15,12 +15,12 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" =20 -#define TYPE_BCM2836 "bcm2836" -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) +#define TYPE_BCM283X "bcm283x" +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) =20 -#define BCM2836_NCPUS 4 +#define BCM283X_NCPUS 4 =20 -typedef struct BCM2836State { +typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -28,9 +28,9 @@ typedef struct BCM2836State { char *cpu_type; uint32_t enabled_cpus; =20 - ARMCPU cpus[BCM2836_NCPUS]; + ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; -} BCM2836State; +} BCM283XState; =20 #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 9266f27c14..1d1908654b 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,7 +25,7 @@ =20 static void bcm2836_init(Object *obj) { - BCM2836State *s =3D BCM2836(obj); + BCM283XState *s =3D BCM283X(obj); =20 object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTRO= L); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -44,7 +44,7 @@ static void bcm2836_init(Object *obj) =20 static void bcm2836_realize(DeviceState *dev, Error **errp) { - BCM2836State *s =3D BCM2836(dev); + BCM283XState *s =3D BCM283X(dev); Object *obj; Error *err =3D NULL; int n; @@ -52,7 +52,7 @@ static void bcm2836_realize(DeviceState *dev, Error **err= p) /* common peripherals from bcm2835 */ =20 obj =3D OBJECT(dev); - for (n =3D 0; n < BCM2836_NCPUS; n++) { + for (n =3D 0; n < BCM283X_NCPUS; n++) { object_initialize(&s->cpus[n], sizeof(s->cpus[n]), s->cpu_type); object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), @@ -102,7 +102,7 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); =20 - for (n =3D 0; n < BCM2836_NCPUS; n++) { + for (n =3D 0; n < BCM283X_NCPUS; n++) { /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ @@ -150,8 +150,9 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) } =20 static Property bcm2836_props[] =3D { - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836= _NCPUS), + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, + BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() }; =20 @@ -164,9 +165,9 @@ static void bcm2836_class_init(ObjectClass *oc, void *d= ata) } =20 static const TypeInfo bcm2836_type_info =3D { - .name =3D TYPE_BCM2836, + .name =3D TYPE_BCM283X, .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(BCM2836State), + .instance_size =3D sizeof(BCM283XState), .instance_init =3D bcm2836_init, .class_init =3D bcm2836_class_init, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 1ac0737149..58c6e80a17 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -32,7 +32,7 @@ static const int raspi_boardid[] =3D {[1] =3D 0xc42, [2] =3D 0xc43, [3] = =3D 0xc44}; =20 typedef struct RasPiState { - BCM2836State soc; + BCM283XState soc; MemoryRegion ram; } RasPiState; =20 @@ -136,7 +136,7 @@ static void raspi_init(MachineState *machine, int versi= on) BusState *bus; DeviceState *carddev; =20 - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); =20 @@ -189,9 +189,9 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); - mc->max_cpus =3D BCM2836_NCPUS; - mc->min_cpus =3D BCM2836_NCPUS; - mc->default_cpus =3D BCM2836_NCPUS; + mc->max_cpus =3D BCM283X_NCPUS; + mc->min_cpus =3D BCM283X_NCPUS; + mc->default_cpus =3D BCM283X_NCPUS; mc->default_ram_size =3D 1024 * 1024 * 1024; mc->ignore_memory_transaction_failures =3D true; }; @@ -212,9 +212,9 @@ static void raspi3_machine_init(MachineClass *mc) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); - mc->max_cpus =3D BCM2836_NCPUS; - mc->min_cpus =3D BCM2836_NCPUS; - mc->default_cpus =3D BCM2836_NCPUS; + mc->max_cpus =3D BCM283X_NCPUS; + mc->min_cpus =3D BCM283X_NCPUS; + mc->default_cpus =3D BCM283X_NCPUS; mc->default_ram_size =3D 1024 * 1024 * 1024; } DEFINE_MACHINE("raspi3", raspi3_machine_init) --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15209561193328.660023023788312; Tue, 13 Mar 2018 08:48:39 -0700 (PDT) Received: from localhost ([::1]:40635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evmAE-0000ei-3w for importer@patchew.org; Tue, 13 Mar 2018 11:48:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47158) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxW-0005i6-KT for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxS-0005ze-Gm for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxK-0005j0-DS; Tue, 13 Mar 2018 11:35:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxB-0003Fi-98; Tue, 13 Mar 2018 15:35:05 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:55 +0000 Message-Id: <20180313153458.26822-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 6/9] hw/arm/bcm2836: Create proper bcm2837 device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The bcm2837 is pretty similar to the bcm2836, but it does have some differences. Notably, the MPIDR affinity aff1 values it sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 uses, and if this is wrong Linux will not boot. Rather than trying to have one device with properties that configure it differently for the two cases, create two separate QOM devices for the two SoCs. We use the same approach as hw/arm/aspeed_soc.c and share code and have a data table that might differ per-SoC. For the moment the two types don't actually have different behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- hw/arm/raspi.c | 3 ++- 3 files changed, 53 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 9a10a76631..93248399ba 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -20,6 +20,13 @@ =20 #define BCM283X_NCPUS 4 =20 +/* These type names are for specific SoCs; other than instantiating + * them, code using these devices should always handle them via the + * BCM283x base class, so they have no BCM2836(obj) etc macros. + */ +#define TYPE_BCM2836 "bcm2836" +#define TYPE_BCM2837 "bcm2837" + typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; @@ -33,4 +40,16 @@ typedef struct BCM283XState { BCM2835PeripheralState peripherals; } BCM283XState; =20 +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + DeviceClass parent_class; + const BCM283XInfo *info; +} BCM283XClass; + +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1d1908654b..07d2705f96 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -23,6 +23,19 @@ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ #define BCM2836_CONTROL_BASE 0x40000000 =20 +struct BCM283XInfo { + const char *name; +}; + +static const BCM283XInfo bcm283x_socs[] =3D { + { + .name =3D TYPE_BCM2836, + }, + { + .name =3D TYPE_BCM2837, + }, +}; + static void bcm2836_init(Object *obj) { BCM283XState *s =3D BCM283X(obj); @@ -156,25 +169,39 @@ static Property bcm2836_props[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -static void bcm2836_class_init(ObjectClass *oc, void *data) +static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); + BCM283XClass *bc =3D BCM283X_CLASS(oc); =20 - dc->props =3D bcm2836_props; + bc->info =3D data; dc->realize =3D bcm2836_realize; + dc->props =3D bcm2836_props; } =20 -static const TypeInfo bcm2836_type_info =3D { +static const TypeInfo bcm283x_type_info =3D { .name =3D TYPE_BCM283X, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(BCM283XState), .instance_init =3D bcm2836_init, - .class_init =3D bcm2836_class_init, + .class_size =3D sizeof(BCM283XClass), + .abstract =3D true, }; =20 static void bcm2836_register_types(void) { - type_register_static(&bcm2836_type_info); + int i; + + type_register_static(&bcm283x_type_info); + for (i =3D 0; i < ARRAY_SIZE(bcm283x_socs); i++) { + TypeInfo ti =3D { + .name =3D bcm283x_socs[i].name, + .parent =3D TYPE_BCM283X, + .class_init =3D bcm283x_class_init, + .class_data =3D (void *) &bcm283x_socs[i], + }; + type_register(&ti); + } } =20 type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 58c6e80a17..f588720138 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -136,7 +136,8 @@ static void raspi_init(MachineState *machine, int versi= on) BusState *bus; DeviceState *carddev; =20 - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); + object_initialize(&s->soc, sizeof(s->soc), + version =3D=3D 3 ? TYPE_BCM2837 : TYPE_BCM2836); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); =20 --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955802378306.0089725197737; Tue, 13 Mar 2018 08:43:22 -0700 (PDT) Received: from localhost ([::1]:40602 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm56-0004HM-Vj for importer@patchew.org; Tue, 13 Mar 2018 11:43:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxV-0005ba-2k for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxQ-0005vH-VA for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxJ-0005j0-Ch; Tue, 13 Mar 2018 11:35:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxC-0003G0-0N; Tue, 13 Mar 2018 15:35:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:56 +0000 Message-Id: <20180313153458.26822-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 7/9] hw/arm/bcm2836: Use correct affinity values for BCM2837 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The BCM2837 sets the Aff1 field of the MPIDR affinity values for the CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it is required for Linux to boot. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2836.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 07d2705f96..7140257c98 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,14 +25,17 @@ =20 struct BCM283XInfo { const char *name; + int clusterid; }; =20 static const BCM283XInfo bcm283x_socs[] =3D { { .name =3D TYPE_BCM2836, + .clusterid =3D 0xf, }, { .name =3D TYPE_BCM2837, + .clusterid =3D 0x0, }, }; =20 @@ -58,6 +61,8 @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s =3D BCM283X(dev); + BCM283XClass *bc =3D BCM283X_GET_CLASS(dev); + const BCM283XInfo *info =3D bc->info; Object *obj; Error *err =3D NULL; int n; @@ -119,7 +124,7 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ - s->cpus[n].mp_affinity =3D 0xF00 | n; + s->cpus[n].mp_affinity =3D (info->clusterid << 8) | n; =20 /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955962430872.8772311020358; Tue, 13 Mar 2018 08:46:02 -0700 (PDT) Received: from localhost ([::1]:40620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm7l-0006vz-Au for importer@patchew.org; Tue, 13 Mar 2018 11:46:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxR-0005WF-QG for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxQ-0005t7-CW for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxI-0005j0-6K; Tue, 13 Mar 2018 11:35:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxC-0003GI-Ne; Tue, 13 Mar 2018 15:35:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:57 +0000 Message-Id: <20180313153458.26822-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 8/9] hw/arm/bcm2836: Hardcode correct CPU type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now we have separate types for BCM2386 and BCM2387, we might as well just hard-code the CPU type they use rather than having it passed through as an object property. This then lets us put the initialization of the CPU object in init rather than realize. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2836.c | 22 +++++++++++++--------- hw/arm/raspi.c | 2 -- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 7140257c98..12f75b55a7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,16 +25,19 @@ =20 struct BCM283XInfo { const char *name; + const char *cpu_type; int clusterid; }; =20 static const BCM283XInfo bcm283x_socs[] =3D { { .name =3D TYPE_BCM2836, + .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"), .clusterid =3D 0xf, }, { .name =3D TYPE_BCM2837, + .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"), .clusterid =3D 0x0, }, }; @@ -42,6 +45,16 @@ static const BCM283XInfo bcm283x_socs[] =3D { static void bcm2836_init(Object *obj) { BCM283XState *s =3D BCM283X(obj); + BCM283XClass *bc =3D BCM283X_GET_CLASS(obj); + const BCM283XInfo *info =3D bc->info; + int n; + + for (n =3D 0; n < BCM283X_NCPUS; n++) { + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), + info->cpu_type); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), + &error_abort); + } =20 object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTRO= L); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -69,14 +82,6 @@ static void bcm2836_realize(DeviceState *dev, Error **er= rp) =20 /* common peripherals from bcm2835 */ =20 - obj =3D OBJECT(dev); - for (n =3D 0; n < BCM283X_NCPUS; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - s->cpu_type); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - obj =3D object_property_get_link(OBJECT(dev), "ram", &err); if (obj =3D=3D NULL) { error_setg(errp, "%s: required ram link not found: %s", @@ -168,7 +173,6 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) } =20 static Property bcm2836_props[] =3D { - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index f588720138..ae15997669 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -150,8 +150,6 @@ static void raspi_init(MachineState *machine, int versi= on) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", &error_abort); int board_rev =3D version =3D=3D 3 ? 0xa02082 : 0xa21041; --=20 2.16.2 From nobody Tue Apr 23 09:48:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520955537754344.0326343892325; Tue, 13 Mar 2018 08:38:57 -0700 (PDT) Received: from localhost ([::1]:40566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evm0v-0000OL-0r for importer@patchew.org; Tue, 13 Mar 2018 11:38:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evlxV-0005fK-O6 for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evlxP-0005sb-Rw for qemu-devel@nongnu.org; Tue, 13 Mar 2018 11:35:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evlxH-0005j0-8X; Tue, 13 Mar 2018 11:35:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxD-0003Gh-Gd; Tue, 13 Mar 2018 15:35:07 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 13 Mar 2018 15:34:58 +0000 Message-Id: <20180313153458.26822-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 9/9] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Andrew Baumann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index ae15997669..06f1e08ca9 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -27,6 +27,7 @@ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ =20 /* Table of Linux board IDs for different Pi versions */ static const int raspi_boardid[] =3D {[1] =3D 0xc42, [2] =3D 0xc43, [3] = =3D 0xc44}; @@ -63,6 +64,40 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_= boot_info *info) info->smp_loader_start); } =20 +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* Unlike the AArch32 version we don't need to call the board setup ho= ok. + * The mechanism for doing the spin-table is also entirely different. + * We must have four 64-bit fields at absolute addresses + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for + * our CPUs, and which we must ensure are zero initialized before + * the primary CPU goes into the kernel. We put these variables inside + * a rom blob, so that the reset for ROM contents zeroes them for us. + */ + static const uint32_t smpboot[] =3D { + 0xd2801b05, /* mov x5, 0xd8 */ + 0xd53800a6, /* mrs x6, mpidr_el1 */ + 0x924004c6, /* and x6, x6, #0x3 */ + 0xd503205f, /* spin: wfe */ + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ + 0xb4ffffc4, /* cbz x4, spin */ + 0xd2800000, /* mov x0, #0x0 */ + 0xd2800001, /* mov x1, #0x0 */ + 0xd2800002, /* mov x2, #0x0 */ + 0xd2800003, /* mov x3, #0x0 */ + 0xd61f0080, /* br x4 */ + }; + + static const uint64_t spintables[] =3D { + 0, 0, 0, 0 + }; + + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR); +} + static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *inf= o) { arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); @@ -99,7 +134,11 @@ static void setup_boot(MachineState *machine, int versi= on, size_t ram_size) /* Pi2 and Pi3 requires SMP setup */ if (version >=3D 2) { binfo.smp_loader_start =3D SMPBOOT_ADDR; - binfo.write_secondary_boot =3D write_smpboot; + if (version =3D=3D 2) { + binfo.write_secondary_boot =3D write_smpboot; + } else { + binfo.write_secondary_boot =3D write_smpboot64; + } binfo.secondary_cpu_reset_hook =3D reset_secondary; } =20 --=20 2.16.2