From nobody Fri May 17 22:57:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151950382135380.6790792699444; Sat, 24 Feb 2018 12:23:41 -0800 (PST) Received: from localhost ([::1]:51337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgM8-00050B-GN for importer@patchew.org; Sat, 24 Feb 2018 15:23:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgHC-00025H-Ik for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epgH9-00084a-8I for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:34 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:51095) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epgH8-00083s-Kn for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:31 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LiGlL-1eL4jV0krb-00nNv0; Sat, 24 Feb 2018 21:18:06 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 24 Feb 2018 21:17:59 +0100 Message-Id: <20180224201802.911-2-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180224201802.911-1-laurent@vivier.eu> References: <20180224201802.911-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K0:79ZAVVs4X/u0/yVjDSxePdwj6US85yL2y/nyUGBlZcrV3xSv4rT DY8g6zpgZHXsx7wRn9YNQzdU/0PgOHMzYEZuqNqCTRmWSTc0v35eyCnRow6zlXUWHghtKBF 4eKj5agOtjxk5Envhufttowa+MRbBZkYbUgYZYKaL9EMjTud9sWsGFppQui9TCg4X/1hAie Jzen0HYtuAsH/Un4IojOA== X-UI-Out-Filterresults: notjunk:1;V01:K0:RgB5fTAh7NE=:zOX73sEVtSYbkVDx7eXo4m YwsHLeR4S+c4YRKjWf0fOc7oAPoIBJITXT5XQK9qKvJH7nS7a5SOmzz0REe9x467NLBxq56PE ekzo49OFpPAngckoE+iF2hjM8Qa6sIz+6+GzVcT+/KWxZ4MDdxoIpCouMSGZx9+NvIMTQeDvj ddFZIv/KehEbvstACceTcMtAbO4DJ6lzcQC773GHiij8tfDZKW9P4pkbhALWSnyahx6h0W7+k LLrH6CJ8gHXivVjtFZBFjKBZzhGl6nDSPNpsJrF12t+CFhPxMeY1kzvjmXGXPIuCKsMHkuOmC VXPXtPdIvG7I3WeIUj062JDeXGcx+fbu/PR1Hb3hyOtTdBLK9m9j1PZ45uMcodzq/ZDI/NLd/ HqfKPZL3NfaXfPyvubKKhs+m/44vVzEBwt/i6zks2+te7nI8xesvQf+nQ+SbWaPfDa2w8njGU vCWjo3iyX0sdOE/PUGyqra+T/9ie+UunB8U5ugwVL4n7CROg+t+fwTx5XBxsUdi0hCMp/jyOH hIHOYdB0O0mOCznTtLruz9f8LShtiXulK1IWM8bF/YmtX9gIJ5cVHWjGGPC6OT41CljroS/b+ wiscK6hExit8s6Y0o4rUrOtHtyzniPPEG3yL3x+PnhS/V86Y//n2s0ZevZDeNegqRdXEHUcTO pLAHwgJ9EkkgybPrmJHlN03z+LPv9dn/l/7x9svD6yAhbkplTaTcHBh8ODOo/llltXhna41hT SLsg/RWUOo67cD5IHcffTmVV0jErvzc4hgVg6vpke1T6+mpXiAGj07O7I3E= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v4 1/4] softfloat: export some functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Laurent Vivier , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Move fpu/softfloat-macros.h to include/fpu/ Export floatx80 functions to be used by target floatx80 specific implementations. Exports: propagateFloatx80NaN(), extractFloatx80Frac(), extractFloatx80Exp(), extractFloatx80Sign(), normalizeFloatx80Subnormal(), packFloatx80(), roundAndPackFloatx80(), normalizeRoundAndPackFloatx80() Also exports packFloat32() that will be used to implement m68k fsinh, fcos, fsin, ftan operations. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- CC: Aurelien Jarno CC: Alex Benn=C3=A9e CC: Peter Maydell fpu/softfloat-specialize.h | 3 +- fpu/softfloat.c | 91 +++--------------------- {fpu =3D> include/fpu}/softfloat-macros.h | 10 +-- include/fpu/softfloat.h | 120 ++++++++++++++++++++++++++++= ++++ 4 files changed, 136 insertions(+), 88 deletions(-) rename {fpu =3D> include/fpu}/softfloat-macros.h (98%) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index e81ca001e1..46126e9e0a 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -1011,8 +1011,7 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, flo= at_status *status) | `b' is a signaling NaN, the invalid exception is raised. *-------------------------------------------------------------------------= ---*/ =20 -static floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, - float_status *status) +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e7fb0d357a..fb4853682e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -93,7 +93,7 @@ this code that are retained. | division and square root approximations. (Can be specialized to target = if | desired.) *-------------------------------------------------------------------------= ---*/ -#include "softfloat-macros.h" +#include "fpu/softfloat-macros.h" =20 /*------------------------------------------------------------------------= ---- | Functions and definitions to determine: (1) whether tininess for underf= low @@ -2192,25 +2192,6 @@ static void =20 } =20 -/*------------------------------------------------------------------------= ---- -| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a -| single-precision floating-point value, returning the result. After being -| shifted into the proper positions, the three fields are simply added -| together to form the result. This means that any integer portion of `zS= ig' -| will be added into the exponent. Since a properly normalized significand -| will have an integer portion equal to 1, the `zExp' input should be 1 le= ss -| than the desired result exponent whenever `zSig' is a complete, normaliz= ed -| significand. -*-------------------------------------------------------------------------= ---*/ - -static inline float32 packFloat32(flag zSign, int zExp, uint32_t zSig) -{ - - return make_float32( - ( ( (uint32_t) zSign )<<31 ) + ( ( (uint32_t) zExp )<<23 ) + zSi= g); - -} - /*------------------------------------------------------------------------= ---- | Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', | and significand `zSig', and returns the proper single-precision floating- @@ -2490,42 +2471,6 @@ static float64 =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the fraction bits of the extended double-precision floating-point -| value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline uint64_t extractFloatx80Frac( floatx80 a ) -{ - - return a.low; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the exponent bits of the extended double-precision floating-point -| value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline int32_t extractFloatx80Exp( floatx80 a ) -{ - - return a.high & 0x7FFF; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the extended double-precision floating-point val= ue -| `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline flag extractFloatx80Sign( floatx80 a ) -{ - - return a.high>>15; - -} - /*------------------------------------------------------------------------= ---- | Normalizes the subnormal extended double-precision floating-point value | represented by the denormalized significand `aSig'. The normalized expo= nent @@ -2533,30 +2478,14 @@ static inline flag extractFloatx80Sign( floatx80 a ) | `zSigPtr', respectively. *-------------------------------------------------------------------------= ---*/ =20 -static void - normalizeFloatx80Subnormal( uint64_t aSig, int32_t *zExpPtr, uint64_t *zS= igPtr ) +void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, + uint64_t *zSigPtr) { int8_t shiftCount; =20 shiftCount =3D countLeadingZeros64( aSig ); *zSigPtr =3D aSig<> 15; +} + +/*------------------------------------------------------------------------= ---- +| Packs the sign `zSign', exponent `zExp', and significand `zSig' into an +| extended double-precision floating-point value, returning the result. +*-------------------------------------------------------------------------= ---*/ + +static inline floatx80 packFloatx80(flag zSign, int32_t zExp, uint64_t zSi= g) +{ + floatx80 z; + + z.low =3D zSig; + z.high =3D (((uint16_t)zSign) << 15) + zExp; + return z; +} + +/*------------------------------------------------------------------------= ---- +| Normalizes the subnormal extended double-precision floating-point value +| represented by the denormalized significand `aSig'. The normalized expo= nent +| and significand are stored at the locations pointed to by `zExpPtr' and +| `zSigPtr', respectively. +*-------------------------------------------------------------------------= ---*/ + +void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, + uint64_t *zSigPtr); + +/*------------------------------------------------------------------------= ---- +| Takes two extended double-precision floating-point values `a' and `b', o= ne +| of which is a NaN, and returns the appropriate NaN result. If either `a= ' or +| `b' is a signaling NaN, the invalid exception is raised. +*-------------------------------------------------------------------------= ---*/ + +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status= ); + +/*------------------------------------------------------------------------= ---- +| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', +| and extended significand formed by the concatenation of `zSig0' and `zSi= g1', +| and returns the proper extended double-precision floating-point value +| corresponding to the abstract input. Ordinarily, the abstract value is +| rounded and packed into the extended double-precision format, with the +| inexact exception raised if the abstract input cannot be represented +| exactly. However, if the abstract value is too large, the overflow and +| inexact exceptions are raised and an infinity or maximal finite value is +| returned. If the abstract value is too small, the input value is rounde= d to +| a subnormal number, and the underflow and inexact exceptions are raised = if +| the abstract input cannot be represented exactly as a subnormal extended +| double-precision floating-point number. +| If `roundingPrecision' is 32 or 64, the result is rounded to the same +| number of bits as single or double precision, respectively. Otherwise, = the +| result is rounded to the full precision of the extended double-precision +| format. +| The input significand must be normalized or smaller. If the input +| significand is not normalized, `zExp' must be 0; in that case, the result +| returned is a subnormal number, and it must not require rounding. The +| handling of underflow and overflow follows the IEC/IEEE Standard for Bin= ary +| Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +floatx80 roundAndPackFloatx80(int8_t roundingPrecision, flag zSign, + int32_t zExp, uint64_t zSig0, uint64_t zSig1, + float_status *status); + +/*------------------------------------------------------------------------= ---- +| Takes an abstract floating-point value having sign `zSign', exponent +| `zExp', and significand formed by the concatenation of `zSig0' and `zSig= 1', +| and returns the proper extended double-precision floating-point value +| corresponding to the abstract input. This routine is just like +| `roundAndPackFloatx80' except that the input significand does not have t= o be +| normalized. +*-------------------------------------------------------------------------= ---*/ + +floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision, + flag zSign, int32_t zExp, + uint64_t zSig0, uint64_t zSig1, + float_status *status); + /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. *-------------------------------------------------------------------------= ---*/ --=20 2.14.3 From nobody Fri May 17 22:57:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519503599655134.6213131540287; Sat, 24 Feb 2018 12:19:59 -0800 (PST) Received: from localhost ([::1]:51319 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgIU-0002iA-28 for importer@patchew.org; Sat, 24 Feb 2018 15:19:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgH0-0001xq-LB for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epgGx-0007r1-DG for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:22 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:45789) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epgGx-0007pj-3a for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:19 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LqpKo-1eCW1k44qA-00eLUh; Sat, 24 Feb 2018 21:18:07 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 24 Feb 2018 21:18:00 +0100 Message-Id: <20180224201802.911-3-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180224201802.911-1-laurent@vivier.eu> References: <20180224201802.911-1-laurent@vivier.eu> X-Provags-ID: V03:K0:jgx4lquWw+vau2HUDw1couImDOMWPqebziyANsNz6AA0az4sYuj z6Rr/rrGg4llacTJE+nHAyqEakrw2jM0Y5ynaIUG59EZz91GBJzNPw5HxnCp3qP4oRVXxt3 7vj0YQ6yGilRPNsk9NUMZDNsYT8jutInU7ORcNXXgB5GVyODbmm9kOdaDeggsX77Tyx/53n lqc9UxUZEAs82N2VHVO+A== X-UI-Out-Filterresults: notjunk:1;V01:K0:XvcX+rI6N8Q=:6psHEPMttrm/p5gXfunJs/ ju/UTqkDvOxfR81LkjZYUK6Xs4TrFUjlG5R0U4FWlBTNeLGo9FG0o3r+5HOLHccl+evBF13+G sg/QIiujTc1u1mYq0ERdzZGWUfbJxsK73TGllknk5qpNiiHpfl2/ZAOSpX1pOF8KPrZkaAQ0a Ph2eCWr16bYJdWznG/1fRY5fXIkCdtPOJuaktrG0X6gwrZ1YUozMCKnZcN9HbmMU4FwkEy5OO cRyKKMsTShuAi42pu2vBDyboQ943940gSSgs1riZ1kPdnh6E2Re9CVVQSHJM9fBTM07lLbFIm zil+boRtuKneh/4FArtqX3z4LNEu0Vn7E9vbJvKCsUCrUWpFw6vUI2fYJi2kQ0ltheTKLlJaS cvtK5Qls/yafhmjG7REye5QzYzYym+jiGVf+9WR2E9SoZ3L0KWFCksG0Bl3xUlwMr4x0DDE9v B6S/20/5aKjp9yMOqOKwi9dMrv7Gvd3vleMB8v9udGlrhxI1M1qkmmA5sRVjY1o8bRZoPlNGh DLPS3kO78RB9dmSLOgHArtZNUroiNBvxwz3GOZ4o543QwXzrpDLFu2s/7bD52zcRP3qSkZSOy RNH00ZhcDW/RoIqEHhzSDF8bWApx2Gww/w/RdEa9WhmcEwMnf3peZNh80VD9zKu3G/d99SeCI i6Coe7I7JWGgNOAJXqBHzmEMS+YzW/g5aHMnuzUN5QR/KzB4MgJOKdADCGDRSqDQLGdqaxUiH yK8+R1/67XluEEkI/3V7dT6ZztwmD9yrBiVgaA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH v4 2/4] target/m68k: add fmod/frem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Using a local m68k floatx80_mod() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] The quotient byte of the FPSR is updated with the result of the operation. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/Makefile.objs | 3 +- target/m68k/cpu.h | 1 + target/m68k/fpu_helper.c | 35 +++++++++++++++- target/m68k/helper.h | 2 + target/m68k/softfloat.c | 105 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/softfloat.h | 26 ++++++++++++ target/m68k/translate.c | 6 +++ 7 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 target/m68k/softfloat.c create mode 100644 target/m68k/softfloat.h diff --git a/target/m68k/Makefile.objs b/target/m68k/Makefile.objs index d143f20270..ac61948676 100644 --- a/target/m68k/Makefile.objs +++ b/target/m68k/Makefile.objs @@ -1,4 +1,5 @@ obj-y +=3D m68k-semi.o -obj-y +=3D translate.o op_helper.o helper.o cpu.o fpu_helper.o +obj-y +=3D translate.o op_helper.o helper.o cpu.o +obj-y +=3D fpu_helper.o softfloat.o obj-y +=3D gdbstub.o obj-$(CONFIG_SOFTMMU) +=3D monitor.o diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 65f4fb95cb..2259bf22dc 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -427,6 +427,7 @@ typedef enum { /* Quotient */ =20 #define FPSR_QT_MASK 0x00ff0000 +#define FPSR_QT_SHIFT 16 =20 /* Floating-Point Control Register */ /* Rounding mode */ diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 3c5a82aaa0..8286228b81 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "fpu/softfloat.h" +#include "softfloat.h" =20 /* Undefined offsets may be different on various FPU. * On 68040 they return 0.0 (floatx80_zero) @@ -509,3 +509,36 @@ uint32_t HELPER(fmovemd_ld_postinc)(CPUM68KState *env,= uint32_t addr, { return fmovem_postinc(env, addr, mask, cpu_ld_float64_ra); } + +static void make_quotient(CPUM68KState *env, floatx80 val) +{ + int32_t quotient; + int sign; + + if (floatx80_is_any_nan(val)) { + return; + } + + quotient =3D floatx80_to_int32(val, &env->fp_status); + sign =3D quotient < 0; + if (sign) { + quotient =3D -quotient; + } + + quotient =3D (sign << 7) | (quotient & 0x7f); + env->fpsr =3D (env->fpsr & ~FPSR_QT_MASK) | (quotient << FPSR_QT_SHIFT= ); +} + +void HELPER(fmod)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + res->d =3D floatx80_mod(val1->d, val0->d, &env->fp_status); + + make_quotient(env, res->d); +} + +void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + res->d =3D floatx80_rem(val1->d, val0->d, &env->fp_status); + + make_quotient(env, res->d); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 7f400f0def..76a0590c9c 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -63,6 +63,8 @@ DEF_HELPER_3(fmovemx_ld_postinc, i32, env, i32, i32) DEF_HELPER_3(fmovemd_st_predec, i32, env, i32, i32) DEF_HELPER_3(fmovemd_st_postinc, i32, env, i32, i32) DEF_HELPER_3(fmovemd_ld_postinc, i32, env, i32, i32) +DEF_HELPER_4(fmod, void, env, fp, fp, fp) +DEF_HELPER_4(frem, void, env, fp, fp, fp) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c new file mode 100644 index 0000000000..8c77757b4e --- /dev/null +++ b/target/m68k/softfloat.c @@ -0,0 +1,105 @@ +/* + * Ported from a work by Andreas Grabher for Previous, NeXT Computer Emula= tor, + * derived from NetBSD M68040 FPSP functions, + * derived from release 2a of the SoftFloat IEC/IEEE Floating-point Arithm= etic + * Package. Those parts of the code (and some later contributions) are + * provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file will be taken to be licensed under + * the Softfloat-2a license unless specifically indicated otherwise. + */ + +/* Portions of this work are licensed under the terms of the GNU GPL, + * version 2 or later. See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "softfloat.h" +#include "fpu/softfloat-macros.h" + +/*------------------------------------------------------------------------= ---- + | Returns the modulo remainder of the extended double-precision floating-= point + | value `a' with respect to the corresponding value `b'. + *------------------------------------------------------------------------= ----*/ + +floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) +{ + flag aSign, zSign; + int32_t aExp, bExp, expDiff; + uint64_t aSig0, aSig1, bSig; + uint64_t qTemp, term0, term1; + + aSig0 =3D extractFloatx80Frac(a); + aExp =3D extractFloatx80Exp(a); + aSign =3D extractFloatx80Sign(a); + bSig =3D extractFloatx80Frac(b); + bExp =3D extractFloatx80Exp(b); + + if (aExp =3D=3D 0x7FFF) { + if ((uint64_t) (aSig0 << 1) + || ((bExp =3D=3D 0x7FFF) && (uint64_t) (bSig << 1))) { + return propagateFloatx80NaN(a, b, status); + } + goto invalid; + } + if (bExp =3D=3D 0x7FFF) { + if ((uint64_t) (bSig << 1)) { + return propagateFloatx80NaN(a, b, status); + } + return a; + } + if (bExp =3D=3D 0) { + if (bSig =3D=3D 0) { + invalid: + float_raise(float_flag_invalid, status); + return floatx80_default_nan(status); + } + normalizeFloatx80Subnormal(bSig, &bExp, &bSig); + } + if (aExp =3D=3D 0) { + if ((uint64_t) (aSig0 << 1) =3D=3D 0) { + return a; + } + normalizeFloatx80Subnormal(aSig0, &aExp, &aSig0); + } + bSig |=3D LIT64(0x8000000000000000); + zSign =3D aSign; + expDiff =3D aExp - bExp; + aSig1 =3D 0; + if (expDiff < 0) { + return a; + } + qTemp =3D (bSig <=3D aSig0); + if (qTemp) { + aSig0 -=3D bSig; + } + expDiff -=3D 64; + while (0 < expDiff) { + qTemp =3D estimateDiv128To64(aSig0, aSig1, bSig); + qTemp =3D (2 < qTemp) ? qTemp - 2 : 0; + mul64To128(bSig, qTemp, &term0, &term1); + sub128(aSig0, aSig1, term0, term1, &aSig0, &aSig1); + shortShift128Left(aSig0, aSig1, 62, &aSig0, &aSig1); + } + expDiff +=3D 64; + if (0 < expDiff) { + qTemp =3D estimateDiv128To64(aSig0, aSig1, bSig); + qTemp =3D (2 < qTemp) ? qTemp - 2 : 0; + qTemp >>=3D 64 - expDiff; + mul64To128(bSig, qTemp << (64 - expDiff), &term0, &term1); + sub128(aSig0, aSig1, term0, term1, &aSig0, &aSig1); + shortShift128Left(0, bSig, 64 - expDiff, &term0, &term1); + while (le128(term0, term1, aSig0, aSig1)) { + ++qTemp; + sub128(aSig0, aSig1, term0, term1, &aSig0, &aSig1); + } + } + return + normalizeRoundAndPackFloatx80( + 80, zSign, bExp + expDiff, aSig0, aSig1, status); +} diff --git a/target/m68k/softfloat.h b/target/m68k/softfloat.h new file mode 100644 index 0000000000..8d8ca0fc45 --- /dev/null +++ b/target/m68k/softfloat.h @@ -0,0 +1,26 @@ +/* + * Ported from a work by Andreas Grabher for Previous, NeXT Computer Emula= tor, + * derived from NetBSD M68040 FPSP functions, + * derived from release 2a of the SoftFloat IEC/IEEE Floating-point Arithm= etic + * Package. Those parts of the code (and some later contributions) are + * provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file will be taken to be licensed under + * the Softfloat-2a license unless specifically indicated otherwise. + */ + +/* Portions of this work are licensed under the terms of the GNU GPL, + * version 2 or later. See the COPYING file in the top-level directory. + */ + +#ifndef TARGET_M68K_SOFTFLOAT_H +#define TARGET_M68K_SOFTFLOAT_H +#include "fpu/softfloat.h" + +floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status); +#endif diff --git a/target/m68k/translate.c b/target/m68k/translate.c index a22993c7ce..f8db26fa8e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5081,6 +5081,9 @@ DISAS_INSN(fpu) case 0x64: /* fddiv */ gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x21: /* fmod */ + gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x22: /* fadd */ gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest); break; @@ -5102,6 +5105,9 @@ DISAS_INSN(fpu) case 0x24: /* fsgldiv */ gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x25: /* frem */ + gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x27: /* fsglmul */ gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; --=20 2.14.3 From nobody Fri May 17 22:57:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519503744462316.37689901597776; Sat, 24 Feb 2018 12:22:24 -0800 (PST) Received: from localhost ([::1]:51333 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgKt-0004Ka-MR for importer@patchew.org; Sat, 24 Feb 2018 15:22:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epgHA-00023b-ED for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epgH7-00083X-72 for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:32 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:54695) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epgH6-00082W-T3 for qemu-devel@nongnu.org; Sat, 24 Feb 2018 15:18:29 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Lpis6-1eDcUL2dOw-00fRxP; Sat, 24 Feb 2018 21:18:07 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 24 Feb 2018 21:18:01 +0100 Message-Id: <20180224201802.911-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180224201802.911-1-laurent@vivier.eu> References: <20180224201802.911-1-laurent@vivier.eu> X-Provags-ID: V03:K0:ycTfELJ3xZyIEsExKQc7ozg+kMec+qqk7JOdgs66kRjEZy4USlX AUDiGcB4BDv7CrL2xPSoVmcdh4U33R4u5idaspuJQWjGOWUHkpfzbRY21Lnp+jSZq/+H6pl NJ9llN4oDBGiDNGu4MkxqV5iiDCXJGKC9e008+3jPJyjS3Hec+lF40XywtIfGJGUuA4iicR ZxVcqcytlUmG6M+kdqsbQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:V+R590I1b1g=:sQr1+ZOxDDKtwyF0s4H3CA Xvrli2cCjrGQ1s9AWOgwfd++sWpCzM5CI3yF9H30UGIPuDpAawyBHY6nngOSedPHHPxAwOSZT rtNywh1AZg+wklfRiJm49B6CGm3i5zXbpfaJtF9mahq5lV0beNUZYDE4JuLhofY7oaQkgEGyJ BYVh91AdPSBdTiPi5jSiK07V3uiI8f3hAnczsyba4CnTg8KKw6i6LzgvtB7SVEIUqhc/qt6Bd D7Qeiq6mR7UynnLdh7cPiQ1SF0LakXKdZEoy9QkuishfC46aHBCIDBGCnLCO4ogi9stg1LeZ9 rhRLe5Er9bRJL0ekxcCANnewCQ/jlmYXzYxBEyl83yuEvzlC+mtZXRmO0To7jtJy+f8R6N47X 4hxwrqNvLR76/wFQHwlFfLJJi748CzxUDEPyENsc3ZOeWASNNr3P1bRMqUFyo/tlR/pTDkJyh ciwkCR4Ib6y0LAljCU+SFp+bXansh1RgKXkRoJ03phaCDS7z/KJkWGmwGV57DyBMyVDDneIwb StSZprFAemL32E+kRjZOOu9wz6Gk4By8fpKoJLrQSs6AkTo/Mz3DKuCJmO+zMdcCQ3F6cSU4t CNPV4eM73zndQ28syyV0rvPssCNjPTA0XFYQSIcYJySNZwzYnSLvZHAEuETGGfzznnJrlJ6Gg l5a1ldPvx5bB04neRJHcm2fd4TgZllQh9mvN3MdLY5YEgsW9IPrgJcWwjKivsk4M7sxhia3nq MwzJBoWO6MGv1hpi6ddcTwFjUZZIwfvZUdNPDQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH v4 3/4] softfloat: use floatx80_infinity in softfloat X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- CC: Aurelien Jarno v4: fix floatx80_to_int64() to check for NaN, not for infinity fix floatx80_is_infinity() to ignore mantissa's MSB fpu/softfloat-specialize.h | 14 ++++++++++++++ fpu/softfloat.c | 39 +++++++++++++++++++++++++-------------- include/fpu/softfloat.h | 13 +++++++++++-- 3 files changed, 50 insertions(+), 16 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 46126e9e0a..9ccb59422c 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -177,6 +177,20 @@ floatx80 floatx80_default_nan(float_status *status) return r; } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated extended double-precision inf. +*-------------------------------------------------------------------------= ---*/ + +#define floatx80_infinity_high 0x7FFF +#if defined(TARGET_M68K) +#define floatx80_infinity_low LIT64(0x0000000000000000) +#else +#define floatx80_infinity_low LIT64(0x8000000000000000) +#endif + +const floatx80 floatx80_infinity + =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); + /*------------------------------------------------------------------------= ---- | The pattern for a default generated quadruple-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index fb4853682e..e124df9f7e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2636,7 +2636,9 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, flag zSign, ) { return packFloatx80( zSign, 0x7FFE, ~ roundMask ); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( zExp <=3D 0 ) { isTiny =3D @@ -3182,7 +3184,9 @@ floatx80 float32_to_floatx80(float32 a, float_status = *status) if (aSig) { return commonNaNToFloatx80(float32ToCommonNaN(a, status), stat= us); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); @@ -4037,7 +4041,9 @@ floatx80 float64_to_floatx80(float64 a, float_status = *status) if (aSig) { return commonNaNToFloatx80(float64ToCommonNaN(a, status), stat= us); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); @@ -4549,10 +4555,7 @@ int64_t floatx80_to_int64(floatx80 a, float_status *= status) if ( shiftCount <=3D 0 ) { if ( shiftCount ) { float_raise(float_flag_invalid, status); - if ( ! aSign - || ( ( aExp =3D=3D 0x7FFF ) - && ( aSig !=3D LIT64( 0x8000000000000000 ) ) ) - ) { + if (!aSign || floatx80_is_any_nan(a)) { return LIT64( 0x7FFFFFFFFFFFFFFF ); } return (int64_t) LIT64( 0x8000000000000000 ); @@ -4858,7 +4861,9 @@ static floatx80 addFloatx80Sigs(floatx80 a, floatx80 = b, flag zSign, if ((uint64_t)(bSig << 1)) { return propagateFloatx80NaN(a, b, status); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) ++expDiff; shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); @@ -4933,7 +4938,8 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 = b, flag zSign, if ((uint64_t)(bSig << 1)) { return propagateFloatx80NaN(a, b, status); } - return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign ^ 1, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) ++expDiff; shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); @@ -5038,7 +5044,8 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_s= tatus *status) return propagateFloatx80NaN(a, b, status); } if ( ( bExp | bSig ) =3D=3D 0 ) goto invalid; - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( bExp =3D=3D 0x7FFF ) { if ((uint64_t)(bSig << 1)) { @@ -5049,7 +5056,8 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_s= tatus *status) float_raise(float_flag_invalid, status); return floatx80_default_nan(status); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( zSign, 0, 0 ); @@ -5103,7 +5111,8 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_s= tatus *status) } goto invalid; } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( bExp =3D=3D 0x7FFF ) { if ((uint64_t)(bSig << 1)) { @@ -5119,7 +5128,8 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_s= tatus *status) return floatx80_default_nan(status); } float_raise(float_flag_divbyzero, status); - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); } @@ -5942,7 +5952,8 @@ floatx80 float128_to_floatx80(float128 a, float_statu= s *status) if ( aSig0 | aSig1 ) { return commonNaNToFloatx80(float128ToCommonNaN(a, status), sta= tus); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloatx80( aSign, 0, 0= ); diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 125dcb5586..873a520e3e 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -563,6 +563,11 @@ float32 floatx80_to_float32(floatx80, float_status *st= atus); float64 floatx80_to_float64(floatx80, float_status *status); float128 floatx80_to_float128(floatx80, float_status *status); =20 +/*------------------------------------------------------------------------= ---- +| The pattern for an extended double-precision inf. +*-------------------------------------------------------------------------= ---*/ +extern const floatx80 floatx80_infinity; + /*------------------------------------------------------------------------= ---- | Software IEC/IEEE extended double-precision operations. *-------------------------------------------------------------------------= ---*/ @@ -603,7 +608,12 @@ static inline floatx80 floatx80_chs(floatx80 a) =20 static inline int floatx80_is_infinity(floatx80 a) { - return (a.high & 0x7fff) =3D=3D 0x7fff && a.low =3D=3D 0x8000000000000= 000LL; +#if defined(TARGET_M68K) + return (a.high & 0x7fff) =3D=3D floatx80_infinity.high && !(a.low << 1= ); +#else + return (a.high & 0x7fff) =3D=3D floatx80_infinity.high && + a.low =3D=3D floatx80_infinity.low; +#endif } =20 static inline int floatx80_is_neg(floatx80 a) @@ -646,7 +656,6 @@ static inline bool floatx80_invalid_encoding(floatx80 a) #define floatx80_ln2 make_floatx80(0x3ffe, 0xb17217f7d1cf79acLL) #define floatx80_pi make_floatx80(0x4000, 0xc90fdaa22168c235LL) #define floatx80_half make_floatx80(0x3ffe, 0x8000000000000000LL) -#define floatx80_infinity make_floatx80(0x7fff, 0x8000000000000000LL) =20 /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the extended double-precision floating-point --=20 2.14.3 From nobody Fri May 17 22:57:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Using local m68k floatx80_getman(), floatx80_getexp(), floatx80_scale() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/fpu_helper.c | 15 +++++ target/m68k/helper.h | 3 + target/m68k/softfloat.c | 144 +++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/softfloat.h | 3 + target/m68k/translate.c | 9 +++ 5 files changed, 174 insertions(+) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 8286228b81..cdb9b50462 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -542,3 +542,18 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg= *val0, FPReg *val1) =20 make_quotient(env, res->d); } + +void HELPER(fgetexp)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + res->d =3D floatx80_getexp(val->d, &env->fp_status); +} + +void HELPER(fgetman)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + res->d =3D floatx80_getman(val->d, &env->fp_status); +} + +void HELPER(fscale)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val= 1) +{ + res->d =3D floatx80_scale(val1->d, val0->d, &env->fp_status); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 76a0590c9c..c348dced3a 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -65,6 +65,9 @@ DEF_HELPER_3(fmovemd_st_postinc, i32, env, i32, i32) DEF_HELPER_3(fmovemd_ld_postinc, i32, env, i32, i32) DEF_HELPER_4(fmod, void, env, fp, fp, fp) DEF_HELPER_4(frem, void, env, fp, fp, fp) +DEF_HELPER_3(fgetexp, void, env, fp, fp) +DEF_HELPER_3(fgetman, void, env, fp, fp) +DEF_HELPER_4(fscale, void, env, fp, fp, fp) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index 8c77757b4e..9cb141900c 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -22,6 +22,19 @@ #include "softfloat.h" #include "fpu/softfloat-macros.h" =20 +static floatx80 propagateFloatx80NaNOneArg(floatx80 a, float_status *statu= s) +{ + if (floatx80_is_signaling_nan(a, status)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + return floatx80_maybe_silence_nan(a, status); +} + /*------------------------------------------------------------------------= ---- | Returns the modulo remainder of the extended double-precision floating-= point | value `a' with respect to the corresponding value `b'. @@ -103,3 +116,134 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_s= tatus *status) normalizeRoundAndPackFloatx80( 80, zSign, bExp + expDiff, aSig0, aSig1, status); } + +/*------------------------------------------------------------------------= ---- + | Returns the mantissa of the extended double-precision floating-point + | value `a'. + *------------------------------------------------------------------------= ----*/ + +floatx80 floatx80_getman(floatx80 a, float_status *status) +{ + flag aSign; + int32_t aExp; + uint64_t aSig; + + aSig =3D extractFloatx80Frac(a); + aExp =3D extractFloatx80Exp(a); + aSign =3D extractFloatx80Sign(a); + + if (aExp =3D=3D 0x7FFF) { + if ((uint64_t) (aSig << 1)) { + return propagateFloatx80NaNOneArg(a , status); + } + float_raise(float_flag_invalid , status); + return floatx80_default_nan(status); + } + + if (aExp =3D=3D 0) { + if (aSig =3D=3D 0) { + return packFloatx80(aSign, 0, 0); + } + normalizeFloatx80Subnormal(aSig, &aExp, &aSig); + } + + return roundAndPackFloatx80(status->floatx80_rounding_precision, aSign, + 0x3FFF, aSig, 0, status); +} + +/*------------------------------------------------------------------------= ---- + | Returns the exponent of the extended double-precision floating-point + | value `a' as an extended double-precision value. + *------------------------------------------------------------------------= ----*/ + +floatx80 floatx80_getexp(floatx80 a, float_status *status) +{ + flag aSign; + int32_t aExp; + uint64_t aSig; + + aSig =3D extractFloatx80Frac(a); + aExp =3D extractFloatx80Exp(a); + aSign =3D extractFloatx80Sign(a); + + if (aExp =3D=3D 0x7FFF) { + if ((uint64_t) (aSig << 1)) { + return propagateFloatx80NaNOneArg(a , status); + } + float_raise(float_flag_invalid , status); + return floatx80_default_nan(status); + } + + if (aExp =3D=3D 0) { + if (aSig =3D=3D 0) { + return packFloatx80(aSign, 0, 0); + } + normalizeFloatx80Subnormal(aSig, &aExp, &aSig); + } + + return int32_to_floatx80(aExp - 0x3FFF, status); +} + +/*------------------------------------------------------------------------= ---- + | Scales extended double-precision floating-point value in operand `a' by + | value `b'. The function truncates the value in the second operand 'b' to + | an integral value and adds that value to the exponent of the operand 'a= '. + | The operation performed according to the IEC/IEEE Standard for Binary + | Floating-Point Arithmetic. + *------------------------------------------------------------------------= ----*/ + +floatx80 floatx80_scale(floatx80 a, floatx80 b, float_status *status) +{ + flag aSign, bSign; + int32_t aExp, bExp, shiftCount; + uint64_t aSig, bSig; + + aSig =3D extractFloatx80Frac(a); + aExp =3D extractFloatx80Exp(a); + aSign =3D extractFloatx80Sign(a); + bSig =3D extractFloatx80Frac(b); + bExp =3D extractFloatx80Exp(b); + bSign =3D extractFloatx80Sign(b); + + if (bExp =3D=3D 0x7FFF) { + if ((uint64_t) (bSig << 1) || + ((aExp =3D=3D 0x7FFF) && (uint64_t) (aSig << 1))) { + return propagateFloatx80NaN(a, b, status); + } + float_raise(float_flag_invalid , status); + return floatx80_default_nan(status); + } + if (aExp =3D=3D 0x7FFF) { + if ((uint64_t) (aSig << 1)) { + return propagateFloatx80NaN(a, b, status); + } + return packFloatx80(aSign, floatx80_infinity.high, + floatx80_infinity.low); + } + if (aExp =3D=3D 0) { + if (aSig =3D=3D 0) { + return packFloatx80(aSign, 0, 0); + } + if (bExp < 0x3FFF) { + return a; + } + normalizeFloatx80Subnormal(aSig, &aExp, &aSig); + } + + if (bExp < 0x3FFF) { + return a; + } + + if (0x400F < bExp) { + aExp =3D bSign ? -0x6001 : 0xE000; + return roundAndPackFloatx80(status->floatx80_rounding_precision, + aSign, aExp, aSig, 0, status); + } + + shiftCount =3D 0x403E - bExp; + bSig >>=3D shiftCount; + aExp =3D bSign ? (aExp - bSig) : (aExp + bSig); + + return roundAndPackFloatx80(status->floatx80_rounding_precision, + aSign, aExp, aSig, 0, status); +} diff --git a/target/m68k/softfloat.h b/target/m68k/softfloat.h index 8d8ca0fc45..78fbc0cd0c 100644 --- a/target/m68k/softfloat.h +++ b/target/m68k/softfloat.h @@ -23,4 +23,7 @@ #include "fpu/softfloat.h" =20 floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status); +floatx80 floatx80_getman(floatx80 a, float_status *status); +floatx80 floatx80_getexp(floatx80 a, float_status *status); +floatx80 floatx80_scale(floatx80 a, floatx80 b, float_status *status); #endif diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f8db26fa8e..dbb24f8d84 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5072,6 +5072,12 @@ DISAS_INSN(fpu) case 0x5e: /* fdneg */ gen_helper_fdneg(cpu_env, cpu_dest, cpu_src); break; + case 0x1e: /* fgetexp */ + gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src); + break; + case 0x1f: /* fgetman */ + gen_helper_fgetman(cpu_env, cpu_dest, cpu_src); + break; case 0x20: /* fdiv */ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; @@ -5108,6 +5114,9 @@ DISAS_INSN(fpu) case 0x25: /* frem */ gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x26: /* fscale */ + gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x27: /* fsglmul */ gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; --=20 2.14.3