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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g3DEJfoYnA4ZEKPBUJIKJiCt3e/U1XrQnB4yUIPoJVs=; b=jLAqDxE2ff3dH6ZuBdQ6Sph+7R8LcQwWVfXVOeWLu5ant2OC1gokCFwe9IRf7DitCB sb522el61ktNwKm6BWjUAy8tGaJk0RlY8DUaiUk+Djh7l+ArKTjQgmDr9wzY2n+ylm2T HakyPLzOw3sNEGkqOUEaXkrTDl91ZjHmzdRxU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g3DEJfoYnA4ZEKPBUJIKJiCt3e/U1XrQnB4yUIPoJVs=; b=iUtglDmwnESCVW+wV5I1uGNFve0bfMqMbTVAMDY8FU5yK+eHROpyqadzgQHxzcTVK7 ivyY1B/4n57l5OJVV2Dzot3bPXuOjjdvDdzprgdi13alCSQl3eqoOnCuQiCnRFGhVDoB oXV/CCBck/b+6Ersc2ZmfEhELjC565xo7dAfIdZuww037qafGk0xYvs8JmDXAo82w7lt r26DCcube8Jux7A61OPn8Cl+WKYKi4j92Msq6EFQHTqARTEQue8grn9dHFB7Zegj0dHq cqFRril+jz0TeM3Ci87zmUABbsqfDiH8PsbePyU6+NT7gC0ngCzRrYeodziFz8rqL1m7 p9Tg== X-Gm-Message-State: APf1xPDHmkSd4wji2HPdO6o3++SXm4hrWP2yZ9ky2Wmc0MaYYPPkyqv2 YfJgkfao0TU/8dlTFr+tI3BvxuHKTWg= X-Google-Smtp-Source: AH8x2259lcBsoy3NP/Is/naQA5bRQHM3XmKNWqW5W/JwVr7jQ+5XFMVxXYSlfS487oHNnpQ+zuet3w== X-Received: by 10.101.91.3 with SMTP id y3mr7764158pgq.260.1518382732211; Sun, 11 Feb 2018 12:58:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:42 -0800 Message-Id: <20180211205848.4568-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 1/7] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 180ab75458..4b102ec356 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4357,7 +4357,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL1_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4365,7 +4365,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL2_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4373,14 +4373,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT, + .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL3_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518383077729328.87029508217404; Sun, 11 Feb 2018 13:04:37 -0800 (PST) Received: from localhost ([::1]:55224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekync-0002mp-Rh for importer@patchew.org; Sun, 11 Feb 2018 16:04:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyi9-0006l0-Cu for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekyi7-0004Af-NL for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:57 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36566) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekyi7-00048l-GU for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:55 -0500 Received: by mail-pg0-x243.google.com with SMTP id j9so5072929pgv.3 for ; Sun, 11 Feb 2018 12:58:55 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=dF1sML3vr/csfHJSssQQ0cB9ZccsJgvF75xdElASwiNpLIwcXEpzU+h7wlf8InzN0I sGNElnWxT7oQ2D9RsrdFUZUpEuY8rdsyAhmtbvBF6rtimblY7g6+Gw8SICzqrGRowlCY nfLl32aqy2MyBsezfYt+tYwJqNoxYFuHFrkJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=J/Z5Y4Tr5hpoyY66J4JyRiE8ywP6uDvLI2vEBixcXK7gtrqXoL60wg/KsXqZip/e5o lNPIpbUsg2qDmkX76j7MxxoHE3+v8oDtUh+7WZCHAw90NIJaEyme8kK4gYT3nyrikzG0 OoqLOZgzO8cKXnCC5fJ2WPMug38/Pljf7JHcxWcDKp6ivPfxjURVlQpEBSQq2bG6nlv7 wdLIiA8QUYLpT2v3Y5BDDxilV1oSXvJwTOSu1bj3izyz/fQgWDPQCdlB6DYz49JDKCcG QO/IDgSdbKDztRiQBb3a2VuFCd3T+zN5O2wkNQZn7SdcwofeUZ1CtyrN+3XK57lINyO0 Wl8Q== X-Gm-Message-State: APf1xPAczcuRi3CZY+V6LP2oN+iBckBbWoESrhmNquBV03ELU+SZVJhn c+AcVPAuyEurbQ6Yul3Pr3U3Z9mA+iY= X-Google-Smtp-Source: AH8x227KLXsWZFHvx77mJzHq/8yL/t/q0gK/KqkFhg1lR1x1yt6XwjEOi3bPxAm1c9XT/KJ8rCyc/g== X-Received: by 10.99.147.72 with SMTP id w8mr7417602pgm.300.1518382733941; Sun, 11 Feb 2018 12:58:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:43 -0800 Message-Id: <20180211205848.4568-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 2/7] target/arm: Enforce FP access to FPCR/FPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 ++++++++++++++++++----------------- target/arm/helper.c | 6 ++++-- target/arm/translate-a64.c | 3 +++ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 521444a5a1..e966a57f8a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1714,7 +1714,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) } =20 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [15..8] indicate what behaviour + * special-behaviour cp reg and bits [11..8] indicate what behaviour * it has. Otherwise it is a simple cp reg, where CONST indicates that * TCG can assume the value to be constant (ie load at translate time) * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END @@ -1735,24 +1735,25 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_FPU 0x1000 /* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xffff +#define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0xff +#define ARM_CP_FLAG_MASK 0x10ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index 4b102ec356..d41fb8371f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3356,10 +3356,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fp= cr_write }, + .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fp= sr_write }, + .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fb1a4cb532..89f50558a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1631,6 +1631,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: break; } + if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + return; + } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { gen_io_start(); --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518382877067122.3106953241138; Sun, 11 Feb 2018 13:01:17 -0800 (PST) Received: from localhost ([::1]:54979 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekykM-0008Ka-2Z for importer@patchew.org; Sun, 11 Feb 2018 16:01:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyiA-0006lp-0z for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekyi9-0004DX-4I for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:58 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:36565) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekyi8-0004C8-U6 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:57 -0500 Received: by mail-pg0-x241.google.com with SMTP id j9so5072948pgv.3 for ; Sun, 11 Feb 2018 12:58:56 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nL6gPUlDY152kgVDfEyFrw2bQqSTgTyjJgXC6doQ4ns=; b=OO+lnWxNmvkWTzfLrcSIaeRL7n6XLGjyybxXO0HWc9X9/3UddV2hiEVFEw29MlpomU OWCLYvtjoblYWTL/TvZwqpwCAv1wDrQKX/N9ZLgzraEPH9xNHpAbGDI+UsOugATlNxPm ZwtFixLV+X/aGqcOFLlj/cntQILV0EpsAIoiQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nL6gPUlDY152kgVDfEyFrw2bQqSTgTyjJgXC6doQ4ns=; b=Vum5WTLnDzuqaZg8HjsZMqg+Y/t08h8qRmofPc3+NvFPCcK3Fa61onGEAUGfnuVfji NQ88knhYrUJLrYlvFodJVXP7u8S+N6tFZqJF1CJ/jMLvxCS9HcFWsxqN3L2L8D/ew02i JB54QbhB+8C3o6cCSzRhndPydMh+z8k0nJsT0GbVP9kM9Jn4D4iDAOg+5ZDOxf/CT0Th a3GMOfOAavtG+J4O8/OKsGHlDDDD4Thxdxusc0oh/7zgOTzlH1fbm8oxnXYvliIpKaOe YDkY2eSN406u4QGWtQE3TJcT2c8GT8laLSic4VgRInfZynqtL/8ROW8JzwduscnJnixQ ov/A== X-Gm-Message-State: APf1xPDl85NvyLAwayBRrJhoqY2fn7I14sEZlSNK02muOCCaK8MOX7Wu zMI5H29CmxgtBDsqh72ucyrviJVVwXA= X-Google-Smtp-Source: AH8x225pe+Yzv6ZvclA21RIIl4O1A8/v8dA3dXeMbI0jvKqMH705aKRbscxXzJVJ+36Re7NVla7kNw== X-Received: by 10.101.88.138 with SMTP id d10mr7978050pgu.52.1518382735654; Sun, 11 Feb 2018 12:58:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:44 -0800 Message-Id: <20180211205848.4568-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 3/7] target/arm: Suppress TB end for FPCR/FPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Nothing in either register affects the TB. Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d41fb8371f..e0184c7162 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3356,11 +3356,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518383100414317.80324382853803; Sun, 11 Feb 2018 13:05:00 -0800 (PST) Received: from localhost ([::1]:55240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekynz-00033R-L2 for importer@patchew.org; Sun, 11 Feb 2018 16:04:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyiC-0006mr-7q for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekyiB-0004HS-0A for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:00 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:38070) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekyiA-0004G0-Mu for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:58:58 -0500 Received: by mail-pg0-x243.google.com with SMTP id l24so115214pgc.5 for ; Sun, 11 Feb 2018 12:58:58 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u9SJZsEYOcc3Fv1vUr4knqPF5dvb+F9pFsuL2qHHgwA=; b=YyWZqkJFVAvIA0Y6tM2lbWiZ9uIPntv2jzsPXGpYZgzDEMmz9bh90WJORDgMmvpQGW IWraHn5tOfNtApZEO4JhTaDAgWxKDceNaXnse7UAf5zjdoeybgofgUFeI+1G6LE3AM6w kR17xWhCNz09q7Ak/PRm1ixp07buIyxOZzevc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u9SJZsEYOcc3Fv1vUr4knqPF5dvb+F9pFsuL2qHHgwA=; b=rG6CtM4jwC6FlkYq5VkCXzadTnWfV9/PZPoD85fBOVnyQxNMqMiaL23o8xFLFzHo23 P2vq0HZitVT8AXnW1zs9NQ3p+6xCrw9nGnpsfxLZkJNb+O2ncB/64B5SdQE5KLCaiFqs Jrw4Nae9FDG1r/FH6mYN3UjAKeSITTU42lv7E4kOJcVBR3aJhhdd8S3mfR2Acl9GLeSA ueHtYpCs8FlvmeDVnIJk0nlKeygkf06swmFKfqmTeSkTZKQiBGfamL6OVXl5ODgimmu5 0UnVbj/vwA+dolNuGp0pc71DV91QIz49FBfUEgMjzQedCpPgJviEGjV4TLx3c7PmG5nu oRDA== X-Gm-Message-State: APf1xPAaXWJWNvfm2qMeiqaaR8826pvB6stQ962Bzqs9nC0Ab4feLDQ6 mcmNS8Z3TH5iG0gYYmy2LEuS9Z70ymY= X-Google-Smtp-Source: AH8x225m6O65HKIgSNWDXpDhMZfWB/0PVS+L1+CMpv/KXYKkoMcqZ6JzEYuzxXWIb12SkaoDRLFJjA== X-Received: by 10.99.113.75 with SMTP id b11mr7982380pgn.271.1518382737273; Sun, 11 Feb 2018 12:58:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:45 -0800 Message-Id: <20180211205848.4568-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 4/7] target/arm: Enforce access to ZCR_EL at translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 22 ++++------------------ target/arm/translate-a64.c | 16 ++++++++++++++++ 4 files changed, 28 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e966a57f8a..51a3e16275 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1750,10 +1750,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x10ff +#define ARM_CP_FLAG_MASK 0x30ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/internals.h b/target/arm/internals.h index 89f5d2fe12..47cc224a46 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -243,6 +243,7 @@ enum arm_exception_class { EC_AA64_HVC =3D 0x16, EC_AA64_SMC =3D 0x17, EC_SYSTEMREGISTERTRAP =3D 0x18, + EC_SVEACCESSTRAP =3D 0x19, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -381,6 +382,11 @@ static inline uint32_t syn_fp_access_trap(int cv, int = cond, bool is_16bit) | (cv << 24) | (cond << 20); } =20 +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/helper.c b/target/arm/helper.c index e0184c7162..550dc3d290 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4335,20 +4335,6 @@ static int sve_exception_el(CPUARMState *env) return 0; } =20 -static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - switch (sve_exception_el(env)) { - case 3: - return CP_ACCESS_TRAP_EL3; - case 2: - return CP_ACCESS_TRAP_EL2; - case 1: - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4359,7 +4345,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D zcr_access, + .access =3D PL1_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4367,7 +4353,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D zcr_access, + .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4375,14 +4361,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, + .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .accessfn =3D zcr_access, + .access =3D PL3_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 89f50558a7..e3881d4999 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1182,6 +1182,19 @@ static inline bool fp_access_check(DisasContext *s) return false; } =20 +/* Check that SVE access is enabled. If it is, return true. + * If not, emit code to generate an appropriate exception and return false. + */ +static inline bool sve_access_check(DisasContext *s) +{ + if (s->sve_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(), + s->sve_excp_el); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -1631,6 +1644,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: break; } + if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; + } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; } --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518382916125509.73159858758265; Sun, 11 Feb 2018 13:01:56 -0800 (PST) Received: from localhost ([::1]:54983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyl1-0000KG-6r for importer@patchew.org; Sun, 11 Feb 2018 16:01:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyiE-0006qN-Co for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekyiC-0004Jz-Dg for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:02 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:44445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekyiC-0004J7-5L for qemu-devel@nongnu.org; Sun, 11 Feb 2018 15:59:00 -0500 Received: by mail-pg0-x241.google.com with SMTP id j9so5587281pgp.11 for ; Sun, 11 Feb 2018 12:58:59 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0RZ/Dwu85IRJts+xxg49wprCBup0YeyQq2OHAWxr7S4=; b=Fx/QatXKxu+Xm+t/sMDOO+ZNw0au4EpoIBDjOxaFa6WgHiplKPqcH8MlOhH3aiIoML BJt/z96t7qMJopTpWqign0oufnMmzquCpizg6K/g/NklR6+Ad8f93OeqfgiKjKU1jdPs lWuz8DvkMEzr7YxJPg0LchfF+cMr1xS0q4Hks= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0RZ/Dwu85IRJts+xxg49wprCBup0YeyQq2OHAWxr7S4=; b=JodwYzGVxg0pFLqGHWrH73zJJDBMAlt0onna3M+22deW3L/SIy27AyWKzWfiLzJkLq gor3bTbYZOJoPFz+lnolz7iiKAJS4Xs55T2ibSBIju9sLm3xJR0Bi/GZKe/03Mb7YV+z E9tFVd30g9VYvBqV7SBmYk5AGIMjJbw1jRbhs6SNgi3PsC3VJJ5oKaH6rVlx4UUTiV88 nsdO79VibJ2uFSC5FXfu494ixlI5PWzn1VHk5W5AlZepIMyl8bpFHK0H3+EjoOY6xk46 EY6Mnr72juTeHt4dDDodVE8noG6ZaGZvfzZBvMMJ0IHobRBZWDd0sUpn1ahG5naRhB0n /0rg== X-Gm-Message-State: APf1xPDRKPxl82gna/+g0rWVRNeVV8va9HVaLPF458JmBaG/dbv1UySX jiZJMAWiE+drVu/RQn3kUyqIWhPBUOo= X-Google-Smtp-Source: AH8x227FxEgpx4XlOg+lyqLOy3G7HKQz3q9RvT00L8fs9olib25iKu4AczwFucJjlP385rGRdg6Duw== X-Received: by 10.99.37.7 with SMTP id l7mr7741682pgl.311.1518382738690; Sun, 11 Feb 2018 12:58:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:46 -0800 Message-Id: <20180211205848.4568-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 5/7] target/arm: Handle SVE registers when using clear_vec_high X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 162 +++++++++++++++++------------------------= ---- 1 file changed, 62 insertions(+), 100 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e3881d4999..1c88539d62 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -602,13 +602,30 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +/* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). + * If SVE is not enabled, then there are only 128 bits in the vector. + */ +static void clear_vec_high(DisasContext *s, bool is_q, int rd) +{ + unsigned ofs =3D fp_reg_offset(s, rd, MO_64); + unsigned vsz =3D vec_full_reg_size(s); + + if (!is_q) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); + tcg_temp_free_i64(tcg_zero); + } + if (vsz > 16) { + tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); + } +} + static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + unsigned ofs =3D fp_reg_offset(s, reg, MO_64); =20 - tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); - tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); - tcg_temp_free_i64(tcg_zero); + tcg_gen_st_i64(v, cpu_env, ofs); + clear_vec_high(s, false, reg); } =20 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) @@ -1009,6 +1026,8 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) =20 tcg_temp_free_i64(tmplo); tcg_temp_free_i64(tmphi); + + clear_vec_high(s, true, destidx); } =20 /* @@ -1124,17 +1143,6 @@ static void write_vec_element_i32(DisasContext *s, T= CGv_i32 tcg_src, } } =20 -/* Clear the high 64 bits of a 128 bit vector (in general non-quad - * vector ops all need to do this). - */ -static void clear_vec_high(DisasContext *s, int rd) -{ - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - write_vec_element(s, tcg_zero, rd, 1, MO_64); - tcg_temp_free_i64(tcg_zero); -} - /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, TCGv_i64 tcg_addr, int size) @@ -2794,12 +2802,13 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) /* For non-quad operations, setting a slice of the low * 64 bits of the register clears the high 64 bits (in * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). We optimize - * by noticing that we only need to do this the first - * time we touch a register. + * that 'rval' is a 64 bit wide variable). + * For quad operations, we might still need to zero the + * high bits of SVE. We optimize by noticing that we = only + * need to do this the first time we touch a register. */ - if (!is_q && e =3D=3D 0 && (r =3D=3D 0 || xs =3D=3D se= lem - 1)) { - clear_vec_high(s, tt); + if (e =3D=3D 0 && (r =3D=3D 0 || xs =3D=3D selem - 1))= { + clear_vec_high(s, is_q, tt); } } tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); @@ -2942,10 +2951,9 @@ static void disas_ldst_single_struct(DisasContext *s= , uint32_t insn) write_vec_element(s, tcg_tmp, rt, 0, MO_64); if (is_q) { write_vec_element(s, tcg_tmp, rt, 1, MO_64); - } else { - clear_vec_high(s, rt); } tcg_temp_free_i64(tcg_tmp); + clear_vec_high(s, is_q, rt); } else { /* Load/store one element per register */ if (is_load) { @@ -6718,7 +6726,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, } =20 if (!is_q) { - clear_vec_high(s, rd); write_vec_element(s, tcg_final, rd, 0, MO_64); } else { write_vec_element(s, tcg_final, rd, 1, MO_64); @@ -6731,7 +6738,8 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, tcg_temp_free_i64(tcg_rd); tcg_temp_free_i32(tcg_rd_narrowed); tcg_temp_free_i64(tcg_final); - return; + + clear_vec_high(s, is_q, rd); } =20 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ @@ -6795,10 +6803,7 @@ static void handle_simd_qshl(DisasContext *s, bool s= calar, bool is_q, tcg_temp_free_i64(tcg_op); } tcg_temp_free_i64(tcg_shift); - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { TCGv_i32 tcg_shift =3D tcg_const_i32(shift); static NeonGenTwoOpEnvFn * const fns[2][2][3] =3D { @@ -6847,8 +6852,8 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, } tcg_temp_free_i32(tcg_shift); =20 - if (!is_q && !scalar) { - clear_vec_high(s, rd); + if (!scalar) { + clear_vec_high(s, is_q, rd); } } } @@ -6901,13 +6906,11 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, } } =20 - if (!is_double && elements =3D=3D 2) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_int); tcg_temp_free_ptr(tcg_fpst); tcg_temp_free_i32(tcg_shift); + + clear_vec_high(s, elements << size =3D=3D 16, rd); } =20 /* UCVTF/SCVTF - Integer to FP conversion */ @@ -6995,9 +6998,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, write_vec_element(s, tcg_op, rd, pass, MO_64); tcg_temp_free_i64(tcg_op); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { int maxpass =3D is_scalar ? 1 : is_q ? 4 : 2; for (pass =3D 0; pass < maxpass; pass++) { @@ -7016,8 +7017,8 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, } tcg_temp_free_i32(tcg_op); } - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } =20 @@ -7502,10 +7503,7 @@ static void handle_3same_float(DisasContext *s, int = size, int elements, =20 tcg_temp_free_ptr(fpst); =20 - if ((elements << size) < 4) { - /* scalar, or non-quad vector op */ - clear_vec_high(s, rd); - } + clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); } =20 /* AdvSIMD scalar three same @@ -7831,13 +7829,11 @@ static void handle_2misc_fcmp_zero(DisasContext *s,= int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_zero); tcg_temp_free_i64(tcg_op); + + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_zero =3D tcg_const_i32(0); @@ -7888,8 +7884,8 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_zero); tcg_temp_free_i32(tcg_op); - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } =20 @@ -7925,12 +7921,9 @@ static void handle_2misc_reciprocal(DisasContext *s,= int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_op); + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); @@ -7970,8 +7963,8 @@ static void handle_2misc_reciprocal(DisasContext *s, = int opcode, } tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_op); - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } tcg_temp_free_ptr(fpst); @@ -8077,9 +8070,7 @@ static void handle_2misc_narrow(DisasContext *s, bool= scalar, write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 /* Remaining saturating accumulating ops */ @@ -8104,12 +8095,9 @@ static void handle_2misc_satacc(DisasContext *s, boo= l is_scalar, bool is_u, } write_vec_element(s, tcg_rd, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_rn); + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_rn =3D tcg_temp_new_i32(); TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); @@ -8167,13 +8155,9 @@ static void handle_2misc_satacc(DisasContext *s, boo= l is_scalar, bool is_u, } write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); } - - if (!is_q) { - clear_vec_high(s, rd); - } - tcg_temp_free_i32(tcg_rd); tcg_temp_free_i32(tcg_rn); + clear_vec_high(s, is_q, rd); } } =20 @@ -8664,9 +8648,7 @@ static void handle_vec_simd_shri(DisasContext *s, boo= l is_q, bool is_u, tcg_temp_free_i64(tcg_round); =20 done: - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) @@ -8855,19 +8837,18 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, } =20 if (!is_q) { - clear_vec_high(s, rd); write_vec_element(s, tcg_final, rd, 0, MO_64); } else { write_vec_element(s, tcg_final, rd, 1, MO_64); } - if (round) { tcg_temp_free_i64(tcg_round); } tcg_temp_free_i64(tcg_rn); tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_final); - return; + + clear_vec_high(s, is_q, rd); } =20 =20 @@ -9261,9 +9242,7 @@ static void handle_3rd_narrowing(DisasContext *s, int= is_q, int is_u, int size, write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int= rm) @@ -9671,9 +9650,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 if (fpst) { @@ -10161,10 +10138,7 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) tcg_temp_free_i32(tcg_op2); } } - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 /* AdvSIMD three same @@ -10303,9 +10277,7 @@ static void handle_rev(DisasContext *s, int opcode,= bool u, write_vec_element(s, tcg_tmp, rd, i, grp_size); tcg_temp_free_i64(tcg_tmp); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { int revmask =3D (1 << grp_size) - 1; int esize =3D 8 << size; @@ -10949,9 +10921,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) tcg_temp_free_i32(tcg_op); } } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); =20 if (need_rmode) { gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); @@ -11130,11 +11100,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) tcg_temp_free_i64(tcg_res); } =20 - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_idx); + clear_vec_high(s, !is_scalar, rd); } else if (!is_long) { /* 32 bit floating point, or 16 or 32 bit integer. * For the 16 bit scalar case we use the usual Neon helpers and @@ -11238,10 +11205,7 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } =20 tcg_temp_free_i32(tcg_idx); - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { /* long ops: 16x16->32 or 32x32->64 */ TCGv_i64 tcg_res[2]; @@ -11318,9 +11282,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i64(tcg_idx); =20 - if (is_scalar) { - clear_vec_high(s, rd); - } + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_idx =3D tcg_temp_new_i32(); =20 --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518383264277255.24076770240936; Sun, 11 Feb 2018 13:07:44 -0800 (PST) Received: from localhost ([::1]:55382 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyqZ-00058P-Ci for importer@patchew.org; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.58.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:58:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4hOy7n5pJAw8G9xcz1wTKD3qCTCNW8VnLlPINSLP6eo=; b=H/XTmSCa/51fLuVRGQuxAA2INYE47ZOZBQLgdt8X1ZWapffGqT/Fwm8+K0JWDasZqn FuAAbPbKxkYoNc7mTwt01wuc8mUqlLQuzEW2s4S7Cqet44fkl7gIHzd9be2/dvc+tOHA bwpsQeKhU827STAiAPgcOY6Aqt+W3WtbAfVr4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4hOy7n5pJAw8G9xcz1wTKD3qCTCNW8VnLlPINSLP6eo=; b=S1ijMFu6eZBCHcEgs7RDkUvNyb3C0gC77Pky8PDbVc+dPKDU0u8M4f3kyNtLnZnqN7 TEYd232+XOelmtq7UKspj5Rfh2XCtPo25z1CI7b9NX6gTWDZ03e2UQ5e9G1tFkFIT6qS 0rspTDsVXzQS+ETZK13eLU8JJilbz9OBluYBSkDfh+bsVrMrPVgkEt4/4c/HG3cgy25y n77lK2/zRWugFtWS6HFoDNzzhGASqD1qjMyzGC2yJQSiWXoeQZnrNlAnAMAChKl98t/4 2nsTlNIup+mVC+x9agua+PvaLfia9/yiMAtRIYvYqDHTZPpmPGpuWv8sn+BCWNQp79X2 fj6w== X-Gm-Message-State: APf1xPBBIGrRokFobAGk17OhaRIB6axdfh+ykxkZSBOJMRD2GCisBtvv oS+SDFrB7JivrfYVbwNSbvI+L2eepkM= X-Google-Smtp-Source: AH8x225PON69tYAKPbxPOr4EKexQ7JwBHxDsQS51SMYAzGt7xXutbFZxkUNDzFC/3cWrFV8VbKajbQ== X-Received: by 10.99.115.16 with SMTP id o16mr7851778pgc.362.1518382740199; Sun, 11 Feb 2018 12:59:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:47 -0800 Message-Id: <20180211205848.4568-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 6/7] linux-user: Support SVE in aarch64 signal frames X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/signal.c | 348 ++++++++++++++++++++++++++++++++++++++++++------= ---- 1 file changed, 283 insertions(+), 65 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index 9a380b9e31..af953175db 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1443,35 +1443,61 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; =20 -/* - * Auxiliary context saved in the sigcontext.__reserved array. Not exporte= d to - * user space as it will change with the addition of new context. User spa= ce - * should check the magic/size information. - */ -struct target_aux_context { - struct target_fpsimd_context fpsimd; - /* additional context to be added before "end" */ - struct target_aarch64_ctx end; +#define TARGET_EXTRA_MAGIC 0x45585401 + +struct target_extra_context { + struct target_aarch64_ctx head; + uint64_t datap; /* 16-byte aligned pointer to extra space cast to __u6= 4 */ + uint32_t size; /* size in bytes of the extra space */ + uint32_t reserved[3]; +}; + +#define TARGET_SVE_MAGIC 0x53564501 + +struct target_sve_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; }; =20 +#define TARGET_SVE_VQ_BYTES 16 + +#define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8)) + +#define TARGET_SVE_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N)) +#define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (= N)) +#define TARGET_SVE_SIG_FFR_OFFSET(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 16)) +#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; +}; + +struct target_rt_frame_record { uint64_t fp; uint64_t lr; uint32_t tramp[2]; }; =20 -static int target_setup_sigframe(struct target_rt_sigframe *sf, - CPUARMState *env, target_sigset_t *set) +static void target_setup_general_frame(struct target_rt_sigframe *sf, + CPUARMState *env, target_sigset_t *= set) { int i; - struct target_aux_context *aux =3D - (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; =20 - /* set up the stack frame for unwinding */ - __put_user(env->xregs[29], &sf->fp); - __put_user(env->xregs[30], &sf->lr); + __put_user(0, &sf->uc.tuc_flags); + __put_user(0, &sf->uc.tuc_link); + + __put_user(target_sigaltstack_used.ss_sp, &sf->uc.tuc_stack.ss_sp); + __put_user(sas_ss_flags(env->xregs[31]), &sf->uc.tuc_stack.ss_flags); + __put_user(target_sigaltstack_used.ss_size, &sf->uc.tuc_stack.ss_size); =20 for (i =3D 0; i < 31; i++) { __put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]); @@ -1485,39 +1511,79 @@ static int target_setup_sigframe(struct target_rt_s= igframe *sf, for (i =3D 0; i < TARGET_NSIG_WORDS; i++) { __put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]); } +} + +static void target_setup_end_record(struct target_aarch64_ctx *end) +{ + __put_user(0, &end->magic); + __put_user(0, &end->size); +} + +static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsim= d, + CPUARMState *env) +{ + int i; + + __put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic); + __put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size); + __put_user(vfp_get_fpsr(env), &fpsimd->fpsr); + __put_user(vfp_get_fpcr(env), &fpsimd->fpcr); =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); - __put_user(q[1], &aux->fpsimd.vregs[i * 2]); + __put_user(q[0], &fpsimd->vregs[i * 2 + 1]); + __put_user(q[1], &fpsimd->vregs[i * 2]); #else - __put_user(q[0], &aux->fpsimd.vregs[i * 2]); - __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[0], &fpsimd->vregs[i * 2]); + __put_user(q[1], &fpsimd->vregs[i * 2 + 1]); #endif } - __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr); - __put_user(vfp_get_fpcr(env), &aux->fpsimd.fpcr); - __put_user(TARGET_FPSIMD_MAGIC, &aux->fpsimd.head.magic); - __put_user(sizeof(struct target_fpsimd_context), - &aux->fpsimd.head.size); +} =20 - /* set the "end" magic */ - __put_user(0, &aux->end.magic); - __put_user(0, &aux->end.size); +static void target_setup_extra_record(struct target_extra_context *extra, + uint64_t datap, uint32_t extra_size) +{ + __put_user(TARGET_EXTRA_MAGIC, &extra->head.magic); + __put_user(sizeof(struct target_extra_context), &extra->head.size); + __put_user(datap, &extra->datap); + __put_user(extra_size, &extra->size); +} =20 - return 0; +static void target_setup_sve_record(struct target_sve_context *sve, + CPUARMState *env, int vq, int size) +{ + int i, j; + + __put_user(TARGET_SVE_MAGIC, &sve->head.magic); + __put_user(size, &sve->head.size); + __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + + /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + * at a subsequent address. This corresponds to a little-endian store + * of our 64-bit hunks. + */ + for (i =3D 0; i < 32; ++i) { + uint64_t *z =3D (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __put_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i =3D 0; i <=3D 16; ++i) { + uint16_t *p =3D (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j =3D 0; j < vq; ++j) { + uint64_t r =3D env->vfp.pregs[i].p[j >> 2]; + __put_user_e(r >> ((j & 3) * 16), p + j, le); + } + } } =20 -static int target_restore_sigframe(CPUARMState *env, - struct target_rt_sigframe *sf) +static void target_restore_general_frame(CPUARMState *env, + struct target_rt_sigframe *sf) { sigset_t set; - int i; - struct target_aux_context *aux =3D - (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; - uint32_t magic, size, fpsr, fpcr; uint64_t pstate; + int i; =20 target_to_host_sigset(&set, &sf->uc.tuc_sigmask); set_sigmask(&set); @@ -1530,34 +1596,134 @@ static int target_restore_sigframe(CPUARMState *en= v, __get_user(env->pc, &sf->uc.tuc_mcontext.pc); __get_user(pstate, &sf->uc.tuc_mcontext.pstate); pstate_write(env, pstate); +} =20 - __get_user(magic, &aux->fpsimd.head.magic); - __get_user(size, &aux->fpsimd.head.size); +static void target_restore_fpsimd_record(CPUARMState *env, + struct target_fpsimd_context *fps= imd) +{ + uint32_t fpsr, fpcr; + int i; =20 - if (magic !=3D TARGET_FPSIMD_MAGIC - || size !=3D sizeof(struct target_fpsimd_context)) { - return 1; - } + __get_user(fpsr, &fpsimd->fpsr); + vfp_set_fpsr(env, fpsr); + __get_user(fpcr, &fpsimd->fpcr); + vfp_set_fpcr(env, fpcr); =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __get_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); - __get_user(q[1], &aux->fpsimd.vregs[i * 2]); + __get_user(q[0], &fpsimd->vregs[i * 2 + 1]); + __get_user(q[1], &fpsimd->vregs[i * 2]); #else - __get_user(q[0], &aux->fpsimd.vregs[i * 2]); - __get_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[0], &fpsimd->vregs[i * 2]); + __get_user(q[1], &fpsimd->vregs[i * 2 + 1]); #endif } - __get_user(fpsr, &aux->fpsimd.fpsr); - vfp_set_fpsr(env, fpsr); - __get_user(fpcr, &aux->fpsimd.fpcr); - vfp_set_fpcr(env, fpcr); +} + +static void target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, int = vq) +{ + int i, j; + + /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + * at a subsequent address. This corresponds to a little-endian store + * of our 64-bit hunks. + */ + for (i =3D 0; i < 32; ++i) { + uint64_t *z =3D (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __get_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i =3D 0; i <=3D 16; ++i) { + uint16_t *p =3D (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j =3D 0; j < vq; ++j) { + uint16_t r; + __get_user_e(r, p + j, le); + if (j & 3) { + env->vfp.pregs[i].p[j >> 2] |=3D (uint64_t)r << ((j & 3) *= 16); + } else { + env->vfp.pregs[i].p[j >> 2] =3D r; + } + } + } +} + +static int target_restore_sigframe(CPUARMState *env, + struct target_rt_sigframe *sf) +{ + struct target_aarch64_ctx *ctx, *extra =3D NULL; + struct target_fpsimd_context *fpsimd =3D NULL; + struct target_sve_context *sve =3D NULL; + int vq =3D 0, sve_size =3D 0; + + target_restore_general_frame(env, sf); + + ctx =3D (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved; + while (ctx) { + uint32_t magic, size; + + __get_user(magic, &ctx->magic); + __get_user(size, &ctx->size); + switch (magic) { + case TARGET_FPSIMD_MAGIC: + if (fpsimd || size !=3D sizeof(struct target_fpsimd_context)) { + return 1; + } + fpsimd =3D (struct target_fpsimd_context *)ctx; + break; + + case TARGET_SVE_MAGIC: + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); + if (!sve && size =3D=3D sve_size) { + sve =3D (struct target_sve_context *)ctx; + break; + } + } + return 1; + + case TARGET_EXTRA_MAGIC: + if (size !=3D sizeof(struct target_extra_context)) { + return 1; + } + extra =3D (void *)((struct target_extra_context *)ctx)->datap; + break; + + default: + /* Unknown record -- we certainly didn't generate it. + Did we in fact get out of sync? */ + return 1; + + case 0: + if (size !=3D 0) { + return 1; + } + ctx =3D extra; + extra =3D NULL; + continue; + } + ctx =3D (void *)ctx + size; + } + + /* Require FPSIMD always, since we always restore FPSR/FPCR from there= . */ + if (!fpsimd) { + return 1; + } + target_restore_fpsimd_record(env, fpsimd); + + /* SVE data, if present, overwrites FPSIMD data. */ + if (sve) { + target_restore_sve_record(env, sve, vq); + } =20 return 0; } =20 -static abi_ulong get_sigframe(struct target_sigaction *ka, CPUARMState *en= v) +static abi_ulong get_sigframe(struct target_sigaction *ka, + CPUARMState *env, int size) { abi_ulong sp; =20 @@ -1570,7 +1736,7 @@ static abi_ulong get_sigframe(struct target_sigaction= *ka, CPUARMState *env) sp =3D target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_= size; } =20 - sp =3D (sp - sizeof(struct target_rt_sigframe)) & ~15; + sp =3D (sp - size) & ~15; =20 return sp; } @@ -1579,25 +1745,76 @@ static void target_setup_frame(int usig, struct tar= get_sigaction *ka, target_siginfo_t *info, target_sigset_t *se= t, CPUARMState *env) { + int std_size =3D sizeof(struct target_rt_sigframe); + int size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__res= erved); + int fpsimd_ofs, end1_ofs, fr_ofs; + int sve_ofs =3D 0, extra_ofs =3D 0, end2_ofs =3D 0; + int vq =3D 0, sve_size =3D 0, extra_size =3D 0; struct target_rt_sigframe *frame; + struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; =20 - frame_addr =3D get_sigframe(ka, env); + /* Reserve space for standard exit marker. */ + std_size -=3D sizeof(struct target_aarch64_ctx); + + /* FPSIMD record is always in the standard space. */ + fpsimd_ofs =3D size; + size +=3D sizeof(struct target_fpsimd_context); + end1_ofs =3D size; + + /* SVE state needs saving only if it exists. */ + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + + /* For VQ <=3D 6, there is room in the standard space. */ + if (sve_size <=3D std_size) { + sve_ofs =3D size; + size +=3D sve_size; + end1_ofs =3D size; + } else { + /* Otherwise we need to allocate extra space. */ + extra_ofs =3D size; + size +=3D sizeof(struct target_extra_context); + end1_ofs =3D size; + size +=3D QEMU_ALIGN_UP(sizeof(struct target_aarch64_ctx), 16); + + extra_size =3D sve_size + sizeof(struct target_aarch64_ctx); + sve_ofs =3D size; + size +=3D sve_size; + end2_ofs =3D size; + } + } + size +=3D sizeof(struct target_aarch64_ctx); + + fr_ofs =3D size; + size +=3D sizeof(struct target_rt_frame_record); + + frame_addr =3D get_sigframe(ka, env, size); trace_user_setup_frame(env, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv; } =20 - __put_user(0, &frame->uc.tuc_flags); - __put_user(0, &frame->uc.tuc_link); + target_setup_general_frame(frame, env, set); + target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); + if (extra_ofs) { + target_setup_extra_record((void *)frame + extra_ofs, + frame_addr + sve_ofs, extra_size); + } + target_setup_end_record((void *)frame + end1_ofs); + if (sve_ofs) { + target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size= ); + } + if (end2_ofs) { + target_setup_end_record((void *)frame + end2_ofs); + } + + /* set up the stack frame for unwinding */ + fr =3D (void *)frame + fr_ofs; + __put_user(env->xregs[29], &fr->fp); + __put_user(env->xregs[30], &fr->lr); =20 - __put_user(target_sigaltstack_used.ss_sp, - &frame->uc.tuc_stack.ss_sp); - __put_user(sas_ss_flags(env->xregs[31]), - &frame->uc.tuc_stack.ss_flags); - __put_user(target_sigaltstack_used.ss_size, - &frame->uc.tuc_stack.ss_size); - target_setup_sigframe(frame, env, set); if (ka->sa_flags & TARGET_SA_RESTORER) { return_addr =3D ka->sa_restorer; } else { @@ -1606,13 +1823,14 @@ static void target_setup_frame(int usig, struct tar= get_sigaction *ka, * Since these are instructions they need to be put as little-endi= an * regardless of target default or current CPU endianness. */ - __put_user_e(0xd2801168, &frame->tramp[0], le); - __put_user_e(0xd4000001, &frame->tramp[1], le); - return_addr =3D frame_addr + offsetof(struct target_rt_sigframe, t= ramp); + __put_user_e(0xd2801168, &fr->tramp[0], le); + __put_user_e(0xd4000001, &fr->tramp[1], le); + return_addr =3D frame_addr + fr_ofs + + offsetof(struct target_rt_frame_record, tramp); } env->xregs[0] =3D usig; env->xregs[31] =3D frame_addr; - env->xregs[29] =3D env->xregs[31] + offsetof(struct target_rt_sigframe= , fp); + env->xregs[29] =3D frame_addr + fr_ofs; env->pc =3D ka->_sa_handler; env->xregs[30] =3D return_addr; if (info) { --=20 2.14.3 From nobody Sat Apr 27 21:24:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518383254324834.0940459549721; Sun, 11 Feb 2018 13:07:34 -0800 (PST) Received: from localhost ([::1]:55380 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekyqR-00051d-6m for importer@patchew.org; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.59.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:59:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XNE6HRogROpjH970mSZvci6V/G9pwgU/mAd5NppeIP0=; b=Ay9geIMU7SCGT2QjCa77oVuAxxIqykoEwuHiZ1b8TQsyySc7FR/3P6IQ9BKnnIsAkA H8DZT3nSvg8G2+0QH1MfLl0PvSt7cVzYyDZGTA/z+xvCaLNEj5C/4WhMV/MiftwUZV9t tt/nsK+bey9EJg7+ILTE/kn4zFbQVXw8iXqho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XNE6HRogROpjH970mSZvci6V/G9pwgU/mAd5NppeIP0=; b=cs5lNd84yVYXtn+BxkI7J9tGpJgk1v9NG8EMgz8eaB/m+Z6NxZPsi/eAZB5gwh9xRx Tzke039aofGXm0EVKl/GubgbtBXDtOLuo4Kzhs/1TIReDGxmQpzXMSYDmAGt4Qd8POzF 4tTnew8UKtSx0Fwk17g0ppRuvD85dE/8qhKtOlh9i3B0CIaWOecavOsoL9XXp9XXGVH2 csnN7l63sMnkpkssrz3cg+o+9cfrOP92c14PuCU15TuvrFLJUjB3Z6RSybwdTufz7Tw5 VbKp1XTlRBHXMt5RLyBQe5vt35GQzU2dgV9VFyKmAF+RmH+kNIdxUkwiXKl5rhGj8hlE kkeg== X-Gm-Message-State: APf1xPAIpY3tKTRlOwjeV4li3N4jgfZ5XgHwPfSFwwsBiD3/V5XO07rY ynAVidxk5jUZcBGUQ2WUdAURtI3BVtI= X-Google-Smtp-Source: AH8x224Vp1EA7bd2DItVGeElKXkoCfEU6wEsFDbiOI+0M1q1UvEvzpWbywmImRgiDsYHXnLuuqwywA== X-Received: by 2002:a17:902:7297:: with SMTP id d23-v6mr2607507pll.417.1518382741763; Sun, 11 Feb 2018 12:59:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:48 -0800 Message-Id: <20180211205848.4568-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 7/7] linux-user: Implement aarch64 PR_SVE_SET/GET_VL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ linux-user/syscall.c | 20 +++++++++++++++++ target/arm/cpu64.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 83 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 51a3e16275..8e1016cfd6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -842,6 +842,8 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, C= PUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +unsigned aarch64_get_sve_vlen(CPUARMState *env); +unsigned aarch64_set_sve_vlen(CPUARMState *env, unsigned vlen); #endif =20 target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 82b35a6bdf..4840bf502f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10659,6 +10659,26 @@ abi_long do_syscall(void *cpu_env, int num, abi_lo= ng arg1, break; } #endif +#ifdef TARGET_AARCH64 + case 50: /* PR_SVE_SET_VL */ + /* We cannot support either PR_SVE_SET_VL_ONEXEC + or PR_SVE_VL_INHERIT. Therefore, anything above + ARM_MAX_VQ results in EINVAL. */ + if (!arm_feature(cpu_env, ARM_FEATURE_SVE) + || arg2 > ARM_MAX_VQ * 16 || arg2 & 15) { + ret =3D -TARGET_EINVAL; + } else { + ret =3D aarch64_set_sve_vlen(cpu_env, arg2); + } + break; + case 51: /* PR_SVE_GET_VL */ + if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { + ret =3D aarch64_get_sve_vlen(cpu_env); + } else { + ret =3D -TARGET_EINVAL; + } + break; +#endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: /* Disable seccomp to prevent the target disabling syscalls we diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..6dee78f006 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,3 +363,64 @@ static void aarch64_cpu_register_types(void) } =20 type_init(aarch64_cpu_register_types) + +/* Return the current cumulative SVE VLEN. */ +unsigned aarch64_get_sve_vlen(CPUARMState *env) +{ + return ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; +} + +/* Set the cumulative ZCR.EL to VLEN, or the nearest supported value. + Return the new value. */ +unsigned aarch64_set_sve_vlen(CPUARMState *env, unsigned vl) +{ + unsigned vq =3D vl / 16; + unsigned old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + + if (vq < 1) { + vq =3D 1; + } else if (vq > ARM_MAX_VQ) { + vq =3D ARM_MAX_VQ; + } + env->vfp.zcr_el[1] =3D vq - 1; + + /* The manual sez that when SVE is enabled and VL is widened the + * implementation is allowed to zero the previously inaccessible + * portion of the registers. The corollary to that is that when + * SVE is enabled and VL is narrowed we are also allowed to zero + * the now inaccessible portion of the registers. + * + * The intent of this is that no predicate bit beyond VL is ever set. + * Which means that some operations on predicate registers themselves + * may operate on full uint64_t or even unrolled across the maximum + * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally + * may well be cheaper than conditionals to restrict to the operation + * to the relevant portion of a uint16_t[16]. + * + * ??? Need to move this somewhere else, so that it applies to + * changes to the real system registers and EL state changes. + */ + if (vq < old_vq) { + unsigned i, j; + uint64_t pmask; + + /* Zap the high bits of the zregs. */ + for (i =3D 0; i < 32; i++) { + memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)= ); + } + + /* Zap the high bits of the pregs and ffr. */ + pmask =3D 0; + if (vq & 3) { + pmask =3D ~(-1ULL << (16 * (vq & 3))); + } + for (j =3D vq / 4; j < ARM_MAX_VQ / 4; j++) { + for (i =3D 0; i < 17; ++i) { + env->vfp.pregs[i].p[j] &=3D pmask; + } + pmask =3D 0; + } + } + + return vq * 16; +} --=20 2.14.3