From nobody Fri May 3 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518304083155970.9798016968197; Sat, 10 Feb 2018 15:08:03 -0800 (PST) Received: from localhost ([::1]:45838 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeFU-0007tH-0Q for importer@patchew.org; Sat, 10 Feb 2018 18:08:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDC-0006Tf-Fb for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDA-00081t-F9 for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:38 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDA-00080z-4o for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:36 -0500 Received: by mail-pg0-x243.google.com with SMTP id o13so5479854pgs.2 for ; Sat, 10 Feb 2018 15:05:36 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g3DEJfoYnA4ZEKPBUJIKJiCt3e/U1XrQnB4yUIPoJVs=; b=f9/SLfeLlcQnt6SOD/c5sH6VcE8OeLdHWazaEEKneO1VuE+CBB08f+KW2CTKl8dH9E MT/jZuU+5scYueJjHij5l1lcAWp7j3ASl3+0baNdKA410kzaHDMA8wDL72XTZGPLBtY3 bDET9WIjjAINhqFz/5oE2yVUtCtJN4bnSfBIU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g3DEJfoYnA4ZEKPBUJIKJiCt3e/U1XrQnB4yUIPoJVs=; b=BjGdKGA8sgaSGteLnlIsERIjjh5IRSwwzNGVWRoIp6j5yDgatKcehGSHaMSOka/6Wc AL2mFX6usoBYhofwKYgqdiS64wiTc3TtQ/pgUBekn6n9cpEfglucrInrWsXpJOPhWVmv TDmpbh6Wm6ErJmW5x7c3UuJ0w9AhtQR90Rf331vtGu1JUMremDp9vkCyAP/uxh0gogMZ KLDh49sA7GTgreZjADlAEXbQiTlBjCVpHgv2ZvAKkJH+XYIxUAGMrtQf3R7n1aX1xUcM 33wQx/pw4H70J8iI/gW83viQqSpaOz6uTvfM/kx9ZjWxqmZJt0pf/d+ZzPDIqXjEuoNV W21w== X-Gm-Message-State: APf1xPCyQVHjpTX+lN4jfPozbP1LoIV3GGGzGnDzfeTfPcbJB4kic8Zt lfQ198CFo+tWenEy52aS90UL5bjnBro= X-Google-Smtp-Source: AH8x224D578MuHgl+oPR+Qxyxk9GHwKC3jzvHkmuzTucUxm55wlL/enDRl5Hue0mhf4L6vYtQvNVvA== X-Received: by 10.99.186.73 with SMTP id l9mr3060866pgu.83.1518303934793; Sat, 10 Feb 2018 15:05:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:26 -0800 Message-Id: <20180210230530.8421-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 1/5] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 180ab75458..4b102ec356 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4357,7 +4357,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL1_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4365,7 +4365,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL2_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4373,14 +4373,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT, + .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .access =3D PL3_RW, .accessfn =3D zcr_access, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; --=20 2.14.3 From nobody Fri May 3 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518304095074582.4906014845897; Sat, 10 Feb 2018 15:08:15 -0800 (PST) Received: from localhost ([::1]:45845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeFe-00082a-VR for importer@patchew.org; Sat, 10 Feb 2018 18:08:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDE-0006VW-Ba for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDB-00083y-QS for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:40 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:40696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDB-000833-Jv for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:37 -0500 Received: by mail-pg0-x244.google.com with SMTP id g2so5473717pgn.7 for ; Sat, 10 Feb 2018 15:05:37 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=CoWOskR625v8onaamWjTOW47R45NzFqwOH/2bNk7Mgi1DcD7yMItWxnXtQGYPdB/rO qkNVbEeesIYZ6tEk9xQjHORB84mYNjL9pzCe7pFWhS/AsGkQNGQrWG1jzjU9PJbXejKB BGbZyKfVU+oaTvE18Z31xgBQojG5EUo3nW7v0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=hT99sFP2yMXdVA4z9AndTnQkFHgzkDCI7uCsNkaFcKUNy7uXV6cfkBEX2h89mbTVv0 iXJ87Hgwk3SOhlx+ocSB3p/qivMAV476szdFTqyuXqSYQlNzUoYrlbawSzk2Y7df1sv6 s0i870Z6IzJDwS5x5A05shttvh4O3kdXn4bslCzd+Lxi76DlouC3dgD4OL+uHEQXMN0U PKJCmpmJfayevaRTYbYB8uFIWyYnzA6MCSDm1/0YAQIzqE5TlAGkp7a/rdCRe+tM/8yL mLw1sqAODFFD8YLPsXCXyGpPLNZy368Wq6nteLbeiWGZvy/9p0SGjaGATo8a1cst1QYp H+Nw== X-Gm-Message-State: APf1xPBdlpRfHiKd7Bgx5WQLTHM/Ml+JHU3rRidpnQIVL+EpzpHwN65l hdY1/iYetxXxVwNyGqT/pUBUtBLoKSs= X-Google-Smtp-Source: AH8x224akJm/UDgpo8uqmBHhROyHQNO1IJNPB0DHCnoa/uHLrN0zgLEdHMOksVDeXUm8fZ8K6Ptdtw== X-Received: by 10.99.110.3 with SMTP id j3mr5883490pgc.85.1518303936259; Sat, 10 Feb 2018 15:05:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:27 -0800 Message-Id: <20180210230530.8421-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 2/5] target/arm: Enforce FP access to FPCR/FPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 ++++++++++++++++++----------------- target/arm/helper.c | 6 ++++-- target/arm/translate-a64.c | 3 +++ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 521444a5a1..e966a57f8a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1714,7 +1714,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) } =20 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [15..8] indicate what behaviour + * special-behaviour cp reg and bits [11..8] indicate what behaviour * it has. Otherwise it is a simple cp reg, where CONST indicates that * TCG can assume the value to be constant (ie load at translate time) * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END @@ -1735,24 +1735,25 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_FPU 0x1000 /* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xffff +#define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0xff +#define ARM_CP_FLAG_MASK 0x10ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index 4b102ec356..d41fb8371f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3356,10 +3356,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fp= cr_write }, + .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fp= sr_write }, + .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fb1a4cb532..89f50558a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1631,6 +1631,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: break; } + if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + return; + } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { gen_io_start(); --=20 2.14.3 From nobody Fri May 3 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518304239177424.52368460266416; Sat, 10 Feb 2018 15:10:39 -0800 (PST) Received: from localhost ([::1]:46039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeI2-0001eZ-Cx for importer@patchew.org; Sat, 10 Feb 2018 18:10:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDF-0006WV-5X for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDD-000864-3r for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:41 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:42647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDC-00084d-TK for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:39 -0500 Received: by mail-pg0-x244.google.com with SMTP id m28so5476354pgc.9 for ; Sat, 10 Feb 2018 15:05:38 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nL6gPUlDY152kgVDfEyFrw2bQqSTgTyjJgXC6doQ4ns=; b=J++wUl1mkqmg1ABHuTnPIu5s2IrBMHnmGDWB8GUUo2Af2zjvXOmKyXATr3FZCRJ2tR fHBQ7xYkbj89ABEBdlzIBssjiawMRl4G+NFWpzSsSREu7KWhFWEPeiOQu+vfyjy/TIn5 KNGnOBQrpjO2zDunFZmWIW2yKe0EkSnQoeH3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nL6gPUlDY152kgVDfEyFrw2bQqSTgTyjJgXC6doQ4ns=; b=mxoODPNPLywq2Yk5Z/hitIYilkV0zJF694j+ls7Iro1IIlUgt6nz3vM3iDDW1HVPAV m5P8RDIVCg8J1PUZy6A2sTz0oZcUYkv0POBIdN21BmKki+i3g7sssGtCEqHmaemgDJbe bI934bwnjaRs1AxPzJXw0snXmRLqekb38RHXKmqXsAwwgez+A332G8qgNjR9St+VGQKa uzVvisU2uqgO1RfhV1sW10NexPx+fco8MoKhrIAkQqlerU1gjVsXotMYK+8bLbf0CA12 XjWOMw5btLZ4xb81+dFKFEKgEXe82ksQFk8VLBNP8M/h3yQbqjG0nRQWRnO6h4mZ/+eF BW+g== X-Gm-Message-State: APf1xPCznZq1uGSdWWnMAf+3SSFSxVUZkMSSk+gIsRfsmEh50GDRITFo PK3Znf1V/5CSw0nK9OTOdRRrY0khvrw= X-Google-Smtp-Source: AH8x224KUh34REYkT1VlvHDvIFjGXvpKD00878L9+mqLQS5FQghhz/qxuxrvFHuC4opQpXhUgUNe5g== X-Received: by 10.99.113.11 with SMTP id m11mr5916701pgc.57.1518303937698; Sat, 10 Feb 2018 15:05:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:28 -0800 Message-Id: <20180210230530.8421-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 3/5] target/arm: Suppress TB end for FPCR/FPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Nothing in either register affects the TB. Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d41fb8371f..e0184c7162 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3356,11 +3356,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, --=20 2.14.3 From nobody Fri May 3 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518304259699343.31614448329526; Sat, 10 Feb 2018 15:10:59 -0800 (PST) Received: from localhost ([::1]:46056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeIM-0001w2-QI for importer@patchew.org; Sat, 10 Feb 2018 18:10:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58655) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDH-0006a8-Oq for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDE-00088k-K3 for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:43 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:46488) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDE-000874-7R for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:40 -0500 Received: by mail-pf0-x244.google.com with SMTP id z79so2675404pff.13 for ; Sat, 10 Feb 2018 15:05:40 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u9SJZsEYOcc3Fv1vUr4knqPF5dvb+F9pFsuL2qHHgwA=; b=MnYQgg4tjq4xVGN8vHjFa6v94oM7FNOFnkcm1AYLgTzLWAyywxFp/4u/H/biDClOw8 syHQ2dUZpHTnKKubX3MKn+V6lmnFlP21RDHCArWvUXR8NNwq6EMEP3O5m0mLzawxsEkC +oXaTP39SppjPBxaViC7i2uoxMnzeTPfHO1Mc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u9SJZsEYOcc3Fv1vUr4knqPF5dvb+F9pFsuL2qHHgwA=; b=ZtyLFXrjKFTZSVNIfIq3EWLO0drDrzbxsOd8yOyfwuKFjaciVMKLnDX1Lf+w6xTpYI TT3j8mw2UfdvEb6xECOSg1qz9L/6CCEyoHRXrazUmj9uy4YuQOqPPqgo0YNGMkLcE3m9 q/+89TFcZ/UzeAOMiO3HQ9h+tJFDSGx1lq8/a2vO0DZsCK+Rae+fwqQFlZs2sYcEPuyQ 5BlMDcpBCbpHuupBw/B79yMsttOv+zjqvbkmJxRmveJdp1eMkFrkRzv4mGfB3Qd1kJTF 8e0GNQgI3ku7SraJh7p0fBK0M2j/5vHU00jfnL+fqGC37VlBpI4cAPT9pt6UwFL9+DLK J0Uw== X-Gm-Message-State: APf1xPDyMcnYfb9OJvg3HNlpVG8pMUYEXRLE+uCcewkLA7+ijdqZegMp 3Q2BSZ6X6HUMNWRgAJ6MOhza9j127fI= X-Google-Smtp-Source: AH8x227uieApZO31HYepA9CpcRSv8Fj2R5HOUBm3KFfAkY5td7y/jtiMvdMyHQA8AEUuAIBR8kh5mg== X-Received: by 10.101.77.140 with SMTP id p12mr5786154pgq.195.1518303938865; Sat, 10 Feb 2018 15:05:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:29 -0800 Message-Id: <20180210230530.8421-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 4/5] target/arm: Enforce access to ZCR_EL at translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 22 ++++------------------ target/arm/translate-a64.c | 16 ++++++++++++++++ 4 files changed, 28 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e966a57f8a..51a3e16275 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1750,10 +1750,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x10ff +#define ARM_CP_FLAG_MASK 0x30ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/internals.h b/target/arm/internals.h index 89f5d2fe12..47cc224a46 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -243,6 +243,7 @@ enum arm_exception_class { EC_AA64_HVC =3D 0x16, EC_AA64_SMC =3D 0x17, EC_SYSTEMREGISTERTRAP =3D 0x18, + EC_SVEACCESSTRAP =3D 0x19, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -381,6 +382,11 @@ static inline uint32_t syn_fp_access_trap(int cv, int = cond, bool is_16bit) | (cv << 24) | (cond << 20); } =20 +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/helper.c b/target/arm/helper.c index e0184c7162..550dc3d290 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4335,20 +4335,6 @@ static int sve_exception_el(CPUARMState *env) return 0; } =20 -static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - switch (sve_exception_el(env)) { - case 3: - return CP_ACCESS_TRAP_EL3; - case 2: - return CP_ACCESS_TRAP_EL2; - case 1: - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4359,7 +4345,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D zcr_access, + .access =3D PL1_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4367,7 +4353,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D zcr_access, + .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4375,14 +4361,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, + .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .accessfn =3D zcr_access, + .access =3D PL3_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 89f50558a7..e3881d4999 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1182,6 +1182,19 @@ static inline bool fp_access_check(DisasContext *s) return false; } =20 +/* Check that SVE access is enabled. If it is, return true. + * If not, emit code to generate an appropriate exception and return false. + */ +static inline bool sve_access_check(DisasContext *s) +{ + if (s->sve_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(), + s->sve_excp_el); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -1631,6 +1644,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: break; } + if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; + } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; } --=20 2.14.3 From nobody Fri May 3 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518304373580502.40881345972446; Sat, 10 Feb 2018 15:12:53 -0800 (PST) Received: from localhost ([::1]:46306 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeKC-0003SX-Ki for importer@patchew.org; Sat, 10 Feb 2018 18:12:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDL-0006eW-W3 for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDG-0008Aa-3Y for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:47 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:32944) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDF-00089L-O5 for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:41 -0500 Received: by mail-pg0-x241.google.com with SMTP id u1so5488643pgr.0 for ; Sat, 10 Feb 2018 15:05:41 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0RZ/Dwu85IRJts+xxg49wprCBup0YeyQq2OHAWxr7S4=; b=jEnZiYXJB+t/RICbmVxBMRr8hio7Zzfw+/NhrIkVATu/DRFlXLMaKbv19Scz+6+/7j pD7uFIkeOikmQO2KUa+m0kU6VNJfzbTlzItpZoJM6k35CysQGSUp2aWk+B71ofdHZl3Y Cu3UY0RclRVfPKPS2wCSGwomYk6K5E0crj9wE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0RZ/Dwu85IRJts+xxg49wprCBup0YeyQq2OHAWxr7S4=; b=CF3zHwOnY5kxLSDkwa+NTS8RMuEIEnrWKEP1wv+hGMlhboYEbQ3tdOC8uMDg8mnH2C tX8GYIT3RtbHjIfdo6phXXA5m31owk0urVej6ai7/fCHlbXkEZJnPHSvNZE5AB75bn6s DO6SxKWYGdq+TCHh9FJ6wQ2oB929pFZnoAPyyWZe6/FLuGDEtMLhb8pGr3XemnUuqmjw bN6tZ5WsQ670LbGiDcGZELHkTEaKLmEC/AfZUF+YoBqDnS/38V4vupPPCIb11K+p94r/ bmluUSpAPaPAcEDGue0ZtitwuiBXVq8epkvH0kr12y61cdWlV5V/NxAcaz8wZnlBnjZr eX0A== X-Gm-Message-State: APf1xPDby8Ej6WaJm3KwQrtalkwgqRDWO2dWFm7IGTEwNejuEbB5BN9f hk7hs0hIgbhmInMWZADNZ3yotz8f19A= X-Google-Smtp-Source: AH8x224GIuMB/hrMHrliUfJ7xxs0xFLcMt0W84ZHnj/0F8Ku9Sb4Hozqp3mYh7Bh7KjeRXWLdJCQqA== X-Received: by 10.101.71.129 with SMTP id e1mr5865207pgs.430.1518303940329; Sat, 10 Feb 2018 15:05:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:30 -0800 Message-Id: <20180210230530.8421-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 5/5] target/arm: Handle SVE registers when using clear_vec_high X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 162 +++++++++++++++++------------------------= ---- 1 file changed, 62 insertions(+), 100 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e3881d4999..1c88539d62 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -602,13 +602,30 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +/* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). + * If SVE is not enabled, then there are only 128 bits in the vector. + */ +static void clear_vec_high(DisasContext *s, bool is_q, int rd) +{ + unsigned ofs =3D fp_reg_offset(s, rd, MO_64); + unsigned vsz =3D vec_full_reg_size(s); + + if (!is_q) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); + tcg_temp_free_i64(tcg_zero); + } + if (vsz > 16) { + tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); + } +} + static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + unsigned ofs =3D fp_reg_offset(s, reg, MO_64); =20 - tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); - tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); - tcg_temp_free_i64(tcg_zero); + tcg_gen_st_i64(v, cpu_env, ofs); + clear_vec_high(s, false, reg); } =20 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) @@ -1009,6 +1026,8 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) =20 tcg_temp_free_i64(tmplo); tcg_temp_free_i64(tmphi); + + clear_vec_high(s, true, destidx); } =20 /* @@ -1124,17 +1143,6 @@ static void write_vec_element_i32(DisasContext *s, T= CGv_i32 tcg_src, } } =20 -/* Clear the high 64 bits of a 128 bit vector (in general non-quad - * vector ops all need to do this). - */ -static void clear_vec_high(DisasContext *s, int rd) -{ - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - write_vec_element(s, tcg_zero, rd, 1, MO_64); - tcg_temp_free_i64(tcg_zero); -} - /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, TCGv_i64 tcg_addr, int size) @@ -2794,12 +2802,13 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) /* For non-quad operations, setting a slice of the low * 64 bits of the register clears the high 64 bits (in * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). We optimize - * by noticing that we only need to do this the first - * time we touch a register. + * that 'rval' is a 64 bit wide variable). + * For quad operations, we might still need to zero the + * high bits of SVE. We optimize by noticing that we = only + * need to do this the first time we touch a register. */ - if (!is_q && e =3D=3D 0 && (r =3D=3D 0 || xs =3D=3D se= lem - 1)) { - clear_vec_high(s, tt); + if (e =3D=3D 0 && (r =3D=3D 0 || xs =3D=3D selem - 1))= { + clear_vec_high(s, is_q, tt); } } tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); @@ -2942,10 +2951,9 @@ static void disas_ldst_single_struct(DisasContext *s= , uint32_t insn) write_vec_element(s, tcg_tmp, rt, 0, MO_64); if (is_q) { write_vec_element(s, tcg_tmp, rt, 1, MO_64); - } else { - clear_vec_high(s, rt); } tcg_temp_free_i64(tcg_tmp); + clear_vec_high(s, is_q, rt); } else { /* Load/store one element per register */ if (is_load) { @@ -6718,7 +6726,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, } =20 if (!is_q) { - clear_vec_high(s, rd); write_vec_element(s, tcg_final, rd, 0, MO_64); } else { write_vec_element(s, tcg_final, rd, 1, MO_64); @@ -6731,7 +6738,8 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, tcg_temp_free_i64(tcg_rd); tcg_temp_free_i32(tcg_rd_narrowed); tcg_temp_free_i64(tcg_final); - return; + + clear_vec_high(s, is_q, rd); } =20 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ @@ -6795,10 +6803,7 @@ static void handle_simd_qshl(DisasContext *s, bool s= calar, bool is_q, tcg_temp_free_i64(tcg_op); } tcg_temp_free_i64(tcg_shift); - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { TCGv_i32 tcg_shift =3D tcg_const_i32(shift); static NeonGenTwoOpEnvFn * const fns[2][2][3] =3D { @@ -6847,8 +6852,8 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, } tcg_temp_free_i32(tcg_shift); =20 - if (!is_q && !scalar) { - clear_vec_high(s, rd); + if (!scalar) { + clear_vec_high(s, is_q, rd); } } } @@ -6901,13 +6906,11 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, } } =20 - if (!is_double && elements =3D=3D 2) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_int); tcg_temp_free_ptr(tcg_fpst); tcg_temp_free_i32(tcg_shift); + + clear_vec_high(s, elements << size =3D=3D 16, rd); } =20 /* UCVTF/SCVTF - Integer to FP conversion */ @@ -6995,9 +6998,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, write_vec_element(s, tcg_op, rd, pass, MO_64); tcg_temp_free_i64(tcg_op); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { int maxpass =3D is_scalar ? 1 : is_q ? 4 : 2; for (pass =3D 0; pass < maxpass; pass++) { @@ -7016,8 +7017,8 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, } tcg_temp_free_i32(tcg_op); } - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } =20 @@ -7502,10 +7503,7 @@ static void handle_3same_float(DisasContext *s, int = size, int elements, =20 tcg_temp_free_ptr(fpst); =20 - if ((elements << size) < 4) { - /* scalar, or non-quad vector op */ - clear_vec_high(s, rd); - } + clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); } =20 /* AdvSIMD scalar three same @@ -7831,13 +7829,11 @@ static void handle_2misc_fcmp_zero(DisasContext *s,= int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_zero); tcg_temp_free_i64(tcg_op); + + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_zero =3D tcg_const_i32(0); @@ -7888,8 +7884,8 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_zero); tcg_temp_free_i32(tcg_op); - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } =20 @@ -7925,12 +7921,9 @@ static void handle_2misc_reciprocal(DisasContext *s,= int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_op); + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); @@ -7970,8 +7963,8 @@ static void handle_2misc_reciprocal(DisasContext *s, = int opcode, } tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_op); - if (!is_q && !is_scalar) { - clear_vec_high(s, rd); + if (!is_scalar) { + clear_vec_high(s, is_q, rd); } } tcg_temp_free_ptr(fpst); @@ -8077,9 +8070,7 @@ static void handle_2misc_narrow(DisasContext *s, bool= scalar, write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 /* Remaining saturating accumulating ops */ @@ -8104,12 +8095,9 @@ static void handle_2misc_satacc(DisasContext *s, boo= l is_scalar, bool is_u, } write_vec_element(s, tcg_rd, rd, pass, MO_64); } - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_rn); + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_rn =3D tcg_temp_new_i32(); TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); @@ -8167,13 +8155,9 @@ static void handle_2misc_satacc(DisasContext *s, boo= l is_scalar, bool is_u, } write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); } - - if (!is_q) { - clear_vec_high(s, rd); - } - tcg_temp_free_i32(tcg_rd); tcg_temp_free_i32(tcg_rn); + clear_vec_high(s, is_q, rd); } } =20 @@ -8664,9 +8648,7 @@ static void handle_vec_simd_shri(DisasContext *s, boo= l is_q, bool is_u, tcg_temp_free_i64(tcg_round); =20 done: - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) @@ -8855,19 +8837,18 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, } =20 if (!is_q) { - clear_vec_high(s, rd); write_vec_element(s, tcg_final, rd, 0, MO_64); } else { write_vec_element(s, tcg_final, rd, 1, MO_64); } - if (round) { tcg_temp_free_i64(tcg_round); } tcg_temp_free_i64(tcg_rn); tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_final); - return; + + clear_vec_high(s, is_q, rd); } =20 =20 @@ -9261,9 +9242,7 @@ static void handle_3rd_narrowing(DisasContext *s, int= is_q, int is_u, int size, write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int= rm) @@ -9671,9 +9650,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 if (fpst) { @@ -10161,10 +10138,7 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) tcg_temp_free_i32(tcg_op2); } } - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } =20 /* AdvSIMD three same @@ -10303,9 +10277,7 @@ static void handle_rev(DisasContext *s, int opcode,= bool u, write_vec_element(s, tcg_tmp, rd, i, grp_size); tcg_temp_free_i64(tcg_tmp); } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { int revmask =3D (1 << grp_size) - 1; int esize =3D 8 << size; @@ -10949,9 +10921,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) tcg_temp_free_i32(tcg_op); } } - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); =20 if (need_rmode) { gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); @@ -11130,11 +11100,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) tcg_temp_free_i64(tcg_res); } =20 - if (is_scalar) { - clear_vec_high(s, rd); - } - tcg_temp_free_i64(tcg_idx); + clear_vec_high(s, !is_scalar, rd); } else if (!is_long) { /* 32 bit floating point, or 16 or 32 bit integer. * For the 16 bit scalar case we use the usual Neon helpers and @@ -11238,10 +11205,7 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } =20 tcg_temp_free_i32(tcg_idx); - - if (!is_q) { - clear_vec_high(s, rd); - } + clear_vec_high(s, is_q, rd); } else { /* long ops: 16x16->32 or 32x32->64 */ TCGv_i64 tcg_res[2]; @@ -11318,9 +11282,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i64(tcg_idx); =20 - if (is_scalar) { - clear_vec_high(s, rd); - } + clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_idx =3D tcg_temp_new_i32(); =20 --=20 2.14.3