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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v6 1/5] target/arm: implement SHA-512 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SHA-512 instructions that have been added as an optional extensions to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/crypto_helper.c | 90 +++++++++++++++- target/arm/helper.h | 5 + target/arm/translate-a64.c | 110 ++++++++++++++++++++ 4 files changed, 205 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a923e42d8bf..32a18510e70b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1372,6 +1372,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ + ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 9ca0bdead7bb..3d8d1fb5e7cf 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -1,7 +1,7 @@ /* * crypto_helper.c - emulate v8 Crypto Extensions instructions * - * Copyright (C) 2013 - 2014 Linaro Ltd + * Copyright (C) 2013 - 2018 Linaro Ltd * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -419,3 +419,91 @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void= *vm) rd[0] =3D d.l[0]; rd[1] =3D d.l[1]; } + +/* + * The SHA-512 logical functions (same as above but using 64-bit operands) + */ + +static uint64_t cho512(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & (y ^ z)) ^ z; +} + +static uint64_t maj512(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & y) | ((x | y) & z); +} + +static uint64_t S0_512(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static uint64_t S1_512(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static uint64_t s0_512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static uint64_t s1_512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + uint64_t d0 =3D rd[0]; + uint64_t d1 =3D rd[1]; + + d1 +=3D S1_512(rm[1]) + cho512(rm[1], rn[0], rn[1]); + d0 +=3D S1_512(d1 + rm[0]) + cho512(d1 + rm[0], rm[1], rn[0]); + + rd[0] =3D d0; + rd[1] =3D d1; +} + +void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + uint64_t d0 =3D rd[0]; + uint64_t d1 =3D rd[1]; + + d1 +=3D S0_512(rm[0]) + maj512(rn[0], rm[1], rm[0]); + d0 +=3D S0_512(d1) + maj512(d1, rm[0], rm[1]); + + rd[0] =3D d0; + rd[1] =3D d1; +} + +void HELPER(crypto_sha512su0)(void *vd, void *vn) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t d0 =3D rd[0]; + uint64_t d1 =3D rd[1]; + + d0 +=3D s0_512(rd[1]); + d1 +=3D s0_512(rn[0]); + + rd[0] =3D d0; + rd[1] =3D d1; +} + +void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + + rd[0] +=3D s1_512(rn[0]) + rm[0]; + rd[1] +=3D s1_512(rn[1]) + rm[1]; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 5dec2e62626b..81d460702867 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -534,6 +534,11 @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 10eef870fee2..888f5a39a283 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11132,6 +11132,114 @@ static void disas_crypto_two_reg_sha(DisasContext= *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); } =20 +/* Crypto three-reg SHA512 + * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 + * +-----------------------+------+---+---+-----+--------+------+------+ + * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | + * +-----------------------+------+---+---+-----+--------+------+------+ + */ +static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int o =3D extract32(insn, 14, 1); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + int feature; + CryptoThreeOpFn *genfn; + + if (o =3D=3D 0) { + switch (opcode) { + case 0: /* SHA512H */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512h; + break; + case 1: /* SHA512H2 */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512h2; + break; + case 2: /* SHA512SU1 */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512su1; + break; + default: + unallocated_encoding(s); + return; + } + } else { + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + if (genfn) { + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + } else { + g_assert_not_reached(); + } +} + +/* Crypto two-reg SHA512 + * 31 12 11 10 9 5 4 0 + * +-----------------------------------------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | + * +-----------------------------------------+--------+------+------+ + */ +static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; + int feature; + CryptoTwoOpFn *genfn; + + switch (opcode) { + case 0: /* SHA512SU0 */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512su0; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + + genfn(tcg_rd_ptr, tcg_rn_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11161,6 +11269,8 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, + { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0x00000000, 0x00000000, NULL } }; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v6 2/5] target/arm: implement SHA-3 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SHA-3 instructions that have been added as an optional extensions to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/translate-a64.c | 148 +++++++++++++++++++- 2 files changed, 145 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32a18510e70b..d0b19e0cbc88 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1373,6 +1373,7 @@ enum arm_features { ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ + ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 888f5a39a283..f697a51ca7ec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11162,9 +11162,10 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) feature =3D ARM_FEATURE_V8_SHA512; genfn =3D gen_helper_crypto_sha512su1; break; - default: - unallocated_encoding(s); - return; + case 3: /* RAX1 */ + feature =3D ARM_FEATURE_V8_SHA3; + genfn =3D NULL; + break; } } else { unallocated_encoding(s); @@ -11193,7 +11194,28 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); tcg_temp_free_ptr(tcg_rm_ptr); } else { - g_assert_not_reached(); + TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; + int pass; + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + + tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + tcg_temp_free_i64(tcg_res[0]); + tcg_temp_free_i64(tcg_res[1]); } } =20 @@ -11240,6 +11262,122 @@ static void disas_crypto_two_reg_sha512(DisasCont= ext *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); } =20 +/* Crypto four-register + * 31 23 22 21 20 16 15 14 10 9 5 4 0 + * +-------------------+-----+------+---+------+------+------+ + * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | + * +-------------------+-----+------+---+------+------+------+ + */ +static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) +{ + int op0 =3D extract32(insn, 21, 2); + int rm =3D extract32(insn, 16, 5); + int ra =3D extract32(insn, 10, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + int feature; + + switch (op0) { + case 0: /* EOR3 */ + case 1: /* BCAX */ + feature =3D ARM_FEATURE_V8_SHA3; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + if (op0 < 2) { + TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; + int pass; + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_op3 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + read_vec_element(s, tcg_op3, ra, pass, MO_64); + + if (op0 =3D=3D 0) { + /* EOR3 */ + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); + } else { + /* BCAX */ + tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); + } + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + tcg_temp_free_i64(tcg_op3); + tcg_temp_free_i64(tcg_res[0]); + tcg_temp_free_i64(tcg_res[1]); + } else { + g_assert_not_reached(); + } +} + +/* Crypto XAR + * 31 21 20 16 15 10 9 5 4 0 + * +-----------------------+------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | + * +-----------------------+------+--------+------+------+ + */ +static void disas_crypto_xar(DisasContext *s, uint32_t insn) +{ + int rm =3D extract32(insn, 16, 5); + int imm6 =3D extract32(insn, 10, 6); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + + tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); + tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + tcg_temp_free_i64(tcg_res[0]); + tcg_temp_free_i64(tcg_res[1]); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11271,6 +11409,8 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, + { 0xce000000, 0xff808000, disas_crypto_four_reg }, + { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0x00000000, 0x00000000, NULL } }; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v6 3/5] target/arm: implement SM3 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SM3 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/crypto_helper.c | 96 ++++++++++++++++++++ target/arm/helper.h | 4 + target/arm/translate-a64.c | 88 +++++++++++++++++- 4 files changed, 186 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d0b19e0cbc88..18383666e02d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1374,6 +1374,7 @@ enum arm_features { ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 3d8d1fb5e7cf..2f6744edb088 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -507,3 +507,99 @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void= *vm) rd[0] +=3D s1_512(rn[0]) + rm[0]; rd[1] +=3D s1_512(rn[1]) + rm[1]; } + +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + t =3D CR_ST_WORD(d, 0) ^ CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 1), 17= ); + CR_ST_WORD(d, 0) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 1) ^ CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 2), 17= ); + CR_ST_WORD(d, 1) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 2) ^ CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 3), 17= ); + CR_ST_WORD(d, 2) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 3) ^ CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 0), 17= ); + CR_ST_WORD(d, 3) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t =3D CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 0), 25); + + CR_ST_WORD(d, 0) ^=3D t; + CR_ST_WORD(d, 1) ^=3D CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 1), 25); + CR_ST_WORD(d, 2) ^=3D CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 2), 25); + CR_ST_WORD(d, 3) ^=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(m, 3), 25) ^ + ror32(t, 17) ^ ror32(t, 2) ^ ror32(t, 26); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, + uint32_t opcode) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + assert(imm2 < 4); + + if (opcode =3D=3D 0 || opcode =3D=3D 2) { + /* SM3TT1A, SM3TT2A */ + t =3D par(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 1) { + /* SM3TT1B */ + t =3D maj(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 3) { + /* SM3TT2B */ + t =3D cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else { + g_assert_not_reached(); + } + + t +=3D CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2); + + CR_ST_WORD(d, 0) =3D CR_ST_WORD(d, 1); + + if (opcode < 2) { + /* SM3TT1A, SM3TT1B */ + t +=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 3), 20); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 23); + } else { + /* SM3TT2A, SM3TT2B */ + t +=3D CR_ST_WORD(n, 3); + t ^=3D rol32(t, 9) ^ rol32(t, 17); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 13); + } + + CR_ST_WORD(d, 2) =3D CR_ST_WORD(d, 3); + CR_ST_WORD(d, 3) =3D t; + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 81d460702867..9d9f42cc89a6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,6 +539,10 @@ DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32= , i32) +DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f697a51ca7ec..afa1e7b5a27f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11168,8 +11168,19 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) break; } } else { - unallocated_encoding(s); - return; + switch (opcode) { + case 0: /* SM3PARTW1 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw1; + break; + case 1: /* SM3PARTW2 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw2; + break; + default: + unallocated_encoding(s); + return; + } } =20 if (!arm_dc_feature(s, feature)) { @@ -11282,6 +11293,9 @@ static void disas_crypto_four_reg(DisasContext *s, = uint32_t insn) case 1: /* BCAX */ feature =3D ARM_FEATURE_V8_SHA3; break; + case 2: /* SM3SS1 */ + feature =3D ARM_FEATURE_V8_SM3; + break; default: unallocated_encoding(s); return; @@ -11329,7 +11343,33 @@ static void disas_crypto_four_reg(DisasContext *s,= uint32_t insn) tcg_temp_free_i64(tcg_res[0]); tcg_temp_free_i64(tcg_res[1]); } else { - g_assert_not_reached(); + TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; + + tcg_op1 =3D tcg_temp_new_i32(); + tcg_op2 =3D tcg_temp_new_i32(); + tcg_op3 =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + tcg_zero =3D tcg_const_i32(0); + + read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); + read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); + read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); + + tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); + tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); + tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); + tcg_gen_rotri_i32(tcg_res, tcg_res, 25); + + write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); + write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); + write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); + write_vec_element_i32(s, tcg_res, rd, 3, MO_32); + + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_op3); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_zero); } } =20 @@ -11378,6 +11418,47 @@ static void disas_crypto_xar(DisasContext *s, uint= 32_t insn) tcg_temp_free_i64(tcg_res[1]); } =20 +/* Crypto three-reg imm2 + * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 + * +-----------------------+------+-----+------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | + * +-----------------------+------+-----+------+--------+------+------+ + */ +static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int imm2 =3D extract32(insn, 12, 2); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; + TCGv_i32 tcg_imm2, tcg_opcode; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + tcg_imm2 =3D tcg_const_i32(imm2); + tcg_opcode =3D tcg_const_i32(opcode); + + gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2, + tcg_opcode); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + tcg_temp_free_i32(tcg_imm2); + tcg_temp_free_i32(tcg_opcode); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11411,6 +11492,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, + { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.11.0 From nobody Mon Apr 29 06:39:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15180028133841002.0349382325488; Wed, 7 Feb 2018 03:26:53 -0800 (PST) Received: from localhost ([::1]:52117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNsK-00056m-7j for importer@patchew.org; Wed, 07 Feb 2018 06:26:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNjY-0005El-Cw for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v6 4/5] target/arm: implement SM4 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SM4 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/crypto_helper.c | 91 ++++++++++++++++++++ target/arm/helper.h | 3 + target/arm/translate-a64.c | 8 ++ 4 files changed, 103 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18383666e02d..bad13a76d06c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1375,6 +1375,7 @@ enum arm_features { ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 2f6744edb088..cc339ea7e0ca 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -603,3 +603,94 @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm= , uint32_t imm2, rd[0] =3D d.l[0]; rd[1] =3D d.l[1]; } + +static uint8_t const sm4_sbox[] =3D { + 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, + 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05, + 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, + 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, + 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, + 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62, + 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, + 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6, + 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, + 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8, + 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, + 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35, + 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, + 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87, + 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, + 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e, + 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, + 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1, + 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, + 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3, + 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, + 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f, + 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, + 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51, + 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, + 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8, + 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, + 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0, + 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, + 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84, + 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, + 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, +}; + +void HELPER(crypto_sm4e)(void *vd, void *vn) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + uint32_t t, i; + + for (i =3D 0; i < 4; i++) { + t =3D CR_ST_WORD(d, (i + 1) % 4) ^ + CR_ST_WORD(d, (i + 2) % 4) ^ + CR_ST_WORD(d, (i + 3) % 4) ^ + CR_ST_WORD(n, i); + + t =3D sm4_sbox[t & 0xff] | + sm4_sbox[(t >> 8) & 0xff] << 8 | + sm4_sbox[(t >> 16) & 0xff] << 16 | + sm4_sbox[(t >> 24) & 0xff] << 24; + + CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18= ) ^ + rol32(t, 24); + } + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t, i; + + d =3D n; + for (i =3D 0; i < 4; i++) { + t =3D CR_ST_WORD(d, (i + 1) % 4) ^ + CR_ST_WORD(d, (i + 2) % 4) ^ + CR_ST_WORD(d, (i + 3) % 4) ^ + CR_ST_WORD(m, i); + + t =3D sm4_sbox[t & 0xff] | + sm4_sbox[(t >> 8) & 0xff] << 8 | + sm4_sbox[(t >> 16) & 0xff] << 16 | + sm4_sbox[(t >> 24) & 0xff] << 24; + + CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 13) ^ rol32(t, 23); + } + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 9d9f42cc89a6..6383d7d09e0d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -543,6 +543,9 @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32, i32) DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index afa1e7b5a27f..186f2ebae9f2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11177,6 +11177,10 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) feature =3D ARM_FEATURE_V8_SM3; genfn =3D gen_helper_crypto_sm3partw2; break; + case 2: /* SM4EKEY */ + feature =3D ARM_FEATURE_V8_SM4; + genfn =3D gen_helper_crypto_sm4ekey; + break; default: unallocated_encoding(s); return; @@ -11250,6 +11254,10 @@ static void disas_crypto_two_reg_sha512(DisasConte= xt *s, uint32_t insn) feature =3D ARM_FEATURE_V8_SHA512; genfn =3D gen_helper_crypto_sha512su0; break; + case 1: /* SM4E */ + feature =3D ARM_FEATURE_V8_SM4; + genfn =3D gen_helper_crypto_sm4e; + break; default: unallocated_encoding(s); return; --=20 2.11.0 From nobody Mon Apr 29 06:39:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 07 Feb 2018 03:17:47 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Wed, 7 Feb 2018 11:17:29 +0000 Message-Id: <20180207111729.15737-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180207111729.15737-1-ard.biesheuvel@linaro.org> References: <20180207111729.15737-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel --- linux-user/elfload.c | 19 +++++++++++++++++++ target/arm/cpu64.c | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..7922ab8eab79 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 =3D 1 << 5, ARM_HWCAP_A64_SHA2 =3D 1 << 6, ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, + ARM_HWCAP_A64_DCPOP =3D 1 << 16, + ARM_HWCAP_A64_SHA3 =3D 1 << 17, + ARM_HWCAP_A64_SM3 =3D 1 << 18, + ARM_HWCAP_A64_SM4 =3D 1 << 19, + ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, + ARM_HWCAP_A64_SHA512 =3D 1 << 21, + ARM_HWCAP_A64_SVE =3D 1 << 22, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..1c330adc281b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ --=20 2.11.0