From nobody Sun May 5 16:12:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517911099212460.18436338132994; Tue, 6 Feb 2018 01:58:19 -0800 (PST) Received: from localhost ([::1]:48521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej014-0006cx-9y for importer@patchew.org; Tue, 06 Feb 2018 04:58:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36841) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eizyy-0005KC-Ly for qemu-devel@nongnu.org; Tue, 06 Feb 2018 04:56:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eizyt-0006pF-O4 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 04:56:08 -0500 Received: from mail.ispras.ru ([83.149.199.45]:39852) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eizyt-0006p5-FU for qemu-devel@nongnu.org; Tue, 06 Feb 2018 04:56:03 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id A3BFB54008B; Tue, 6 Feb 2018 12:56:02 +0300 (MSK) From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Date: Tue, 06 Feb 2018 12:56:03 +0300 Message-ID: <20180206095603.26500.5959.stgit@pasha-VirtualBox> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH] m68k: implement movep instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dovgaluk@ispras.ru, laurent@vivier.eu, pavel.dovgaluk@ispras.ru Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This patch implements movep instruction. It moves data between a data regis= ter and alternate bytes within the address space starting at the location specified and incrementing by two. It was designed for the original 68000 and used in firmwares for interfacing the 8-bit peripherals through the 16-bit data bus. Without this patch opcode for this instruction is recognized as some bitop. Signed-off-by: Pavel Dovgalyuk Signed-off-by: Mihail Abakumov --- target/m68k/translate.c | 53 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f0e86a7..a849c74 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2071,6 +2071,55 @@ DISAS_INSN(movem) tcg_temp_free(addr); } =20 +DISAS_INSN(movep) +{ + uint8_t i; + uint8_t op; + uint16_t displ; + TCGv reg; + TCGv addr; + TCGv abuf; + TCGv dbuf; + + op =3D (insn >> 6) & 7; + displ =3D read_im16(env, s); + + addr =3D AREG(insn, 0); + reg =3D DREG(insn, 9); + + abuf =3D tcg_temp_new(); + tcg_gen_addi_i32(abuf, addr, displ); + dbuf =3D tcg_temp_new(); + + if (op & 1) { + i =3D 4; + } else { + i =3D 2; + } + + if (op & 2) { + for ( ; i > 0 ; i--) { + tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8); + gen_store(s, OS_BYTE, abuf, dbuf); + if (i > 1) { + tcg_gen_addi_i32(abuf, abuf, 2); + } + } + } else { + tcg_gen_movi_i32(reg, 0); + for ( ; i > 0 ; i--) { + dbuf =3D gen_load(s, OS_BYTE, abuf, 1); + tcg_gen_or_i32(reg, reg, dbuf); + if (i > 1) { + tcg_gen_shli_i32(reg, reg, 8); + tcg_gen_addi_i32(abuf, abuf, 2); + } + } + } + tcg_temp_free(abuf); + tcg_temp_free(dbuf); +} + DISAS_INSN(bitop_im) { int opsize; @@ -5579,9 +5628,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(chk2, 00c0, f9c0, CHK2); INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); BASE(bitop_reg, 0100, f1c0); + BASE(movep, 0108, f1f8); BASE(bitop_reg, 0140, f1c0); + BASE(movep, 0148, f1f8); BASE(bitop_reg, 0180, f1c0); + BASE(movep, 0188, f1f8); BASE(bitop_reg, 01c0, f1c0); + BASE(movep, 01c8, f1f8); INSN(arith_im, 0280, fff8, CF_ISA_A); INSN(arith_im, 0200, ff00, M68000); INSN(undef, 02c0, ffc0, M68000);