This patchset is the result of comparing the registers
listed in the v8M Arm ARM against what QEMU was implementing.
It adds a collection of generally unexciting missing registers
(most of which we can simply NOP or make reads-as-written).
There are also a couple of bug fixes in there, of which the
worst is the byte-to-interrupt-number conversions being
completely wrong in several places. I think we didn't notice
that before because if you only deal with the bottom 32
interrupts then they're all in the first register in the
enable/pend/etc banks...

These patches sit on top of the derived-exceptions patchset,
but any conflicts should be purely textual.

Based-on: <1517324542-6607-1-git-send-email-peter.maydell@linaro.org>

thanks
-- PMM

Peter Maydell (8):
  hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
  hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
  hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
  hw/intc/armv7m_nvic: Implement v8M CPPWR register
  hw/intc/armv7m_nvic: Implement cache ID registers
  hw/intc/armv7m_nvic: Implement SCR
  target/arm: Implement writing to CONTROL_NS for v8M
  hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions

 target/arm/cpu.h      | 16 +++++++++
 hw/intc/armv7m_nvic.c | 95 +++++++++++++++++++++++++++++++++++++--------------
 target/arm/cpu.c      | 28 +++++++++++++++
 target/arm/helper.c   | 10 ++++++
 target/arm/machine.c  | 48 ++++++++++++++++++++++++++
 5 files changed, 172 insertions(+), 25 deletions(-)

-- 
2.16.1