From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15176544117081023.8019688993414; Sat, 3 Feb 2018 02:40:11 -0800 (PST) Received: from localhost ([::1]:39513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvEs-0003NX-Eo for importer@patchew.org; Sat, 03 Feb 2018 05:40:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCh-0001ym-NG for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCf-0008Sk-6h for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:51 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36238 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCe-0008Pn-T3 for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:49 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCh-0000hl-CA; Sat, 03 Feb 2018 10:37:53 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:18 +0000 Message-Id: <20180203103727.26457-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 01/10] cuda: do not use old_mmio accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/cuda.c | 40 ++++++++-------------------------------- 1 file changed, 8 insertions(+), 32 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 008d8bd4d5..23b7e0f5b0 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -275,7 +275,7 @@ static void cuda_delay_set_sr_int(CUDAState *s) timer_mod(s->sr_delay_timer, expire); } =20 -static uint32_t cuda_readb(void *opaque, hwaddr addr) +static uint64_t cuda_read(void *opaque, hwaddr addr, unsigned size) { CUDAState *s =3D opaque; uint32_t val; @@ -350,7 +350,7 @@ static uint32_t cuda_readb(void *opaque, hwaddr addr) return val; } =20 -static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val) +static void cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) { CUDAState *s =3D opaque; =20 @@ -780,38 +780,14 @@ static void cuda_receive_packet_from_host(CUDAState *= s, } } =20 -static void cuda_writew (void *opaque, hwaddr addr, uint32_t value) -{ -} - -static void cuda_writel (void *opaque, hwaddr addr, uint32_t value) -{ -} - -static uint32_t cuda_readw (void *opaque, hwaddr addr) -{ - return 0; -} - -static uint32_t cuda_readl (void *opaque, hwaddr addr) -{ - return 0; -} - static const MemoryRegionOps cuda_ops =3D { - .old_mmio =3D { - .write =3D { - cuda_writeb, - cuda_writew, - cuda_writel, - }, - .read =3D { - cuda_readb, - cuda_readw, - cuda_readl, - }, - }, + .read =3D cuda_read, + .write =3D cuda_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, }; =20 static bool cuda_timer_exist(void *opaque, int version_id) --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654587408955.3018107912707; Sat, 3 Feb 2018 02:43:07 -0800 (PST) Received: from localhost ([::1]:39611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvHm-000644-Jd for importer@patchew.org; Sat, 03 Feb 2018 05:43:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCi-0001zr-2M for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCg-0008TB-Fp for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:52 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36240 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCg-0008Qk-5A for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:50 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCj-0000hl-Sb; Sat, 03 Feb 2018 10:37:54 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:19 +0000 Message-Id: <20180203103727.26457-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 02/10] cuda: don't allow writes to port output pins X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the direction registers as a mask to ensure that only input pins are updated upon write. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/cuda.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 23b7e0f5b0..7214e7adcb 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -359,11 +359,11 @@ static void cuda_write(void *opaque, hwaddr addr, uin= t64_t val, unsigned size) =20 switch(addr) { case CUDA_REG_B: - s->b =3D val; + s->b =3D (s->b & ~s->dirb) | (val & s->dirb); cuda_update(s); break; case CUDA_REG_A: - s->a =3D val; + s->a =3D (s->a & ~s->dira) | (val & s->dira); break; case CUDA_REG_DIRB: s->dirb =3D val; --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654410819436.7083780193484; Sat, 3 Feb 2018 02:40:10 -0800 (PST) Received: from localhost ([::1]:39512 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvEp-0003Lk-L5 for importer@patchew.org; Sat, 03 Feb 2018 05:40:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50428) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCh-0001yo-NK for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCg-0008T3-4o for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:51 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36245 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCf-0008RJ-R0 for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:50 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCk-0000hl-TS; Sat, 03 Feb 2018 10:37:55 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:20 +0000 Message-Id: <20180203103727.26457-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 03/10] cuda: don't call cuda_update() when writing to ACR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The wire protocol for reading data to/from the VIA is triggered by changing inputs on port B rather than changing the timer configuration via the ACR. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/cuda.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 7214e7adcb..ba14dbeacd 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -406,7 +406,6 @@ static void cuda_write(void *opaque, hwaddr addr, uint6= 4_t val, unsigned size) case CUDA_REG_ACR: s->acr =3D val; cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_V= IRTUAL)); - cuda_update(s); break; case CUDA_REG_PCR: s->pcr =3D val; --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654734718345.83080641707113; Sat, 3 Feb 2018 02:45:34 -0800 (PST) Received: from localhost ([::1]:39886 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvK6-0008TW-8x for importer@patchew.org; Sat, 03 Feb 2018 05:45:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCj-00020Q-OG for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCg-0008Tc-Ts for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:53 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36248 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCg-0008RR-Ko for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:50 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCl-0000hl-Vm; Sat, 03 Feb 2018 10:37:56 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:21 +0000 Message-Id: <20180203103727.26457-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 04/10] cuda: introduce CUDAState parameter to get_counter() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will be required shortly and also happens to match nicely with the corresponding signature for set_counter(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/cuda.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index ba14dbeacd..f036e8d7e1 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -150,7 +150,7 @@ static uint64_t get_tb(uint64_t time, uint64_t freq) return muldiv64(time, freq, NANOSECONDS_PER_SECOND); } =20 -static unsigned int get_counter(CUDATimer *ti) +static unsigned int get_counter(CUDAState *s, CUDATimer *ti) { int64_t d; unsigned int counter; @@ -295,12 +295,12 @@ static uint64_t cuda_read(void *opaque, hwaddr addr, = unsigned size) val =3D s->dira; break; case CUDA_REG_T1CL: - val =3D get_counter(&s->timers[0]) & 0xff; + val =3D get_counter(s, &s->timers[0]) & 0xff; s->ifr &=3D ~T1_INT; cuda_update_irq(s); break; case CUDA_REG_T1CH: - val =3D get_counter(&s->timers[0]) >> 8; + val =3D get_counter(s, &s->timers[0]) >> 8; cuda_update_irq(s); break; case CUDA_REG_T1LL: @@ -311,12 +311,12 @@ static uint64_t cuda_read(void *opaque, hwaddr addr, = unsigned size) val =3D (s->timers[0].latch >> 8) & 0xff; break; case CUDA_REG_T2CL: - val =3D get_counter(&s->timers[1]) & 0xff; + val =3D get_counter(s, &s->timers[1]) & 0xff; s->ifr &=3D ~T2_INT; cuda_update_irq(s); break; case CUDA_REG_T2CH: - val =3D get_counter(&s->timers[1]) >> 8; + val =3D get_counter(s, &s->timers[1]) >> 8; break; case CUDA_REG_SR: val =3D s->sr; --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151765473171582.81594746153985; Sat, 3 Feb 2018 02:45:31 -0800 (PST) Received: from localhost ([::1]:39881 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvK4-0008SO-6r for importer@patchew.org; Sat, 03 Feb 2018 05:45:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCn-00023i-HE for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:38:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCj-0008VS-Ju for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:57 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36250 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCj-0008Ry-8T for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:53 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCn-0000hl-0K; Sat, 03 Feb 2018 10:37:59 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:22 +0000 Message-Id: <20180203103727.26457-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 05/10] cuda: rename frequency property to tb_frequency X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to more easily differentiate between the timebase frequency = used to calibrate the MacOS timers and the actual frequency of the hardware cloc= k as indicated by CUDA_TIMER_FREQ. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/cuda.c | 10 +++++----- hw/misc/macio/macio.c | 2 +- hw/ppc/mac.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index f036e8d7e1..a200320e7d 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -158,8 +158,8 @@ static unsigned int get_counter(CUDAState *s, CUDATimer= *ti) uint64_t current_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootu= p. */ - tb_diff =3D get_tb(current_time, ti->frequency) - ti->load_time; - d =3D (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24); + tb_diff =3D get_tb(current_time, ti->tb_frequency) - ti->load_time; + d =3D (tb_diff * 0xBF401675E5DULL) / (ti->tb_frequency << 24); =20 if (ti->index =3D=3D 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -179,7 +179,7 @@ static void set_counter(CUDAState *s, CUDATimer *ti, un= signed int val) { CUDA_DPRINTF("T%d.counter=3D%d\n", 1 + ti->index, val); ti->load_time =3D get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->frequency); + s->tb_frequency); ti->counter_value =3D val; cuda_timer_update(s, ti, ti->load_time); } @@ -878,7 +878,7 @@ static void cuda_realizefn(DeviceState *dev, Error **er= rp) struct tm tm; =20 s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s= ); - s->timers[0].frequency =3D s->frequency; + s->timers[0].frequency =3D s->tb_frequency; s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s= ); s->timers[1].frequency =3D (SCALE_US * 6000) / 4700; =20 @@ -909,7 +909,7 @@ static void cuda_initfn(Object *obj) } =20 static Property cuda_properties[] =3D { - DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0), + DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 44f91d1e7f..a639b09e00 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -451,7 +451,7 @@ void macio_init(PCIDevice *d, macio_state->escc_mem =3D escc_mem; /* Note: this code is strongly inspirated from the corresponding code in PearPC */ - qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "frequency", + qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency", macio_state->frequency); =20 qdev_init_nofail(DEVICE(d)); diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index b501af1653..fa78115c95 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -99,7 +99,7 @@ typedef struct CUDAState { CUDATimer timers[2]; =20 uint32_t tick_offset; - uint64_t frequency; + uint64_t tb_frequency; =20 uint8_t last_b; uint8_t last_acr; --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654589364841.9549660750345; Sat, 3 Feb 2018 02:43:09 -0800 (PST) Received: from localhost ([::1]:39612 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvHo-00064y-GN for importer@patchew.org; Sat, 03 Feb 2018 05:43:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCh-0001yn-Mf for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCf-0008SS-2h for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:51 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36253 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCe-0008SC-Oa for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:48 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCp-0000hl-NC; Sat, 03 Feb 2018 10:38:00 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:23 +0000 Message-Id: <20180203103727.26457-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 06/10] cuda: minor cosmetic tidy-ups to get_next_irq_time() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/cuda.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index a200320e7d..3336ed46b2 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -184,36 +184,37 @@ static void set_counter(CUDAState *s, CUDATimer *ti, = unsigned int val) cuda_timer_update(s, ti, ti->load_time); } =20 -static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) +static int64_t get_next_irq_time(CUDATimer *ti, int64_t current_time) { int64_t d, next_time; unsigned int counter; =20 /* current counter value */ - d =3D muldiv64(current_time - s->load_time, + d =3D muldiv64(current_time - ti->load_time, CUDA_TIMER_FREQ, NANOSECONDS_PER_SECOND); /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <=3D (s->counter_value + 1)) { - counter =3D (s->counter_value - d) & 0xffff; + if (d <=3D (ti->counter_value + 1)) { + counter =3D (ti->counter_value - d) & 0xffff; } else { - counter =3D (d - (s->counter_value + 1)) % (s->latch + 2); - counter =3D (s->latch - counter) & 0xffff; + counter =3D (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter =3D (ti->latch - counter) & 0xffff; } =20 /* Note: we consider the irq is raised on 0 */ if (counter =3D=3D 0xffff) { - next_time =3D d + s->latch + 1; + next_time =3D d + ti->latch + 1; } else if (counter =3D=3D 0) { - next_time =3D d + s->latch + 2; + next_time =3D d + ti->latch + 2; } else { next_time =3D d + counter; } CUDA_DPRINTF("latch=3D%d counter=3D%" PRId64 " delta_next=3D%" PRId64 = "\n", - s->latch, d, next_time - d); + ti->latch, d, next_time - d); next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, CUDA_TIMER_F= REQ) + - s->load_time; - if (next_time <=3D current_time) + ti->load_time; + if (next_time <=3D current_time) { next_time =3D current_time + 1; + } return next_time; } =20 --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654411712255.73550653360599; Sat, 3 Feb 2018 02:40:11 -0800 (PST) Received: from localhost ([::1]:39515 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvEv-0003Rt-9r for importer@patchew.org; Sat, 03 Feb 2018 05:40:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCi-0001zz-Eb for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCg-0008TD-Fj for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:52 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36256 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCg-0008So-4j for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:50 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCq-0000hl-Ux; Sat, 03 Feb 2018 10:38:02 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:24 +0000 Message-Id: <20180203103727.26457-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 07/10] cuda: set timer 1 frequency property to CUDA_TIMER_FREQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have successfully decoupled the timebase frequency and the hard= ware timer frequency, set the timer 1 frequency property to CUDA_TIMER_FREQ and = alter get_next_irq_time() to use it rather than the hard-coded constant. In addition to this we must now switch the tb_diff calculation over to use = the timebase frequency now that the hardware clock frequency and the timebase frequency are different. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/cuda.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 3336ed46b2..00e71fcd5e 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -158,8 +158,8 @@ static unsigned int get_counter(CUDAState *s, CUDATimer= *ti) uint64_t current_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootu= p. */ - tb_diff =3D get_tb(current_time, ti->tb_frequency) - ti->load_time; - d =3D (tb_diff * 0xBF401675E5DULL) / (ti->tb_frequency << 24); + tb_diff =3D get_tb(current_time, s->tb_frequency) - ti->load_time; + d =3D (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); =20 if (ti->index =3D=3D 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -191,7 +191,7 @@ static int64_t get_next_irq_time(CUDATimer *ti, int64_t= current_time) =20 /* current counter value */ d =3D muldiv64(current_time - ti->load_time, - CUDA_TIMER_FREQ, NANOSECONDS_PER_SECOND); + ti->frequency, NANOSECONDS_PER_SECOND); /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <=3D (ti->counter_value + 1)) { counter =3D (ti->counter_value - d) & 0xffff; @@ -210,7 +210,7 @@ static int64_t get_next_irq_time(CUDATimer *ti, int64_t= current_time) } CUDA_DPRINTF("latch=3D%d counter=3D%" PRId64 " delta_next=3D%" PRId64 = "\n", ti->latch, d, next_time - d); - next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, CUDA_TIMER_F= REQ) + + next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequenc= y) + ti->load_time; if (next_time <=3D current_time) { next_time =3D current_time + 1; @@ -879,7 +879,7 @@ static void cuda_realizefn(DeviceState *dev, Error **er= rp) struct tm tm; =20 s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s= ); - s->timers[0].frequency =3D s->tb_frequency; + s->timers[0].frequency =3D CUDA_TIMER_FREQ; s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s= ); s->timers[1].frequency =3D (SCALE_US * 6000) / 4700; =20 --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654888115673.5876987719063; Sat, 3 Feb 2018 02:48:08 -0800 (PST) Received: from localhost ([::1]:40245 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvMb-00020n-BQ for importer@patchew.org; Sat, 03 Feb 2018 05:48:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50487) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCm-00022V-55 for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCh-0008UL-Th for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:56 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36259 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCh-0008TV-HO for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:51 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCs-0000hl-97; Sat, 03 Feb 2018 10:38:03 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:25 +0000 Message-Id: <20180203103727.26457-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 08/10] cuda: factor out timebase-derived counter value and load time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit b981289c49 "PPC: Cuda: Use cuda timer to expose tbfreq to guest" alt= ered the timer calculations from those based upon the hardware CUDA clock freque= ncy to those based upon the CPU timebase frequency. In fact we can isolate the differences to 2 simple changes: one to the coun= ter read value and another to the counter load time. Move these changes into separate functions so the implementation can be swapped later. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/cuda.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 00e71fcd5e..184d151702 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -145,21 +145,29 @@ static void cuda_update_irq(CUDAState *s) } } =20 -static uint64_t get_tb(uint64_t time, uint64_t freq) +static uint64_t get_counter_value(CUDAState *s, CUDATimer *ti) { - return muldiv64(time, freq, NANOSECONDS_PER_SECOND); + /* Reverse of the tb calculation algorithm that Mac OS X uses on bootu= p */ + uint64_t tb_diff =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + s->tb_frequency, NANOSECONDS_PER_SECOND) - + ti->load_time; + + return (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); +} + +static uint64_t get_counter_load_time(CUDAState *s, CUDATimer *ti) +{ + uint64_t load_time =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + s->tb_frequency, NANOSECONDS_PER_SECOND); + return load_time; } =20 static unsigned int get_counter(CUDAState *s, CUDATimer *ti) { int64_t d; unsigned int counter; - uint64_t tb_diff; - uint64_t current_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 - /* Reverse of the tb calculation algorithm that Mac OS X uses on bootu= p. */ - tb_diff =3D get_tb(current_time, s->tb_frequency) - ti->load_time; - d =3D (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); + d =3D get_counter_value(s, ti); =20 if (ti->index =3D=3D 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -178,8 +186,7 @@ static unsigned int get_counter(CUDAState *s, CUDATimer= *ti) static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) { CUDA_DPRINTF("T%d.counter=3D%d\n", 1 + ti->index, val); - ti->load_time =3D get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->tb_frequency); + ti->load_time =3D get_counter_load_time(s, ti); ti->counter_value =3D val; cuda_timer_update(s, ti, ti->load_time); } --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654595459259.06185186926814; Sat, 3 Feb 2018 02:43:15 -0800 (PST) Received: from localhost ([::1]:39642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvHu-0006Cq-FA for importer@patchew.org; Sat, 03 Feb 2018 05:43:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvCt-0002Ad-8s for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:38:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvCl-0008WA-HS for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:38:03 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36262 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvCk-0008Vf-W4 for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:37:55 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCt-0000hl-Mm; Sat, 03 Feb 2018 10:38:06 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:26 +0000 Message-Id: <20180203103727.26457-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 09/10] misc: introduce new mos6522 VIA device and enable it for ppc builds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and includi= ng a conversion to trace-events. Signed-off-by: Mark Cave-Ayland --- default-configs/ppc-softmmu.mak | 1 + hw/misc/Makefile.objs | 3 + hw/misc/mos6522.c | 505 ++++++++++++++++++++++++++++++++++++= ++++ hw/misc/trace-events | 7 + include/hw/misc/mos6522.h | 149 ++++++++++++ 5 files changed, 665 insertions(+) create mode 100644 hw/misc/mos6522.c create mode 100644 include/hw/misc/mos6522.h diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index 3baed6a8fd..8aeb221be4 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -29,6 +29,7 @@ CONFIG_MAC=3Dy CONFIG_ESCC=3Dy CONFIG_MACIO=3Dy CONFIG_SUNGEM=3Dy +CONFIG_MOS6522=3Dy CONFIG_CUDA=3Dy CONFIG_ADB=3Dy CONFIG_MAC_NVRAM=3Dy diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index d517f83e81..1cd7989ea7 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -17,6 +17,9 @@ common-obj-$(CONFIG_INTEGRATOR_DEBUG) +=3D arm_integrator= _debug.o common-obj-$(CONFIG_A9SCU) +=3D a9scu.o common-obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o =20 +# Mac devices +common-obj-$(CONFIG_MOS6522) +=3D mos6522.o + # PKUnity SoC devices common-obj-$(CONFIG_PUV3) +=3D puv3_pm.o =20 diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c new file mode 100644 index 0000000000..bc69d0e053 --- /dev/null +++ b/hw/misc/mos6522.c @@ -0,0 +1,505 @@ +/* + * QEMU MOS6522 VIA emulation + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/input/adb.h" +#include "hw/misc/mos6522.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "qemu/cutils.h" +#include "qemu/log.h" +#include "trace.h" + +/* XXX: implement all timer modes */ + +static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time); + +static void mos6522_update_irq(MOS6522State *s) +{ + if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) +{ + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (ti->index =3D=3D 0) { + return mdc->get_timer1_counter_value(s, ti); + } else { + return mdc->get_timer2_counter_value(s, ti); + } +} + +static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) +{ + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (ti->index =3D=3D 0) { + return mdc->get_timer1_load_time(s, ti); + } else { + return mdc->get_timer2_load_time(s, ti); + } +} + +static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) +{ + int64_t d; + unsigned int counter; + + d =3D get_counter_value(s, ti); + + if (ti->index =3D=3D 0) { + /* the timer goes down from latch to -1 (period of latch + 2) */ + if (d <=3D (ti->counter_value + 1)) { + counter =3D (ti->counter_value - d) & 0xffff; + } else { + counter =3D (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter =3D (ti->latch - counter) & 0xffff; + } + } else { + counter =3D (ti->counter_value - d) & 0xffff; + } + return counter; +} + +static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int va= l) +{ + trace_mos6522_set_counter(1 + ti->index, val); + ti->load_time =3D get_load_time(s, ti); + ti->counter_value =3D val; + mos6522_timer_update(s, ti, ti->load_time); +} + +static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time) +{ + int64_t d, next_time; + unsigned int counter; + + /* current counter value */ + d =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + ti->frequency, NANOSECONDS_PER_SECOND); + + /* the timer goes down from latch to -1 (period of latch + 2) */ + if (d <=3D (ti->counter_value + 1)) { + counter =3D (ti->counter_value - d) & 0xffff; + } else { + counter =3D (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter =3D (ti->latch - counter) & 0xffff; + } + + /* Note: we consider the irq is raised on 0 */ + if (counter =3D=3D 0xffff) { + next_time =3D d + ti->latch + 1; + } else if (counter =3D=3D 0) { + next_time =3D d + ti->latch + 2; + } else { + next_time =3D d + counter; + } + trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); + next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequenc= y) + + ti->load_time; + if (next_time <=3D current_time) { + next_time =3D current_time + 1; + } + return next_time; +} + +static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time) +{ + if (!ti->timer) { + return; + } + if (ti->index =3D=3D 0 && (s->acr & T1MODE) !=3D T1MODE_CONT) { + timer_del(ti->timer); + } else { + ti->next_irq_time =3D get_next_irq_time(s, ti, current_time); + timer_mod(ti->timer, ti->next_irq_time); + } +} + +static void mos6522_timer1(void *opaque) +{ + MOS6522State *s =3D opaque; + MOS6522Timer *ti =3D &s->timers[0]; + + mos6522_timer_update(s, ti, ti->next_irq_time); + s->ifr |=3D T1_INT; + mos6522_update_irq(s); +} + +static void mos6522_timer2(void *opaque) +{ + MOS6522State *s =3D opaque; + MOS6522Timer *ti =3D &s->timers[1]; + + mos6522_timer_update(s, ti, ti->next_irq_time); + s->ifr |=3D T2_INT; + mos6522_update_irq(s); +} + +static void mos6522_set_sr_int(MOS6522State *s) +{ + trace_mos6522_set_sr_int(); + s->ifr |=3D SR_INT; + mos6522_update_irq(s); +} + +static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *t= i) +{ + uint64_t d; + + d =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + ti->frequency, NANOSECONDS_PER_SECOND); + + return d; +} + +static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) +{ + uint64_t load_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + return load_time; +} + +static void mos6522_portA_write(MOS6522State *s) +{ + qemu_log_mask(LOG_UNIMP, "portA_write unimplemented"); +} + +static void mos6522_portB_write(MOS6522State *s) +{ + qemu_log_mask(LOG_UNIMP, "portB_write unimplemented"); +} + +uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) +{ + MOS6522State *s =3D opaque; + uint32_t val; + + switch (addr) { + case VIA_REG_B: + val =3D s->b; + break; + case VIA_REG_A: + val =3D s->a; + break; + case VIA_REG_DIRB: + val =3D s->dirb; + break; + case VIA_REG_DIRA: + val =3D s->dira; + break; + case VIA_REG_T1CL: + val =3D get_counter(s, &s->timers[0]) & 0xff; + s->ifr &=3D ~T1_INT; + mos6522_update_irq(s); + break; + case VIA_REG_T1CH: + val =3D get_counter(s, &s->timers[0]) >> 8; + mos6522_update_irq(s); + break; + case VIA_REG_T1LL: + val =3D s->timers[0].latch & 0xff; + break; + case VIA_REG_T1LH: + /* XXX: check this */ + val =3D (s->timers[0].latch >> 8) & 0xff; + break; + case VIA_REG_T2CL: + val =3D get_counter(s, &s->timers[1]) & 0xff; + s->ifr &=3D ~T2_INT; + mos6522_update_irq(s); + break; + case VIA_REG_T2CH: + val =3D get_counter(s, &s->timers[1]) >> 8; + break; + case VIA_REG_SR: + val =3D s->sr; + s->ifr &=3D ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); + mos6522_update_irq(s); + break; + case VIA_REG_ACR: + val =3D s->acr; + break; + case VIA_REG_PCR: + val =3D s->pcr; + break; + case VIA_REG_IFR: + val =3D s->ifr; + if (s->ifr & s->ier) { + val |=3D 0x80; + } + break; + case VIA_REG_IER: + val =3D s->ier | 0x80; + break; + default: + case VIA_REG_ANH: + val =3D s->anh; + break; + } + + if (addr !=3D VIA_REG_IFR || val !=3D 0) { + trace_mos6522_read(addr, val); + } + + return val; +} + +void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + MOS6522State *s =3D opaque; + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + trace_mos6522_write(addr, val); + + switch (addr) { + case VIA_REG_B: + s->b =3D (s->b & ~s->dirb) | (val & s->dirb); + mdc->portB_write(s); + break; + case VIA_REG_A: + s->a =3D (s->a & ~s->dira) | (val & s->dira); + mdc->portA_write(s); + break; + case VIA_REG_DIRB: + s->dirb =3D val; + break; + case VIA_REG_DIRA: + s->dira =3D val; + break; + case VIA_REG_T1CL: + s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T1CH: + s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); + s->ifr &=3D ~T1_INT; + set_counter(s, &s->timers[0], s->timers[0].latch); + break; + case VIA_REG_T1LL: + s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T1LH: + s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); + s->ifr &=3D ~T1_INT; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T2CL: + s->timers[1].latch =3D (s->timers[1].latch & 0xff00) | val; + break; + case VIA_REG_T2CH: + /* To ensure T2 generates an interrupt on zero crossing with the + common timer code, write the value directly from the latch to + the counter */ + s->timers[1].latch =3D (s->timers[1].latch & 0xff) | (val << 8); + s->ifr &=3D ~T2_INT; + set_counter(s, &s->timers[1], s->timers[1].latch); + break; + case VIA_REG_SR: + s->sr =3D val; + break; + case VIA_REG_ACR: + s->acr =3D val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_PCR: + s->pcr =3D val; + break; + case VIA_REG_IFR: + /* reset bits */ + s->ifr &=3D ~val; + mos6522_update_irq(s); + break; + case VIA_REG_IER: + if (val & IER_SET) { + /* set bits */ + s->ier |=3D val & 0x7f; + } else { + /* reset bits */ + s->ier &=3D ~val; + } + mos6522_update_irq(s); + break; + default: + case VIA_REG_ANH: + s->anh =3D val; + break; + } +} + +static const MemoryRegionOps mos6522_ops =3D { + .read =3D mos6522_read, + .write =3D mos6522_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static bool mos6522_timer_exist(void *opaque, int version_id) +{ + MOS6522Timer *s =3D opaque; + + return s->timer !=3D NULL; +} + +static const VMStateDescription vmstate_mos6522_timer =3D { + .name =3D "mos6522_timer", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16(latch, MOS6522Timer), + VMSTATE_UINT16(counter_value, MOS6522Timer), + VMSTATE_INT64(load_time, MOS6522Timer), + VMSTATE_INT64(next_irq_time, MOS6522Timer), + VMSTATE_TIMER_PTR_TEST(timer, MOS6522Timer, mos6522_timer_exist), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_mos6522 =3D { + .name =3D "mos6522", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(a, MOS6522State), + VMSTATE_UINT8(b, MOS6522State), + VMSTATE_UINT8(dira, MOS6522State), + VMSTATE_UINT8(dirb, MOS6522State), + VMSTATE_UINT8(sr, MOS6522State), + VMSTATE_UINT8(acr, MOS6522State), + VMSTATE_UINT8(pcr, MOS6522State), + VMSTATE_UINT8(ifr, MOS6522State), + VMSTATE_UINT8(ier, MOS6522State), + VMSTATE_UINT8(anh, MOS6522State), + VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 1, + vmstate_mos6522_timer, MOS6522Timer), + VMSTATE_END_OF_LIST() + } +}; + +static void mos6522_reset(DeviceState *dev) +{ + MOS6522State *s =3D MOS6522(dev); + + s->b =3D 0; + s->a =3D 0; + s->dirb =3D 0xff; + s->dira =3D 0; + s->sr =3D 0; + s->acr =3D 0; + s->pcr =3D 0; + s->ifr =3D 0; + s->ier =3D 0; + /* s->ier =3D T1_INT | SR_INT; */ + s->anh =3D 0; + + s->timers[0].latch =3D 0xffff; + set_counter(s, &s->timers[0], 0xffff); + + s->timers[1].latch =3D 0xffff; +} + +static void mos6522_realize(DeviceState *dev, Error **errp) +{ + MOS6522State *s =3D MOS6522(dev); + + s->timers[0].frequency =3D s->frequency; + s->timers[1].frequency =3D s->frequency; +} + +static void mos6522_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + MOS6522State *s =3D MOS6522(obj); + int i; + + memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); + sysbus_init_mmio(sbd, &s->mem); + sysbus_init_irq(sbd, &s->irq); + + for (i =3D 0; i < ARRAY_SIZE(s->timers); i++) { + s->timers[i].index =3D i; + } + + s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1= , s); + s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2= , s); +} + +static Property mos6522_properties[] =3D { + DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void mos6522_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->realize =3D mos6522_realize; + dc->reset =3D mos6522_reset; + dc->vmsd =3D &vmstate_mos6522; + dc->props =3D mos6522_properties; + mdc->parent_realize =3D dc->realize; + mdc->set_sr_int =3D mos6522_set_sr_int; + mdc->portB_write =3D mos6522_portB_write; + mdc->portA_write =3D mos6522_portA_write; + mdc->get_timer1_counter_value =3D mos6522_get_counter_value; + mdc->get_timer2_counter_value =3D mos6522_get_counter_value; + mdc->get_timer1_load_time =3D mos6522_get_load_time; + mdc->get_timer2_load_time =3D mos6522_get_load_time; +} + +static const TypeInfo mos6522_type_info =3D { + .name =3D TYPE_MOS6522, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MOS6522State), + .instance_init =3D mos6522_init, + .abstract =3D true, + .class_size =3D sizeof(MOS6522DeviceClass), + .class_init =3D mos6522_class_init, +}; + +static void mos6522_register_types(void) +{ + type_register_static(&mos6522_type_info); +} + +type_init(mos6522_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 616579a403..108ca46d16 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -66,3 +66,10 @@ mps2_scc_cfg_read(unsigned function, unsigned device, ui= nt32_t value) "MPS2 SCC msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysr= eg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x= %08" HWADDR_PRIx " data 0x%08" PRIx32 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status = register" + +# hw/misc/mos6522.c +mos6522_set_counter(int index, unsigned int val) "T%d.counter=3D%d" +mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch= =3D%d counter=3D0x%"PRId64 " delta_next=3D0x%"PRId64 +mos6522_set_sr_int(void) "set sr_int" +mos6522_write(uint64_t addr, uint64_t val) "reg=3D0x%"PRIx64 " val=3D0x%"P= RIx64 +mos6522_read(uint64_t addr, unsigned val) "reg=3D0x%"PRIx64 " val=3D0x%x" diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h new file mode 100644 index 0000000000..db78b0a81c --- /dev/null +++ b/include/hw/misc/mos6522.h @@ -0,0 +1,149 @@ +/* + * QEMU MOS6522 VIA emulation + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef MOS6522_H +#define MOS6522_H + +#include "exec/memory.h" +#include "hw/sysbus.h" +#include "hw/ide/internal.h" +#include "hw/input/adb.h" + +/* Bits in ACR */ +#define SR_CTRL 0x1c /* Shift register control bits */ +#define SR_EXT 0x0c /* Shift on external clock */ +#define SR_OUT 0x10 /* Shift out if 1 */ + +/* Bits in IFR and IER */ +#define IER_SET 0x80 /* set bits in IER */ +#define IER_CLR 0 /* clear bits in IER */ +#define SR_INT 0x04 /* Shift register full/empty */ +#define SR_DATA_INT 0x08 +#define SR_CLOCK_INT 0x10 +#define T1_INT 0x40 /* Timer 1 interrupt */ +#define T2_INT 0x20 /* Timer 2 interrupt */ + +/* Bits in ACR */ +#define T1MODE 0xc0 /* Timer 1 mode */ +#define T1MODE_CONT 0x40 /* continuous interrupts */ + +/* VIA registers */ +#define VIA_REG_B 0x00 +#define VIA_REG_A 0x01 +#define VIA_REG_DIRB 0x02 +#define VIA_REG_DIRA 0x03 +#define VIA_REG_T1CL 0x04 +#define VIA_REG_T1CH 0x05 +#define VIA_REG_T1LL 0x06 +#define VIA_REG_T1LH 0x07 +#define VIA_REG_T2CL 0x08 +#define VIA_REG_T2CH 0x09 +#define VIA_REG_SR 0x0a +#define VIA_REG_ACR 0x0b +#define VIA_REG_PCR 0x0c +#define VIA_REG_IFR 0x0d +#define VIA_REG_IER 0x0e +#define VIA_REG_ANH 0x0f + +/** + * MOS6522Timer: + * @counter_value: counter value at load time + */ +typedef struct MOS6522Timer { + int index; + uint16_t latch; + uint16_t counter_value; + int64_t load_time; + int64_t next_irq_time; + uint64_t frequency; + QEMUTimer *timer; +} MOS6522Timer; + +/** + * MOS6522State: + * @b: B-side data + * @a: A-side data + * @dirb: B-side direction (1=3Doutput) + * @dira: A-side direction (1=3Doutput) + * @sr: Shift register + * @acr: Auxiliary control register + * @pcr: Peripheral control register + * @ifr: Interrupt flag register + * @ier: Interrupt enable register + * @anh: A-side data, no handshake + * @last_b: last value of B register + * @last_acr: last value of ACR register + */ +typedef struct MOS6522State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion mem; + /* VIA registers */ + uint8_t b; + uint8_t a; + uint8_t dirb; + uint8_t dira; + uint8_t sr; + uint8_t acr; + uint8_t pcr; + uint8_t ifr; + uint8_t ier; + uint8_t anh; + + MOS6522Timer timers[2]; + uint64_t frequency; + + qemu_irq irq; +} MOS6522State; + +#define TYPE_MOS6522 "mos6522" +#define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522) + +typedef struct MOS6522DeviceClass { + DeviceClass parent_class; + + DeviceRealize parent_realize; + void (*set_sr_int)(MOS6522State *dev); + void (*portB_write)(MOS6522State *dev); + void (*portA_write)(MOS6522State *dev); + /* These are used to influence the CUDA MacOS timebase calibration */ + uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); + uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); + uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti); + uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti); +} MOS6522DeviceClass; + +#define MOS6522_DEVICE_CLASS(cls) \ + OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522) +#define MOS6522_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522) + +uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size); +void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size); + +#endif /* MOS6522_H */ --=20 2.11.0 From nobody Fri May 3 19:18:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517654924448953.7851035186927; Sat, 3 Feb 2018 02:48:44 -0800 (PST) Received: from localhost ([::1]:40280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvND-0002OJ-KM for importer@patchew.org; Sat, 03 Feb 2018 05:48:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehvL4-0001FG-JN for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:46:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehvL1-0005nE-Da for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:46:30 -0500 Received: from chuckie.co.uk ([82.165.15.123]:36284 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehvL0-0005mz-TO for qemu-devel@nongnu.org; Sat, 03 Feb 2018 05:46:27 -0500 Received: from host86-175-243-217.range86-175.btcentralplus.com ([86.175.243.217] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ehvCx-0000hl-42; Sat, 03 Feb 2018 10:38:10 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, lvivier@redhat.com Date: Sat, 3 Feb 2018 10:37:27 +0000 Message-Id: <20180203103727.26457-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> References: <20180203103727.26457-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.243.217 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 10/10] cuda: convert to use the shared mos6522 device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the relevant hooks as required for the MacOS timer calibration and dela= yed SR interrupt. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/cuda.c | 606 ++++++++++++++---------------------------------= ---- hw/ppc/mac.h | 87 ++++---- 2 files changed, 204 insertions(+), 489 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 184d151702..15d9176733 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -26,15 +26,14 @@ #include "hw/hw.h" #include "hw/ppc/mac.h" #include "hw/input/adb.h" +#include "hw/misc/mos6522.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" #include "qemu/cutils.h" #include "qemu/log.h" =20 -/* XXX: implement all timer modes */ - -/* debug CUDA */ -//#define DEBUG_CUDA +/* debug CUDA packets */ +//#define DEBUG_CUDA_PACKET =20 /* debug CUDA packets */ //#define DEBUG_CUDA_PACKET @@ -47,426 +46,114 @@ #endif =20 /* Bits in B data register: all active low */ -#define TREQ 0x08 /* Transfer request (input) */ -#define TACK 0x10 /* Transfer acknowledge (output) */ -#define TIP 0x20 /* Transfer in progress (output) */ - -/* Bits in ACR */ -#define SR_CTRL 0x1c /* Shift register control bits */ -#define SR_EXT 0x0c /* Shift on external clock */ -#define SR_OUT 0x10 /* Shift out if 1 */ - -/* Bits in IFR and IER */ -#define IER_SET 0x80 /* set bits in IER */ -#define IER_CLR 0 /* clear bits in IER */ -#define SR_INT 0x04 /* Shift register full/empty */ -#define SR_DATA_INT 0x08 -#define SR_CLOCK_INT 0x10 -#define T1_INT 0x40 /* Timer 1 interrupt */ -#define T2_INT 0x20 /* Timer 2 interrupt */ - -/* Bits in ACR */ -#define T1MODE 0xc0 /* Timer 1 mode */ -#define T1MODE_CONT 0x40 /* continuous interrupts */ +#define TREQ 0x08 /* Transfer request (input) */ +#define TACK 0x10 /* Transfer acknowledge (output) */ +#define TIP 0x20 /* Transfer in progress (output) */ =20 /* commands (1st byte) */ -#define ADB_PACKET 0 -#define CUDA_PACKET 1 -#define ERROR_PACKET 2 -#define TIMER_PACKET 3 -#define POWER_PACKET 4 -#define MACIIC_PACKET 5 -#define PMU_PACKET 6 - - -/* CUDA commands (2nd byte) */ -#define CUDA_WARM_START 0x0 -#define CUDA_AUTOPOLL 0x1 -#define CUDA_GET_6805_ADDR 0x2 -#define CUDA_GET_TIME 0x3 -#define CUDA_GET_PRAM 0x7 -#define CUDA_SET_6805_ADDR 0x8 -#define CUDA_SET_TIME 0x9 -#define CUDA_POWERDOWN 0xa -#define CUDA_POWERUP_TIME 0xb -#define CUDA_SET_PRAM 0xc -#define CUDA_MS_RESET 0xd -#define CUDA_SEND_DFAC 0xe -#define CUDA_BATTERY_SWAP_SENSE 0x10 -#define CUDA_RESET_SYSTEM 0x11 -#define CUDA_SET_IPL 0x12 -#define CUDA_FILE_SERVER_FLAG 0x13 -#define CUDA_SET_AUTO_RATE 0x14 -#define CUDA_GET_AUTO_RATE 0x16 -#define CUDA_SET_DEVICE_LIST 0x19 -#define CUDA_GET_DEVICE_LIST 0x1a -#define CUDA_SET_ONE_SECOND_MODE 0x1b -#define CUDA_SET_POWER_MESSAGES 0x21 -#define CUDA_GET_SET_IIC 0x22 -#define CUDA_WAKEUP 0x23 -#define CUDA_TIMER_TICKLE 0x24 -#define CUDA_COMBINED_FORMAT_IIC 0x25 +#define ADB_PACKET 0 +#define CUDA_PACKET 1 +#define ERROR_PACKET 2 +#define TIMER_PACKET 3 +#define POWER_PACKET 4 +#define MACIIC_PACKET 5 +#define PMU_PACKET 6 =20 #define CUDA_TIMER_FREQ (4700000 / 6) =20 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ #define RTC_OFFSET 2082844800 =20 -/* CUDA registers */ -#define CUDA_REG_B 0x00 -#define CUDA_REG_A 0x01 -#define CUDA_REG_DIRB 0x02 -#define CUDA_REG_DIRA 0x03 -#define CUDA_REG_T1CL 0x04 -#define CUDA_REG_T1CH 0x05 -#define CUDA_REG_T1LL 0x06 -#define CUDA_REG_T1LH 0x07 -#define CUDA_REG_T2CL 0x08 -#define CUDA_REG_T2CH 0x09 -#define CUDA_REG_SR 0x0a -#define CUDA_REG_ACR 0x0b -#define CUDA_REG_PCR 0x0c -#define CUDA_REG_IFR 0x0d -#define CUDA_REG_IER 0x0e -#define CUDA_REG_ANH 0x0f - -static void cuda_update(CUDAState *s); static void cuda_receive_packet_from_host(CUDAState *s, const uint8_t *data, int len); -static void cuda_timer_update(CUDAState *s, CUDATimer *ti, - int64_t current_time); =20 -static void cuda_update_irq(CUDAState *s) -{ - if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { - qemu_irq_raise(s->irq); - } else { - qemu_irq_lower(s->irq); - } -} +/* MacOS uses timer 1 for calibration on startup, so we use + * the timebase frequency and cuda_get_counter_value() with + * cuda_get_load_time() to steer MacOS to calculate calibrate its timers + * correctly for both TCG and KVM (see commit b981289c49 "PPC: Cuda: Use c= uda + * timer to expose tbfreq to guest" for more information) */ =20 -static uint64_t get_counter_value(CUDAState *s, CUDATimer *ti) +static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) { + MOS6522CUDAState *mcs =3D container_of(s, MOS6522CUDAState, parent_obj= ); + CUDAState *cs =3D mcs->cuda; + /* Reverse of the tb calculation algorithm that Mac OS X uses on bootu= p */ uint64_t tb_diff =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->tb_frequency, NANOSECONDS_PER_SECOND) - + cs->tb_frequency, NANOSECONDS_PER_SECOND) - ti->load_time; =20 - return (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); + return (tb_diff * 0xBF401675E5DULL) / (cs->tb_frequency << 24); } =20 -static uint64_t get_counter_load_time(CUDAState *s, CUDATimer *ti) +static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) { + MOS6522CUDAState *mcs =3D container_of(s, MOS6522CUDAState, parent_obj= ); + CUDAState *cs =3D mcs->cuda; + uint64_t load_time =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->tb_frequency, NANOSECONDS_PER_SECOND); + cs->tb_frequency, NANOSECONDS_PER_SECOND= ); return load_time; } =20 -static unsigned int get_counter(CUDAState *s, CUDATimer *ti) -{ - int64_t d; - unsigned int counter; - - d =3D get_counter_value(s, ti); - - if (ti->index =3D=3D 0) { - /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <=3D (ti->counter_value + 1)) { - counter =3D (ti->counter_value - d) & 0xffff; - } else { - counter =3D (d - (ti->counter_value + 1)) % (ti->latch + 2); - counter =3D (ti->latch - counter) & 0xffff; - } - } else { - counter =3D (ti->counter_value - d) & 0xffff; - } - return counter; -} - -static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) -{ - CUDA_DPRINTF("T%d.counter=3D%d\n", 1 + ti->index, val); - ti->load_time =3D get_counter_load_time(s, ti); - ti->counter_value =3D val; - cuda_timer_update(s, ti, ti->load_time); -} - -static int64_t get_next_irq_time(CUDATimer *ti, int64_t current_time) -{ - int64_t d, next_time; - unsigned int counter; - - /* current counter value */ - d =3D muldiv64(current_time - ti->load_time, - ti->frequency, NANOSECONDS_PER_SECOND); - /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <=3D (ti->counter_value + 1)) { - counter =3D (ti->counter_value - d) & 0xffff; - } else { - counter =3D (d - (ti->counter_value + 1)) % (ti->latch + 2); - counter =3D (ti->latch - counter) & 0xffff; - } - - /* Note: we consider the irq is raised on 0 */ - if (counter =3D=3D 0xffff) { - next_time =3D d + ti->latch + 1; - } else if (counter =3D=3D 0) { - next_time =3D d + ti->latch + 2; - } else { - next_time =3D d + counter; - } - CUDA_DPRINTF("latch=3D%d counter=3D%" PRId64 " delta_next=3D%" PRId64 = "\n", - ti->latch, d, next_time - d); - next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequenc= y) + - ti->load_time; - if (next_time <=3D current_time) { - next_time =3D current_time + 1; - } - return next_time; -} - -static void cuda_timer_update(CUDAState *s, CUDATimer *ti, - int64_t current_time) -{ - if (!ti->timer) - return; - if (ti->index =3D=3D 0 && (s->acr & T1MODE) !=3D T1MODE_CONT) { - timer_del(ti->timer); - } else { - ti->next_irq_time =3D get_next_irq_time(ti, current_time); - timer_mod(ti->timer, ti->next_irq_time); - } -} - -static void cuda_timer1(void *opaque) -{ - CUDAState *s =3D opaque; - CUDATimer *ti =3D &s->timers[0]; - - cuda_timer_update(s, ti, ti->next_irq_time); - s->ifr |=3D T1_INT; - cuda_update_irq(s); -} - -static void cuda_timer2(void *opaque) -{ - CUDAState *s =3D opaque; - CUDATimer *ti =3D &s->timers[1]; - - cuda_timer_update(s, ti, ti->next_irq_time); - s->ifr |=3D T2_INT; - cuda_update_irq(s); -} - static void cuda_set_sr_int(void *opaque) { CUDAState *s =3D opaque; + MOS6522CUDAState *mcs =3D s->mos6522_cuda; + MOS6522State *ms =3D MOS6522(mcs); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); =20 - CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__); - s->ifr |=3D SR_INT; - cuda_update_irq(s); + mdc->set_sr_int(ms); } =20 static void cuda_delay_set_sr_int(CUDAState *s) { + MOS6522CUDAState *mcs =3D s->mos6522_cuda; + MOS6522State *ms =3D MOS6522(mcs); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); int64_t expire; =20 - if (s->dirb =3D=3D 0xff) { - /* Not in Mac OS, fire the IRQ directly */ - cuda_set_sr_int(s); + if (ms->dirb =3D=3D 0xff || s->sr_delay_ns =3D=3D 0) { + /* Disabled or not in Mac OS, fire the IRQ directly */ + mdc->set_sr_int(ms); return; } =20 CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__); =20 - expire =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 300 * SCALE_US; + expire =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->sr_delay_ns; timer_mod(s->sr_delay_timer, expire); } =20 -static uint64_t cuda_read(void *opaque, hwaddr addr, unsigned size) -{ - CUDAState *s =3D opaque; - uint32_t val; - - addr =3D (addr >> 9) & 0xf; - switch(addr) { - case CUDA_REG_B: - val =3D s->b; - break; - case CUDA_REG_A: - val =3D s->a; - break; - case CUDA_REG_DIRB: - val =3D s->dirb; - break; - case CUDA_REG_DIRA: - val =3D s->dira; - break; - case CUDA_REG_T1CL: - val =3D get_counter(s, &s->timers[0]) & 0xff; - s->ifr &=3D ~T1_INT; - cuda_update_irq(s); - break; - case CUDA_REG_T1CH: - val =3D get_counter(s, &s->timers[0]) >> 8; - cuda_update_irq(s); - break; - case CUDA_REG_T1LL: - val =3D s->timers[0].latch & 0xff; - break; - case CUDA_REG_T1LH: - /* XXX: check this */ - val =3D (s->timers[0].latch >> 8) & 0xff; - break; - case CUDA_REG_T2CL: - val =3D get_counter(s, &s->timers[1]) & 0xff; - s->ifr &=3D ~T2_INT; - cuda_update_irq(s); - break; - case CUDA_REG_T2CH: - val =3D get_counter(s, &s->timers[1]) >> 8; - break; - case CUDA_REG_SR: - val =3D s->sr; - s->ifr &=3D ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); - cuda_update_irq(s); - break; - case CUDA_REG_ACR: - val =3D s->acr; - break; - case CUDA_REG_PCR: - val =3D s->pcr; - break; - case CUDA_REG_IFR: - val =3D s->ifr; - if (s->ifr & s->ier) { - val |=3D 0x80; - } - break; - case CUDA_REG_IER: - val =3D s->ier | 0x80; - break; - default: - case CUDA_REG_ANH: - val =3D s->anh; - break; - } - if (addr !=3D CUDA_REG_IFR || val !=3D 0) { - CUDA_DPRINTF("read: reg=3D0x%x val=3D%02x\n", (int)addr, val); - } - - return val; -} - -static void cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) -{ - CUDAState *s =3D opaque; - - addr =3D (addr >> 9) & 0xf; - CUDA_DPRINTF("write: reg=3D0x%x val=3D%02x\n", (int)addr, val); - - switch(addr) { - case CUDA_REG_B: - s->b =3D (s->b & ~s->dirb) | (val & s->dirb); - cuda_update(s); - break; - case CUDA_REG_A: - s->a =3D (s->a & ~s->dira) | (val & s->dira); - break; - case CUDA_REG_DIRB: - s->dirb =3D val; - break; - case CUDA_REG_DIRA: - s->dira =3D val; - break; - case CUDA_REG_T1CL: - s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; - cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_V= IRTUAL)); - break; - case CUDA_REG_T1CH: - s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); - s->ifr &=3D ~T1_INT; - set_counter(s, &s->timers[0], s->timers[0].latch); - break; - case CUDA_REG_T1LL: - s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; - cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_V= IRTUAL)); - break; - case CUDA_REG_T1LH: - s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); - s->ifr &=3D ~T1_INT; - cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_V= IRTUAL)); - break; - case CUDA_REG_T2CL: - s->timers[1].latch =3D (s->timers[1].latch & 0xff00) | val; - break; - case CUDA_REG_T2CH: - /* To ensure T2 generates an interrupt on zero crossing with the - common timer code, write the value directly from the latch to - the counter */ - s->timers[1].latch =3D (s->timers[1].latch & 0xff) | (val << 8); - s->ifr &=3D ~T2_INT; - set_counter(s, &s->timers[1], s->timers[1].latch); - break; - case CUDA_REG_SR: - s->sr =3D val; - break; - case CUDA_REG_ACR: - s->acr =3D val; - cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_V= IRTUAL)); - break; - case CUDA_REG_PCR: - s->pcr =3D val; - break; - case CUDA_REG_IFR: - /* reset bits */ - s->ifr &=3D ~val; - cuda_update_irq(s); - break; - case CUDA_REG_IER: - if (val & IER_SET) { - /* set bits */ - s->ier |=3D val & 0x7f; - } else { - /* reset bits */ - s->ier &=3D ~val; - } - cuda_update_irq(s); - break; - default: - case CUDA_REG_ANH: - s->anh =3D val; - break; - } -} - /* NOTE: TIP and TREQ are negated */ static void cuda_update(CUDAState *s) { + MOS6522CUDAState *mcs =3D s->mos6522_cuda; + MOS6522State *ms =3D MOS6522(mcs); int packet_received, len; =20 packet_received =3D 0; - if (!(s->b & TIP)) { + if (!(ms->b & TIP)) { /* transfer requested from host */ =20 - if (s->acr & SR_OUT) { + if (ms->acr & SR_OUT) { /* data output */ - if ((s->b & (TACK | TIP)) !=3D (s->last_b & (TACK | TIP))) { + if ((ms->b & (TACK | TIP)) !=3D (s->last_b & (TACK | TIP))) { if (s->data_out_index < sizeof(s->data_out)) { - CUDA_DPRINTF("send: %02x\n", s->sr); - s->data_out[s->data_out_index++] =3D s->sr; + CUDA_DPRINTF("send: %02x\n", ms->sr); + s->data_out[s->data_out_index++] =3D ms->sr; cuda_delay_set_sr_int(s); } } } else { if (s->data_in_index < s->data_in_size) { /* data input */ - if ((s->b & (TACK | TIP)) !=3D (s->last_b & (TACK | TIP)))= { - s->sr =3D s->data_in[s->data_in_index++]; - CUDA_DPRINTF("recv: %02x\n", s->sr); + if ((ms->b & (TACK | TIP)) !=3D (s->last_b & (TACK | TIP))= ) { + ms->sr =3D s->data_in[s->data_in_index++]; + CUDA_DPRINTF("recv: %02x\n", ms->sr); /* indicate end of transfer */ if (s->data_in_index >=3D s->data_in_size) { - s->b =3D (s->b | TREQ); + ms->b =3D (ms->b | TREQ); } cuda_delay_set_sr_int(s); } @@ -474,12 +161,13 @@ static void cuda_update(CUDAState *s) } } else { /* no transfer requested: handle sync case */ - if ((s->last_b & TIP) && (s->b & TACK) !=3D (s->last_b & TACK)) { + if ((s->last_b & TIP) && (ms->b & TACK) !=3D (s->last_b & TACK)) { /* update TREQ state each time TACK change state */ - if (s->b & TACK) - s->b =3D (s->b | TREQ); - else - s->b =3D (s->b & ~TREQ); + if (ms->b & TACK) { + ms->b =3D (ms->b | TREQ); + } else { + ms->b =3D (ms->b & ~TREQ); + } cuda_delay_set_sr_int(s); } else { if (!(s->last_b & TIP)) { @@ -490,13 +178,13 @@ static void cuda_update(CUDAState *s) } /* signal if there is data to read */ if (s->data_in_index < s->data_in_size) { - s->b =3D (s->b & ~TREQ); + ms->b =3D (ms->b & ~TREQ); } } } =20 - s->last_acr =3D s->acr; - s->last_b =3D s->b; + s->last_acr =3D ms->acr; + s->last_b =3D ms->b; =20 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() recursively */ @@ -538,9 +226,8 @@ static void cuda_adb_poll(void *opaque) obuf[1] =3D 0x40; /* polled data */ cuda_send_packet_to_host(s, obuf, olen + 2); } - timer_mod(s->adb_poll_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))= ); + timer_mod(s->adb_poll_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); } =20 /* description of commands */ @@ -787,35 +474,35 @@ static void cuda_receive_packet_from_host(CUDAState *= s, } } =20 -static const MemoryRegionOps cuda_ops =3D { - .read =3D cuda_read, - .write =3D cuda_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 1, - }, -}; +static uint64_t mos6522_cuda_read(void *opaque, hwaddr addr, unsigned size) +{ + CUDAState *s =3D opaque; + MOS6522CUDAState *mcs =3D s->mos6522_cuda; + MOS6522State *ms =3D MOS6522(mcs); =20 -static bool cuda_timer_exist(void *opaque, int version_id) + addr =3D (addr >> 9) & 0xf; + return mos6522_read(ms, addr, size); +} + +static void mos6522_cuda_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { - CUDATimer *s =3D opaque; + CUDAState *s =3D opaque; + MOS6522CUDAState *mcs =3D s->mos6522_cuda; + MOS6522State *ms =3D MOS6522(mcs); =20 - return s->timer !=3D NULL; + addr =3D (addr >> 9) & 0xf; + mos6522_write(ms, addr, val, size); } =20 -static const VMStateDescription vmstate_cuda_timer =3D { - .name =3D "cuda_timer", - .version_id =3D 0, - .minimum_version_id =3D 0, - .fields =3D (VMStateField[]) { - VMSTATE_UINT16(latch, CUDATimer), - VMSTATE_UINT16(counter_value, CUDATimer), - VMSTATE_INT64(load_time, CUDATimer), - VMSTATE_INT64(next_irq_time, CUDATimer), - VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist), - VMSTATE_END_OF_LIST() - } +static const MemoryRegionOps mos6522_cuda_ops =3D { + .read =3D mos6522_cuda_read, + .write =3D mos6522_cuda_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, }; =20 static const VMStateDescription vmstate_cuda =3D { @@ -823,18 +510,8 @@ static const VMStateDescription vmstate_cuda =3D { .version_id =3D 4, .minimum_version_id =3D 4, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(a, CUDAState), - VMSTATE_UINT8(b, CUDAState), VMSTATE_UINT8(last_b, CUDAState), - VMSTATE_UINT8(dira, CUDAState), - VMSTATE_UINT8(dirb, CUDAState), - VMSTATE_UINT8(sr, CUDAState), - VMSTATE_UINT8(acr, CUDAState), VMSTATE_UINT8(last_acr, CUDAState), - VMSTATE_UINT8(pcr, CUDAState), - VMSTATE_UINT8(ifr, CUDAState), - VMSTATE_UINT8(ier, CUDAState), - VMSTATE_UINT8(anh, CUDAState), VMSTATE_INT32(data_in_size, CUDAState), VMSTATE_INT32(data_in_index, CUDAState), VMSTATE_INT32(data_out_index, CUDAState), @@ -844,8 +521,6 @@ static const VMStateDescription vmstate_cuda =3D { VMSTATE_BUFFER(data_in, CUDAState), VMSTATE_BUFFER(data_out, CUDAState), VMSTATE_UINT32(tick_offset, CUDAState), - VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1, - vmstate_cuda_timer, CUDATimer), VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState), VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState), VMSTATE_END_OF_LIST() @@ -856,61 +531,48 @@ static void cuda_reset(DeviceState *dev) { CUDAState *s =3D CUDA(dev); =20 - s->b =3D 0; - s->a =3D 0; - s->dirb =3D 0xff; - s->dira =3D 0; - s->sr =3D 0; - s->acr =3D 0; - s->pcr =3D 0; - s->ifr =3D 0; - s->ier =3D 0; - // s->ier =3D T1_INT | SR_INT; - s->anh =3D 0; s->data_in_size =3D 0; s->data_in_index =3D 0; s->data_out_index =3D 0; s->autopoll =3D 0; - - s->timers[0].latch =3D 0xffff; - set_counter(s, &s->timers[0], 0xffff); - - s->timers[1].latch =3D 0xffff; - - s->sr_delay_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int= , s); } =20 -static void cuda_realizefn(DeviceState *dev, Error **errp) +static void cuda_realize(DeviceState *dev, Error **errp) { CUDAState *s =3D CUDA(dev); + SysBusDevice *sbd; + MOS6522State *ms; + DeviceState *d; struct tm tm; =20 - s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s= ); - s->timers[0].frequency =3D CUDA_TIMER_FREQ; - s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s= ); - s->timers[1].frequency =3D (SCALE_US * 6000) / 4700; + d =3D qdev_create(NULL, TYPE_MOS6522_CUDA); + object_property_set_link(OBJECT(d), OBJECT(s), "cuda", errp); + qdev_init_nofail(d); + s->mos6522_cuda =3D MOS6522_CUDA(d); + + /* Pass IRQ from 6522 */ + ms =3D MOS6522(d); + sbd =3D SYS_BUS_DEVICE(s); + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms)); =20 qemu_get_timedate(&tm, 0); s->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; =20 + s->sr_delay_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int= , s); + s->sr_delay_ns =3D 300 * SCALE_US; + s->adb_poll_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, = s); - s->autopoll_rate_ms =3D 20; s->adb_poll_mask =3D 0xffff; + s->autopoll_rate_ms =3D 20; } =20 -static void cuda_initfn(Object *obj) +static void cuda_init(Object *obj) { - SysBusDevice *d =3D SYS_BUS_DEVICE(obj); CUDAState *s =3D CUDA(obj); - int i; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000); - sysbus_init_mmio(d, &s->mem); - sysbus_init_irq(d, &s->irq); - - for (i =3D 0; i < ARRAY_SIZE(s->timers); i++) { - s->timers[i].index =3D i; - } + memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x20= 00); + sysbus_init_mmio(sbd, &s->mem); =20 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, DEVICE(obj), "adb.0"); @@ -925,7 +587,7 @@ static void cuda_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - dc->realize =3D cuda_realizefn; + dc->realize =3D cuda_realize; dc->reset =3D cuda_reset; dc->vmsd =3D &vmstate_cuda; dc->props =3D cuda_properties; @@ -936,12 +598,62 @@ static const TypeInfo cuda_type_info =3D { .name =3D TYPE_CUDA, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(CUDAState), - .instance_init =3D cuda_initfn, + .instance_init =3D cuda_init, .class_init =3D cuda_class_init, }; =20 +static void mos6522_cuda_portB_write(MOS6522State *s) +{ + MOS6522CUDAState *mcs =3D container_of(s, MOS6522CUDAState, parent_obj= ); + + cuda_update(mcs->cuda); +} + +static void mos6522_cuda_realize(DeviceState *dev, Error **errp) +{ + MOS6522State *ms =3D MOS6522(dev); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); + + mdc->parent_realize(dev, errp); + + ms->timers[0].frequency =3D CUDA_TIMER_FREQ; + ms->timers[1].frequency =3D (SCALE_US * 6000) / 4700; +} + +static void mos6522_cuda_init(Object *obj) +{ + MOS6522CUDAState *s =3D MOS6522_CUDA(obj); + + object_property_add_link(obj, "cuda", TYPE_OBJECT, + (Object **) &s->cuda, + qdev_prop_allow_set_link_before_realize, + 0, NULL); +} + +static void mos6522_cuda_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->realize =3D mos6522_cuda_realize; + mdc->portB_write =3D mos6522_cuda_portB_write; + mdc->get_timer1_counter_value =3D cuda_get_counter_value; + mdc->get_timer2_counter_value =3D cuda_get_counter_value; + mdc->get_timer1_load_time =3D cuda_get_load_time; + mdc->get_timer2_load_time =3D cuda_get_load_time; +} + +static const TypeInfo mos6522_cuda_type_info =3D { + .name =3D TYPE_MOS6522_CUDA, + .parent =3D TYPE_MOS6522, + .instance_size =3D sizeof(MOS6522CUDAState), + .instance_init =3D mos6522_cuda_init, + .class_init =3D mos6522_cuda_class_init, +}; + static void cuda_register_types(void) { + type_register_static(&mos6522_cuda_type_info); type_register_static(&cuda_type_info); } =20 diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index fa78115c95..3e9f13d9b4 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -30,6 +30,7 @@ #include "hw/sysbus.h" #include "hw/ide/internal.h" #include "hw/input/adb.h" +#include "hw/misc/mos6522.h" =20 /* SMP is not enabled, for now */ #define MAX_CPUS 1 @@ -44,59 +45,48 @@ =20 #define ESCC_CLOCK 3686400 =20 +/* CUDA commands (2nd byte) */ +#define CUDA_WARM_START 0x0 +#define CUDA_AUTOPOLL 0x1 +#define CUDA_GET_6805_ADDR 0x2 +#define CUDA_GET_TIME 0x3 +#define CUDA_GET_PRAM 0x7 +#define CUDA_SET_6805_ADDR 0x8 +#define CUDA_SET_TIME 0x9 +#define CUDA_POWERDOWN 0xa +#define CUDA_POWERUP_TIME 0xb +#define CUDA_SET_PRAM 0xc +#define CUDA_MS_RESET 0xd +#define CUDA_SEND_DFAC 0xe +#define CUDA_BATTERY_SWAP_SENSE 0x10 +#define CUDA_RESET_SYSTEM 0x11 +#define CUDA_SET_IPL 0x12 +#define CUDA_FILE_SERVER_FLAG 0x13 +#define CUDA_SET_AUTO_RATE 0x14 +#define CUDA_GET_AUTO_RATE 0x16 +#define CUDA_SET_DEVICE_LIST 0x19 +#define CUDA_GET_DEVICE_LIST 0x1a +#define CUDA_SET_ONE_SECOND_MODE 0x1b +#define CUDA_SET_POWER_MESSAGES 0x21 +#define CUDA_GET_SET_IIC 0x22 +#define CUDA_WAKEUP 0x23 +#define CUDA_TIMER_TICKLE 0x24 +#define CUDA_COMBINED_FORMAT_IIC 0x25 + /* Cuda */ #define TYPE_CUDA "cuda" #define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA) =20 -/** - * CUDATimer: - * @counter_value: counter value at load time - */ -typedef struct CUDATimer { - int index; - uint16_t latch; - uint16_t counter_value; - int64_t load_time; - int64_t next_irq_time; - uint64_t frequency; - QEMUTimer *timer; -} CUDATimer; - -/** - * CUDAState: - * @b: B-side data - * @a: A-side data - * @dirb: B-side direction (1=3Doutput) - * @dira: A-side direction (1=3Doutput) - * @sr: Shift register - * @acr: Auxiliary control register - * @pcr: Peripheral control register - * @ifr: Interrupt flag register - * @ier: Interrupt enable register - * @anh: A-side data, no handshake - * @last_b: last value of B register - * @last_acr: last value of ACR register - */ +typedef struct MOS6522CUDAState MOS6522CUDAState; + typedef struct CUDAState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - MemoryRegion mem; - /* cuda registers */ - uint8_t b; - uint8_t a; - uint8_t dirb; - uint8_t dira; - uint8_t sr; - uint8_t acr; - uint8_t pcr; - uint8_t ifr; - uint8_t ier; - uint8_t anh; =20 ADBBusState adb_bus; - CUDATimer timers[2]; + MOS6522CUDAState *mos6522_cuda; =20 uint32_t tick_offset; uint64_t tb_frequency; @@ -105,6 +95,7 @@ typedef struct CUDAState { uint8_t last_acr; =20 /* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */ + uint64_t sr_delay_ns; QEMUTimer *sr_delay_timer; =20 int data_in_size; @@ -120,6 +111,18 @@ typedef struct CUDAState { QEMUTimer *adb_poll_timer; } CUDAState; =20 +/* MOS6522 CUDA */ +typedef struct MOS6522CUDAState { + /*< private >*/ + MOS6522State parent_obj; + + CUDAState *cuda; +} MOS6522CUDAState; + +#define TYPE_MOS6522_CUDA "mos6522-cuda" +#define MOS6522_CUDA(obj) OBJECT_CHECK(MOS6522CUDAState, (obj), \ + TYPE_MOS6522_CUDA) + /* MacIO */ #define TYPE_OLDWORLD_MACIO "macio-oldworld" #define TYPE_NEWWORLD_MACIO "macio-newworld" --=20 2.11.0