From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893479698432.2430546329848; Thu, 25 Jan 2018 07:17:59 -0800 (PST) Received: from localhost ([::1]:46102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejHq-0007T4-UF for importer@patchew.org; Thu, 25 Jan 2018 10:17:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFi-0006Eo-Ac for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFc-0000j3-BS for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:46 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:60965) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFc-0000i4-2F for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:40 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M852L-1f0EJ63dcP-00viWa; Thu, 25 Jan 2018 16:15:38 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:28 +0100 Message-Id: <20180125151535.25256-2-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:0E9A5nJwf3gqKfEXt+CD0qY3pqvESWwNDQqsM+qu6jpVFhlylKX ujf7tO0YNd9JaRzhM2KjCuHLsxjONLt86hmNmcbI4jtmSa5Y4caTPfvJrw143MEGlZ0UkjB e7nzWao8T80GrpF4L9iguu4B1UypRshQKaKZCpNfTqPVo5F/xvpiYse9klJZy0WzUYVhmA6 1sx6Hwjp8RJZ7jnnOBiBQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:VSQ9hf5/E4w=:HUIYvcQzf/iSh7ZuPggo7h vkyzh+6OAdzKRVr7rQuspmpfdb2MiZ5HR5RhjY+WNEEM99cxTCmVDmA7WgV/c69XZYEt3LBnI AxqhztHmFhSpOF/CwCAMmxQ7l3X0AZJqsO0XEoAUTWvsKcRVoUGQlXP6gpjfy/vZXlqwHgDIr 8GohVm576UlbUcjJE0grT+uROi96Ph6DLdVJoVJ4ayPj0Y1MC1XLn4Qi2N1ENEqrWsbM1huQJ hSjYKgK+88JijIdRv/ehLPh1AZd2U58XYaU5s3UxMvU2TNEdI0F0U6yysmfnjcmUyfLrGm21Y QCt60M3k54Jhbipd9szOWoPWReGayI4o18NQ9qYHwh3W7o18yApUTj4AGgesioMFG3ix0UEVC 25zpqauzpKS6XohbmVPNjeNiwhGTRsU5v7pOm9VFR5l7odLLiI6ahNmjsEZpBsMyChR6iAQoW KcnjOq6P+Uh2R2/Lf7IYwl9vQpUGRLRpm43ZkKPm/Cnyptlgop7KAcdkqM1zNWb2UHae/jBIm if4yqx+sODySS8NlPM5oT5FR/2yayO8GXvQhnsBWZyAIiUmhcpeX4kT0yzShdbkDIDn8sC4+l n9dqQFJURkYEy38oEsxKfKrrNKO6Y4Vl2bQr/UVZGHVgAtC0FJxtTkBYd7MP1FiGs/PSFYRSK cDs0oWW4k/QGTBFDhNzP3TWSIn1ICpaItGs8UzgyYpL2itBfsCtTrKGzrIuu5nU+51aTNaVVo k0zcXtka17t35aPgxBUo/6GoekKs/0vz5V/psw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 1/8] target/m68k: fix TCG variable double free X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" t64 is also unconditionally freed after the switch () { ... } Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20180119114444.7590-1-laurent@vivier.eu> --- target/m68k/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f0e86a73d4..ea18df940a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -969,7 +969,6 @@ static void gen_load_fp(DisasContext *s, int opsize, TC= Gv addr, TCGv_ptr fp) case OS_DOUBLE: tcg_gen_qemu_ld64(t64, addr, index); gen_helper_extf64(cpu_env, fp, t64); - tcg_temp_free_i64(t64); break; case OS_EXTENDED: if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 25 Jan 2018 10:15:41 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MPbr3-1eipyt0zGz-004iIW; Thu, 25 Jan 2018 16:15:39 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:29 +0100 Message-Id: <20180125151535.25256-3-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:hgwDJ+KkhwDWEzFaAQ8FyJeqqU2eZAPqzKq3ibcHWiSoR0iVOKs 3+me8y/syQd3pNjHqAnwbCebKKZU4AMIH0/Re8iCCxKsDd8DIQAdXhria6VMfXSEzLe8/GW XzLqChC30XMNK87xHvtUJb7hJIAE4/96GdYRPMqxuc+leo/QJwoJdIx8SHkBIODUPAyJCiw 8pJBujqG//YqzbMhn5DnA== X-UI-Out-Filterresults: notjunk:1;V01:K0:mNa67h1F8bs=:/MFDdeI6OZq76XfzvgWW7t oMgg39tYQfGSMiqbGq+FdwcDe4oWl041ARKFH1ZuxBWV7Cf2wu27HG2si5NkpiQH/95nZs8k3 fWgHeBIiFf3UU3dJTMFOzpp0NRsNrOO38iAwlALJsUl6vcvtrTs7Ql4NsxtwBJoQ1eU2q65hl XKdW9ej8M07UHuKZyVng6X9+VACm+C0RpNz/gIEUmcA7GKgWFEXgGIKDfPSgCACRN3kagX2PW JpykbEaCwMDfqrJ5NG5vCbCCZ7gI1XbpNE/OGdjh9r/gdAX/myYoIbZW8rlpvBxa96PLB+Uco LfVffNc5ST7/RZQDUv1K6oWGclyTjbP50YwYXqXgSUps1GGSuJiRxB2ulZVentS0bn240Jbqc hjgnKYN3wKKRvr2zQPMaAxIz8xai3BAhy37wxfMg6U/ItusVKuVXMtuSIxfruITlEVgF4Fxsg zXM8ziTuE9fxwywpKfY/sUFXv5ASgsg3L5NKtjh897DcE7PhD33/9ZGx/ECNENiy7XqoItz3b Gy+nD9ZntODbSRfLVtSVtEF323h3stZBf74eOTOxIHmfB+YZE7q3/R9kMJku63ZYpsr+LA2HJ tiK/1YDFrSbpoQSa1qZ0nCr5a7VnWoO9HVIJ4ABLdjcihR5N8BdfvJvyROPzn2Jk32WBnIvw9 prJiuxmT8evlMVHsLiIxRForjjcyd9fCrA5pQJLpLqu1g70Od/9aUiQIzyqpPdxEq/nJe/Hi8 gRTVKG+U/EH7BZzwjk4JrL6ntJOQiLcJIddzMA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 2/8] accel/tcg: add size paremeter in tlb_fill() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier Reviewed-by: David Hildenbrand Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-2-laurent@vivier.eu> --- accel/tcg/cputlb.c | 13 ++++++++----- accel/tcg/softmmu_template.h | 14 ++++++++------ accel/tcg/user-exec.c | 2 +- include/exec/exec-all.h | 6 +++--- include/qom/cpu.h | 2 +- target/alpha/cpu.h | 2 +- target/alpha/helper.c | 4 ++-- target/alpha/mem_helper.c | 6 +++--- target/arm/cpu.c | 4 ++-- target/arm/op_helper.c | 4 ++-- target/cris/cpu.h | 2 +- target/cris/helper.c | 4 ++-- target/cris/op_helper.c | 6 +++--- target/hppa/cpu.h | 3 ++- target/hppa/helper.c | 2 +- target/hppa/op_helper.c | 2 +- target/i386/cpu.h | 2 +- target/i386/excp_helper.c | 4 ++-- target/i386/mem_helper.c | 6 +++--- target/lm32/cpu.h | 2 +- target/lm32/helper.c | 2 +- target/lm32/op_helper.c | 6 +++--- target/m68k/cpu.h | 2 +- target/m68k/helper.c | 4 ++-- target/m68k/op_helper.c | 6 +++--- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/op_helper.c | 6 +++--- target/mips/helper.c | 2 +- target/mips/internal.h | 2 +- target/mips/op_helper.c | 10 +++++----- target/moxie/cpu.h | 2 +- target/moxie/helper.c | 10 +++++----- target/nios2/cpu.h | 2 +- target/nios2/helper.c | 6 ++++-- target/nios2/mmu.c | 6 +++--- target/openrisc/cpu.h | 2 +- target/openrisc/mmu.c | 8 ++++---- target/openrisc/mmu_helper.c | 6 +++--- target/ppc/cpu.h | 2 +- target/ppc/mmu_helper.c | 4 ++-- target/ppc/user_only_helper.c | 2 +- target/s390x/excp_helper.c | 4 ++-- target/s390x/internal.h | 2 +- target/s390x/mem_helper.c | 8 ++++---- target/sh4/cpu.h | 2 +- target/sh4/helper.c | 4 ++-- target/sh4/op_helper.c | 6 +++--- target/sparc/cpu.h | 2 +- target/sparc/ldst_helper.c | 6 +++--- target/sparc/mmu_helper.c | 6 +++--- target/tilegx/cpu.c | 4 ++-- target/tricore/op_helper.c | 4 ++-- target/unicore32/cpu.h | 2 +- target/unicore32/helper.c | 2 +- target/unicore32/op_helper.c | 6 +++--- target/unicore32/softmmu.c | 2 +- target/xtensa/op_helper.c | 4 ++-- 58 files changed, 129 insertions(+), 121 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fd84209df..05439039e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -880,7 +880,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { if (!VICTIM_TLB_HIT(addr_read, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_INST_FETCH, mmu_idx, 0); + tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); } } iotlbentry =3D &env->iotlb[mmu_idx][index]; @@ -928,7 +928,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) * Otherwise the function will return, and there will be a valid * entry in the TLB for this access. */ -void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, +void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr) { int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -938,7 +938,8 @@ void probe_write(CPUArchState *env, target_ulong addr, = int mmu_idx, !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); } } } @@ -981,7 +982,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); + tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, + mmu_idx, retaddr); } tlb_addr =3D tlbe->addr_write & ~TLB_INVALID_MASK; } @@ -995,7 +997,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, =20 /* Let the guest notice RMW on a write-only page. */ if (unlikely(tlbe->addr_read !=3D (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD, + mmu_idx, retaddr); /* Since we don't support reads and writes to different addresses, and we do have the proper page loaded for write, this shouldn't ever return. But just in case, handle via stop-the-world. */ diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index 3fc5144316..239ea6692b 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -124,7 +124,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, + tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); } tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; @@ -191,7 +191,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, + tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); } tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; @@ -283,7 +283,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); + tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, + mmu_idx, retaddr); } tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; } @@ -316,7 +317,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; if (page2 !=3D (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -359,7 +360,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); + tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, + mmu_idx, retaddr); } tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; } @@ -392,7 +394,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; if (page2 !=3D (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c973752562..a0a4a1924e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -149,7 +149,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, cc =3D CPU_GET_CLASS(cpu); /* see if it is an MMU fault */ g_assert(cc->handle_mmu_fault); - ret =3D cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX); + ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); =20 if (ret =3D=3D 0) { /* The MMU fault was handled without causing real CPU fault. diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b37f7d8d92..e5afd2e6d3 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -253,7 +253,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); -void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, +void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) @@ -436,8 +436,8 @@ void tb_lock_reset(void); struct MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs); =20 -void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); +void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 #endif =20 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 93bd546879..aff88fa16f 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -174,7 +174,7 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); - int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, + int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, int mmu_index); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 0a9ad35f06..09720c2f3b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -479,7 +479,7 @@ void alpha_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, int mmu_idx); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 36407f77f5..bbf72cadfb 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -103,7 +103,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned re= g, uint64_t val) } =20 #if defined(CONFIG_USER_ONLY) -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { AlphaCPU *cpu =3D ALPHA_CPU(cs); @@ -247,7 +247,7 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) return (fail >=3D 0 ? -1 : phys); } =20 -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw, int mmu_idx) { AlphaCPU *cpu =3D ALPHA_CPU(cs); diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 430eea470b..e19ab91ec9 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -69,12 +69,12 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D alpha_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); if (unlikely(ret !=3D 0)) { /* Exception index and error code are already set */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cc1856c32b..9da6ea505c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1689,8 +1689,8 @@ static Property arm_cpu_properties[] =3D { }; =20 #ifdef CONFIG_USER_ONLY -static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, - int mmu_idx) +static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 712c5c55b6..abd00f845d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -172,8 +172,8 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUA= ccessType access_type, * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { bool ret; ARMMMUFaultInfo fi =3D {}; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b64fa3542c..764b35cbae 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -283,7 +283,7 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 /* Support function regs. */ diff --git a/target/cris/helper.c b/target/cris/helper.c index af78cca8b9..d2ec349191 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -53,7 +53,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { CRISCPU *cpu =3D CRIS_CPU(cs); @@ -76,7 +76,7 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] =3D ccs; } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index e92505c907..becd831b6b 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -41,8 +41,8 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { CRISCPU *cpu =3D CRIS_CPU(cs); CPUCRISState *env =3D &cpu->env; @@ -50,7 +50,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 D_LOG("%s pc=3D%x tpc=3D%x ra=3D%p\n", __func__, env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret =3D cris_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8d14077763..1a35eae1fa 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -132,7 +132,8 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler =20 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mi= dx); +int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, + int rw, int midx); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ba04a9a52b..23f7af7018 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -65,7 +65,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) env->psw_cb =3D cb; } =20 -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3104404e8d..fdbf64ae3c 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -139,7 +139,7 @@ static void do_stby_e(CPUHPPAState *env, target_ulong a= ddr, target_ulong val, /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ #ifndef CONFIG_USER_ONLY - probe_write(env, addr, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); #endif break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 30cc5628d2..f91e37d25d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1504,7 +1504,7 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, +int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, int is_write, int mmu_idx); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index cef44495ab..cb4d1b7d33 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -138,7 +138,7 @@ void raise_exception_ra(CPUX86State *env, int exception= _index, uintptr_t retaddr } =20 #if defined(CONFIG_USER_ONLY) -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int is_write, int mmu_idx) { X86CPU *cpu =3D X86_CPU(cs); @@ -162,7 +162,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, * 0 =3D nothing more to do * 1 =3D generate PF fault */ -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int is_write1, int mmu_idx) { X86CPU *cpu =3D X86_CPU(cs); diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 70f67668ab..a8ae694a9c 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -199,12 +199,12 @@ void helper_boundl(CPUX86State *env, target_ulong a0,= int v) * from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D x86_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); if (ret) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 2279594f40..ce0a2f24c4 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -263,7 +263,7 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler =20 -int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 #include "exec/cpu-all.h" diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 929cc36c14..a039a993ff 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -25,7 +25,7 @@ #include "exec/semihost.h" #include "exec/log.h" =20 -int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { LM32CPU *cpu =3D LM32_CPU(cs); diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 30f670eee8..577f8306e3 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -144,12 +144,12 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D lm32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D lm32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); if (unlikely(ret)) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 2985b039e1..c60564a047 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -418,7 +418,7 @@ static inline int cpu_mmu_index (CPUM68KState *env, boo= l ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 #include "exec/cpu-all.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index a999389e9a..ef0ec5dadf 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -308,7 +308,7 @@ void m68k_switch_sp(CPUM68KState *env) =20 #if defined(CONFIG_USER_ONLY) =20 -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { M68kCPU *cpu =3D M68K_CPU(cs); @@ -328,7 +328,7 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) return addr; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { int prot; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index c61ca9392f..67697d4e6d 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -39,12 +39,12 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KSta= te *env) /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); if (unlikely(ret)) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 52b6b6aec7..f3e7405a62 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -367,7 +367,7 @@ static inline int cpu_mmu_index (CPUMBState *env, bool = ifetch) return MMU_KERNEL_IDX; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); =20 #include "exec/cpu-all.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index da394d1dfc..fac6ee9263 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -38,7 +38,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] =3D env->sregs[SR_PC]; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { cs->exception_index =3D 0xaa; @@ -48,7 +48,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, = int rw, =20 #else /* !CONFIG_USER_ONLY */ =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4cf51568df..869072a2d1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -33,12 +33,12 @@ * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); if (unlikely(ret)) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/mips/helper.c b/target/mips/helper.c index ea076261af..8cf91ce339 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -535,7 +535,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) } #endif =20 -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { MIPSCPU *cpu =3D MIPS_CPU(cs); diff --git a/target/mips/internal.h b/target/mips/internal.h index 45ded3484c..e41051f8e6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -202,7 +202,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 /* op_helper.c */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e537a8bfd8..798cdad030 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2451,12 +2451,12 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, do_raise_exception_err(env, excp, error_code, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); if (ret) { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; @@ -4190,10 +4190,10 @@ static inline void ensure_writable_pages(CPUMIPSSta= te *env, target_ulong page_addr; if (unlikely(MSA_PAGESPAN(addr))) { /* first page */ - probe_write(env, addr, mmu_idx, retaddr); + probe_write(env, addr, 0, mmu_idx, retaddr); /* second page */ page_addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, page_addr, mmu_idx, retaddr); + probe_write(env, page_addr, 0, mmu_idx, retaddr); } #endif } diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index d37e6a5572..a01f480821 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -142,7 +142,7 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *= env, target_ulong *pc, *flags =3D 0; } =20 -int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, +int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); =20 #endif /* MOXIE_CPU_H */ diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 6890ffd71c..b8e86560da 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -29,12 +29,12 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D moxie_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); if (unlikely(ret)) { cpu_loop_exit_restore(cs, retaddr); } @@ -94,7 +94,7 @@ void moxie_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { MoxieCPU *cpu =3D MOXIE_CPU(cs); @@ -107,7 +107,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, =20 #else /* !CONFIG_USER_ONLY */ =20 -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { MoxieCPU *cpu =3D MOXIE_CPU(cs); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 88823a6d4d..204b39add7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -252,7 +252,7 @@ static inline int cpu_mmu_index(CPUNios2State *env, boo= l ifetch) MMU_SUPERVISOR_IDX; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, +int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size, int rw, int mmu_idx); =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 9f741a8f19..a169c91eaa 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -37,7 +37,8 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mm= u_idx) +int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { cs->exception_index =3D 0xaa; /* Page 0x1000 is kuser helper */ @@ -232,7 +233,8 @@ static int cpu_nios2_handle_virtual_page( return 1; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mm= u_idx) +int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0cd8647510..69b71cba4a 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -35,12 +35,12 @@ #define MMU_LOG(x) #endif =20 -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D nios2_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); if (unlikely(ret)) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index cc22dc8871..fb46cc9986 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -356,7 +356,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, = vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, +int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); =20 diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index ce2a29dd1a..2bd782f89b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,8 +178,8 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCP= U *cpu, } =20 #ifndef CONFIG_USER_ONLY -int openrisc_cpu_handle_mmu_fault(CPUState *cs, - vaddr address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int ret =3D 0; @@ -202,8 +202,8 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, return ret; } #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, - vaddr address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int ret =3D 0; diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a3e182c42d..97e1d17b5a 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -25,12 +25,12 @@ =20 #ifndef CONFIG_USER_ONLY =20 -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu= _idx); =20 if (ret) { /* Raise Exception. */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 603a38cae8..9f8cbbe7aa 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1308,7 +1308,7 @@ void ppc_translate_init(void); int cpu_ppc_signal_handler (int host_signum, void *pinfo, void *puc); #if defined(CONFIG_USER_ONLY) -int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int r= w, int mmu_idx); #endif =20 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 298c15e961..16ef5acaa2 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2925,8 +2925,8 @@ void helper_check_tlb_flush_global(CPUPPCState *env) NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 6aff34713f..2f1477f102 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" =20 -int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f4697a884d..e8f7a40c2b 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -55,7 +55,7 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { S390CPU *cpu =3D S390_CPU(cs); @@ -83,7 +83,7 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, int rw, int mmu_idx) { S390CPU *cpu =3D S390_CPU(cs); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 1a88e4beb4..fea165ffe4 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -323,7 +323,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index c957febc6d..427b795a78 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -39,10 +39,10 @@ NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret =3D s390_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + int ret =3D s390_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu= _idx); if (unlikely(ret !=3D 0)) { cpu_loop_exit_restore(cs, retaddr); } @@ -1440,7 +1440,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, =20 /* Sanity check writability of the store address. */ #ifndef CONFIG_USER_ONLY - probe_write(env, a2, mem_idx, ra); + probe_write(env, a2, 0, mem_idx, ra); #endif =20 /* Note that the compare-and-swap is atomic, and the store is atomic, = but diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index a2c26e0597..52a4568dd5 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -246,7 +246,7 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, in= t rw, int mmu_idx); =20 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 680b583e53..2ff0cf4060 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -34,7 +34,7 @@ void superh_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, int mmu_idx) { SuperHCPU *cpu =3D SUPERH_CPU(cs); @@ -458,7 +458,7 @@ static int get_physical_address(CPUSH4State * env, targ= et_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } =20 -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, int mmu_idx) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index d798f239cf..4b8bbf63b4 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -40,12 +40,12 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D superh_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_i= dx); if (ret) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9fde547fac..3eaffb354e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -582,7 +582,7 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintp= tr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, int mmu_idx); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index fb489cb5fd..5bc090213c 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1929,12 +1929,12 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CP= UState *cs, vaddr addr, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D sparc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); if (ret) { cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index f2d2250e7a..f8886ae039 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -27,7 +27,7 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, int mmu_idx) { SPARCCPU *cpu =3D SPARC_CPU(cs); @@ -208,7 +208,7 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, int mmu_idx) { SPARCCPU *cpu =3D SPARC_CPU(cs); @@ -713,7 +713,7 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, int mmu_idx) { SPARCCPU *cpu =3D SPARC_CPU(cs); diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2ef8ea7daa..c140b461ac 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -112,8 +112,8 @@ static void tilegx_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, - int mmu_idx) +static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int si= ze, + int rw, int mmu_idx) { TileGXCPU *cpu =3D TILEGX_CPU(cs); =20 diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 40ed229486..098f217c2a 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2806,8 +2806,8 @@ static inline void QEMU_NORETURN do_raise_exception_e= rr(CPUTriCoreState *env, cpu_loop_exit_restore(cs, pc); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; ret =3D cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 3dc6fbc6c7..a3cc71416d 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -181,7 +181,7 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32Sta= te *env, target_ulong *pc } } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index 3393d2c020..a5ff2ddb74 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -230,7 +230,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) cpu_abort(cs, "NO interrupt in user mode\n"); } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int access_type, int mmu_idx) { cpu_abort(cs, "NO mmu fault in user mode\n"); diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 8788642a7f..e0a15882d3 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -244,12 +244,12 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint3= 2_t x, uint32_t i) } =20 #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; =20 - ret =3D uc32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret =3D uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); if (unlikely(ret)) { /* now we have a real cpu fault */ cpu_loop_exit_restore(cs, retaddr); diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index d8d76968f3..00c7e0d028 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,7 +215,7 @@ do_fault: return code; } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int access_type, int mmu_idx) { UniCore32CPU *cpu =3D UNICORE32_CPU(cs); diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 012552817f..43182b113e 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -50,8 +50,8 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 25 Jan 2018 10:15:41 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M1TKv-1eteja1var-00tXjY; Thu, 25 Jan 2018 16:15:39 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:30 +0100 Message-Id: <20180125151535.25256-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:sHuMrHZYdXNKcjQKvdUPwhnmP//ubjEEzGWLgCJLD+U3lzg3DyR FpHGx6H0S2uMS7wj/ayAEpr/vL6V8OfjLm3PZ6nwCqrZAYIJLVOhHFKeGLzKfs6LbVu8a2W rxp7yLkmZIoV3+j3xOuB46UqQpid/P4RMwUFHux6ORZCEm4+WPl/bQqC37KoB7aI0EiQh7Q /QiwD0ZPHX0KcdXdLPn/w== X-UI-Out-Filterresults: notjunk:1;V01:K0:yhP4FfDfXNE=:N58AjEsevv4emqSUMRSg8f uQR/AeAVuRo71zmuAQam3lSTpZEzWdn7zPI7s8pF1ZbZ3JaT5vyw1TYQ1QO+H8d6X9swQAvXa /U8V+DFH//8qByE0U5WEpfU7LAaHmMe1QLdglsKZyowYvl8GScuk3WMWovqUNqJ4H0ix5nfoT B2pMWpgkwX4ULdgiSABr5SSqktLWzbM1rTaogEZ2n8sdw4z4aihFTFRj/1Bvd5FHdeCsgACum A6sYDXaFQSDxtSTEOql75DBjdvtr6Ifo4Jx3bodxUQ5NAb6WxwxAGjpbnES0KlV/OVT0d0oqR VM1llFbLY9sAFEw96TDGA7LZC9SfBZHW9AoagI238R6MYpxp6j9O7GCsWLs2U+7lagPXJBIN+ 2KvXuQlS/0bvAOrM7V7WvMjEqdvDl5Wg6ufVoiJPbHrynvtwzGybigoRzofWIwCoEt3IRZWtj A2/fSYBZnKmWmaHZP/8Gnz0GYcp0o+Wq9vj5xTW3wR1M2HFLvuGM7DMxy3tu6qdOVRj2Go+oV dZ/zyeH4fgDgqD3K16K+LHSRmbhdRiSrWaDvqciU1Y0cYu6mXgnZdUA/vLCOAp0DG3yvSzMKe d99IJ6m3mZ4EY0i3TjF9THteGZoG0SWdaJS/CwCAi9YJXZt/+NcThzdzDh3T7aObcpz6ZWBBy 43PVj8nzwYLu/L4xjxlpJ3MDTqRqOd3I9GIQx+nIOsqvJyq6fGDkRuoxI16smpvi4K1NhS+mZ Td0xPm3eI+s9LcfG3IVGAUlIMhml0JTywKf25Q== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 3/8] target/m68k: add MC68040 MMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only add MC68040 MMU page table processing and related registers (Special Status Word, Translation Control Register, User Root Pointer and Supervisor Root Pointer). Transparent Translation Registers, DFC/SFC and pflush/ptest will be added later. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-3-laurent@vivier.eu> --- target/m68k/cpu.c | 4 +- target/m68k/cpu.h | 115 +++++++++++++++++++++++-- target/m68k/helper.c | 222 ++++++++++++++++++++++++++++++++++++++++++++= ++-- target/m68k/monitor.c | 2 + target/m68k/op_helper.c | 94 +++++++++++++++++++- target/m68k/translate.c | 2 + 6 files changed, 423 insertions(+), 16 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 03126ba543..98919b358b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -269,9 +269,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D m68k_cpu_handle_mmu_fault; -#else +#if defined(CONFIG_SOFTMMU) + cc->do_unassigned_access =3D m68k_cpu_unassigned_access; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index c60564a047..38a74476ee 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -116,6 +116,12 @@ typedef struct CPUM68KState { /* MMU status. */ struct { uint32_t ar; + uint32_t ssw; + /* 68040 */ + uint16_t tcr; + uint32_t urp; + uint32_t srp; + bool fault; } mmu; =20 /* Control registers. */ @@ -226,6 +232,92 @@ typedef enum { #define M68K_USP 1 #define M68K_ISP 2 =20 +/* bits for 68040 special status word */ +#define M68K_CP_040 0x8000 +#define M68K_CU_040 0x4000 +#define M68K_CT_040 0x2000 +#define M68K_CM_040 0x1000 +#define M68K_MA_040 0x0800 +#define M68K_ATC_040 0x0400 +#define M68K_LK_040 0x0200 +#define M68K_RW_040 0x0100 +#define M68K_SIZ_040 0x0060 +#define M68K_TT_040 0x0018 +#define M68K_TM_040 0x0007 + +#define M68K_TM_040_DATA 0x0001 +#define M68K_TM_040_CODE 0x0002 +#define M68K_TM_040_SUPER 0x0004 + +/* bits for 68040 write back status word */ +#define M68K_WBV_040 0x80 +#define M68K_WBSIZ_040 0x60 +#define M68K_WBBYT_040 0x20 +#define M68K_WBWRD_040 0x40 +#define M68K_WBLNG_040 0x00 +#define M68K_WBTT_040 0x18 +#define M68K_WBTM_040 0x07 + +/* bus access size codes */ +#define M68K_BA_SIZE_MASK 0x60 +#define M68K_BA_SIZE_BYTE 0x20 +#define M68K_BA_SIZE_WORD 0x40 +#define M68K_BA_SIZE_LONG 0x00 +#define M68K_BA_SIZE_LINE 0x60 + +/* bus access transfer type codes */ +#define M68K_BA_TT_MOVE16 0x08 + +/* bits for 68040 MMU status register (mmusr) */ +#define M68K_MMU_B_040 0x0800 +#define M68K_MMU_G_040 0x0400 +#define M68K_MMU_U1_040 0x0200 +#define M68K_MMU_U0_040 0x0100 +#define M68K_MMU_S_040 0x0080 +#define M68K_MMU_CM_040 0x0060 +#define M68K_MMU_M_040 0x0010 +#define M68K_MMU_WP_040 0x0004 +#define M68K_MMU_T_040 0x0002 +#define M68K_MMU_R_040 0x0001 + +#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ + M68K_MMU_U0_040 | M68K_MMU_S_040 | \ + M68K_MMU_CM_040 | M68K_MMU_M_040 | \ + M68K_MMU_WP_040) + +/* bits for 68040 MMU Translation Control Register */ +#define M68K_TCR_ENABLED 0x8000 +#define M68K_TCR_PAGE_8K 0x4000 + +/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ +#define M68K_DESC_WRITEPROT 0x00000004 +#define M68K_DESC_USED 0x00000008 +#define M68K_DESC_MODIFIED 0x00000010 +#define M68K_DESC_CACHEMODE 0x00000060 +#define M68K_DESC_CM_WRTHRU 0x00000000 +#define M68K_DESC_CM_COPYBK 0x00000020 +#define M68K_DESC_CM_SERIAL 0x00000040 +#define M68K_DESC_CM_NCACHE 0x00000060 +#define M68K_DESC_SUPERONLY 0x00000080 +#define M68K_DESC_USERATTR 0x00000300 +#define M68K_DESC_USERATTR_SHIFT 8 +#define M68K_DESC_GLOBAL 0x00000400 +#define M68K_DESC_URESERVED 0x00000800 + +#define M68K_4K_PAGE_MASK (~0xff) +#define M68K_POINTER_BASE(entry) (entry & ~0x1ff) +#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) +#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) +#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) +#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) +#define M68K_8K_PAGE_MASK (~0x7f) +#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) +#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) +#define M68K_UDT_VALID(entry) (entry & 2) +#define M68K_PDT_VALID(entry) (entry & 3) +#define M68K_PDT_INDIRECT(entry) ((entry & 3) =3D=3D 2) +#define M68K_INDIRECT_POINTER(addr) (addr & ~3) + /* m68k Control Registers */ =20 /* ColdFire */ @@ -387,16 +479,23 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fpri= ntf); =20 void register_m68k_insns (CPUM68KState *env); =20 -#ifdef CONFIG_USER_ONLY /* Coldfire Linux uses 8k pages * and m68k linux uses 4k pages - * use the smaller one + * use the smallest one */ #define TARGET_PAGE_BITS 12 -#else -/* Smallest TLB entry size is 1k. */ -#define TARGET_PAGE_BITS 10 -#endif + +enum { + /* 1 bit to define user level / supervisor access */ + ACCESS_SUPER =3D 0x01, + /* 1 bit to indicate direction */ + ACCESS_STORE =3D 0x02, + /* 1 bit to indicate debug access */ + ACCESS_DEBUG =3D 0x04, + /* Type of instruction that generated the access */ + ACCESS_CODE =3D 0x10, /* Code fetch access */ + ACCESS_DATA =3D 0x20, /* Data load/store access */ +}; =20 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 @@ -412,6 +511,7 @@ void register_m68k_insns (CPUM68KState *env); /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user +#define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) { @@ -420,6 +520,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, boo= l ifetch) =20 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); +void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi, + unsigned size); =20 #include "exec/cpu-all.h" =20 diff --git a/target/m68k/helper.c b/target/m68k/helper.c index ef0ec5dadf..f1d3c8c7dd 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -212,6 +212,15 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t= reg, uint32_t val) m68k_switch_sp(env); return; /* MC680[34]0 */ + case M68K_CR_TC: + env->mmu.tcr =3D val; + return; + case M68K_CR_SRP: + env->mmu.srp =3D val; + return; + case M68K_CR_URP: + env->mmu.urp =3D val; + return; case M68K_CR_USP: env->sp[M68K_USP] =3D val; return; @@ -238,12 +247,19 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, u= int32_t reg) case M68K_CR_CACR: return env->cacr; /* MC680[34]0 */ + case M68K_CR_TC: + return env->mmu.tcr; + case M68K_CR_SRP: + return env->mmu.srp; case M68K_CR_USP: return env->sp[M68K_USP]; case M68K_CR_MSP: return env->sp[M68K_SSP]; case M68K_CR_ISP: return env->sp[M68K_ISP]; + /* MC68040/MC68LC040 */ + case M68K_CR_URP: + return env->mmu.urp; } cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", reg); @@ -320,23 +336,215 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, =20 #else =20 -/* MMU */ +/* MMU: 68040 only */ + +static int get_physical_address(CPUM68KState *env, hwaddr *physical, + int *prot, target_ulong address, + int access_type, target_ulong *page_size) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + uint32_t entry; + uint32_t next; + target_ulong page_mask; + bool debug =3D access_type & ACCESS_DEBUG; + int page_bits; + + /* Page Table Root Pointer */ + *prot =3D PAGE_READ | PAGE_WRITE; + if (access_type & ACCESS_CODE) { + *prot |=3D PAGE_EXEC; + } + if (access_type & ACCESS_SUPER) { + next =3D env->mmu.srp; + } else { + next =3D env->mmu.urp; + } + + /* Root Index */ + entry =3D M68K_POINTER_BASE(next) | M68K_ROOT_INDEX(address); + + next =3D ldl_phys(cs->as, entry); + if (!M68K_UDT_VALID(next)) { + return -1; + } + if (!(next & M68K_DESC_USED) && !debug) { + stl_phys(cs->as, entry, next | M68K_DESC_USED); + } + if (next & M68K_DESC_WRITEPROT) { + *prot &=3D ~PAGE_WRITE; + if (access_type & ACCESS_STORE) { + return -1; + } + } + + /* Pointer Index */ + entry =3D M68K_POINTER_BASE(next) | M68K_POINTER_INDEX(address); + + next =3D ldl_phys(cs->as, entry); + if (!M68K_UDT_VALID(next)) { + return -1; + } + if (!(next & M68K_DESC_USED) && !debug) { + stl_phys(cs->as, entry, next | M68K_DESC_USED); + } + if (next & M68K_DESC_WRITEPROT) { + *prot &=3D ~PAGE_WRITE; + if (access_type & ACCESS_STORE) { + return -1; + } + } + + /* Page Index */ + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + entry =3D M68K_8K_PAGE_BASE(next) | M68K_8K_PAGE_INDEX(address); + } else { + entry =3D M68K_4K_PAGE_BASE(next) | M68K_4K_PAGE_INDEX(address); + } + + next =3D ldl_phys(cs->as, entry); + + if (!M68K_PDT_VALID(next)) { + return -1; + } + if (M68K_PDT_INDIRECT(next)) { + next =3D ldl_phys(cs->as, M68K_INDIRECT_POINTER(next)); + } + if (access_type & ACCESS_STORE) { + if (next & M68K_DESC_WRITEPROT) { + if (!(next & M68K_DESC_USED) && !debug) { + stl_phys(cs->as, entry, next | M68K_DESC_USED); + } + } else if ((next & (M68K_DESC_MODIFIED | M68K_DESC_USED)) !=3D + (M68K_DESC_MODIFIED | M68K_DESC_USED) && !debug= ) { + stl_phys(cs->as, entry, + next | (M68K_DESC_MODIFIED | M68K_DESC_USED)); + } + } else { + if (!(next & M68K_DESC_USED) && !debug) { + stl_phys(cs->as, entry, next | M68K_DESC_USED); + } + } + + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + page_bits =3D 13; + } else { + page_bits =3D 12; + } + *page_size =3D 1 << page_bits; + page_mask =3D ~(*page_size - 1); + *physical =3D next & page_mask; + + if (next & M68K_DESC_WRITEPROT) { + *prot &=3D ~PAGE_WRITE; + if (access_type & ACCESS_STORE) { + return -1; + } + } + if (next & M68K_DESC_SUPERONLY) { + if ((access_type & ACCESS_SUPER) =3D=3D 0) { + return -1; + } + } + + return 0; +} =20 -/* TODO: This will need fixing once the MMU is implemented. */ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - return addr; + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + int access_type; + target_ulong page_size; + + if ((env->mmu.tcr & M68K_TCR_ENABLED) =3D=3D 0) { + /* MMU disabled */ + return addr; + } + + access_type =3D ACCESS_DATA | ACCESS_DEBUG; + if (env->sr & SR_S) { + access_type |=3D ACCESS_SUPER; + } + if (get_physical_address(env, &phys_addr, &prot, + addr, access_type, &page_size) !=3D 0) { + return -1; + } + return phys_addr; } =20 int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + hwaddr physical; int prot; + int access_type; + int ret; + target_ulong page_size; + + if ((env->mmu.tcr & M68K_TCR_ENABLED) =3D=3D 0) { + /* MMU disabled */ + tlb_set_page(cs, address & TARGET_PAGE_MASK, + address & TARGET_PAGE_MASK, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + return 0; + } + + if (rw =3D=3D 2) { + access_type =3D ACCESS_CODE; + rw =3D 0; + } else { + access_type =3D ACCESS_DATA; + if (rw) { + access_type |=3D ACCESS_STORE; + } + } =20 - address &=3D TARGET_PAGE_MASK; - prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + if (mmu_idx !=3D MMU_USER_IDX) { + access_type |=3D ACCESS_SUPER; + } + + ret =3D get_physical_address(&cpu->env, &physical, &prot, + address, access_type, &page_size); + if (ret =3D=3D 0) { + address &=3D TARGET_PAGE_MASK; + physical +=3D address & (page_size - 1); + tlb_set_page(cs, address, physical, + prot, mmu_idx, TARGET_PAGE_SIZE); + return 0; + } + /* page fault */ + env->mmu.ssw =3D M68K_ATC_040; + switch (size) { + case 1: + env->mmu.ssw |=3D M68K_BA_SIZE_BYTE; + break; + case 2: + env->mmu.ssw |=3D M68K_BA_SIZE_WORD; + break; + case 4: + env->mmu.ssw |=3D M68K_BA_SIZE_LONG; + break; + } + if (access_type & ACCESS_SUPER) { + env->mmu.ssw |=3D M68K_TM_040_SUPER; + } + if (access_type & ACCESS_CODE) { + env->mmu.ssw |=3D M68K_TM_040_CODE; + } else { + env->mmu.ssw |=3D M68K_TM_040_DATA; + } + if (!(access_type & ACCESS_STORE)) { + env->mmu.ssw |=3D M68K_RW_040; + } + env->mmu.ar =3D address; + cs->exception_index =3D EXCP_ACCESS; + return 1; } =20 /* Notify CPU of a pending interrupt. Prioritization and vectoring should diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 52781e85f0..2b83e3bc0d 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -31,6 +31,8 @@ static const MonitorDef monitor_defs[] =3D { { "ssp", offsetof(CPUM68KState, sp[0]) }, { "usp", offsetof(CPUM68KState, sp[1]) }, { "isp", offsetof(CPUM68KState, sp[2]) }, + { "urp", offsetof(CPUM68KState, mmu.urp) }, + { "srp", offsetof(CPUM68KState, mmu.srp) }, { NULL }, }; =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 67697d4e6d..f023901061 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -360,7 +360,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int = is_hw) sp =3D env->aregs[7]; =20 sp &=3D ~1; - if (cs->exception_index =3D=3D EXCP_ADDRESS) { + if (cs->exception_index =3D=3D EXCP_ACCESS) { + if (env->mmu.fault) { + cpu_abort(cs, "DOUBLE MMU FAULT\n"); + } + env->mmu.fault =3D true; + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* push data 3 */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* push data 2 */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* push data 1 */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* write back 1 / push data 0 */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* write back 1 address */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* write back 2 data */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* write back 2 address */ + sp -=3D 4; + cpu_stl_kernel(env, sp, 0); /* write back 3 data */ + sp -=3D 4; + cpu_stl_kernel(env, sp, env->mmu.ar); /* write back 3 address */ + sp -=3D 4; + cpu_stl_kernel(env, sp, env->mmu.ar); /* fault address */ + sp -=3D 2; + cpu_stw_kernel(env, sp, 0); /* write back 1 status */ + sp -=3D 2; + cpu_stw_kernel(env, sp, 0); /* write back 2 status */ + sp -=3D 2; + cpu_stw_kernel(env, sp, 0); /* write back 3 status */ + sp -=3D 2; + cpu_stw_kernel(env, sp, env->mmu.ssw); /* special status word */ + sp -=3D 4; + cpu_stl_kernel(env, sp, env->mmu.ar); /* effective address */ + do_stack_frame(env, &sp, 7, oldsr, 0, retaddr); + env->mmu.fault =3D false; + if (qemu_loglevel_mask(CPU_LOG_INT)) { + qemu_log(" " + "ssw: %08x ea: %08x\n", + env->mmu.ssw, env->mmu.ar); + } + } else if (cs->exception_index =3D=3D EXCP_ADDRESS) { do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); } else if (cs->exception_index =3D=3D EXCP_ILLEGAL || cs->exception_index =3D=3D EXCP_DIV0 || @@ -408,6 +450,56 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KSt= ate *env) { do_interrupt_all(env, 1); } + +void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, + bool is_exec, int is_asi, unsigned size) +{ + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; +#ifdef DEBUG_UNASSIGNED + qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=3D%d exe= =3D%d\n", + addr, is_write, is_exec); +#endif + if (env =3D=3D NULL) { + /* when called from gdb, env is NULL */ + return; + } + + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ssw |=3D M68K_ATC_040; + /* FIXME: manage MMU table access error */ + env->mmu.ssw &=3D ~M68K_TM_040; + if (env->sr & SR_S) { /* SUPERVISOR */ + env->mmu.ssw |=3D M68K_TM_040_SUPER; + } + if (is_exec) { /* instruction or data */ + env->mmu.ssw |=3D M68K_TM_040_CODE; + } else { + env->mmu.ssw |=3D M68K_TM_040_DATA; + } + env->mmu.ssw &=3D ~M68K_BA_SIZE_MASK; + switch (size) { + case 1: + env->mmu.ssw |=3D M68K_BA_SIZE_BYTE; + break; + case 2: + env->mmu.ssw |=3D M68K_BA_SIZE_WORD; + break; + case 4: + env->mmu.ssw |=3D M68K_BA_SIZE_LONG; + break; + } + + if (!is_write) { + env->mmu.ssw |=3D M68K_RW_040; + } + + env->mmu.ar =3D addr; + + cs->exception_index =3D EXCP_ACCESS; + cpu_loop_exit(cs); + } +} #endif =20 bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ea18df940a..fd6db3e1fc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5980,6 +5980,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, env->current_sp =3D=3D M68K_USP ? "->" : " ", env->sp[M68K= _USP], env->current_sp =3D=3D M68K_ISP ? "->" : " ", env->sp[M68K= _ISP]); cpu_fprintf(f, "VBR =3D 0x%08x\n", env->vbr); + cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n", + env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp); #endif } =20 --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893857890208.73314868756597; Thu, 25 Jan 2018 07:24:17 -0800 (PST) Received: from localhost ([::1]:46247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejNw-0004mf-V4 for importer@patchew.org; Thu, 25 Jan 2018 10:24:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFi-0006Ej-5t for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFd-0000jv-Sl for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:46 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:56604) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFd-0000jH-IH for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:41 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Lb6lR-1f2UQH0Xbl-00kdlc; Thu, 25 Jan 2018 16:15:40 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:31 +0100 Message-Id: <20180125151535.25256-5-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:PEdsEXCr7cEq3aaC4MhFiNJJgwF8Cp1nMyVZYv3VVCRzlCO09ex 7beyic4uc/NBRUWB+SQX9g0Tu4HbTvDqVn/jOMB7cUh6crQDVSsuroJDCSzuIxfLwH6VLq4 acVOAuUe8eUpwqMCECtitjKH7auTmFO0a1E+/J5JcIHXrla7/vDJ6sklQ0A/8YW4izN6SYr s/JKGhBCgh26OyLbd/iuA== X-UI-Out-Filterresults: notjunk:1;V01:K0:de3SzzfcEho=:2Rtmcw955ermItQeeHMOuS +a4E5CSFiTKLTrlVqnG1B2A+Vdj1DwK7RHCIYQpxncEPhCqE/E75k4oHNES4iylllGLEeLHoa wJx35fC3MLD1u7d45WprobUnq3zcAlauY3oKF4GJDDPLRVkvFU4NDFN8WljKuqjcSHw+tzMX+ /bgqLjXk93muYsVO59iZw8UNd3rSpri/HE/ZfQi9DIUfHXRft0m894QTHJ6aFkozg3PCkifT4 b7sVd4IseukXpWTYdBeLU+YKbf7a6gc7JDTky40xdyCif24TYkPqcPefSM84IqatdCd7I/0Et zT/pmzGpN7Ar/5ww4q5hWgwpx7mNWGYCzEqkdK2wPnWYzzaNOnKf+z9vOzMnSduvsfWluVS3e 2RgVVbceZIEMQr8MoKpAaHwEH3cONOr8H48CKkYaVaIay/soUclw5wYxnTs/jC1jsBjADOiLz 2Qmqo9QUEAf2R4WrZovMYCbQL/q+RoETnxcLH6wsWoR37FifZnfdDOHhytwN21qnDkmNcSP7P kkrNmo/jSKug8DoLrOfezPhX4PrG4ybL7l+RK2XcxzYNLei/o5aH2EtWhxhoDX3YbHVZKSCd2 fR4MGt6u3Bnmf5XI3nC+AbdRQyBQvNiPSq4hTEMkV+Ldk+qksh2MAJTwGsXuJmTn/6OFg3nMN U0kNhThmC9RxJLt5KO0YqaGn9eAL0o/FyJ8Ryr9ueH2znA/JSbq6239EWaFjIfBMCJAhmLIE5 YCnzSJPBcHoEG2MpkNtArgJFkDtCcG8wuGOnXw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PULL 4/8] target/m68k: add Transparent Translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-4-laurent@vivier.eu> --- target/m68k/cpu.h | 18 +++++++++++ target/m68k/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/monitor.c | 4 +++ target/m68k/translate.c | 3 ++ 4 files changed, 104 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 38a74476ee..1c2bbac56d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -76,6 +76,14 @@ #define EXCP_RTE 0x100 #define EXCP_HALT_INSN 0x101 =20 +#define M68K_DTTR0 0 +#define M68K_DTTR1 1 +#define M68K_ITTR0 2 +#define M68K_ITTR1 3 + +#define M68K_MAX_TTR 2 +#define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] + #define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 @@ -122,6 +130,7 @@ typedef struct CPUM68KState { uint32_t urp; uint32_t srp; bool fault; + uint32_t ttr[4]; } mmu; =20 /* Control registers. */ @@ -318,6 +327,15 @@ typedef enum { #define M68K_PDT_INDIRECT(entry) ((entry & 3) =3D=3D 2) #define M68K_INDIRECT_POINTER(addr) (addr & ~3) =20 +/* bits for 68040 MMU Transparent Translation Registers */ +#define M68K_TTR_ADDR_BASE 0xff000000 +#define M68K_TTR_ADDR_MASK 0x00ff0000 +#define M68K_TTR_ADDR_MASK_SHIFT 8 +#define M68K_TTR_ENABLED 0x00008000 +#define M68K_TTR_SFIELD 0x00006000 +#define M68K_TTR_SFIELD_USER 0x0000 +#define M68K_TTR_SFIELD_SUPER 0x2000 + /* m68k Control Registers */ =20 /* ColdFire */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index f1d3c8c7dd..58528f64ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -230,6 +230,19 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t= reg, uint32_t val) case M68K_CR_ISP: env->sp[M68K_ISP] =3D val; return; + /* MC68040/MC68LC040 */ + case M68K_CR_ITT0: + env->mmu.ttr[M68K_ITTR0] =3D val; + return; + case M68K_CR_ITT1: + env->mmu.ttr[M68K_ITTR1] =3D val; + return; + case M68K_CR_DTT0: + env->mmu.ttr[M68K_DTTR0] =3D val; + return; + case M68K_CR_DTT1: + env->mmu.ttr[M68K_DTTR1] =3D val; + return; } cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x =3D 0x%= x\n", reg, val); @@ -260,6 +273,14 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, ui= nt32_t reg) /* MC68040/MC68LC040 */ case M68K_CR_URP: return env->mmu.urp; + case M68K_CR_ITT0: + return env->mmu.ttr[M68K_ITTR0]; + case M68K_CR_ITT1: + return env->mmu.ttr[M68K_ITTR1]; + case M68K_CR_DTT0: + return env->mmu.ttr[M68K_DTTR0]; + case M68K_CR_DTT1: + return env->mmu.ttr[M68K_DTTR1]; } cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", reg); @@ -338,6 +359,53 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, =20 /* MMU: 68040 only */ =20 +static int check_TTR(uint32_t ttr, int *prot, target_ulong addr, + int access_type) +{ + uint32_t base, mask; + + /* check if transparent translation is enabled */ + if ((ttr & M68K_TTR_ENABLED) =3D=3D 0) { + return 0; + } + + /* check mode access */ + switch (ttr & M68K_TTR_SFIELD) { + case M68K_TTR_SFIELD_USER: + /* match only if user */ + if ((access_type & ACCESS_SUPER) !=3D 0) { + return 0; + } + break; + case M68K_TTR_SFIELD_SUPER: + /* match only if supervisor */ + if ((access_type & ACCESS_SUPER) =3D=3D 0) { + return 0; + } + break; + default: + /* all other values disable mode matching (FC2) */ + break; + } + + /* check address matching */ + + base =3D ttr & M68K_TTR_ADDR_BASE; + mask =3D (ttr & M68K_TTR_ADDR_MASK) ^ M68K_TTR_ADDR_MASK; + mask <<=3D M68K_TTR_ADDR_MASK_SHIFT; + + if ((addr & mask) !=3D (base & mask)) { + return 0; + } + + *prot =3D PAGE_READ | PAGE_EXEC; + if ((ttr & M68K_DESC_WRITEPROT) =3D=3D 0) { + *prot |=3D PAGE_WRITE; + } + + return 1; +} + static int get_physical_address(CPUM68KState *env, hwaddr *physical, int *prot, target_ulong address, int access_type, target_ulong *page_size) @@ -349,6 +417,17 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, target_ulong page_mask; bool debug =3D access_type & ACCESS_DEBUG; int page_bits; + int i; + + /* Transparent Translation (physical =3D logical) */ + for (i =3D 0; i < M68K_MAX_TTR; i++) { + if (check_TTR(env->mmu.TTR(access_type, i), + prot, address, access_type)) { + *physical =3D address & TARGET_PAGE_MASK; + *page_size =3D TARGET_PAGE_SIZE; + return 0; + } + } =20 /* Page Table Root Pointer */ *prot =3D PAGE_READ | PAGE_WRITE; diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 2b83e3bc0d..a20af6b09c 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -33,6 +33,10 @@ static const MonitorDef monitor_defs[] =3D { { "isp", offsetof(CPUM68KState, sp[2]) }, { "urp", offsetof(CPUM68KState, mmu.urp) }, { "srp", offsetof(CPUM68KState, mmu.srp) }, + { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) }, + { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, + { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, + { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, { NULL }, }; =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index fd6db3e1fc..b33b3c6828 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5982,6 +5982,9 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, cpu_fprintf(f, "VBR =3D 0x%08x\n", env->vbr); cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n", env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp); + cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", + env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], + env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); #endif } =20 --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893488532768.4745549444445; Thu, 25 Jan 2018 07:18:08 -0800 (PST) Received: from localhost ([::1]:46103 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejHz-0007ax-N3 for importer@patchew.org; Thu, 25 Jan 2018 10:18:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFg-0006EK-OR for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFe-0000kO-Lg for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:44 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:53786) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFe-0000je-8T for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:42 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MHKOl-1eaYWd2J87-00E1yI; Thu, 25 Jan 2018 16:15:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:32 +0100 Message-Id: <20180125151535.25256-6-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:4hTDSXMpXQ4DL4/WJ91Zf3DIO93HiiTv/wWRibI9L4LD1mYWtKN P6OCNCJJQYBZmMD5m+C29cYlly3jnktOix/I5PcxJhPy1LMYtcEZcKzlqDehLWa446GMTjB NM94B2A4+MwD9vTNmOQaafWvptYJyFmFHQjo0zRosPJMJnkKb7zJOHlr2kNiBWHDMsy2tui ekZD12XXPmK0ygikNL5kQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:2grLtj2dQK8=:eMjkcIdJ9HtsiKQ81wcVGv Hgo4b3vTQggoWxgqn2YxeT3TRKtrk2D+DL0Tdcb78xSNwXYcxfHkA9JxlVTD86z78iTtfm1jS 7PI/s7lo9rnVWH+/RQ8KRVkYF7iYU89DCZoZphx6jjXb+x6EkjzR4Y4KGM9vI8EsJuokWA+gA pxH615eGDMyAbjBT9c5qWgRq3VObifi/rkAWQtzGMG3M4lBKMc6486TkAKj3DixpYmd+piGVb qd7P98G9zOVLBYgNaxZbG3hgadG/qPj2OMYHY7FU1ogtnidFbZme7p5lqtM0sSWdlYBW691zc /EfsfweEOnaSmTrme87Ju56Ey175j68P75AFXc1y+tAciU1bELxe9vK+Ps8doox3OrVPQlX5V 7rtGPaWTFwCpWnbfXmmg45rCf+5eSgQbBVVF8vrEac8ZfTDvgt5YNIbT+U32pz/0kPA47NmF9 4OPCpEFDGy3tUBMJ0nrvCHhAStO1c5KNjjUG3U4q+jDsV4lrJrjpha3ALmS2bcbtjhJqMz2ka PVGfeoVjmYOienO0cjCvOPaI+kZNGNxFnUMVytf0gUBvsDZ9MDp/cVx1Qhu4iovCiDE9m0JGF mmTa/v35cMCWP55bi6mA0xw1KUsHHUuYFN0EyAkUKjqlhpOQaqQK0NEQ7Dsjr4x3hmh3uZY2G TzFf0wXHoAALk1/5cQy+8yL9t9ngxjGKF2TuZh8dn6rPcI61WyygOMNjoy4uyXAGJoUNr2NkG 90B1/NfxVObf1rK8AWenW4j+TrLjRHyRghJiKg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 5/8] target/m68k: add index parameter to gen_load()/gen_store() and Co. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction "moves" can select source and destination address space (user or kernel). This patch modifies all the load/store functions to be able to provide the address space the caller wants to use instead of using the current one. All the callers are modified to provide the default address space to these functions. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-5-laurent@vivier.eu> --- target/m68k/translate.c | 125 +++++++++++++++++++++++++-------------------= ---- 1 file changed, 66 insertions(+), 59 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b33b3c6828..ecb89e4239 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -281,10 +281,10 @@ static inline void gen_addr_fault(DisasContext *s) =20 /* Generate a load from the specified address. Narrow values are sign extended to full register width. */ -static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int s= ign) +static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr, + int sign, int index) { TCGv tmp; - int index =3D IS_USER(s); tmp =3D tcg_temp_new_i32(); switch(opsize) { case OS_BYTE: @@ -309,9 +309,9 @@ static inline TCGv gen_load(DisasContext * s, int opsiz= e, TCGv addr, int sign) } =20 /* Generate a store. */ -static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv = val) +static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv = val, + int index) { - int index =3D IS_USER(s); switch(opsize) { case OS_BYTE: tcg_gen_qemu_st8(val, addr, index); @@ -336,13 +336,13 @@ typedef enum { /* Generate an unsigned load if VAL is 0 a signed load if val is -1, otherwise generate a store. */ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, - ea_what what) + ea_what what, int index) { if (what =3D=3D EA_STORE) { - gen_store(s, opsize, addr, val); + gen_store(s, opsize, addr, val, index); return store_dummy; } else { - return gen_load(s, opsize, addr, what =3D=3D EA_LOADS); + return gen_load(s, opsize, addr, what =3D=3D EA_LOADS, index); } } =20 @@ -464,7 +464,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) } if ((ext & 3) !=3D 0) { /* memory indirect */ - base =3D gen_load(s, OS_LONG, add, 0); + base =3D gen_load(s, OS_LONG, add, 0, IS_USER(s)); if ((ext & 0x44) =3D=3D 4) { add =3D gen_addr_index(s, ext, tmp); tcg_gen_add_i32(tmp, add, base); @@ -793,7 +793,8 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s,= uint16_t insn, a write otherwise it is a read (0 =3D=3D sign extend, -1 =3D=3D zero ex= tend). ADDRP is non-null for readwrite operands. */ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int = reg0, - int opsize, TCGv val, TCGv *addrp, ea_what what) + int opsize, TCGv val, TCGv *addrp, ea_what what, + int index) { TCGv reg, tmp, result; int32_t offset; @@ -817,10 +818,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasConte= xt *s, int mode, int reg0, } case 2: /* Indirect register */ reg =3D get_areg(s, reg0); - return gen_ldst(s, opsize, reg, val, what); + return gen_ldst(s, opsize, reg, val, what, index); case 3: /* Indirect postincrement. */ reg =3D get_areg(s, reg0); - result =3D gen_ldst(s, opsize, reg, val, what); + result =3D gen_ldst(s, opsize, reg, val, what, index); if (what =3D=3D EA_STORE || !addrp) { TCGv tmp =3D tcg_temp_new(); if (reg0 =3D=3D 7 && opsize =3D=3D OS_BYTE && @@ -844,7 +845,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, *addrp =3D tmp; } } - result =3D gen_ldst(s, opsize, tmp, val, what); + result =3D gen_ldst(s, opsize, tmp, val, what, index); if (what =3D=3D EA_STORE || !addrp) { delay_set_areg(s, reg0, tmp, false); } @@ -863,7 +864,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, *addrp =3D tmp; } } - return gen_ldst(s, opsize, tmp, val, what); + return gen_ldst(s, opsize, tmp, val, what, index); case 7: /* Other */ switch (reg0) { case 0: /* Absolute short. */ @@ -904,11 +905,11 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasConte= xt *s, int mode, int reg0, } =20 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, - int opsize, TCGv val, TCGv *addrp, ea_what what) + int opsize, TCGv val, TCGv *addrp, ea_what what, int in= dex) { int mode =3D extract32(insn, 3, 3); int reg0 =3D REG(insn, 0); - return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what); + return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index= ); } =20 static TCGv_ptr gen_fp_ptr(int freg) @@ -941,11 +942,11 @@ static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src) tcg_temp_free_i64(t64); } =20 -static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr f= p) +static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr f= p, + int index) { TCGv tmp; TCGv_i64 t64; - int index =3D IS_USER(s); =20 t64 =3D tcg_temp_new_i64(); tmp =3D tcg_temp_new(); @@ -995,11 +996,11 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp) tcg_temp_free_i64(t64); } =20 -static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr = fp) +static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr = fp, + int index) { TCGv tmp; TCGv_i64 t64; - int index =3D IS_USER(s); =20 t64 =3D tcg_temp_new_i64(); tmp =3D tcg_temp_new(); @@ -1050,17 +1051,18 @@ static void gen_store_fp(DisasContext *s, int opsiz= e, TCGv addr, TCGv_ptr fp) } =20 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr, - TCGv_ptr fp, ea_what what) + TCGv_ptr fp, ea_what what, int index) { if (what =3D=3D EA_STORE) { - gen_store_fp(s, opsize, addr, fp); + gen_store_fp(s, opsize, addr, fp, index); } else { - gen_load_fp(s, opsize, addr, fp); + gen_load_fp(s, opsize, addr, fp, index); } } =20 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode, - int reg0, int opsize, TCGv_ptr fp, ea_what what) + int reg0, int opsize, TCGv_ptr fp, ea_what what, + int index) { TCGv reg, addr, tmp; TCGv_i64 t64; @@ -1108,11 +1110,11 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, return -1; case 2: /* Indirect register */ addr =3D get_areg(s, reg0); - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); return 0; case 3: /* Indirect postincrement. */ addr =3D cpu_aregs[reg0]; - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize)); return 0; case 4: /* Indirect predecrememnt. */ @@ -1120,7 +1122,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCon= text *s, int mode, if (IS_NULL_QREG(addr)) { return -1; } - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); tcg_gen_mov_i32(cpu_aregs[reg0], addr); return 0; case 5: /* Indirect displacement. */ @@ -1130,7 +1132,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCon= text *s, int mode, if (IS_NULL_QREG(addr)) { return -1; } - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); return 0; case 7: /* Other */ switch (reg0) { @@ -1199,11 +1201,11 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, } =20 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn, - int opsize, TCGv_ptr fp, ea_what what) + int opsize, TCGv_ptr fp, ea_what what, int index) { int mode =3D extract32(insn, 3, 3); int reg0 =3D REG(insn, 0); - return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what); + return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index); } =20 typedef struct { @@ -1423,7 +1425,7 @@ static void gen_lookup_tb(DisasContext *s) =20 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ result =3D gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ - op_sign ? EA_LOADS : EA_LOADU); \ + op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \ if (IS_NULL_QREG(result)) { \ gen_addr_fault(s); \ return; \ @@ -1431,7 +1433,8 @@ static void gen_lookup_tb(DisasContext *s) } while (0) =20 #define DEST_EA(env, insn, opsize, val, addrp) do { \ - TCGv ea_result =3D gen_ea(env, s, insn, opsize, val, addrp, EA_STO= RE); \ + TCGv ea_result =3D gen_ea(env, s, insn, opsize, val, addrp, \ + EA_STORE, IS_USER(s)); \ if (IS_NULL_QREG(ea_result)) { \ gen_addr_fault(s); \ return; \ @@ -1768,13 +1771,14 @@ DISAS_INSN(abcd_mem) /* Indirect pre-decrement load (mode 4) */ =20 src =3D gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU); + NULL_QREG, NULL, EA_LOADU, IS_USER(s)); dest =3D gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU); + NULL_QREG, &addr, EA_LOADU, IS_USER(s)); =20 bcd_add(dest, src); =20 - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, + EA_STORE, IS_USER(s)); =20 bcd_flags(dest); } @@ -1804,13 +1808,14 @@ DISAS_INSN(sbcd_mem) /* Indirect pre-decrement load (mode 4) */ =20 src =3D gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU); + NULL_QREG, NULL, EA_LOADU, IS_USER(s)); dest =3D gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU); + NULL_QREG, &addr, EA_LOADU, IS_USER(s)); =20 bcd_sub(dest, src); =20 - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, + EA_STORE, IS_USER(s)); =20 bcd_flags(dest); } @@ -1947,7 +1952,7 @@ static void gen_push(DisasContext *s, TCGv val) =20 tmp =3D tcg_temp_new(); tcg_gen_subi_i32(tmp, QREG_SP, 4); - gen_store(s, OS_LONG, tmp, val); + gen_store(s, OS_LONG, tmp, val, IS_USER(s)); tcg_gen_mov_i32(QREG_SP, tmp); tcg_temp_free(tmp); } @@ -2016,7 +2021,7 @@ DISAS_INSN(movem) /* memory to register */ for (i =3D 0; i < 16; i++) { if (mask & (1 << i)) { - r[i] =3D gen_load(s, opsize, addr, 1); + r[i] =3D gen_load(s, opsize, addr, 1, IS_USER(s)); tcg_gen_add_i32(addr, addr, incr); } } @@ -2048,10 +2053,10 @@ DISAS_INSN(movem) */ tmp =3D tcg_temp_new(); tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); - gen_store(s, opsize, addr, tmp); + gen_store(s, opsize, addr, tmp, IS_USER(s)); tcg_temp_free(tmp); } else { - gen_store(s, opsize, addr, mreg(i)); + gen_store(s, opsize, addr, mreg(i), IS_USER(s)); } } } @@ -2059,7 +2064,7 @@ DISAS_INSN(movem) } else { for (i =3D 0; i < 16; i++) { if (mask & (1 << i)) { - gen_store(s, opsize, addr, mreg(i)); + gen_store(s, opsize, addr, mreg(i), IS_USER(s)); tcg_gen_add_i32(addr, addr, incr); } } @@ -2779,7 +2784,7 @@ static void gen_link(DisasContext *s, uint16_t insn, = int32_t offset) reg =3D AREG(insn, 0); tmp =3D tcg_temp_new(); tcg_gen_subi_i32(tmp, QREG_SP, 4); - gen_store(s, OS_LONG, tmp, reg); + gen_store(s, OS_LONG, tmp, reg, IS_USER(s)); if ((insn & 7) !=3D 7) { tcg_gen_mov_i32(reg, tmp); } @@ -2812,7 +2817,7 @@ DISAS_INSN(unlk) src =3D tcg_temp_new(); reg =3D AREG(insn, 0); tcg_gen_mov_i32(src, reg); - tmp =3D gen_load(s, OS_LONG, src, 0); + tmp =3D gen_load(s, OS_LONG, src, 0, IS_USER(s)); tcg_gen_mov_i32(reg, tmp); tcg_gen_addi_i32(QREG_SP, src, 4); tcg_temp_free(src); @@ -2839,7 +2844,7 @@ DISAS_INSN(rtd) TCGv tmp; int16_t offset =3D read_im16(env, s); =20 - tmp =3D gen_load(s, OS_LONG, QREG_SP, 0); + tmp =3D gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s)); tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4); gen_jmp(s, tmp); } @@ -2848,7 +2853,7 @@ DISAS_INSN(rts) { TCGv tmp; =20 - tmp =3D gen_load(s, OS_LONG, QREG_SP, 0); + tmp =3D gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s)); tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); gen_jmp(s, tmp); } @@ -3084,15 +3089,15 @@ DISAS_INSN(subx_mem) =20 addr_src =3D AREG(insn, 0); tcg_gen_subi_i32(addr_src, addr_src, opsize); - src =3D gen_load(s, opsize, addr_src, 1); + src =3D gen_load(s, opsize, addr_src, 1, IS_USER(s)); =20 addr_dest =3D AREG(insn, 9); tcg_gen_subi_i32(addr_dest, addr_dest, opsize); - dest =3D gen_load(s, opsize, addr_dest, 1); + dest =3D gen_load(s, opsize, addr_dest, 1, IS_USER(s)); =20 gen_subx(s, src, dest, opsize); =20 - gen_store(s, opsize, addr_dest, QREG_CC_N); + gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); } =20 DISAS_INSN(mov3q) @@ -3144,10 +3149,10 @@ DISAS_INSN(cmpm) =20 /* Post-increment load (mode 3) from Ay. */ src =3D gen_ea_mode(env, s, 3, REG(insn, 0), opsize, - NULL_QREG, NULL, EA_LOADS); + NULL_QREG, NULL, EA_LOADS, IS_USER(s)); /* Post-increment load (mode 3) from Ax. */ dst =3D gen_ea_mode(env, s, 3, REG(insn, 9), opsize, - NULL_QREG, NULL, EA_LOADS); + NULL_QREG, NULL, EA_LOADS, IS_USER(s)); =20 gen_update_cc_cmp(s, dst, src, opsize); } @@ -3290,15 +3295,15 @@ DISAS_INSN(addx_mem) =20 addr_src =3D AREG(insn, 0); tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); - src =3D gen_load(s, opsize, addr_src, 1); + src =3D gen_load(s, opsize, addr_src, 1, IS_USER(s)); =20 addr_dest =3D AREG(insn, 9); tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); - dest =3D gen_load(s, opsize, addr_dest, 1); + dest =3D gen_load(s, opsize, addr_dest, 1, IS_USER(s)); =20 gen_addx(s, src, dest, opsize); =20 - gen_store(s, opsize, addr_dest, QREG_CC_N); + gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); } =20 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) @@ -4328,9 +4333,9 @@ DISAS_INSN(chk2) addr2 =3D tcg_temp_new(); tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize)); =20 - bound1 =3D gen_load(s, opsize, addr1, 1); + bound1 =3D gen_load(s, opsize, addr1, 1, IS_USER(s)); tcg_temp_free(addr1); - bound2 =3D gen_load(s, opsize, addr2, 1); + bound2 =3D gen_load(s, opsize, addr2, 1, IS_USER(s)); tcg_temp_free(addr2); =20 reg =3D tcg_temp_new(); @@ -4843,7 +4848,8 @@ DISAS_INSN(fpu) case 3: /* fmove out */ cpu_src =3D gen_fp_ptr(REG(ext, 7)); opsize =3D ext_opsize(ext, 10); - if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) =3D=3D -1) { + if (gen_ea_fp(env, s, insn, opsize, cpu_src, + EA_STORE, IS_USER(s)) =3D=3D -1) { gen_addr_fault(s); } gen_helper_ftst(cpu_env, cpu_src); @@ -4865,7 +4871,8 @@ DISAS_INSN(fpu) /* Source effective address. */ opsize =3D ext_opsize(ext, 10); cpu_src =3D gen_fp_result_ptr(); - if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) =3D=3D -1) { + if (gen_ea_fp(env, s, insn, opsize, cpu_src, + EA_LOADS, IS_USER(s)) =3D=3D -1) { gen_addr_fault(s); return; } @@ -5264,7 +5271,7 @@ DISAS_INSN(mac) tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); /* Load the value now to ensure correct exception behavior. Perform writeback after reading the MAC inputs. */ - loadval =3D gen_load(s, OS_LONG, addr, 0); + loadval =3D gen_load(s, OS_LONG, addr, 0, IS_USER(s)); =20 acc ^=3D 1; rx =3D (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893666212796.903630792094; Thu, 25 Jan 2018 07:21:06 -0800 (PST) Received: from localhost ([::1]:46123 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejKi-0001mw-9U for importer@patchew.org; Thu, 25 Jan 2018 10:20:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFi-0006El-7d for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFe-0000kk-W8 for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:46 -0500 Received: from mout.kundenserver.de ([212.227.126.134]:53026) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFe-0000js-MB for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:42 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MZhpC-1eMWAt0k2Q-00LZxb; Thu, 25 Jan 2018 16:15:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:33 +0100 Message-Id: <20180125151535.25256-7-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:LEdtwIXqKFyFazPGZ/O8CdUeFvXVnxbSxz66qwi0Swd5i3D5pFV hga3wrmWRf3xcNRiWtDMmEZLMVvx1+udPQfdnsQV7jTNcNMqtDG52PWVlpv2fSpLlk+WI0b x5INjwT3RAFW7QlGtu0T7n5bI4vUfckKd1LrOEfDeaJeej6oqLlQKIqU2OWHrQliq91XDw+ XOmzlUsCCjr6RYg3dGSNw== X-UI-Out-Filterresults: notjunk:1;V01:K0:iTnfBwOQRto=:MYvMAL3DaXkVeUVQsGBJC9 re3+qjMUJRRIPHK1UTfrxZ/rRR4tcu/z0QWsggLsiRIz3fbK2abSPKrpqBlySTvD2XyAT2/G4 H9ZE/AlPdr0Wyv1/n9vSh9OXbPG9GSawDiJIrndKLkWIMvPIRz54bUr7WBvpn9+GdXBSbqJZw Dhd79k3DTTggD+bxCMWvvvYeyZEIZaFCyGPHrAGvWkGQ7m59xyVQDhDzBWH5H6a1OfKTaRfLV RjlJTz9IeRvVULO7pl/IIxqtsDURX+lmKHwrxANFglJ+DOjgXDCk8LO1q8WnkhxDRrBxE5IzY 6tt52cDdRhpMN+Vy2p4rikUYZfibCzzWvZVtAY2NQkgw8gLWfqTA3/I14piVC4583kOvnGf34 HSNfCCcZaa+2mH3aZYVDlWsh2KmY7Ar53K/GrmjRnQu6RC6hYBakOb2dVLWd2FxlWOsJFz6jj THU0yzYpFx73HgRc2JEQgd8/ZcZ4K3TDbPIe00R3pAHzzY8Fjl6iJdLuMw1vxaTOGkpuVqOwX G+/b4SDk/3ahYwJrZpfGTWFttyPskSoTJBsrQf31MO1SiuNu7B24jZbmnMDXpHE3Fuo0N1RBq VwB3HdIHWPfDrRdHe/ulOej5jCEey5J56OdiPMRYxIUj7NMKCVGXoZlfT2DTTVZ+1lJkOpG5X K248dAG0O9wk2eirgB0owU2QgGGIgXGDbwAHx1dvqc/+vH5tmhjs8LUmo2k56rhqJ6fulHlL5 LIF6drz5IlaYXp+zA/i+3J+n2tgYmb+Fkm5tDg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 6/8] target/m68k: add moves X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" and introduce SFC and DFC control registers. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-6-laurent@vivier.eu> --- target/m68k/cpu.h | 19 ++++++++++++-- target/m68k/helper.c | 10 +++++++ target/m68k/monitor.c | 2 ++ target/m68k/op_helper.c | 4 +-- target/m68k/translate.c | 70 +++++++++++++++++++++++++++++++++++++++++++++= +--- 5 files changed, 98 insertions(+), 7 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 1c2bbac56d..cc1759bb5d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -138,6 +138,8 @@ typedef struct CPUM68KState { uint32_t mbar; uint32_t rambar0; uint32_t cacr; + uint32_t sfc; + uint32_t dfc; =20 int pending_vector; int pending_level; @@ -544,13 +546,26 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr = addr, =20 #include "exec/cpu-all.h" =20 +/* TB flags */ +#define TB_FLAGS_MACSR 0x0f +#define TB_FLAGS_MSR_S_BIT 13 +#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) +#define TB_FLAGS_SFC_S_BIT 14 +#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) +#define TB_FLAGS_DFC_S_BIT 15 +#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) + static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *p= c, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D (env->sr & SR_S) /* Bit 13 */ - | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } } =20 #endif diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 58528f64ff..80db0b75b0 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -203,6 +203,12 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t= reg, uint32_t val) =20 switch (reg) { /* MC680[1234]0 */ + case M68K_CR_SFC: + env->sfc =3D val & 7; + return; + case M68K_CR_DFC: + env->dfc =3D val & 7; + return; case M68K_CR_VBR: env->vbr =3D val; return; @@ -254,6 +260,10 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, ui= nt32_t reg) =20 switch (reg) { /* MC680[1234]0 */ + case M68K_CR_SFC: + return env->sfc; + case M68K_CR_DFC: + return env->dfc; case M68K_CR_VBR: return env->vbr; /* MC680[234]0 */ diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index a20af6b09c..c31feb4b02 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -31,6 +31,8 @@ static const MonitorDef monitor_defs[] =3D { { "ssp", offsetof(CPUM68KState, sp[0]) }, { "usp", offsetof(CPUM68KState, sp[1]) }, { "isp", offsetof(CPUM68KState, sp[2]) }, + { "sfc", offsetof(CPUM68KState, sfc) }, + { "dfc", offsetof(CPUM68KState, dfc) }, { "urp", offsetof(CPUM68KState, mmu.urp) }, { "srp", offsetof(CPUM68KState, mmu.srp) }, { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) }, diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index f023901061..4609caa546 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -399,8 +399,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int i= s_hw) env->mmu.fault =3D false; if (qemu_loglevel_mask(CPU_LOG_INT)) { qemu_log(" " - "ssw: %08x ea: %08x\n", - env->mmu.ssw, env->mmu.ar); + "ssw: %08x ea: %08x sfc: %d dfc: %d\n", + env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); } } else if (cs->exception_index =3D=3D EXCP_ADDRESS) { do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ecb89e4239..c0edaa533c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -115,7 +115,6 @@ typedef struct DisasContext { int is_jmp; CCOp cc_op; /* Current CC operation */ int cc_op_synced; - int user; struct TranslationBlock *tb; int singlestep_enabled; TCGv_i64 mactmp; @@ -178,7 +177,11 @@ static void do_writebacks(DisasContext *s) #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 #else -#define IS_USER(s) s->user +#define IS_USER(s) (!(s->tb->flags & TB_FLAGS_MSR_S)) +#define SFC_INDEX(s) ((s->tb->flags & TB_FLAGS_SFC_S) ? \ + MMU_KERNEL_IDX : MMU_USER_IDX) +#define DFC_INDEX(s) ((s->tb->flags & TB_FLAGS_DFC_S) ? \ + MMU_KERNEL_IDX : MMU_USER_IDX) #endif =20 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t in= sn); @@ -4453,6 +4456,64 @@ DISAS_INSN(move_from_sr) } =20 #if defined(CONFIG_SOFTMMU) +DISAS_INSN(moves) +{ + int opsize; + uint16_t ext; + TCGv reg; + TCGv addr; + int extend; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + ext =3D read_im16(env, s); + + opsize =3D insn_opsize(insn); + + if (ext & 0x8000) { + /* address register */ + reg =3D AREG(ext, 12); + extend =3D 1; + } else { + /* data register */ + reg =3D DREG(ext, 12); + extend =3D 0; + } + + addr =3D gen_lea(env, s, insn, opsize); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + + if (ext & 0x0800) { + /* from reg to ea */ + gen_store(s, opsize, addr, reg, DFC_INDEX(s)); + } else { + /* from ea to reg */ + TCGv tmp =3D gen_load(s, opsize, addr, 0, SFC_INDEX(s)); + if (extend) { + gen_ext(reg, tmp, opsize, 1); + } else { + gen_partset_reg(opsize, reg, tmp); + } + } + switch (extract32(insn, 3, 3)) { + case 3: /* Indirect postincrement. */ + tcg_gen_addi_i32(AREG(insn, 0), addr, + REG(insn, 0) =3D=3D 7 && opsize =3D=3D OS_BYTE + ? 2 + : opsize_bytes(opsize)); + break; + case 4: /* Indirect predecrememnt. */ + tcg_gen_mov_i32(AREG(insn, 0), addr); + break; + } +} + DISAS_INSN(move_to_sr) { if (IS_USER(s)) { @@ -5607,6 +5668,9 @@ void register_m68k_insns (CPUM68KState *env) BASE(bitop_im, 08c0, ffc0); INSN(arith_im, 0a80, fff8, CF_ISA_A); INSN(arith_im, 0a00, ff00, M68000); +#if defined(CONFIG_SOFTMMU) + INSN(moves, 0e00, ff00, M68000); +#endif INSN(cas, 0ac0, ffc0, CAS); INSN(cas, 0cc0, ffc0, CAS); INSN(cas, 0ec0, ffc0, CAS); @@ -5828,7 +5892,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_synced =3D 1; dc->singlestep_enabled =3D cs->singlestep_enabled; - dc->user =3D (env->sr & SR_S) =3D=3D 0; dc->done_mac =3D 0; dc->writeback_mask =3D 0; num_insns =3D 0; @@ -5987,6 +6050,7 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, env->current_sp =3D=3D M68K_USP ? "->" : " ", env->sp[M68K= _USP], env->current_sp =3D=3D M68K_ISP ? "->" : " ", env->sp[M68K= _ISP]); cpu_fprintf(f, "VBR =3D 0x%08x\n", env->vbr); + cpu_fprintf(f, "SFC =3D %x DFC %x\n", env->sfc, env->dfc); cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n", env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp); cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893668492746.12305765725; Thu, 25 Jan 2018 07:21:08 -0800 (PST) Received: from localhost ([::1]:46122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejKh-0001l8-7o for importer@patchew.org; Thu, 25 Jan 2018 10:20:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFi-0006Em-9C for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFf-0000lD-KP for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:46 -0500 Received: from mout.kundenserver.de ([212.227.126.134]:62674) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFf-0000kI-An for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:43 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LgtFa-1fAz8d2eTW-00oBbP; Thu, 25 Jan 2018 16:15:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:34 +0100 Message-Id: <20180125151535.25256-8-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:gBa5kLY2bx+pRPpNmc2vvWJ/eOzUa6y9vzDsyG1NGRm/ompn5qf k8X/c75BkK8CA0McVe6LjyV4mQhDzQJCEPPFOOrVJHm5OK7RKtuDZexPhXj+KCuNai0OEFY qdJobFFWjyQNg7EwHaWDLYw7pSsmJ4zAoTLDKMa1lk2sG3LXHZ1FCP72u883W+uCmgLuJkA o4L2lYZPjNJQ/NZwlNq/A== X-UI-Out-Filterresults: notjunk:1;V01:K0:4WrAijYb4hg=:H9PpuPZyP5syhgwQjfkk88 e9C5Vx+q2yYDdbCmQiEz5Pm98OiIuGkjkHmBOSeArdFNTg2K0DUbVyD6fDfAx2sJuOm7LU+xL hUFaNr8XKUx7XNzWnjKWafLoAVEfFD1VG25ag0iILMN/7iCUHIr+Kze9RNwzfzaaPfgi4aSdw ouFI+qEjngzoi72xpQM5GdrGR8qCK9p6zzBlne/cnd23BoBz/altWMT5r7Ec8DOr7CxXiPLL2 mkdYAYkFpe4WAN/qkY/xVQLvEbwPRECQA67uqJVQwP/6TVvL7l8RPycBtHs4sRhAioPWauQIx oGAsycgUNLPiQ9n+Txb1SHIJUtM5BPqehyEuBGqKlZzcGxZWwfTg8iOXHfUs4Z+9PR91P3Sd9 BEcokGJRJO9hlylEFDWlOmnrVE1PgZ5rBPSMHQuTt/pxZpAUuiFKR9OK9xdHmz+FxivbrTAZD KJLqpE4ab6yqepL0uC8h+lgn2XRadEcMSUJ8KyKCOSl6DKMjzoerYrSPoSepPQre5JWXCA2cW 6r5zcmKGdZccr7vQRWrS4R2qN8RAnj1UQpFA2a0GsiYFtT0jnsIlpevAL5gTGl0HF7l86gohq aihdcr+nZ+p2CsBbI2sOaN1w/rZaFoiX3kMhRnYtRKWMg0wkPxUUZ4kw/sfJhVCnBcDYMx9Vv oiE+taDVhwCAIiKm0/RpS65a7S8g0XybOFEU9aTpS1Ph8Bdf3XwWgmh5vcOJgXWziJk0H1hSs 7VnLjNeuuyV7cJcTE+QWcz7tgwlTcApjk1kK5A== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 7/8] target/m68k: add pflush/ptest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-7-laurent@vivier.eu> --- target/m68k/cpu.h | 3 ++ target/m68k/helper.c | 73 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 2 ++ target/m68k/monitor.c | 1 + target/m68k/op_helper.c | 1 + target/m68k/translate.c | 33 ++++++++++++++++++++++ 6 files changed, 113 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cc1759bb5d..0739c3f5c8 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -131,6 +131,7 @@ typedef struct CPUM68KState { uint32_t srp; bool fault; uint32_t ttr[4]; + uint32_t mmusr; } mmu; =20 /* Control registers. */ @@ -512,6 +513,8 @@ enum { ACCESS_STORE =3D 0x02, /* 1 bit to indicate debug access */ ACCESS_DEBUG =3D 0x04, + /* PTEST instruction */ + ACCESS_PTEST =3D 0x08, /* Type of instruction that generated the access */ ACCESS_CODE =3D 0x10, /* Code fetch access */ ACCESS_DATA =3D 0x20, /* Data load/store access */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 80db0b75b0..9fd9d3f1ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -221,6 +221,9 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t = reg, uint32_t val) case M68K_CR_TC: env->mmu.tcr =3D val; return; + case M68K_CR_MMUSR: + env->mmu.mmusr =3D val; + return; case M68K_CR_SRP: env->mmu.srp =3D val; return; @@ -272,6 +275,8 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uin= t32_t reg) /* MC680[34]0 */ case M68K_CR_TC: return env->mmu.tcr; + case M68K_CR_MMUSR: + return env->mmu.mmusr; case M68K_CR_SRP: return env->mmu.srp; case M68K_CR_USP: @@ -433,6 +438,10 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, for (i =3D 0; i < M68K_MAX_TTR; i++) { if (check_TTR(env->mmu.TTR(access_type, i), prot, address, access_type)) { + if (access_type & ACCESS_PTEST) { + /* Transparent Translation Register bit */ + env->mmu.mmusr =3D M68K_MMU_T_040 | M68K_MMU_R_040; + } *physical =3D address & TARGET_PAGE_MASK; *page_size =3D TARGET_PAGE_SIZE; return 0; @@ -461,6 +470,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -478,6 +490,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -524,6 +539,12 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, page_mask =3D ~(*page_size - 1); *physical =3D next & page_mask; =20 + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D next & M68K_MMU_SR_MASK_040; + env->mmu.mmusr |=3D *physical & 0xfffff000; + env->mmu.mmusr |=3D M68K_MMU_R_040; + } + if (next & M68K_DESC_WRITEPROT) { *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { @@ -1078,6 +1099,58 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_= t val, uint32_t acc) } =20 #if defined(CONFIG_SOFTMMU) +void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + hwaddr physical; + int access_type; + int prot; + int ret; + target_ulong page_size; + + access_type =3D ACCESS_PTEST; + if (env->dfc & 4) { + access_type |=3D ACCESS_SUPER; + } + if ((env->dfc & 3) =3D=3D 2) { + access_type |=3D ACCESS_CODE; + } + if (!is_read) { + access_type |=3D ACCESS_STORE; + } + + env->mmu.mmusr =3D 0; + env->mmu.ssw =3D 0; + ret =3D get_physical_address(env, &physical, &prot, addr, + access_type, &page_size); + if (ret =3D=3D 0) { + addr &=3D TARGET_PAGE_MASK; + physical +=3D addr & (page_size - 1); + tlb_set_page(cs, addr, physical, + prot, access_type & ACCESS_SUPER ? + MMU_KERNEL_IDX : MMU_USER_IDX, page_size); + } +} + +void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + + switch (opmode) { + case 0: /* Flush page entry if not global */ + case 1: /* Flush page entry */ + tlb_flush_page(CPU(cpu), addr); + break; + case 2: /* Flush all except global entries */ + tlb_flush(CPU(cpu)); + break; + case 3: /* Flush all entries */ + tlb_flush(CPU(cpu)); + break; + } +} + void HELPER(reset)(CPUM68KState *env) { /* FIXME: reset all except CPU */ diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 57f210aa14..7f400f0def 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -101,5 +101,7 @@ DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) =20 #if defined(CONFIG_SOFTMMU) +DEF_HELPER_3(ptest, void, env, i32, i32) +DEF_HELPER_3(pflush, void, env, i32, i32) DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index c31feb4b02..486213cd8b 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -39,6 +39,7 @@ static const MonitorDef monitor_defs[] =3D { { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, + { "mmusr", offsetof(CPUM68KState, mmu.mmusr) }, { NULL }, }; =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 4609caa546..ffea9693fc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -466,6 +466,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, bool is_write, } =20 if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr =3D 0; env->mmu.ssw |=3D M68K_ATC_040; /* FIXME: manage MMU table access error */ env->mmu.ssw &=3D ~M68K_TM_040; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c0edaa533c..34db97b8a0 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4661,6 +4661,35 @@ DISAS_INSN(cinv) /* Invalidate cache line. Implement as no-op. */ } =20 +#if defined(CONFIG_SOFTMMU) +DISAS_INSN(pflush) +{ + TCGv opmode; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + opmode =3D tcg_const_i32((insn >> 3) & 3); + gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); + tcg_temp_free(opmode); +} + +DISAS_INSN(ptest) +{ + TCGv is_read; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + is_read =3D tcg_const_i32((insn >> 5) & 1); + gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); + tcg_temp_free(is_read); +} +#endif + DISAS_INSN(wddata) { gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); @@ -5854,6 +5883,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(cpushl, f428, ff38, CF_ISA_A); INSN(cpush, f420, ff20, M68040); INSN(cinv, f400, ff20, M68040); + INSN(pflush, f500, ffe0, M68040); + INSN(ptest, f548, ffd8, M68040); INSN(wddata, fb00, ff00, CF_ISA_A); INSN(wdebug, fbc0, ffc0, CF_ISA_A); #endif @@ -6056,6 +6087,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); + cpu_fprintf(f, "MMUSR %08x, fault at %08x\n", + env->mmu.mmusr, env->mmu.ar); #endif } =20 --=20 2.14.3 From nobody Thu May 2 19:46:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893818925197.3456165630248; Thu, 25 Jan 2018 07:23:38 -0800 (PST) Received: from localhost ([::1]:46241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejNH-00047r-Ou for importer@patchew.org; Thu, 25 Jan 2018 10:23:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFj-0006Fv-ES for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFf-0000lR-VR for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:47 -0500 Received: from mout.kundenserver.de ([212.227.126.135]:52336) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFf-0000kU-KW for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:43 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MPKs8-1ej6xq0NqS-004RBN; Thu, 25 Jan 2018 16:15:42 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:35 +0100 Message-Id: <20180125151535.25256-9-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:eTyjjWT4Ujb2a3wg1FyRCdix+DLavLhIfywle+X9/GAwbQe1lX0 x1MacB/KqP/NKpjlqsmGMmuLR2fyxpyrhBX3dBvxpam6CnFQjNda4b0Ls2GR2jInzyubtUA yPr850Be3/v7VlK/xsWSz1xRFggH99U3ufiWtpyIcrHb36LGMTuQpCjFOtUahR1wCsrm6UB zrktxDCUvUsfrcceygn5w== X-UI-Out-Filterresults: notjunk:1;V01:K0:ipnE1Ovkqa4=:dtF7AsBQGnhiEEsTEg/nqI uTkJDfPJ1Yi4sAzfyYwmXjamWS5vN/kq9hQFZher7gpZHUESNNDbZ6cei6ZPUJuRnXiwZPfzH yGKwpcPqzLmIXD8MB4+chJsyJpCCz25MZAlKo6tI9J2QdxNaXdE6CA2PryOPgaSYiJveN4iMg tTbgY3d5BT3CSYZycQzHaAXy/nl6wPXcWNBpOkab8As9Cio6gkRpsHGopmTdk2ALiewp7fYBc HCMV7rZWAvb+7aT45HLlOvcZc4qo2sAG+5UsU51UMGit13a/3Hls2lE2sUo455/flZK4GceCF Qad6RoyFRA66xQAF4JvyU+ML8b5xZGRaxn6qAYYgDmI8APtJ28JoScbOXYDb5PJ4HN6Rbq7Ld wwgg/hWhAmUCWEEpwe//n5fIz+eXfez/KAWC/YdB+/kxxXsqVeYs6KNh919UPWDJH9E/s61Ro 2xiceDdw2CBuChdWYpYaxByrpWv85DvsCRP6/qUNI+GkwaopyzmJBkZjFpHQQP+b+DyhhNcm5 iGBskXULWtcK/WiGWkPBMP2D1WCjeV7ksFpd+FFzz3pWeO+zEQWrpeOjmSqlx7NBANJaebfaW NlKBnRxjPmG8QKsfZoaD2zamMaWg3sbWXvb0f6hQDzugPpnETXX7R6W+Ia/B6QNt38crIIOHl 5Nfv2J3sRminbr7DyiPrJO4amFo528c3WKkdPUP+4qZqhPCDPf24Yv1ZosebbOcWr/dG6w/Qo LknAP2ZKzvVbJctMI0MqUcFRgo/vRPT7xUZLoQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PULL 8/8] target/m68k: add HMP command "info tlb" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Dump MMU state and address mappings. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-8-laurent@vivier.eu> --- hmp-commands-info.hx | 2 +- target/m68k/cpu.h | 4 + target/m68k/helper.c | 218 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/monitor.c | 13 +++ 4 files changed, 236 insertions(+), 1 deletion(-) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 54c3e5eac6..ad590a4ffb 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -216,7 +216,7 @@ Show PCI information. ETEXI =20 #if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) |= | \ - defined(TARGET_PPC) || defined(TARGET_XTENSA) + defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) { .name =3D "tlb", .args_type =3D "", diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 0739c3f5c8..627fb787b6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -316,6 +316,7 @@ typedef enum { #define M68K_DESC_GLOBAL 0x00000400 #define M68K_DESC_URESERVED 0x00000800 =20 +#define M68K_ROOT_POINTER_ENTRIES 128 #define M68K_4K_PAGE_MASK (~0xff) #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) @@ -329,6 +330,8 @@ typedef enum { #define M68K_PDT_VALID(entry) (entry & 3) #define M68K_PDT_INDIRECT(entry) ((entry & 3) =3D=3D 2) #define M68K_INDIRECT_POINTER(addr) (addr & ~3) +#define M68K_TTS_POINTER_SHIFT 18 +#define M68K_TTS_ROOT_SHIFT 25 =20 /* bits for 68040 MMU Transparent Translation Registers */ #define M68K_TTR_ADDR_BASE 0xff000000 @@ -571,4 +574,5 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *e= nv, target_ulong *pc, } } =20 +void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env); #endif diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9fd9d3f1ff..20155c7801 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -374,6 +374,224 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, =20 /* MMU: 68040 only */ =20 +static void print_address_zone(FILE *f, fprintf_function cpu_fprintf, + uint32_t logical, uint32_t physical, + uint32_t size, int attr) +{ + cpu_fprintf(f, "%08x - %08x -> %08x - %08x %c ", + logical, logical + size - 1, + physical, physical + size - 1, + attr & 4 ? 'W' : '-'); + size >>=3D 10; + if (size < 1024) { + cpu_fprintf(f, "(%d KiB)\n", size); + } else { + size >>=3D 10; + if (size < 1024) { + cpu_fprintf(f, "(%d MiB)\n", size); + } else { + size >>=3D 10; + cpu_fprintf(f, "(%d GiB)\n", size); + } + } +} + +static void dump_address_map(FILE *f, fprintf_function cpu_fprintf, + CPUM68KState *env, uint32_t root_pointer) +{ + int i, j, k; + int tic_size, tic_shift; + uint32_t tib_mask; + uint32_t tia, tib, tic; + uint32_t logical =3D 0xffffffff, physical =3D 0xffffffff; + uint32_t first_logical =3D 0xffffffff, first_physical =3D 0xffffffff; + uint32_t last_logical, last_physical; + int32_t size; + int last_attr =3D -1, attr =3D -1; + M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + /* 8k page */ + tic_size =3D 32; + tic_shift =3D 13; + tib_mask =3D M68K_8K_PAGE_MASK; + } else { + /* 4k page */ + tic_size =3D 64; + tic_shift =3D 12; + tib_mask =3D M68K_4K_PAGE_MASK; + } + for (i =3D 0; i < M68K_ROOT_POINTER_ENTRIES; i++) { + tia =3D ldl_phys(cs->as, M68K_POINTER_BASE(root_pointer) + i * 4); + if (!M68K_UDT_VALID(tia)) { + continue; + } + for (j =3D 0; j < M68K_ROOT_POINTER_ENTRIES; j++) { + tib =3D ldl_phys(cs->as, M68K_POINTER_BASE(tia) + j * 4); + if (!M68K_UDT_VALID(tib)) { + continue; + } + for (k =3D 0; k < tic_size; k++) { + tic =3D ldl_phys(cs->as, (tib & tib_mask) + k * 4); + if (!M68K_PDT_VALID(tic)) { + continue; + } + if (M68K_PDT_INDIRECT(tic)) { + tic =3D ldl_phys(cs->as, M68K_INDIRECT_POINTER(tic)); + } + + last_logical =3D logical; + logical =3D (i << M68K_TTS_ROOT_SHIFT) | + (j << M68K_TTS_POINTER_SHIFT) | + (k << tic_shift); + + last_physical =3D physical; + physical =3D tic & ~((1 << tic_shift) - 1); + + last_attr =3D attr; + attr =3D tic & ((1 << tic_shift) - 1); + + if ((logical !=3D (last_logical + (1 << tic_shift))) || + (physical !=3D (last_physical + (1 << tic_shift))) || + (attr & 4) !=3D (last_attr & 4)) { + + if (first_logical !=3D 0xffffffff) { + size =3D last_logical + (1 << tic_shift) - + first_logical; + print_address_zone(f, cpu_fprintf, first_logical, + first_physical, size, last_attr= ); + } + first_logical =3D logical; + first_physical =3D physical; + } + } + } + } + if (first_logical !=3D logical || (attr & 4) !=3D (last_attr & 4)) { + size =3D logical + (1 << tic_shift) - first_logical; + print_address_zone(f, cpu_fprintf, first_logical, first_physical, = size, + last_attr); + } +} + +#define DUMP_CACHEFLAGS(a) \ + switch (a & M68K_DESC_CACHEMODE) { \ + case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \ + cpu_fprintf(f, "T"); \ + break; \ + case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \ + cpu_fprintf(f, "C"); \ + break; \ + case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ + cpu_fprintf(f, "S"); \ + break; \ + case M68K_DESC_CM_NCACHE: /* noncachable */ \ + cpu_fprintf(f, "N"); \ + break; \ + } + +static void dump_ttr(FILE *f, fprintf_function cpu_fprintf, uint32_t ttr) +{ + if ((ttr & M68K_TTR_ENABLED) =3D=3D 0) { + cpu_fprintf(f, "disabled\n"); + return; + } + cpu_fprintf(f, "Base: 0x%08x Mask: 0x%08x Control: ", + ttr & M68K_TTR_ADDR_BASE, + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); + switch (ttr & M68K_TTR_SFIELD) { + case M68K_TTR_SFIELD_USER: + cpu_fprintf(f, "U"); + break; + case M68K_TTR_SFIELD_SUPER: + cpu_fprintf(f, "S"); + break; + default: + cpu_fprintf(f, "*"); + break; + } + DUMP_CACHEFLAGS(ttr); + if (ttr & M68K_DESC_WRITEPROT) { + cpu_fprintf(f, "R"); + } else { + cpu_fprintf(f, "W"); + } + cpu_fprintf(f, " U: %d\n", (ttr & M68K_DESC_USERATTR) >> + M68K_DESC_USERATTR_SHIFT); +} + +void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env) +{ + if ((env->mmu.tcr & M68K_TCR_ENABLED) =3D=3D 0) { + cpu_fprintf(f, "Translation disabled\n"); + return; + } + cpu_fprintf(f, "Page Size: "); + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + cpu_fprintf(f, "8kB\n"); + } else { + cpu_fprintf(f, "4kB\n"); + } + + cpu_fprintf(f, "MMUSR: "); + if (env->mmu.mmusr & M68K_MMU_B_040) { + cpu_fprintf(f, "BUS ERROR\n"); + } else { + cpu_fprintf(f, "Phy=3D%08x Flags: ", env->mmu.mmusr & 0xfffff000); + /* flags found on the page descriptor */ + if (env->mmu.mmusr & M68K_MMU_G_040) { + cpu_fprintf(f, "G"); /* Global */ + } else { + cpu_fprintf(f, "."); + } + if (env->mmu.mmusr & M68K_MMU_S_040) { + cpu_fprintf(f, "S"); /* Supervisor */ + } else { + cpu_fprintf(f, "."); + } + if (env->mmu.mmusr & M68K_MMU_M_040) { + cpu_fprintf(f, "M"); /* Modified */ + } else { + cpu_fprintf(f, "."); + } + if (env->mmu.mmusr & M68K_MMU_WP_040) { + cpu_fprintf(f, "W"); /* Write protect */ + } else { + cpu_fprintf(f, "."); + } + if (env->mmu.mmusr & M68K_MMU_T_040) { + cpu_fprintf(f, "T"); /* Transparent */ + } else { + cpu_fprintf(f, "."); + } + if (env->mmu.mmusr & M68K_MMU_R_040) { + cpu_fprintf(f, "R"); /* Resident */ + } else { + cpu_fprintf(f, "."); + } + cpu_fprintf(f, " Cache: "); + DUMP_CACHEFLAGS(env->mmu.mmusr); + cpu_fprintf(f, " U: %d\n", (env->mmu.mmusr >> 8) & 3); + cpu_fprintf(f, "\n"); + } + + cpu_fprintf(f, "ITTR0: "); + dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR0]); + cpu_fprintf(f, "ITTR1: "); + dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR1]); + cpu_fprintf(f, "DTTR0: "); + dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR0]); + cpu_fprintf(f, "DTTR1: "); + dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR1]); + + cpu_fprintf(f, "SRP: 0x%08x\n", env->mmu.srp); + dump_address_map(f, cpu_fprintf, env, env->mmu.srp); + + cpu_fprintf(f, "URP: 0x%08x\n", env->mmu.urp); + dump_address_map(f, cpu_fprintf, env, env->mmu.urp); +} + static int check_TTR(uint32_t ttr, int *prot, target_ulong addr, int access_type) { diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 486213cd8b..db582a34ac 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -8,6 +8,19 @@ #include "qemu/osdep.h" #include "cpu.h" #include "monitor/hmp-target.h" +#include "monitor/monitor.h" + +void hmp_info_tlb(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env1 =3D mon_get_cpu_env(); + + if (!env1) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env1); +} =20 static const MonitorDef monitor_defs[] =3D { { "d0", offsetof(CPUM68KState, dregs[0]) }, --=20 2.14.3