From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151683652545339.58322557756742; Wed, 24 Jan 2018 15:28:45 -0800 (PST) Received: from localhost ([::1]:54458 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUTE-0005jS-Em for importer@patchew.org; Wed, 24 Jan 2018 18:28:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUR8-0004MV-PP for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUR5-0001aN-Fe for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:34 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:36257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUR5-0001a1-7V for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:31 -0500 Received: by mail-pf0-x242.google.com with SMTP id 23so4371424pfp.3 for ; Wed, 24 Jan 2018 15:26:31 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3Tk83VL5NyWiwRlQYKh5W1M5rBym+jzTf9jTTK7nKgo=; b=jScFC+Swhk3K3oDKiprrdV6A9emMTRxO20ZFTPnpHOYo/jhRk6iyjhpxoZdNUSWCRc Ytc+awkJjKnoG4GRDNwJof41sNTaD/op51abSChwwrUyLaKdxFhxJOxjF5TmW1VajP8D w3N2ddMe79iX06rG5oeIieS+uOKDm6a4QWfDM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3Tk83VL5NyWiwRlQYKh5W1M5rBym+jzTf9jTTK7nKgo=; b=kCWDX6kOS4u1NhnsNpuSNMprwkD80Kq824my7ZV8zZ5JLQQAYhs3jPg14jcLMnLuhV Mq9AvLBwYEtb/I4WEmiJXIsYbl9nmzyFeP0TZ8g2yA9BAXjRzhQ2LP1dXKRvhgw4AGsU dan3pbGvSxzwVZR2/VNHxTKXbTeKFwZWgh2eZlTVe2OogQJnJB1mofBsqT+FQXxKNQCc UCi64dKIy0vf9G/GMIP2SYzTx4LtQ0rdnJrEjpo0jXQ6RGxFXa+4inNW/NLfYxBIIooR lx90jnQro0nR31WxteMTzykwa+0xO8bpzb5ahkELpxJ6M8J1IPjhNZ49VO3FftXn4XCk 5pAw== X-Gm-Message-State: AKwxytf9kh6BR9/pdHhZ9blEU1N0N/Qbx6OgIz+rlMlANxBQFApOrB02 ciC/TM/1FRlRF4O/QfzZiAAv7Ym9/NI= X-Google-Smtp-Source: AH8x225ZhZgGhpvsajqEBb7MMYu5ttv4TUenWlD5vX3Q5xVdw4UX17QMPnDL/miu5m7jH8sIet8KQQ== X-Received: by 2002:a17:902:bcc5:: with SMTP id o5-v6mr9681325pls.67.1516836389665; Wed, 24 Jan 2018 15:26:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:41 -0800 Message-Id: <20180124232625.30105-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 01/45] target/hppa: Skeleton support for hppa-softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Helge Deller With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- include/sysemu/arch_init.h | 1 + target/hppa/cpu.h | 1 + arch_init.c | 2 ++ hw/hppa/machine.c | 38 ++++++++++++++++++++++++++++++++ target/hppa/cpu.c | 5 +++++ target/hppa/helper.c | 10 --------- target/hppa/mem_helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/op_helper.c | 13 +++++++++-- hw/hppa/Makefile.objs | 1 + target/hppa/Makefile.objs | 2 +- 10 files changed, 114 insertions(+), 13 deletions(-) create mode 100644 hw/hppa/machine.c create mode 100644 target/hppa/mem_helper.c create mode 100644 hw/hppa/Makefile.objs diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 8751c468ed..f999bfd3be 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_MOXIE =3D (1 << 15), QEMU_ARCH_TRICORE =3D (1 << 16), QEMU_ARCH_NIOS2 =3D (1 << 17), + QEMU_ARCH_HPPA =3D (1 << 18), }; =20 extern const uint32_t arch_type; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8d14077763..7fad92144c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -133,6 +133,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); =20 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mi= dx); +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); diff --git a/arch_init.c b/arch_init.c index a0b8ed6167..4c36f2b076 100644 --- a/arch_init.c +++ b/arch_init.c @@ -53,6 +53,8 @@ int graphic_depth =3D 32; #define QEMU_ARCH QEMU_ARCH_CRIS #elif defined(TARGET_I386) #define QEMU_ARCH QEMU_ARCH_I386 +#elif defined(TARGET_HPPA) +#define QEMU_ARCH QEMU_ARCH_HPPA #elif defined(TARGET_M68K) #define QEMU_ARCH QEMU_ARCH_M68K #elif defined(TARGET_LM32) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c new file mode 100644 index 0000000000..79958da18f --- /dev/null +++ b/hw/hppa/machine.c @@ -0,0 +1,38 @@ +/* + * QEMU HPPA hardware system emulator. + * Copyright 2018 Helge Deller + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "elf.h" +#include "hw/loader.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "sysemu/sysemu.h" +#include "hw/timer/mc146818rtc.h" +#include "hw/ide.h" +#include "hw/timer/i8254.h" +#include "hw/char/serial.h" +#include "qemu/cutils.h" +#include "qapi/error.h" + + +static void machine_hppa_init(MachineState *machine) +{ +} + +static void machine_hppa_machine_init(MachineClass *mc) +{ + mc->desc =3D "HPPA generic machine"; + mc->init =3D machine_hppa_init; + mc->block_default_type =3D IF_SCSI; + mc->max_cpus =3D 1; + mc->is_default =3D 1; + mc->default_ram_size =3D 512 * M_BYTE; + mc->default_boot_order =3D "cd"; +} + +DEFINE_MACHINE("hppa", machine_hppa_machine_init) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9e7b0d4ccb..f6d92de972 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -132,7 +132,12 @@ static void hppa_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; +#ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; +#else + cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; +#endif + cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->tcg_initialize =3D hppa_translate_init; =20 diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ba04a9a52b..d6d6f06cb0 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -65,16 +65,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong ps= w) env->psw_cb =3D cb; } =20 -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int rw, int mmu_idx) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - - cs->exception_index =3D EXCP_SIGSEGV; - cpu->env.ior =3D address; - return 1; -} - void hppa_cpu_do_interrupt(CPUState *cs) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c new file mode 100644 index 0000000000..e0802bc935 --- /dev/null +++ b/target/hppa/mem_helper.c @@ -0,0 +1,54 @@ +/* + * HPPA memory access helper routines + * + * Copyright (c) 2017 Helge Deller + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, + int rw, int mmu_idx) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + + cs->exception_index =3D EXCP_SIGSEGV; + cpu->env.ior =3D address; + return 1; +} +#else +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + /* Stub */ + return addr; +} + +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, + int mmu_idx, uintptr_t retaddr) +{ + /* Stub */ + int prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + hwaddr phys =3D addr; + + /* Success! Store the translation into the QEMU TLB. */ + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); +} +#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3104404e8d..9c7603588f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -58,9 +58,9 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t = val, uint32_t mask, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY uint32_t old, new, cmp; =20 -#ifdef CONFIG_USER_ONLY uint32_t *haddr =3D g2h(addr - 1); old =3D *haddr; while (1) { @@ -72,7 +72,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, old =3D cmp; } #else -#error "Not implemented." + /* FIXME -- we can do better. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #endif } =20 @@ -158,12 +159,20 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, targe= t_ulong addr, =20 target_ulong HELPER(probe_r)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); +#else + return 1; /* FIXME */ +#endif } =20 target_ulong HELPER(probe_w)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); +#else + return 1; /* FIXME */ +#endif } =20 void HELPER(loaded_fr0)(CPUHPPAState *env) diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs new file mode 100644 index 0000000000..46b2ae18de --- /dev/null +++ b/hw/hppa/Makefile.objs @@ -0,0 +1 @@ +obj-y +=3D machine.o diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index 263446fa0b..d89285307b 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1 @@ -obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o +obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836714754466.6091540037138; Wed, 24 Jan 2018 15:31:54 -0800 (PST) Received: from localhost ([::1]:54480 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUWD-0008Ei-0e for importer@patchew.org; Wed, 24 Jan 2018 18:31:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUR8-0004MU-PO for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUR6-0001as-R0 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:34 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:39453) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUR6-0001ad-IX for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:32 -0500 Received: by mail-pf0-x241.google.com with SMTP id e11so4363328pff.6 for ; Wed, 24 Jan 2018 15:26:32 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=/D3ilS4wflTksMAoF+YKaff+lQbvvqDLvk8pG7D1+9Y=; b=MOaeRiPw46SU/ZN9b0+f8mY0717RtW3Bhiv2RKtZSoiO1FYCqn22GOj2nMVjcX4Yhc +/BMnhtCbnbcrtykNEyer9CQv/pqJk2Dnp9GLGravcV+lJ/GdKLwVobXV0dGutQt3BON KVYHLzOn1WXeAetUer3pb1Wxc23pcrMWTFNzw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/D3ilS4wflTksMAoF+YKaff+lQbvvqDLvk8pG7D1+9Y=; b=krU6KkDAQeorGAcn9e9XDAv3dqqjGAxY23B53h+3bAgW7D43jFMs3hKeMh9UHVdzy6 bApzoRMoETRhcN8V8HZSW+z1K+/kBmSyGP1Q/2CiDac2DeZJOIhwcEU72NvtJ8gbyoiX id8uHd7pE6S1PYXZuXZdz7UZmJ1UviB6mNTYoR7/bv9sZmBYC06nXN5sHQOx1ZCMv88/ xpWLmX4zp7sXqrSZ4bSy/NWPmXYOpuX2tOuC1sOJ1tm8WtUzjJIlVT4H196JIzqD0a8u TD7s8K4cRr7P+PuQTqmqMAWLoB4R83JvQ08xuZHIFYiTdsowcjEWPr9nqQYEgh8dGHi+ irDg== X-Gm-Message-State: AKwxyteSjKJOOX2Y5Xo6l+wMBFiSzwAmzkGv1qfHJwEV2DN+vLCvHL/7 Ek+qn7hqIppSkvqDALHdKUYa8cKJqF0= X-Google-Smtp-Source: AH8x2246eFZZV6hi19kUWaoZIi9zsUpi1VdmxRYOZbLFA/D+PcG16wOR9sIeV2xeJpjemr5k2DcKSg== X-Received: by 2002:a17:902:7f0b:: with SMTP id d11-v6mr5406974plm.70.1516836391184; Wed, 24 Jan 2018 15:26:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:42 -0800 Message-Id: <20180124232625.30105-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 02/45] target/hppa: Define the rest of the PSW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/helper.c | 53 ++++++++++++++++++++++++++++++++++++++----------= ---- 2 files changed, 86 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7fad92144c..ea7e495408 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -46,6 +46,52 @@ #define EXCP_SIGILL 4 #define EXCP_SIGFPE 5 =20 +/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ +#define PSW_I 0x00000001 +#define PSW_D 0x00000002 +#define PSW_P 0x00000004 +#define PSW_Q 0x00000008 +#define PSW_R 0x00000010 +#define PSW_F 0x00000020 +#define PSW_G 0x00000040 /* PA1.x only */ +#define PSW_O 0x00000080 /* PA2.0 only */ +#define PSW_CB 0x0000ff00 +#define PSW_M 0x00010000 +#define PSW_V 0x00020000 +#define PSW_C 0x00040000 +#define PSW_B 0x00080000 +#define PSW_X 0x00100000 +#define PSW_N 0x00200000 +#define PSW_L 0x00400000 +#define PSW_H 0x00800000 +#define PSW_T 0x01000000 +#define PSW_S 0x02000000 +#define PSW_E 0x04000000 +#ifdef TARGET_HPPA64 +#define PSW_W 0x08000000 /* PA2.0 only */ +#else +#define PSW_W 0 +#endif +#define PSW_Z 0x40000000 /* PA1.x only */ +#define PSW_Y 0x80000000 /* PA1.x only */ + +#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ + | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) + +/* ssm/rsm instructions number PSW_W and PSW_E differently */ +#define PSW_SM_I PSW_I /* Enable External Interrupts */ +#define PSW_SM_D PSW_D +#define PSW_SM_P PSW_P +#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ +#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ +#ifdef TARGET_HPPA64 +#define PSW_SM_E 0x100 +#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ +#else +#define PSW_SM_E 0 +#define PSW_SM_W 0 +#endif + typedef struct CPUHPPAState CPUHPPAState; =20 struct CPUHPPAState { @@ -56,6 +102,7 @@ struct CPUHPPAState { target_ulong cr26; target_ulong cr27; =20 + target_long psw; /* All psw bits except the following: */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ =20 diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d6d6f06cb0..4231ef3bff 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -39,10 +39,11 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) /* .........................bcdefgh */ psw |=3D (psw >> 12) & 0xf; psw |=3D env->psw_cb_msb << 7; - psw <<=3D 8; + psw =3D (psw & 0xff) << 8; =20 - psw |=3D env->psw_n << 21; - psw |=3D (env->psw_v < 0) << 17; + psw |=3D env->psw_n * PSW_N; + psw |=3D (env->psw_v < 0) * PSW_V; + psw |=3D env->psw; =20 return psw; } @@ -51,8 +52,9 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { target_ulong cb =3D 0; =20 - env->psw_n =3D (psw >> 21) & 1; - env->psw_v =3D -((psw >> 17) & 1); + env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); + env->psw_n =3D (psw / PSW_N) & 1; + env->psw_v =3D -((psw / PSW_V) & 1); env->psw_cb_msb =3D (psw >> 15) & 1; =20 cb |=3D ((psw >> 14) & 1) << 28; @@ -106,22 +108,45 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; + target_ulong psw =3D cpu_hppa_get_psw(env); + target_ulong psw_cb; + char psw_c[20]; int i; =20 - cpu_fprintf(f, "IA_F " TARGET_FMT_lx - " IA_B " TARGET_FMT_lx - " PSW " TARGET_FMT_lx - " [N:" TARGET_FMT_ld " V:%d" - " CB:" TARGET_FMT_lx "]\n ", - env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env), - env->psw_n, env->psw_v < 0, - ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28= )); - for (i =3D 1; i < 32; i++) { + cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", + env->iaoq_f, env->iaoq_b); + + psw_c[0] =3D (psw & PSW_W ? 'W' : '-'); + psw_c[1] =3D (psw & PSW_E ? 'E' : '-'); + psw_c[2] =3D (psw & PSW_S ? 'S' : '-'); + psw_c[3] =3D (psw & PSW_T ? 'T' : '-'); + psw_c[4] =3D (psw & PSW_H ? 'H' : '-'); + psw_c[5] =3D (psw & PSW_L ? 'L' : '-'); + psw_c[6] =3D (psw & PSW_N ? 'N' : '-'); + psw_c[7] =3D (psw & PSW_X ? 'X' : '-'); + psw_c[8] =3D (psw & PSW_B ? 'B' : '-'); + psw_c[9] =3D (psw & PSW_C ? 'C' : '-'); + psw_c[10] =3D (psw & PSW_V ? 'V' : '-'); + psw_c[11] =3D (psw & PSW_M ? 'M' : '-'); + psw_c[12] =3D (psw & PSW_F ? 'F' : '-'); + psw_c[13] =3D (psw & PSW_R ? 'R' : '-'); + psw_c[14] =3D (psw & PSW_Q ? 'Q' : '-'); + psw_c[15] =3D (psw & PSW_P ? 'P' : '-'); + psw_c[16] =3D (psw & PSW_D ? 'D' : '-'); + psw_c[17] =3D (psw & PSW_I ? 'I' : '-'); + psw_c[18] =3D '\0'; + psw_cb =3D ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); + + cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + psw, psw_cb, psw_c); + + for (i =3D 0; i < 32; i++) { cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); if ((i % 4) =3D=3D 3) { cpu_fprintf(f, "\n"); } } + cpu_fprintf(f, "\n"); =20 /* ??? FR */ } --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836909804328.0908451981229; Wed, 24 Jan 2018 15:35:09 -0800 (PST) Received: from localhost ([::1]:54496 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUZR-0002HA-2v for importer@patchew.org; Wed, 24 Jan 2018 18:35:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUR9-0004Mc-D3 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUR8-0001bG-Aq for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:35 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:38590) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUR8-0001b3-4G for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:34 -0500 Received: by mail-pg0-x243.google.com with SMTP id y27so3814540pgc.5 for ; Wed, 24 Jan 2018 15:26:33 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=jWlXGhyGzuQklKuZM0jR3HHQ8HHbSqFzQDbbpF04MmY=; b=kJW73X6EhMLQgSbHd8cyR7bMd/8Myz4xKaZPh10xB0EJa210EaCLsQn3lVdgamg4dd ayG0rixpf5maNtTb9WsHp6XChP9s05lTdqlt/1O5Ixvfn6mAekxCGo98t6l//A4wsg01 TDZ1KKJbabkjA78gjcIF+jIJW4ACVwhi9PBls= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=jWlXGhyGzuQklKuZM0jR3HHQ8HHbSqFzQDbbpF04MmY=; b=ELyPk1ciMVIWF8w2Ad4/7dAwEDiucfpslqDLb23b2J5dVeHDA1ewzvu/uyLmpRn6Cf t+gE5sBDbHlCjSYzcTrnQzwMZZ74ionnh8NPhie2W1Bxn/gQmPe8LePQpkvNclNe4rys /o6ymF4uquFVQJUjxwVx51fBirEpp2v14PDHS0XfjeMqXJ29UPhfLmpfFynvkgn4UleU KQJ4Ks9ZM9WNSyIzHLRl3lP5cLiIY8FMKElroBNhJrD+E0UlZ0xicbYIi6pY/zMyLw1H ruqhLYuOTEc8+q0CgrwGMcjS9qH0YcUVX4/r2qZe/g0M39TkFjEY5vV5OXskOGlUDj6T 3Xdg== X-Gm-Message-State: AKwxyteaw2mf38E5h8UwaLrJUy//leiTxW2oa8uY3sbZwH6bc0zXfM1B MraV9W80BQ7SEGLehnZueyKn85kCKIE= X-Google-Smtp-Source: AH8x225xY6qBbGju0bP9MIP/yqIr8lkDuviKGq5Wq7rvJTvePhFPl5X0SPlqxH4sGGR1Tb5Xgtpl/Q== X-Received: by 2002:a17:902:7244:: with SMTP id c4-v6mr9964386pll.414.1516836392709; Wed, 24 Jan 2018 15:26:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:43 -0800 Message-Id: <20180124232625.30105-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 03/45] target/hppa: Disable gateway page emulation for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 31d9a2a31b..8e357cc60c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1543,6 +1543,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv dest, return DISAS_NEXT; } =20 +#ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific offsets have kernel code mapped to raise permissions to implement @@ -1600,6 +1601,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; } } +#endif =20 static DisasJumpType trans_nop(DisasContext *ctx, uint32_t insn, const DisasInsn *di) @@ -3787,10 +3789,13 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) int i, n; =20 /* Execute one insn. */ +#ifdef CONFIG_USER_ONLY if (ctx->iaoq_f < TARGET_PAGE_SIZE) { ret =3D do_page_zero(ctx); assert(ret !=3D DISAS_NEXT); - } else { + } else +#endif + { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f); @@ -3885,25 +3890,27 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { TranslationBlock *tb =3D dcbase->tb; + target_ulong pc =3D tb->pc; =20 - switch (tb->pc) { +#ifdef CONFIG_USER_ONLY + switch (pc) { case 0x00: qemu_log("IN:\n0x00000000: (null)\n"); - break; + return; case 0xb0: qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); - break; + return; case 0xe0: qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); - break; + return; case 0x100: qemu_log("IN:\n0x00000100: syscall\n"); - break; - default: - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size); - break; + return; } +#endif + + qemu_log("IN: %s\n", lookup_symbol(pc)); + log_target_disas(cs, pc, tb->size); } =20 static const TranslatorOps hppa_tr_ops =3D { --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836716932913.8735595591288; Wed, 24 Jan 2018 15:31:56 -0800 (PST) Received: from localhost ([::1]:54481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUWH-0008IF-4F for importer@patchew.org; Wed, 24 Jan 2018 18:31:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50933) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURB-0004NK-8m for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUR9-0001c0-Pm for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:37 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:43924) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUR9-0001bl-Hb for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:35 -0500 Received: by mail-pg0-x242.google.com with SMTP id n17so3805415pgf.10 for ; Wed, 24 Jan 2018 15:26:35 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=d85lqCspBYOiEahvyujgf0zWY50v14bxlk08GHck46o=; b=iLpRfCLhPOqcd1J/kwcgQfP5A2CT6miHVl7CbePfkxEWjdrq1Iq477MT5NLJOf3yL6 veLBRImlKKK94BOR34R2MAZYMW96mS1ZNfEUzixM7gOLUlbUPJJ2X6AB1xrpgGERBTMO G+gRU0WReX4EiOQKaAI6iu8vAzLK4JH7rf+hU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=d85lqCspBYOiEahvyujgf0zWY50v14bxlk08GHck46o=; b=r6LE8I4LMsNohupqZyvqCS6T53WtyUT88jfDwDfuf0Us1yk/sh/wBIAf+oaXX1IxuQ bWoUMq7aovfDsolH27ksZaEntFcV83NZZakz/rLZnGiONwPJ2EJ7+6yEAlRQJ2CFrLLy EKXu/9s7pfr9CGvDiFYeind49l5LZEXnKceehTW/08UUuHmDSaYX31ql4E6Ek02zDus0 atwsZ2qxt1/ok1HRr/0kglKdLDzVSwgwDhH9QrfDbaHkFLEqUoR7MDMYdZxmHw0ZCYyH 9+5RhbyPgjXw8gDIDobZnQPznHmaxVJ7O3Z5hvMAlxISkTtLleLmSgeCN5IgQFFYg/0Q agsg== X-Gm-Message-State: AKwxytfSNO9KPHkfW19QQ7oQTh4sNKFrSlkOUpyeG2aIlkU5M/W97mUr phaJokWg9FApZLqyGh4ypFuwSJ0/DjQ= X-Google-Smtp-Source: AH8x227YJIMtgz1mPqACl08GBH8/UTmXX1BY6edOZebqlNeBxN/IT/3d7NdKm8YadrVhpPuA5pyqxA== X-Received: by 2002:a17:902:b7cb:: with SMTP id v11-v6mr9513420plz.393.1516836394094; Wed, 24 Jan 2018 15:26:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:44 -0800 Message-Id: <20180124232625.30105-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 04/45] target/hppa: Define hardware exception types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 39 +++++++++++++++++++++++++++---- linux-user/main.c | 26 ++++++++++++++++++--- target/hppa/helper.c | 61 ++++++++++++++++++++++++++++++++++----------= ---- target/hppa/mem_helper.c | 4 +++- target/hppa/op_helper.c | 6 ++--- target/hppa/translate.c | 8 +++---- 6 files changed, 111 insertions(+), 33 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index ea7e495408..d84af91860 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -40,11 +40,40 @@ #define MMU_USER_IDX 0 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define EXCP_SYSCALL 1 -#define EXCP_SYSCALL_LWS 2 -#define EXCP_SIGSEGV 3 -#define EXCP_SIGILL 4 -#define EXCP_SIGFPE 5 +/* Hardware exceptions, interupts, faults, and traps. */ +#define EXCP_HPMC 1 /* high priority machine check */ +#define EXCP_POWER_FAIL 2 +#define EXCP_RC 3 /* recovery counter */ +#define EXCP_EXT_INTERRUPT 4 /* external interrupt */ +#define EXCP_LPMC 5 /* low priority machine check */ +#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault = */ +#define EXCP_IMP 7 /* instruction memory protection trap = */ +#define EXCP_ILL 8 /* illegal instruction trap */ +#define EXCP_BREAK 9 /* break instruction */ +#define EXCP_PRIV_OPR 10 /* privileged operation trap */ +#define EXCP_PRIV_REG 11 /* privileged register trap */ +#define EXCP_OVERFLOW 12 /* signed overflow trap */ +#define EXCP_COND 13 /* trap-on-condition */ +#define EXCP_ASSIST 14 /* assist exception trap */ +#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ +#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ +#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ +#define EXCP_DMP 18 /* data memory protection trap */ +#define EXCP_DMB 19 /* data memory break trap */ +#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ +#define EXCP_PAGE_REF 21 /* page reference trap */ +#define EXCP_ASSIST_EMU 22 /* assist emulation trap */ +#define EXCP_HPT 23 /* high-privilege transfer trap */ +#define EXCP_LPT 24 /* low-privilege transfer trap */ +#define EXCP_TB 25 /* taken branch trap */ +#define EXCP_DMAR 26 /* data memory access rights trap */ +#define EXCP_DMPI 27 /* data memory protection id trap */ +#define EXCP_UNALIGN 28 /* unaligned data reference trap */ +#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ + +/* Exceptions for linux-user emulation. */ +#define EXCP_SYSCALL 30 +#define EXCP_SYSCALL_LWS 31 =20 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ #define PSW_I 0x00000001 diff --git a/linux-user/main.c b/linux-user/main.c index 450eb3ce65..42f4c66ce6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3768,21 +3768,41 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_SIGSEGV: + case EXCP_ITLB_MISS: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_IMP: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_PAGE_REF: + case EXCP_DMAR: + case EXCP_DMPI: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D TARGET_SEGV_ACCERR; info._sifields._sigfault._addr =3D env->ior; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGILL: + case EXCP_UNALIGN: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D 0; + info._sifields._sigfault._addr =3D env->ior; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ILL: + case EXCP_PRIV_OPR: + case EXCP_PRIV_REG: info.si_signo =3D TARGET_SIGILL; info.si_errno =3D 0; info.si_code =3D TARGET_ILL_ILLOPN; info._sifields._sigfault._addr =3D env->iaoq_f; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGFPE: + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; info.si_code =3D 0; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 4231ef3bff..6439179a0e 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -74,25 +74,52 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i =3D cs->exception_index; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] =3D { + [EXCP_HPMC] =3D "high priority machine check", + [EXCP_POWER_FAIL] =3D "power fail interrupt", + [EXCP_RC] =3D "recovery counter trap", + [EXCP_EXT_INTERRUPT] =3D "external interrupt", + [EXCP_LPMC] =3D "low priority machine check", + [EXCP_ITLB_MISS] =3D "instruction tlb miss fault", + [EXCP_IMP] =3D "instruction memory protection trap", + [EXCP_ILL] =3D "illegal instruction trap", + [EXCP_BREAK] =3D "break instruction trap", + [EXCP_PRIV_OPR] =3D "privileged operation trap", + [EXCP_PRIV_REG] =3D "privileged register trap", + [EXCP_OVERFLOW] =3D "overflow trap", + [EXCP_COND] =3D "conditional trap", + [EXCP_ASSIST] =3D "assist exception trap", + [EXCP_DTLB_MISS] =3D "data tlb miss fault", + [EXCP_NA_ITLB_MISS] =3D "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] =3D "non-access data tlb miss", + [EXCP_DMP] =3D "data memory protection trap", + [EXCP_DMB] =3D "data memory break trap", + [EXCP_TLB_DIRTY] =3D "tlb dirty bit trap", + [EXCP_PAGE_REF] =3D "page reference trap", + [EXCP_ASSIST_EMU] =3D "assist emulation trap", + [EXCP_HPT] =3D "high-privilege transfer trap", + [EXCP_LPT] =3D "low-privilege transfer trap", + [EXCP_TB] =3D "taken branch trap", + [EXCP_DMAR] =3D "data memory access rights trap", + [EXCP_DMPI] =3D "data memory protection id trap", + [EXCP_UNALIGN] =3D "unaligned data reference trap", + [EXCP_PER_INTERRUPT] =3D "performance monitor interrupt", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_SYSCALL_LWS] =3D "syscall-lws", + }; static int count; - const char *name =3D ""; - - switch (i) { - case EXCP_SYSCALL: - name =3D "syscall"; - break; - case EXCP_SIGSEGV: - name =3D "sigsegv"; - break; - case EXCP_SIGILL: - name =3D "sigill"; - break; - case EXCP_SIGFPE: - name =3D "sigfpe"; - break; + const char *name =3D NULL; + + if (i >=3D 0 && i < ARRAY_SIZE(names)) { + name =3D names[i]; + } + if (name) { + qemu_log("INT %6d: %s ia_f=3D" TARGET_FMT_lx "\n", + ++count, name, env->iaoq_f); + } else { + qemu_log("INT %6d: unknown %d ia_f=3D" TARGET_FMT_lx "\n", + ++count, i, env->iaoq_f); } - qemu_log("INT %6d: %s ia_f=3D" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); } cs->exception_index =3D -1; } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index e0802bc935..2901f3e29c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,7 +29,9 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { HPPACPU *cpu =3D HPPA_CPU(cs); =20 - cs->exception_index =3D EXCP_SIGSEGV; + /* ??? Test between data page fault and data memory protection trap, + which would affect si_code. */ + cs->exception_index =3D EXCP_DMP; cpu->env.ior =3D address; return 1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 9c7603588f..d6b86834c1 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -44,14 +44,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, in= t excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) { if (unlikely((target_long)cond < 0)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_OVERFLOW, GETPC()); } } =20 void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_COND, GETPC()); } } =20 @@ -235,7 +235,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t = ra) env->fr[0] =3D (uint64_t)shadow << 32; =20 if (hard_exp & shadow) { - dynexcp(env, EXCP_SIGFPE, ra); + dynexcp(env, EXCP_ASSIST, ra); } } =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8e357cc60c..8d85ed9df3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -462,7 +462,7 @@ static DisasJumpType gen_excp(DisasContext *ctx, int ex= ception) static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_SIGILL)); + return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -1578,7 +1578,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) =20 switch (ctx->iaoq_f) { case 0x00: /* Null pointer call */ - gen_excp_1(EXCP_SIGSEGV); + gen_excp_1(EXCP_IMP); return DISAS_NORETURN; =20 case 0xb0: /* LWS */ @@ -1597,7 +1597,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) =20 default: do_sigill: - gen_excp_1(EXCP_SIGILL); + gen_excp_1(EXCP_ILL); return DISAS_NORETURN; } } @@ -1614,7 +1614,7 @@ static DisasJumpType trans_break(DisasContext *ctx, u= int32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_DEBUG)); + return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); } =20 static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837286273213.61828750216114; Wed, 24 Jan 2018 15:41:26 -0800 (PST) Received: from localhost ([::1]:54542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUfU-0007Tb-AZ for importer@patchew.org; Wed, 24 Jan 2018 18:41:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURK-0004U9-Uh for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURD-0001cw-5F for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:46 -0500 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:36056) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURC-0001cX-Lx for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:39 -0500 Received: by mail-pg0-x22f.google.com with SMTP id k68so3818883pga.3 for ; Wed, 24 Jan 2018 15:26:38 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=bZ7EKkQUfoBfunTKHhRsNTz16bT3SkwxXqAB/N1j7CA=; b=Ji+u1ossVgA/wPKjCNihy3VDtWgfxMO+aUnfl35yftIit9tBPCLgIHtospy0XnLebo RVbcD8jmDMciFoKSSfKPFCT1w6xi7PT8k9URVcwRFCIBVFeNuYJDiWEJ1E2LALd67yxE AeTwuSxPOOuMdwLuORuK8WYsGgOWlYDnJtaB0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=bZ7EKkQUfoBfunTKHhRsNTz16bT3SkwxXqAB/N1j7CA=; b=QeJKB957FKPCgAd045II9uKPvPbbciqmj4bdoRBsGUYIWZjjV0jo/2oA9iwjct0R8u bDTdex4d+hGMy9JRYT5V2e2Y+YkRUWctn0LCjIvZDW3ioVvpTcLaI6lZ6OEQ8ZUEIhpy kKL8GVJOGeYMa/NkcAOLj95gGIfWwbZKc6NZjl3iX40P0MKt0eV9qqmGelmee0OFUcra 1pJAQxnYmC4FPyFj0DBXMfF8tzk/+drLoEvlY9muET6xMPGPyXjatE1DXOpuEm87W+93 hAj6xyL3DDxjHuBcsQY/linXvv5ouoxrZ84YzwA3A/llDcYLjJuZ19mAVgkOVqQWZRfJ X4Zg== X-Gm-Message-State: AKwxytf9FEEM+/3uiLnbZARQVIcHj/ztVJ3EYN3Iehc6pZsgsWgnNd0a oz8QahjFeO2SwilgpKjS6sAR1Fq19mU= X-Google-Smtp-Source: AH8x224boqY1EGPPYRWKG+0uJZZ0tjb7Fe+LINv5MguV0TgxmbKZBVXEfozLYMCJobYSZcxpYhOgmA== X-Received: by 2002:a17:902:7046:: with SMTP id h6-v6mr8565261plt.157.1516836395785; Wed, 24 Jan 2018 15:26:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:45 -0800 Message-Id: <20180124232625.30105-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v3 05/45] target/hppa: Split address size from register size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 48 ++- target/hppa/helper.h | 26 +- target/hppa/gdbstub.c | 19 +- target/hppa/helper.c | 18 +- target/hppa/op_helper.c | 22 +- target/hppa/translate.c | 964 ++++++++++++++++++++++++++++++--------------= ---- 6 files changed, 683 insertions(+), 414 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d84af91860..1524ef91b6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,10 @@ #include "qemu-common.h" #include "cpu-qom.h" =20 -/* We only support hppa-linux-user at present, so 32-bit only. */ -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_LONG_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 =20 #define CPUArchState struct CPUHPPAState =20 @@ -123,17 +123,29 @@ =20 typedef struct CPUHPPAState CPUHPPAState; =20 +#if TARGET_REGISTER_BITS =3D=3D 32 +typedef uint32_t target_ureg; +typedef int32_t target_sreg; +#define TREG_FMT_lx "%08"PRIx32 +#define TREG_FMT_ld "%"PRId32 +#else +typedef uint64_t target_ureg; +typedef int64_t target_sreg; +#define TREG_FMT_lx "%016"PRIx64 +#define TREG_FMT_ld "%"PRId64 +#endif + struct CPUHPPAState { - target_ulong gr[32]; + target_ureg gr[32]; uint64_t fr[32]; =20 - target_ulong sar; - target_ulong cr26; - target_ulong cr27; + target_ureg sar; + target_ureg cr26; + target_ureg cr27; =20 - target_long psw; /* All psw bits except the following: */ - target_ulong psw_n; /* boolean */ - target_long psw_v; /* in most significant bit */ + target_ureg psw; /* All psw bits except the following: */ + target_ureg psw_n; /* boolean */ + target_sreg psw_v; /* in most significant bit */ =20 /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in u= se. @@ -142,13 +154,13 @@ struct CPUHPPAState { * host has the appropriate add-with-carry insn to compute the msb). * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. */ - target_ulong psw_cb; /* in least significant bit of next nibble */ - target_ulong psw_cb_msb; /* boolean */ + target_ureg psw_cb; /* in least significant bit of next nibble */ + target_ureg psw_cb_msb; /* boolean */ =20 - target_ulong iaoq_f; /* front */ - target_ulong iaoq_b; /* back, aka next instruction */ + target_ureg iaoq_f; /* front */ + target_ureg iaoq_b; /* back, aka next instruction */ =20 - target_ulong ior; /* interrupt offset register */ + target_ureg ior; /* interrupt offset register */ =20 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -201,8 +213,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, *pflags =3D env->psw_n; } =20 -target_ulong cpu_hppa_get_psw(CPUHPPAState *env); -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +target_ureg cpu_hppa_get_psw(CPUHPPAState *env); +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); void cpu_hppa_loaded_fr0(CPUHPPAState *env); =20 #define cpu_signal_handler cpu_hppa_signal_handler diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 0a6b900555..c720de523b 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,14 +1,24 @@ +#if TARGET_REGISTER_BITS =3D=3D 64 +# define dh_alias_tr i64 +# define dh_is_64bit_tr 1 +#else +# define dh_alias_tr i32 +# define dh_is_64bit_tr 0 +#endif +#define dh_ctype_tr target_ureg +#define dh_is_signed_tr 0 + DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) +DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr) =20 -DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) =20 -DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tr, tl) +DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tr, tl) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) =20 diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index c37a56f238..228d282fe9 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -26,7 +26,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem= _buf, int n) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ulong val; + target_ureg val; =20 switch (n) { case 0: @@ -61,14 +61,25 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *m= em_buf, int n) } break; } - return gdb_get_regl(mem_buf, val); + + if (TARGET_REGISTER_BITS =3D=3D 64) { + return gdb_get_reg64(mem_buf, val); + } else { + return gdb_get_reg32(mem_buf, val); + } } =20 int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ulong val =3D ldtul_p(mem_buf); + target_ureg val; + + if (TARGET_REGISTER_BITS =3D=3D 64) { + val =3D ldq_p(mem_buf); + } else { + val =3D ldl_p(mem_buf); + } =20 switch (n) { case 0: @@ -108,5 +119,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) } break; } - return sizeof(target_ulong); + return sizeof(target_ureg); } diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6439179a0e..b6521f61fc 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,9 +24,9 @@ #include "fpu/softfloat.h" #include "exec/helper-proto.h" =20 -target_ulong cpu_hppa_get_psw(CPUHPPAState *env) +target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { - target_ulong psw; + target_ureg psw; =20 /* Fold carry bits down to 8 consecutive bits. */ /* ??? Needs tweaking for hppa64. */ @@ -48,9 +48,9 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } =20 -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { - target_ulong cb =3D 0; + target_ureg cb =3D 0; =20 env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n =3D (psw / PSW_N) & 1; @@ -135,13 +135,13 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ulong psw =3D cpu_hppa_get_psw(env); - target_ulong psw_cb; + target_ureg psw =3D cpu_hppa_get_psw(env); + target_ureg psw_cb; char psw_c[20]; int i; =20 cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - env->iaoq_f, env->iaoq_b); + (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); =20 psw_c[0] =3D (psw & PSW_W ? 'W' : '-'); psw_c[1] =3D (psw & PSW_E ? 'E' : '-'); @@ -164,11 +164,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw_c[18] =3D '\0'; psw_cb =3D ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); =20 - cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + cpu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n", psw, psw_cb, psw_c); =20 for (i =3D 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); + cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); if ((i % 4) =3D=3D 3) { cpu_fprintf(f, "\n"); } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d6b86834c1..479bfc0fdf 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -41,14 +41,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, in= t excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } =20 -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) +void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { - if (unlikely((target_long)cond < 0)) { + if (unlikely((target_sreg)cond < 0)) { dynexcp(env, EXCP_OVERFLOW, GETPC()); } } =20 -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) +void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { dynexcp(env, EXCP_COND, GETPC()); @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #endif } =20 -static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel) { uintptr_t ra =3D GETPC(); @@ -104,18 +104,18 @@ static void do_stby_b(CPUHPPAState *env, target_ulong= addr, target_ulong val, } } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_b(env, addr, val, false); } =20 void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_b(env, addr, val, true); } =20 -static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel) { uintptr_t ra =3D GETPC(); @@ -146,18 +146,18 @@ static void do_stby_e(CPUHPPAState *env, target_ulong= addr, target_ulong val, } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_e(env, addr, val, false); } =20 void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_e(env, addr, val, true); } =20 -target_ulong HELPER(probe_r)(target_ulong addr) +target_ureg HELPER(probe_r)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); @@ -166,7 +166,7 @@ target_ulong HELPER(probe_r)(target_ulong addr) #endif } =20 -target_ulong HELPER(probe_w)(target_ulong addr) +target_ureg HELPER(probe_w)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8d85ed9df3..dd96147bf1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -30,9 +30,239 @@ #include "trace-tcg.h" #include "exec/log.h" =20 +/* Since we have a distinction between register size and address size, + we need to redefine all of these. */ + +#undef TCGv +#undef tcg_temp_new +#undef tcg_global_reg_new +#undef tcg_global_mem_new +#undef tcg_temp_local_new +#undef tcg_temp_free + +#if TARGET_LONG_BITS =3D=3D 64 +#define TCGv_tl TCGv_i64 +#define tcg_temp_new_tl tcg_temp_new_i64 +#define tcg_temp_free_tl tcg_temp_free_i64 +#if TARGET_REGISTER_BITS =3D=3D 64 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i64 +#else +#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 +#endif +#else +#define TCGv_tl TCGv_i32 +#define tcg_temp_new_tl tcg_temp_new_i32 +#define tcg_temp_free_tl tcg_temp_free_i32 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i32 +#endif + +#if TARGET_REGISTER_BITS =3D=3D 64 +#define TCGv_reg TCGv_i64 + +#define tcg_temp_new tcg_temp_new_i64 +#define tcg_global_reg_new tcg_global_reg_new_i64 +#define tcg_global_mem_new tcg_global_mem_new_i64 +#define tcg_temp_local_new tcg_temp_local_new_i64 +#define tcg_temp_free tcg_temp_free_i64 + +#define tcg_gen_movi_reg tcg_gen_movi_i64 +#define tcg_gen_mov_reg tcg_gen_mov_i64 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 +#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 +#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 +#define tcg_gen_ld_reg tcg_gen_ld_i64 +#define tcg_gen_st8_reg tcg_gen_st8_i64 +#define tcg_gen_st16_reg tcg_gen_st16_i64 +#define tcg_gen_st32_reg tcg_gen_st32_i64 +#define tcg_gen_st_reg tcg_gen_st_i64 +#define tcg_gen_add_reg tcg_gen_add_i64 +#define tcg_gen_addi_reg tcg_gen_addi_i64 +#define tcg_gen_sub_reg tcg_gen_sub_i64 +#define tcg_gen_neg_reg tcg_gen_neg_i64 +#define tcg_gen_subfi_reg tcg_gen_subfi_i64 +#define tcg_gen_subi_reg tcg_gen_subi_i64 +#define tcg_gen_and_reg tcg_gen_and_i64 +#define tcg_gen_andi_reg tcg_gen_andi_i64 +#define tcg_gen_or_reg tcg_gen_or_i64 +#define tcg_gen_ori_reg tcg_gen_ori_i64 +#define tcg_gen_xor_reg tcg_gen_xor_i64 +#define tcg_gen_xori_reg tcg_gen_xori_i64 +#define tcg_gen_not_reg tcg_gen_not_i64 +#define tcg_gen_shl_reg tcg_gen_shl_i64 +#define tcg_gen_shli_reg tcg_gen_shli_i64 +#define tcg_gen_shr_reg tcg_gen_shr_i64 +#define tcg_gen_shri_reg tcg_gen_shri_i64 +#define tcg_gen_sar_reg tcg_gen_sar_i64 +#define tcg_gen_sari_reg tcg_gen_sari_i64 +#define tcg_gen_brcond_reg tcg_gen_brcond_i64 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 +#define tcg_gen_setcond_reg tcg_gen_setcond_i64 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 +#define tcg_gen_mul_reg tcg_gen_mul_i64 +#define tcg_gen_muli_reg tcg_gen_muli_i64 +#define tcg_gen_div_reg tcg_gen_div_i64 +#define tcg_gen_rem_reg tcg_gen_rem_i64 +#define tcg_gen_divu_reg tcg_gen_divu_i64 +#define tcg_gen_remu_reg tcg_gen_remu_i64 +#define tcg_gen_discard_reg tcg_gen_discard_i64 +#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 +#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 +#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 +#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 +#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 +#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 +#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 +#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i64 +#define tcg_gen_eqv_reg tcg_gen_eqv_i64 +#define tcg_gen_nand_reg tcg_gen_nand_i64 +#define tcg_gen_nor_reg tcg_gen_nor_i64 +#define tcg_gen_orc_reg tcg_gen_orc_i64 +#define tcg_gen_clz_reg tcg_gen_clz_i64 +#define tcg_gen_ctz_reg tcg_gen_ctz_i64 +#define tcg_gen_clzi_reg tcg_gen_clzi_i64 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 +#define tcg_gen_rotl_reg tcg_gen_rotl_i64 +#define tcg_gen_rotli_reg tcg_gen_rotli_i64 +#define tcg_gen_rotr_reg tcg_gen_rotr_i64 +#define tcg_gen_rotri_reg tcg_gen_rotri_i64 +#define tcg_gen_deposit_reg tcg_gen_deposit_i64 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 +#define tcg_gen_extract_reg tcg_gen_extract_i64 +#define tcg_gen_sextract_reg tcg_gen_sextract_i64 +#define tcg_const_reg tcg_const_i64 +#define tcg_const_local_reg tcg_const_local_i64 +#define tcg_gen_movcond_reg tcg_gen_movcond_i64 +#define tcg_gen_add2_reg tcg_gen_add2_i64 +#define tcg_gen_sub2_reg tcg_gen_sub2_i64 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 +#if UINTPTR_MAX =3D=3D UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_trunc_i64_i32(TCGV_PTR_TO_NAT(p), r) +#else +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_mov_i64(TCGV_PTR_TO_NAT(p), r) +#endif +#else +#define TCGv_reg TCGv_i32 +#define tcg_temp_new tcg_temp_new_i32 +#define tcg_global_reg_new tcg_global_reg_new_i32 +#define tcg_global_mem_new tcg_global_mem_new_i32 +#define tcg_temp_local_new tcg_temp_local_new_i32 +#define tcg_temp_free tcg_temp_free_i32 + +#define tcg_gen_movi_reg tcg_gen_movi_i32 +#define tcg_gen_mov_reg tcg_gen_mov_i32 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 +#define tcg_gen_ld32u_reg tcg_gen_ld_i32 +#define tcg_gen_ld32s_reg tcg_gen_ld_i32 +#define tcg_gen_ld_reg tcg_gen_ld_i32 +#define tcg_gen_st8_reg tcg_gen_st8_i32 +#define tcg_gen_st16_reg tcg_gen_st16_i32 +#define tcg_gen_st32_reg tcg_gen_st32_i32 +#define tcg_gen_st_reg tcg_gen_st_i32 +#define tcg_gen_add_reg tcg_gen_add_i32 +#define tcg_gen_addi_reg tcg_gen_addi_i32 +#define tcg_gen_sub_reg tcg_gen_sub_i32 +#define tcg_gen_neg_reg tcg_gen_neg_i32 +#define tcg_gen_subfi_reg tcg_gen_subfi_i32 +#define tcg_gen_subi_reg tcg_gen_subi_i32 +#define tcg_gen_and_reg tcg_gen_and_i32 +#define tcg_gen_andi_reg tcg_gen_andi_i32 +#define tcg_gen_or_reg tcg_gen_or_i32 +#define tcg_gen_ori_reg tcg_gen_ori_i32 +#define tcg_gen_xor_reg tcg_gen_xor_i32 +#define tcg_gen_xori_reg tcg_gen_xori_i32 +#define tcg_gen_not_reg tcg_gen_not_i32 +#define tcg_gen_shl_reg tcg_gen_shl_i32 +#define tcg_gen_shli_reg tcg_gen_shli_i32 +#define tcg_gen_shr_reg tcg_gen_shr_i32 +#define tcg_gen_shri_reg tcg_gen_shri_i32 +#define tcg_gen_sar_reg tcg_gen_sar_i32 +#define tcg_gen_sari_reg tcg_gen_sari_i32 +#define tcg_gen_brcond_reg tcg_gen_brcond_i32 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 +#define tcg_gen_setcond_reg tcg_gen_setcond_i32 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 +#define tcg_gen_mul_reg tcg_gen_mul_i32 +#define tcg_gen_muli_reg tcg_gen_muli_i32 +#define tcg_gen_div_reg tcg_gen_div_i32 +#define tcg_gen_rem_reg tcg_gen_rem_i32 +#define tcg_gen_divu_reg tcg_gen_divu_i32 +#define tcg_gen_remu_reg tcg_gen_remu_i32 +#define tcg_gen_discard_reg tcg_gen_discard_i32 +#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 +#define tcg_gen_extu_i32_reg tcg_gen_mov_i32 +#define tcg_gen_ext_i32_reg tcg_gen_mov_i32 +#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 +#define tcg_gen_ext32u_reg tcg_gen_mov_i32 +#define tcg_gen_ext32s_reg tcg_gen_mov_i32 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 +#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i32 +#define tcg_gen_eqv_reg tcg_gen_eqv_i32 +#define tcg_gen_nand_reg tcg_gen_nand_i32 +#define tcg_gen_nor_reg tcg_gen_nor_i32 +#define tcg_gen_orc_reg tcg_gen_orc_i32 +#define tcg_gen_clz_reg tcg_gen_clz_i32 +#define tcg_gen_ctz_reg tcg_gen_ctz_i32 +#define tcg_gen_clzi_reg tcg_gen_clzi_i32 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 +#define tcg_gen_rotl_reg tcg_gen_rotl_i32 +#define tcg_gen_rotli_reg tcg_gen_rotli_i32 +#define tcg_gen_rotr_reg tcg_gen_rotr_i32 +#define tcg_gen_rotri_reg tcg_gen_rotri_i32 +#define tcg_gen_deposit_reg tcg_gen_deposit_i32 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 +#define tcg_gen_extract_reg tcg_gen_extract_i32 +#define tcg_gen_sextract_reg tcg_gen_sextract_i32 +#define tcg_const_reg tcg_const_i32 +#define tcg_const_local_reg tcg_const_local_i32 +#define tcg_gen_movcond_reg tcg_gen_movcond_i32 +#define tcg_gen_add2_reg tcg_gen_add2_i32 +#define tcg_gen_sub2_reg tcg_gen_sub2_i32 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 +#if UINTPTR_MAX =3D=3D UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p), r) +#else +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p), r) +#endif +#endif /* TARGET_REGISTER_BITS */ + typedef struct DisasCond { TCGCond c; - TCGv a0, a1; + TCGv_reg a0, a1; bool a0_is_n; bool a1_is_0; } DisasCond; @@ -41,13 +271,13 @@ typedef struct DisasContext { DisasContextBase base; CPUState *cs; =20 - target_ulong iaoq_f; - target_ulong iaoq_b; - target_ulong iaoq_n; - TCGv iaoq_n_var; + target_ureg iaoq_f; + target_ureg iaoq_b; + target_ureg iaoq_n; + TCGv_reg iaoq_n_var; =20 int ntemps; - TCGv temps[8]; + TCGv_reg temps[8]; =20 DisasCond null_cond; TCGLabel *null_lab; @@ -72,7 +302,7 @@ typedef struct DisasInsn { DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, const struct DisasInsn *f); union { - void (*ttt)(TCGv, TCGv, TCGv); + void (*ttt)(TCGv_reg, TCGv_reg, TCGv_reg); void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32); void (*dedd)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64); void (*wew)(TCGv_i32, TCGv_env, TCGv_i32); @@ -83,16 +313,16 @@ typedef struct DisasInsn { } DisasInsn; =20 /* global register indexes */ -static TCGv cpu_gr[32]; -static TCGv cpu_iaoq_f; -static TCGv cpu_iaoq_b; -static TCGv cpu_sar; -static TCGv cpu_psw_n; -static TCGv cpu_psw_v; -static TCGv cpu_psw_cb; -static TCGv cpu_psw_cb_msb; -static TCGv cpu_cr26; -static TCGv cpu_cr27; +static TCGv_reg cpu_gr[32]; +static TCGv_reg cpu_iaoq_f; +static TCGv_reg cpu_iaoq_b; +static TCGv_reg cpu_sar; +static TCGv_reg cpu_psw_n; +static TCGv_reg cpu_psw_v; +static TCGv_reg cpu_psw_cb; +static TCGv_reg cpu_psw_cb_msb; +static TCGv_reg cpu_cr26; +static TCGv_reg cpu_cr27; =20 #include "exec/gen-icount.h" =20 @@ -100,7 +330,7 @@ void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } =20 - typedef struct { TCGv *var; const char *name; int ofs; } GlobalVar; + typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] =3D { DEF_VAR(sar), DEF_VAR(cr26), @@ -158,26 +388,26 @@ static DisasCond cond_make_n(void) }; } =20 -static DisasCond cond_make_0(TCGCond c, TCGv a0) +static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) { DisasCond r =3D { .c =3D c, .a1 =3D NULL, .a1_is_0 =3D true }; =20 assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); r.a0 =3D tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); =20 return r; } =20 -static DisasCond cond_make(TCGCond c, TCGv a0, TCGv a1) +static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) { DisasCond r =3D { .c =3D c }; =20 assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); r.a0 =3D tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); r.a1 =3D tcg_temp_new(); - tcg_gen_mov_tl(r.a1, a1); + tcg_gen_mov_reg(r.a1, a1); =20 return r; } @@ -186,7 +416,7 @@ static void cond_prep(DisasCond *cond) { if (cond->a1_is_0) { cond->a1_is_0 =3D false; - cond->a1 =3D tcg_const_tl(0); + cond->a1 =3D tcg_const_reg(0); } } =20 @@ -213,32 +443,32 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv get_temp(DisasContext *ctx) +static TCGv_reg get_temp(DisasContext *ctx) { unsigned i =3D ctx->ntemps++; g_assert(i < ARRAY_SIZE(ctx->temps)); return ctx->temps[i] =3D tcg_temp_new(); } =20 -static TCGv load_const(DisasContext *ctx, target_long v) +static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { - TCGv t =3D get_temp(ctx); - tcg_gen_movi_tl(t, v); + TCGv_reg t =3D get_temp(ctx); + tcg_gen_movi_reg(t, v); return t; } =20 -static TCGv load_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv t =3D get_temp(ctx); - tcg_gen_movi_tl(t, 0); + TCGv_reg t =3D get_temp(ctx); + tcg_gen_movi_reg(t, 0); return t; } else { return cpu_gr[reg]; } } =20 -static TCGv dest_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { return get_temp(ctx); @@ -247,18 +477,18 @@ static TCGv dest_gpr(DisasContext *ctx, unsigned reg) } } =20 -static void save_or_nullify(DisasContext *ctx, TCGv dest, TCGv t) +static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) { if (ctx->null_cond.c !=3D TCG_COND_NEVER) { cond_prep(&ctx->null_cond); - tcg_gen_movcond_tl(ctx->null_cond.c, dest, ctx->null_cond.a0, + tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, ctx->null_cond.a1, dest, t); } else { - tcg_gen_mov_tl(dest, t); + tcg_gen_mov_reg(dest, t); } } =20 -static void save_gpr(DisasContext *ctx, unsigned reg, TCGv t) +static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) { if (reg !=3D 0) { save_or_nullify(ctx, cpu_gr[reg], t); @@ -350,17 +580,17 @@ static void nullify_over(DisasContext *ctx) if (ctx->null_cond.a0_is_n) { ctx->null_cond.a0_is_n =3D false; ctx->null_cond.a0 =3D tcg_temp_new(); - tcg_gen_mov_tl(ctx->null_cond.a0, cpu_psw_n); + tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, so that (1) it's clear after nullifying this insn and (2) if this insn nullifies the next, PSW[N] is valid. */ if (ctx->psw_n_nonzero) { ctx->psw_n_nonzero =3D false; - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } =20 - tcg_gen_brcond_tl(ctx->null_cond.c, ctx->null_cond.a0, + tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } @@ -371,13 +601,13 @@ static void nullify_save(DisasContext *ctx) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER) { if (ctx->psw_n_nonzero) { - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } return; } if (!ctx->null_cond.a0_is_n) { cond_prep(&ctx->null_cond); - tcg_gen_setcond_tl(ctx->null_cond.c, cpu_psw_n, + tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero =3D true; } @@ -390,7 +620,7 @@ static void nullify_save(DisasContext *ctx) static void nullify_set(DisasContext *ctx, bool x) { if (ctx->psw_n_nonzero || x) { - tcg_gen_movi_tl(cpu_psw_n, x); + tcg_gen_movi_reg(cpu_psw_n, x); } } =20 @@ -429,16 +659,16 @@ static DisasJumpType nullify_end(DisasContext *ctx, D= isasJumpType status) return status; } =20 -static void copy_iaoq_entry(TCGv dest, target_ulong ival, TCGv vval) +static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) { if (unlikely(ival =3D=3D -1)) { - tcg_gen_mov_tl(dest, vval); + tcg_gen_mov_reg(dest, vval); } else { - tcg_gen_movi_tl(dest, ival); + tcg_gen_movi_reg(dest, ival); } } =20 -static inline target_ulong iaoq_dest(DisasContext *ctx, target_long disp) +static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) { return ctx->iaoq_f + disp + 8; } @@ -465,7 +695,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } =20 -static bool use_goto_tb(DisasContext *ctx, target_ulong dest) +static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_ena= bled) { @@ -485,12 +715,12 @@ static bool use_nullify_skip(DisasContext *ctx) } =20 static void gen_goto_tb(DisasContext *ctx, int which, - target_ulong f, target_ulong b) + target_ureg f, target_ureg b) { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); - tcg_gen_movi_tl(cpu_iaoq_f, f); - tcg_gen_movi_tl(cpu_iaoq_b, b); + tcg_gen_movi_reg(cpu_iaoq_f, f); + tcg_gen_movi_reg(cpu_iaoq_b, b); tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -505,9 +735,9 @@ static void gen_goto_tb(DisasContext *ctx, int which, =20 /* PA has a habit of taking the LSB of a field and using that as the sign, with the rest of the field becoming the least significant bits. */ -static target_long low_sextract(uint32_t val, int pos, int len) +static target_sreg low_sextract(uint32_t val, int pos, int len) { - target_ulong x =3D -(target_ulong)extract32(val, pos, 1); + target_ureg x =3D -(target_ureg)extract32(val, pos, 1); x =3D (x << (len - 1)) | extract32(val, pos + 1, len - 1); return x; } @@ -541,15 +771,15 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } =20 -static target_long assemble_12(uint32_t insn) +static target_sreg assemble_12(uint32_t insn) { - target_ulong x =3D -(target_ulong)(insn & 1); + target_ureg x =3D -(target_ureg)(insn & 1); x =3D (x << 1) | extract32(insn, 2, 1); x =3D (x << 10) | extract32(insn, 3, 10); return x; } =20 -static target_long assemble_16(uint32_t insn) +static target_sreg assemble_16(uint32_t insn) { /* Take the name from PA2.0, which produces a 16-bit number only with wide mode; otherwise a 14-bit number. Since we don't @@ -557,28 +787,28 @@ static target_long assemble_16(uint32_t insn) return low_sextract(insn, 0, 14); } =20 -static target_long assemble_16a(uint32_t insn) +static target_sreg assemble_16a(uint32_t insn) { /* Take the name from PA2.0, which produces a 14-bit shifted number only with wide mode; otherwise a 12-bit shifted number. Since we don't implement wide mode, this is always the 12-bit number. */ - target_ulong x =3D -(target_ulong)(insn & 1); + target_ureg x =3D -(target_ureg)(insn & 1); x =3D (x << 11) | extract32(insn, 2, 11); return x << 2; } =20 -static target_long assemble_17(uint32_t insn) +static target_sreg assemble_17(uint32_t insn) { - target_ulong x =3D -(target_ulong)(insn & 1); + target_ureg x =3D -(target_ureg)(insn & 1); x =3D (x << 5) | extract32(insn, 16, 5); x =3D (x << 1) | extract32(insn, 2, 1); x =3D (x << 10) | extract32(insn, 3, 10); return x << 2; } =20 -static target_long assemble_21(uint32_t insn) +static target_sreg assemble_21(uint32_t insn) { - target_ulong x =3D -(target_ulong)(insn & 1); + target_ureg x =3D -(target_ureg)(insn & 1); x =3D (x << 11) | extract32(insn, 1, 11); x =3D (x << 2) | extract32(insn, 14, 2); x =3D (x << 5) | extract32(insn, 16, 5); @@ -586,9 +816,9 @@ static target_long assemble_21(uint32_t insn) return x << 11; } =20 -static target_long assemble_22(uint32_t insn) +static target_sreg assemble_22(uint32_t insn) { - target_ulong x =3D -(target_ulong)(insn & 1); + target_ureg x =3D -(target_ureg)(insn & 1); x =3D (x << 10) | extract32(insn, 16, 10); x =3D (x << 1) | extract32(insn, 2, 1); x =3D (x << 10) | extract32(insn, 3, 10); @@ -602,10 +832,11 @@ static target_long assemble_22(uint32_t insn) as a whole it would appear that these relations are similar to what a traditional NZCV set of flags would produce. */ =20 -static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) +static DisasCond do_cond(unsigned cf, TCGv_reg res, + TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; - TCGv tmp; + TCGv_reg tmp; =20 switch (cf >> 1) { case 0: /* Never / TR */ @@ -625,8 +856,8 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb= _msb, TCGv sv) break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); - tcg_gen_neg_tl(tmp, cb_msb); - tcg_gen_and_tl(tmp, tmp, res); + tcg_gen_neg_reg(tmp, cb_msb); + tcg_gen_and_reg(tmp, tmp, res); cond =3D cond_make_0(TCG_COND_EQ, tmp); tcg_temp_free(tmp); break; @@ -635,7 +866,7 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb= _msb, TCGv sv) break; case 7: /* OD / EV */ tmp =3D tcg_temp_new(); - tcg_gen_andi_tl(tmp, res, 1); + tcg_gen_andi_reg(tmp, res, 1); cond =3D cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; @@ -653,7 +884,8 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb= _msb, TCGv sv) can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TC= Gv sv) +static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; =20 @@ -686,7 +918,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv res, TCG= v in1, TCGv in2, TCGv sv) /* Similar, but for logicals, where the carry and overflow bits are not computed, and use of them is undefined. */ =20 -static DisasCond do_log_cond(unsigned cf, TCGv res) +static DisasCond do_log_cond(unsigned cf, TCGv_reg res) { switch (cf >> 1) { case 4: case 5: case 6: @@ -698,7 +930,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv res) =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(unsigned orig, TCGv res) +static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) { unsigned c, f; =20 @@ -716,10 +948,11 @@ static DisasCond do_sed_cond(unsigned orig, TCGv res) =20 /* Similar, but for unit conditions. */ =20 -static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) +static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { DisasCond cond; - TCGv tmp, cb =3D NULL; + TCGv_reg tmp, cb =3D NULL; =20 if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -728,10 +961,10 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, = TCGv in1, TCGv in2) */ cb =3D tcg_temp_new(); tmp =3D tcg_temp_new(); - tcg_gen_or_tl(cb, in1, in2); - tcg_gen_and_tl(tmp, in1, in2); - tcg_gen_andc_tl(cb, cb, res); - tcg_gen_or_tl(cb, cb, tmp); + tcg_gen_or_reg(cb, in1, in2); + tcg_gen_and_reg(tmp, in1, in2); + tcg_gen_andc_reg(cb, cb, res); + tcg_gen_or_reg(cb, cb, tmp); tcg_temp_free(tmp); } =20 @@ -747,34 +980,34 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, = TCGv in1, TCGv in2) * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp =3D tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x01010101u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80808080u); + tcg_gen_subi_reg(tmp, res, 0x01010101u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; =20 case 3: /* SHZ / NHZ */ tmp =3D tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x00010001u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80008000u); + tcg_gen_subi_reg(tmp, res, 0x00010001u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; =20 case 4: /* SDC / NDC */ - tcg_gen_andi_tl(cb, cb, 0x88888888u); + tcg_gen_andi_reg(cb, cb, 0x88888888u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 6: /* SBC / NBC */ - tcg_gen_andi_tl(cb, cb, 0x80808080u); + tcg_gen_andi_reg(cb, cb, 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 7: /* SHC / NHC */ - tcg_gen_andi_tl(cb, cb, 0x80008000u); + tcg_gen_andi_reg(cb, cb, 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 @@ -792,38 +1025,40 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res,= TCGv in1, TCGv in2) } =20 /* Compute signed overflow for addition. */ -static TCGv do_add_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { - TCGv sv =3D get_temp(ctx); - TCGv tmp =3D tcg_temp_new(); + TCGv_reg sv =3D get_temp(ctx); + TCGv_reg tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_andc_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_andc_reg(sv, sv, tmp); tcg_temp_free(tmp); =20 return sv; } =20 /* Compute signed overflow for subtraction. */ -static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { - TCGv sv =3D get_temp(ctx); - TCGv tmp =3D tcg_temp_new(); + TCGv_reg sv =3D get_temp(ctx); + TCGv_reg tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_and_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_and_reg(sv, sv, tmp); tcg_temp_free(tmp); =20 return sv; } =20 -static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, - unsigned shift, bool is_l, bool is_tsv, bool i= s_tc, - bool is_c, unsigned cf) +static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned shift, bool is_l, + bool is_tsv, bool is_tc, bool is_c, unsigned c= f) { - TCGv dest, cb, cb_msb, sv, tmp; + TCGv_reg dest, cb, cb_msb, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -833,27 +1068,27 @@ static DisasJumpType do_add(DisasContext *ctx, unsig= ned rt, TCGv in1, TCGv in2, =20 if (shift) { tmp =3D get_temp(ctx); - tcg_gen_shli_tl(tmp, in1, shift); + tcg_gen_shli_reg(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || c =3D=3D 4 || c =3D=3D 5) { - TCGv zero =3D tcg_const_tl(0); + TCGv_reg zero =3D tcg_const_reg(0); cb_msb =3D get_temp(ctx); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, ze= ro); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, z= ero); } tcg_temp_free(zero); if (!is_l) { cb =3D get_temp(ctx); - tcg_gen_xor_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } } else { - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); if (is_c) { - tcg_gen_add_tl(dest, dest, cpu_psw_cb_msb); + tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); } } =20 @@ -872,7 +1107,7 @@ static DisasJumpType do_add(DisasContext *ctx, unsigne= d rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp =3D tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -891,10 +1126,11 @@ static DisasJumpType do_add(DisasContext *ctx, unsig= ned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } =20 -static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, - bool is_tsv, bool is_b, bool is_tc, unsigned c= f) +static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, bool is_tsv, bool is_b, + bool is_tc, unsigned cf) { - TCGv dest, sv, cb, cb_msb, zero, tmp; + TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -902,21 +1138,21 @@ static DisasJumpType do_sub(DisasContext *ctx, unsig= ned rt, TCGv in1, TCGv in2, cb =3D tcg_temp_new(); cb_msb =3D tcg_temp_new(); =20 - zero =3D tcg_const_tl(0); + zero =3D tcg_const_reg(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ - tcg_gen_not_tl(cb, in2); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cb, zero); - tcg_gen_xor_tl(cb, cb, in1); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_not_reg(cb, in2); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_xor_reg(cb, cb, in1); + tcg_gen_xor_reg(cb, cb, dest); } else { /* DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer operations by seeding the high word with 1 and subtracting. */ - tcg_gen_movi_tl(cb_msb, 1); - tcg_gen_sub2_tl(dest, cb_msb, in1, cb_msb, in2, zero); - tcg_gen_eqv_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_movi_reg(cb_msb, 1); + tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); + tcg_gen_eqv_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } tcg_temp_free(zero); =20 @@ -940,7 +1176,7 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigne= d rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp =3D tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -957,14 +1193,14 @@ static DisasJumpType do_sub(DisasContext *ctx, unsig= ned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } =20 -static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf) +static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in= 1, + TCGv_reg in2, unsigned cf) { - TCGv dest, sv; + TCGv_reg dest, sv; DisasCond cond; =20 dest =3D tcg_temp_new(); - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); =20 /* Compute signed overflow if required. */ sv =3D NULL; @@ -976,7 +1212,7 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsi= gned rt, TCGv in1, cond =3D do_sub_cond(cf, dest, in1, in2, sv); =20 /* Clear. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); tcg_temp_free(dest); =20 @@ -986,10 +1222,11 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, un= signed rt, TCGv in1, return DISAS_NEXT; } =20 -static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, - unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest =3D dest_gpr(ctx, rt); + TCGv_reg dest =3D dest_gpr(ctx, rt); =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1003,11 +1240,11 @@ static DisasJumpType do_log(DisasContext *ctx, unsi= gned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } =20 -static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf, bool is_tc, - void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf, bool is_tc, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest; + TCGv_reg dest; DisasCond cond; =20 if (cf =3D=3D 0) { @@ -1022,9 +1259,9 @@ static DisasJumpType do_unit(DisasContext *ctx, unsig= ned rt, TCGv in1, cond =3D do_unit_cond(cf, dest, in1, in2); =20 if (is_tc) { - TCGv tmp =3D tcg_temp_new(); + TCGv_reg tmp =3D tcg_temp_new(); cond_prep(&cond); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -1042,10 +1279,10 @@ static DisasJumpType do_unit(DisasContext *ctx, uns= igned rt, TCGv in1, * =3D 0 for no base register update. */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1055,10 +1292,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 = dest, unsigned rb, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } =20 if (modify =3D=3D 0) { @@ -1072,10 +1309,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 = dest, unsigned rb, } =20 static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1085,10 +1322,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 = dest, unsigned rb, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } =20 if (modify =3D=3D 0) { @@ -1102,10 +1339,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 = dest, unsigned rb, } =20 static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1115,10 +1352,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32= src, unsigned rb, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } =20 tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); @@ -1130,10 +1367,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32= src, unsigned rb, } =20 static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1143,10 +1380,10 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } =20 tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); @@ -1157,19 +1394,19 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, tcg_temp_free(addr); } =20 -#if TARGET_LONG_BITS =3D=3D 64 -#define do_load_tl do_load_64 -#define do_store_tl do_store_64 +#if TARGET_REGISTER_BITS =3D=3D 64 +#define do_load_reg do_load_64 +#define do_store_reg do_store_64 #else -#define do_load_tl do_load_32 -#define do_store_tl do_store_32 +#define do_load_reg do_load_32 +#define do_store_reg do_store_32 #endif =20 static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv dest; + TCGv_reg dest; =20 nullify_over(ctx); =20 @@ -1180,14 +1417,14 @@ static DisasJumpType do_load(DisasContext *ctx, uns= igned rt, unsigned rb, /* Make sure if RT =3D=3D RB, we see the result of the load. */ dest =3D get_temp(ctx); } - do_load_tl(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); save_gpr(ctx, rt, dest); =20 return nullify_end(ctx, DISAS_NEXT); } =20 static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1207,7 +1444,7 @@ static DisasJumpType do_floadw(DisasContext *ctx, uns= igned rt, unsigned rb, } =20 static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1227,15 +1464,15 @@ static DisasJumpType do_floadd(DisasContext *ctx, u= nsigned rt, unsigned rb, } =20 static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_long disp, int modify, TCGMemOp mop) + target_sreg disp, int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_tl(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } =20 static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned r= b, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1250,7 +1487,7 @@ static DisasJumpType do_fstorew(DisasContext *ctx, un= signed rt, unsigned rb, } =20 static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned r= b, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1370,7 +1607,7 @@ static DisasJumpType do_fop_dedd(DisasContext *ctx, u= nsigned rt, =20 /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, +static DisasJumpType do_dbranch(DisasContext *ctx, target_ureg dest, unsigned link, bool is_n) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { @@ -1407,10 +1644,10 @@ static DisasJumpType do_dbranch(DisasContext *ctx, = target_ulong dest, =20 /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool = is_n, +static DisasJumpType do_cbranch(DisasContext *ctx, target_sreg disp, bool = is_n, DisasCond *cond) { - target_ulong dest =3D iaoq_dest(ctx, disp); + target_ureg dest =3D iaoq_dest(ctx, disp); TCGLabel *taken =3D NULL; TCGCond c =3D cond->c; bool n; @@ -1427,7 +1664,7 @@ static DisasJumpType do_cbranch(DisasContext *ctx, ta= rget_long disp, bool is_n, =20 taken =3D gen_new_label(); cond_prep(cond); - tcg_gen_brcond_tl(c, cond->a0, cond->a1, taken); + tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); cond_free(cond); =20 /* Not taken: Condition not satisfied; nullify on backward branches. */ @@ -1468,10 +1705,10 @@ static DisasJumpType do_cbranch(DisasContext *ctx, = target_long disp, bool is_n, =20 /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, +static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, unsigned link, bool is_n) { - TCGv a0, a1, next, tmp; + TCGv_reg a0, a1, next, tmp; TCGCond c; =20 assert(ctx->null_lab =3D=3D NULL); @@ -1481,7 +1718,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv dest, copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } next =3D get_temp(ctx); - tcg_gen_mov_tl(next, dest); + tcg_gen_mov_reg(next, dest); ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D next; if (is_n) { @@ -1500,12 +1737,12 @@ static DisasJumpType do_ibranch(DisasContext *ctx, = TCGv dest, /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we can simply store DEST optimistically. Similarly with IAOQ_B. = */ - tcg_gen_mov_tl(cpu_iaoq_f, dest); - tcg_gen_addi_tl(cpu_iaoq_b, dest, 4); + tcg_gen_mov_reg(cpu_iaoq_f, dest); + tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); =20 nullify_over(ctx); if (link !=3D 0) { - tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); + tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); @@ -1519,19 +1756,19 @@ static DisasJumpType do_ibranch(DisasContext *ctx, = TCGv dest, next =3D get_temp(ctx); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_tl(c, next, a0, a1, tmp, dest); + tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D next; =20 if (link !=3D 0) { - tcg_gen_movcond_tl(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); + tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp= ); } =20 if (is_n) { /* The branch nullifies the next insn, which means the state o= f N after the branch is the inverse of the state of N that appl= ied to the branch. */ - tcg_gen_setcond_tl(tcg_invert_cond(c), cpu_psw_n, a0, a1); + tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); cond_free(&ctx->null_cond); ctx->null_cond =3D cond_make_n(); ctx->psw_n_nonzero =3D true; @@ -1560,7 +1797,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) case TCG_COND_NEVER: break; case TCG_COND_ALWAYS: - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); goto do_sigill; default: /* Since this is always the first (and only) insn within the @@ -1586,9 +1823,9 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_tl(cpu_cr27, cpu_gr[26]); - tcg_gen_mov_tl(cpu_iaoq_f, cpu_gr[31]); - tcg_gen_addi_tl(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; =20 case 0x100: /* SYSCALL */ @@ -1631,8 +1868,8 @@ static DisasJumpType trans_mfia(DisasContext *ctx, ui= nt32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); - TCGv tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, ctx->iaoq_f); + TCGv_reg tmp =3D dest_gpr(ctx, rt); + tcg_gen_movi_reg(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); @@ -1643,10 +1880,10 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, = uint32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); - TCGv tmp =3D dest_gpr(ctx, rt); + TCGv_reg tmp =3D dest_gpr(ctx, rt); =20 /* ??? We don't implement space registers. */ - tcg_gen_movi_tl(tmp, 0); + tcg_gen_movi_reg(tmp, 0); save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); @@ -1658,7 +1895,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, u= int32_t insn, { unsigned rt =3D extract32(insn, 0, 5); unsigned ctl =3D extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; =20 switch (ctl) { case 11: /* SAR */ @@ -1666,7 +1903,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, u= int32_t insn, if (extract32(insn, 14, 1) =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); - tcg_gen_andi_tl(tmp, cpu_sar, 31); + tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); break; } @@ -1698,11 +1935,11 @@ static DisasJumpType trans_mtctl(DisasContext *ctx,= uint32_t insn, { unsigned rin =3D extract32(insn, 16, 5); unsigned ctl =3D extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; =20 if (ctl =3D=3D 11) { /* SAR */ tmp =3D tcg_temp_new(); - tcg_gen_andi_tl(tmp, load_gpr(ctx, rin), TARGET_LONG_BITS - 1); + tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1= ); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); } else { @@ -1718,10 +1955,10 @@ static DisasJumpType trans_mtsarcm(DisasContext *ct= x, uint32_t insn, const DisasInsn *di) { unsigned rin =3D extract32(insn, 16, 5); - TCGv tmp =3D tcg_temp_new(); + TCGv_reg tmp =3D tcg_temp_new(); =20 - tcg_gen_not_tl(tmp, load_gpr(ctx, rin)); - tcg_gen_andi_tl(tmp, tmp, TARGET_LONG_BITS - 1); + tcg_gen_not_reg(tmp, load_gpr(ctx, rin)); + tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); =20 @@ -1733,10 +1970,10 @@ static DisasJumpType trans_ldsid(DisasContext *ctx,= uint32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); - TCGv dest =3D dest_gpr(ctx, rt); + TCGv_reg dest =3D dest_gpr(ctx, rt); =20 /* Since we don't implement space registers, this returns zero. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); =20 cond_free(&ctx->null_cond); @@ -1761,12 +1998,12 @@ static DisasJumpType trans_base_idx_mod(DisasContex= t *ctx, uint32_t insn, { unsigned rb =3D extract32(insn, 21, 5); unsigned rx =3D extract32(insn, 16, 5); - TCGv dest =3D dest_gpr(ctx, rb); - TCGv src1 =3D load_gpr(ctx, rb); - TCGv src2 =3D load_gpr(ctx, rx); + TCGv_reg dest =3D dest_gpr(ctx, rb); + TCGv_reg src1 =3D load_gpr(ctx, rb); + TCGv_reg src2 =3D load_gpr(ctx, rx); =20 /* The only thing we need to do is the base register modification. */ - tcg_gen_add_tl(dest, src1, src2); + tcg_gen_add_reg(dest, src1, src2); save_gpr(ctx, rb, dest); =20 cond_free(&ctx->null_cond); @@ -1779,7 +2016,7 @@ static DisasJumpType trans_probe(DisasContext *ctx, u= int32_t insn, unsigned rt =3D extract32(insn, 0, 5); unsigned rb =3D extract32(insn, 21, 5); unsigned is_write =3D extract32(insn, 6, 1); - TCGv dest; + TCGv_reg dest; =20 nullify_over(ctx); =20 @@ -1821,7 +2058,7 @@ static DisasJumpType trans_add(DisasContext *ctx, uin= t32_t insn, unsigned ext =3D extract32(insn, 8, 4); unsigned shift =3D extract32(insn, 6, 2); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_c =3D false; bool is_l =3D false; bool is_tc =3D false; @@ -1864,7 +2101,7 @@ static DisasJumpType trans_sub(DisasContext *ctx, uin= t32_t insn, unsigned cf =3D extract32(insn, 12, 4); unsigned ext =3D extract32(insn, 6, 6); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_b =3D false; bool is_tc =3D false; bool is_tsv =3D false; @@ -1908,7 +2145,7 @@ static DisasJumpType trans_log(DisasContext *ctx, uin= t32_t insn, unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -1928,8 +2165,8 @@ static DisasJumpType trans_copy(DisasContext *ctx, ui= nt32_t insn, unsigned rt =3D extract32(insn, 0, 5); =20 if (r1 =3D=3D 0) { - TCGv dest =3D dest_gpr(ctx, rt); - tcg_gen_movi_tl(dest, 0); + TCGv_reg dest =3D dest_gpr(ctx, rt); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); } else { save_gpr(ctx, rt, cpu_gr[r1]); @@ -1945,7 +2182,7 @@ static DisasJumpType trans_cmpclr(DisasContext *ctx, = uint32_t insn, unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -1964,7 +2201,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, ui= nt32_t insn, unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -1972,7 +2209,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, ui= nt32_t insn, } tcg_r1 =3D load_gpr(ctx, r1); tcg_r2 =3D load_gpr(ctx, r2); - ret =3D do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_tl); + ret =3D do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_reg); return nullify_end(ctx, ret); } =20 @@ -1984,7 +2221,7 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, = uint32_t insn, unsigned cf =3D extract32(insn, 12, 4); unsigned is_tc =3D extract32(insn, 6, 1); unsigned rt =3D extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2, tmp; + TCGv_reg tcg_r1, tcg_r2, tmp; DisasJumpType ret; =20 if (cf) { @@ -1993,8 +2230,8 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, = uint32_t insn, tcg_r1 =3D load_gpr(ctx, r1); tcg_r2 =3D load_gpr(ctx, r2); tmp =3D get_temp(ctx); - tcg_gen_not_tl(tmp, tcg_r2); - ret =3D do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_tl); + tcg_gen_not_reg(tmp, tcg_r2); + ret =3D do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_reg); return nullify_end(ctx, ret); } =20 @@ -2005,20 +2242,20 @@ static DisasJumpType trans_dcor(DisasContext *ctx, = uint32_t insn, unsigned cf =3D extract32(insn, 12, 4); unsigned is_i =3D extract32(insn, 6, 1); unsigned rt =3D extract32(insn, 0, 5); - TCGv tmp; + TCGv_reg tmp; DisasJumpType ret; =20 nullify_over(ctx); =20 tmp =3D get_temp(ctx); - tcg_gen_shri_tl(tmp, cpu_psw_cb, 3); + tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); if (!is_i) { - tcg_gen_not_tl(tmp, tmp); + tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_tl(tmp, tmp, 0x11111111); - tcg_gen_muli_tl(tmp, tmp, 6); + tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_muli_reg(tmp, tmp, 6); ret =3D do_unit(ctx, rt, tmp, load_gpr(ctx, r2), cf, false, - is_i ? tcg_gen_add_tl : tcg_gen_sub_tl); + is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); =20 return nullify_end(ctx, ret); } @@ -2030,7 +2267,7 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint= 32_t insn, unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); - TCGv dest, add1, add2, addc, zero, in1, in2; + TCGv_reg dest, add1, add2, addc, zero, in1, in2; =20 nullify_over(ctx); =20 @@ -2041,19 +2278,19 @@ static DisasJumpType trans_ds(DisasContext *ctx, ui= nt32_t insn, add2 =3D tcg_temp_new(); addc =3D tcg_temp_new(); dest =3D tcg_temp_new(); - zero =3D tcg_const_tl(0); + zero =3D tcg_const_reg(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ - tcg_gen_add_tl(add1, in1, in1); - tcg_gen_add_tl(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, in1, in1); + tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); =20 /* Add or subtract R2, depending on PSW[V]. Proper computation of carry{8} requires that we subtract via + ~R2 + 1, as described in the manual. By extracting and masking V, we can produce the proper inputs to the addition without movcond. */ - tcg_gen_sari_tl(addc, cpu_psw_v, TARGET_LONG_BITS - 1); - tcg_gen_xor_tl(add2, in2, addc); - tcg_gen_andi_tl(addc, addc, 1); + tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + tcg_gen_xor_reg(add2, in2, addc); + tcg_gen_andi_reg(addc, addc, 1); /* ??? This is only correct for 32-bit. */ tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); @@ -2065,16 +2302,16 @@ static DisasJumpType trans_ds(DisasContext *ctx, ui= nt32_t insn, save_gpr(ctx, rt, dest); =20 /* Write back PSW[CB]. */ - tcg_gen_xor_tl(cpu_psw_cb, add1, add2); - tcg_gen_xor_tl(cpu_psw_cb, cpu_psw_cb, dest); + tcg_gen_xor_reg(cpu_psw_cb, add1, add2); + tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ - tcg_gen_neg_tl(cpu_psw_v, cpu_psw_cb_msb); - tcg_gen_xor_tl(cpu_psw_v, cpu_psw_v, in2); + tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ if (cf) { - TCGv sv =3D NULL; + TCGv_reg sv =3D NULL; if (cf >> 1 =3D=3D 6) { /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); @@ -2092,10 +2329,10 @@ static DisasJumpType trans_ds(DisasContext *ctx, ui= nt32_t insn, static const DisasInsn table_arith_log[] =3D { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ - { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_andc_tl }, - { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_and_tl }, - { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_or_tl }, - { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_xor_tl }, + { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_andc_reg }, + { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_and_reg }, + { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_or_reg }, + { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_xor_reg }, { 0x08000880u, 0xfc000fe0u, trans_cmpclr }, { 0x08000380u, 0xfc000fe0u, trans_uxor }, { 0x08000980u, 0xfc000fa0u, trans_uaddcm }, @@ -2109,13 +2346,13 @@ static const DisasInsn table_arith_log[] =3D { =20 static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) { - target_long im =3D low_sextract(insn, 0, 11); + target_sreg im =3D low_sextract(insn, 0, 11); unsigned e1 =3D extract32(insn, 11, 1); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); unsigned o1 =3D extract32(insn, 26, 1); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -2131,12 +2368,12 @@ static DisasJumpType trans_addi(DisasContext *ctx, = uint32_t insn) =20 static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) { - target_long im =3D low_sextract(insn, 0, 11); + target_sreg im =3D low_sextract(insn, 0, 11); unsigned e1 =3D extract32(insn, 11, 1); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -2152,11 +2389,11 @@ static DisasJumpType trans_subi(DisasContext *ctx, = uint32_t insn) =20 static DisasJumpType trans_cmpiclr(DisasContext *ctx, uint32_t insn) { - target_long im =3D low_sextract(insn, 0, 11); + target_sreg im =3D low_sextract(insn, 0, 11); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; =20 if (cf) { @@ -2224,7 +2461,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, ui= nt32_t insn, unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); TCGMemOp mop =3D MO_TEUL | MO_ALIGN_16; - TCGv zero, addr, base, dest; + TCGv_reg zero, addr, base, dest; int modify, disp =3D 0, scale =3D 0; =20 nullify_over(ctx); @@ -2252,15 +2489,15 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, = uint32_t insn, addr =3D tcg_temp_new(); base =3D load_gpr(ctx, rb); if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } =20 - zero =3D tcg_const_tl(0); - tcg_gen_atomic_xchg_tl(dest, (modify <=3D 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero =3D tcg_const_reg(0); + tcg_gen_atomic_xchg_reg(dest, (modify <=3D 0 ? addr : base), + zero, MMU_USER_IDX, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -2272,20 +2509,20 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, = uint32_t insn, static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { - target_long disp =3D low_sextract(insn, 0, 5); + target_sreg disp =3D low_sextract(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); unsigned a =3D extract32(insn, 13, 1); unsigned rt =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); - TCGv addr, val; + TCGv_reg addr, val; =20 nullify_over(ctx); =20 addr =3D tcg_temp_new(); if (m || disp =3D=3D 0) { - tcg_gen_mov_tl(addr, load_gpr(ctx, rb)); + tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); } else { - tcg_gen_addi_tl(addr, load_gpr(ctx, rb), disp); + tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); } val =3D load_gpr(ctx, rt); =20 @@ -2304,8 +2541,8 @@ static DisasJumpType trans_stby(DisasContext *ctx, ui= nt32_t insn, } =20 if (m) { - tcg_gen_addi_tl(addr, addr, disp); - tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_addi_reg(addr, addr, disp); + tcg_gen_andi_reg(addr, addr, ~3); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -2324,10 +2561,10 @@ static const DisasInsn table_index_mem[] =3D { static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) { unsigned rt =3D extract32(insn, 21, 5); - target_long i =3D assemble_21(insn); - TCGv tcg_rt =3D dest_gpr(ctx, rt); + target_sreg i =3D assemble_21(insn); + TCGv_reg tcg_rt =3D dest_gpr(ctx, rt); =20 - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); =20 @@ -2337,11 +2574,11 @@ static DisasJumpType trans_ldil(DisasContext *ctx, = uint32_t insn) static DisasJumpType trans_addil(DisasContext *ctx, uint32_t insn) { unsigned rt =3D extract32(insn, 21, 5); - target_long i =3D assemble_21(insn); - TCGv tcg_rt =3D load_gpr(ctx, rt); - TCGv tcg_r1 =3D dest_gpr(ctx, 1); + target_sreg i =3D assemble_21(insn); + TCGv_reg tcg_rt =3D load_gpr(ctx, rt); + TCGv_reg tcg_r1 =3D dest_gpr(ctx, 1); =20 - tcg_gen_addi_tl(tcg_r1, tcg_rt, i); + tcg_gen_addi_reg(tcg_r1, tcg_rt, i); save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); =20 @@ -2352,15 +2589,15 @@ static DisasJumpType trans_ldo(DisasContext *ctx, u= int32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); - target_long i =3D assemble_16(insn); - TCGv tcg_rt =3D dest_gpr(ctx, rt); + target_sreg i =3D assemble_16(insn); + TCGv_reg tcg_rt =3D dest_gpr(ctx, rt); =20 /* Special case rb =3D=3D 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ if (rb =3D=3D 0) { - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); } else { - tcg_gen_addi_tl(tcg_rt, cpu_gr[rb], i); + tcg_gen_addi_reg(tcg_rt, cpu_gr[rb], i); } save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); @@ -2373,7 +2610,7 @@ static DisasJumpType trans_load(DisasContext *ctx, ui= nt32_t insn, { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); - target_long i =3D assemble_16(insn); + target_sreg i =3D assemble_16(insn); =20 return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mo= p); } @@ -2382,7 +2619,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, = uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); - target_long i =3D assemble_16a(insn); + target_sreg i =3D assemble_16a(insn); unsigned ext2 =3D extract32(insn, 1, 2); =20 switch (ext2) { @@ -2401,7 +2638,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, = uint32_t insn) =20 static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) { - target_long i =3D assemble_16a(insn); + target_sreg i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); unsigned a =3D extract32(insn, 2, 1); unsigned t0 =3D extract32(insn, 16, 5); @@ -2416,7 +2653,7 @@ static DisasJumpType trans_store(DisasContext *ctx, u= int32_t insn, { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); - target_long i =3D assemble_16(insn); + target_sreg i =3D assemble_16(insn); =20 return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } @@ -2425,7 +2662,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx,= uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); - target_long i =3D assemble_16a(insn); + target_sreg i =3D assemble_16a(insn); unsigned ext2 =3D extract32(insn, 1, 2); =20 switch (ext2) { @@ -2443,7 +2680,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx,= uint32_t insn) =20 static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) { - target_long i =3D assemble_16a(insn); + target_sreg i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); unsigned a =3D extract32(insn, 2, 1); unsigned t0 =3D extract32(insn, 16, 5); @@ -2525,12 +2762,12 @@ static DisasJumpType trans_copr_dw(DisasContext *ct= x, uint32_t insn) static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm, bool is_dw) { - target_long disp =3D assemble_12(insn) * 4; + target_sreg disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); unsigned c =3D extract32(insn, 13, 3); unsigned r =3D extract32(insn, 21, 5); unsigned cf =3D c * 2 + !is_true; - TCGv dest, in1, in2, sv; + TCGv_reg dest, in1, in2, sv; DisasCond cond; =20 nullify_over(ctx); @@ -2543,7 +2780,7 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, ui= nt32_t insn, in2 =3D load_gpr(ctx, r); dest =3D get_temp(ctx); =20 - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); =20 sv =3D NULL; if (c =3D=3D 6) { @@ -2557,12 +2794,12 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, = uint32_t insn, static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm) { - target_long disp =3D assemble_12(insn) * 4; + target_sreg disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); unsigned c =3D extract32(insn, 13, 3); unsigned r =3D extract32(insn, 21, 5); unsigned cf =3D c * 2 + !is_true; - TCGv dest, in1, in2, sv, cb_msb; + TCGv_reg dest, in1, in2, sv, cb_msb; DisasCond cond; =20 nullify_over(ctx); @@ -2579,15 +2816,15 @@ static DisasJumpType trans_addb(DisasContext *ctx, = uint32_t insn, =20 switch (c) { default: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); break; case 4: case 5: cb_msb =3D get_temp(ctx); - tcg_gen_movi_tl(cb_msb, 0); - tcg_gen_add2_tl(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_movi_reg(cb_msb, 0); + tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); break; case 6: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); sv =3D do_add_sv(ctx, dest, in1, in2); break; } @@ -2598,13 +2835,13 @@ static DisasJumpType trans_addb(DisasContext *ctx, = uint32_t insn, =20 static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) { - target_long disp =3D assemble_12(insn) * 4; + target_sreg disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); unsigned c =3D extract32(insn, 15, 1); unsigned r =3D extract32(insn, 16, 5); unsigned p =3D extract32(insn, 21, 5); unsigned i =3D extract32(insn, 26, 1); - TCGv tmp, tcg_r; + TCGv_reg tmp, tcg_r; DisasCond cond; =20 nullify_over(ctx); @@ -2612,9 +2849,9 @@ static DisasJumpType trans_bb(DisasContext *ctx, uint= 32_t insn) tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, r); if (i) { - tcg_gen_shli_tl(tmp, tcg_r, p); + tcg_gen_shli_reg(tmp, tcg_r, p); } else { - tcg_gen_shl_tl(tmp, tcg_r, cpu_sar); + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); } =20 cond =3D cond_make_0(c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -2624,23 +2861,23 @@ static DisasJumpType trans_bb(DisasContext *ctx, ui= nt32_t insn) =20 static DisasJumpType trans_movb(DisasContext *ctx, uint32_t insn, bool is_= imm) { - target_long disp =3D assemble_12(insn) * 4; + target_sreg disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); unsigned c =3D extract32(insn, 13, 3); unsigned t =3D extract32(insn, 16, 5); unsigned r =3D extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; DisasCond cond; =20 nullify_over(ctx); =20 dest =3D dest_gpr(ctx, r); if (is_imm) { - tcg_gen_movi_tl(dest, low_sextract(t, 0, 5)); + tcg_gen_movi_reg(dest, low_sextract(t, 0, 5)); } else if (t =3D=3D 0) { - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); } else { - tcg_gen_mov_tl(dest, cpu_gr[t]); + tcg_gen_mov_reg(dest, cpu_gr[t]); } =20 cond =3D do_sed_cond(c, dest); @@ -2654,7 +2891,7 @@ static DisasJumpType trans_shrpw_sar(DisasContext *ct= x, uint32_t insn, unsigned c =3D extract32(insn, 13, 3); unsigned r1 =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; =20 if (c) { nullify_over(ctx); @@ -2662,22 +2899,22 @@ static DisasJumpType trans_shrpw_sar(DisasContext *= ctx, uint32_t insn, =20 dest =3D dest_gpr(ctx, rt); if (r1 =3D=3D 0) { - tcg_gen_ext32u_tl(dest, load_gpr(ctx, r2)); - tcg_gen_shr_tl(dest, dest, cpu_sar); + tcg_gen_ext32u_reg(dest, load_gpr(ctx, r2)); + tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (r1 =3D=3D r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, load_gpr(ctx, r2)); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 - tcg_gen_concat_tl_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); - tcg_gen_extu_tl_i64(s, cpu_sar); + tcg_gen_concat_reg_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); + tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); - tcg_gen_trunc_i64_tl(dest, t); + tcg_gen_trunc_i64_reg(dest, t); =20 tcg_temp_free_i64(t); tcg_temp_free_i64(s); @@ -2701,7 +2938,7 @@ static DisasJumpType trans_shrpw_imm(DisasContext *ct= x, uint32_t insn, unsigned r1 =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); unsigned sa =3D 31 - cpos; - TCGv dest, t2; + TCGv_reg dest, t2; =20 if (c) { nullify_over(ctx); @@ -2711,16 +2948,16 @@ static DisasJumpType trans_shrpw_imm(DisasContext *= ctx, uint32_t insn, t2 =3D load_gpr(ctx, r2); if (r1 =3D=3D r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, t2); + tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else if (r1 =3D=3D 0) { - tcg_gen_extract_tl(dest, t2, sa, 32 - sa); + tcg_gen_extract_reg(dest, t2, sa, 32 - sa); } else { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_extract_tl(t0, t2, sa, 32 - sa); - tcg_gen_deposit_tl(dest, t0, cpu_gr[r1], 32 - sa, sa); + TCGv_reg t0 =3D tcg_temp_new(); + tcg_gen_extract_reg(t0, t2, sa, 32 - sa); + tcg_gen_deposit_reg(dest, t0, cpu_gr[r1], 32 - sa, sa); tcg_temp_free(t0); } save_gpr(ctx, rt, dest); @@ -2742,7 +2979,7 @@ static DisasJumpType trans_extrw_sar(DisasContext *ct= x, uint32_t insn, unsigned rt =3D extract32(insn, 16, 5); unsigned rr =3D extract32(insn, 21, 5); unsigned len =3D 32 - clen; - TCGv dest, src, tmp; + TCGv_reg dest, src, tmp; =20 if (c) { nullify_over(ctx); @@ -2753,13 +2990,13 @@ static DisasJumpType trans_extrw_sar(DisasContext *= ctx, uint32_t insn, tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_xori_tl(tmp, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); if (is_se) { - tcg_gen_sar_tl(dest, src, tmp); - tcg_gen_sextract_tl(dest, dest, 0, len); + tcg_gen_sar_reg(dest, src, tmp); + tcg_gen_sextract_reg(dest, dest, 0, len); } else { - tcg_gen_shr_tl(dest, src, tmp); - tcg_gen_extract_tl(dest, dest, 0, len); + tcg_gen_shr_reg(dest, src, tmp); + tcg_gen_extract_reg(dest, dest, 0, len); } tcg_temp_free(tmp); save_gpr(ctx, rt, dest); @@ -2783,7 +3020,7 @@ static DisasJumpType trans_extrw_imm(DisasContext *ct= x, uint32_t insn, unsigned rr =3D extract32(insn, 21, 5); unsigned len =3D 32 - clen; unsigned cpos =3D 31 - pos; - TCGv dest, src; + TCGv_reg dest, src; =20 if (c) { nullify_over(ctx); @@ -2792,9 +3029,9 @@ static DisasJumpType trans_extrw_imm(DisasContext *ct= x, uint32_t insn, dest =3D dest_gpr(ctx, rt); src =3D load_gpr(ctx, rr); if (is_se) { - tcg_gen_sextract_tl(dest, src, cpos, len); + tcg_gen_sextract_reg(dest, src, cpos, len); } else { - tcg_gen_extract_tl(dest, src, cpos, len); + tcg_gen_extract_reg(dest, src, cpos, len); } save_gpr(ctx, rt, dest); =20 @@ -2820,11 +3057,11 @@ static DisasJumpType trans_depw_imm_c(DisasContext = *ctx, uint32_t insn, unsigned cpos =3D extract32(insn, 5, 5); unsigned nz =3D extract32(insn, 10, 1); unsigned c =3D extract32(insn, 13, 3); - target_long val =3D low_sextract(insn, 16, 5); + target_sreg val =3D low_sextract(insn, 16, 5); unsigned rt =3D extract32(insn, 21, 5); unsigned len =3D 32 - clen; - target_long mask0, mask1; - TCGv dest; + target_sreg mask0, mask1; + TCGv_reg dest; =20 if (c) { nullify_over(ctx); @@ -2838,14 +3075,14 @@ static DisasJumpType trans_depw_imm_c(DisasContext = *ctx, uint32_t insn, mask1 =3D deposit64(-1, cpos, len, val); =20 if (nz) { - TCGv src =3D load_gpr(ctx, rt); + TCGv_reg src =3D load_gpr(ctx, rt); if (mask1 !=3D -1) { - tcg_gen_andi_tl(dest, src, mask1); + tcg_gen_andi_reg(dest, src, mask1); src =3D dest; } - tcg_gen_ori_tl(dest, src, mask0); + tcg_gen_ori_reg(dest, src, mask0); } else { - tcg_gen_movi_tl(dest, mask0); + tcg_gen_movi_reg(dest, mask0); } save_gpr(ctx, rt, dest); =20 @@ -2868,7 +3105,7 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx= , uint32_t insn, unsigned rt =3D extract32(insn, 21, 5); unsigned rs =3D nz ? rt : 0; unsigned len =3D 32 - clen; - TCGv dest, val; + TCGv_reg dest, val; =20 if (c) { nullify_over(ctx); @@ -2880,9 +3117,9 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx= , uint32_t insn, dest =3D dest_gpr(ctx, rt); val =3D load_gpr(ctx, rr); if (rs =3D=3D 0) { - tcg_gen_deposit_z_tl(dest, val, cpos, len); + tcg_gen_deposit_z_reg(dest, val, cpos, len); } else { - tcg_gen_deposit_tl(dest, cpu_gr[rs], val, cpos, len); + tcg_gen_deposit_reg(dest, cpu_gr[rs], val, cpos, len); } save_gpr(ctx, rt, dest); =20 @@ -2904,7 +3141,7 @@ static DisasJumpType trans_depw_sar(DisasContext *ctx= , uint32_t insn, unsigned rt =3D extract32(insn, 21, 5); unsigned rs =3D nz ? rt : 0; unsigned len =3D 32 - clen; - TCGv val, mask, tmp, shift, dest; + TCGv_reg val, mask, tmp, shift, dest; unsigned msb =3D 1U << (len - 1); =20 if (c) { @@ -2921,17 +3158,17 @@ static DisasJumpType trans_depw_sar(DisasContext *c= tx, uint32_t insn, tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_xori_tl(shift, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); =20 - mask =3D tcg_const_tl(msb + (msb - 1)); - tcg_gen_and_tl(tmp, val, mask); + mask =3D tcg_const_reg(msb + (msb - 1)); + tcg_gen_and_reg(tmp, val, mask); if (rs) { - tcg_gen_shl_tl(mask, mask, shift); - tcg_gen_shl_tl(tmp, tmp, shift); - tcg_gen_andc_tl(dest, cpu_gr[rs], mask); - tcg_gen_or_tl(dest, dest, tmp); + tcg_gen_shl_reg(mask, mask, shift); + tcg_gen_shl_reg(tmp, tmp, shift); + tcg_gen_andc_reg(dest, cpu_gr[rs], mask); + tcg_gen_or_reg(dest, dest, tmp); } else { - tcg_gen_shl_tl(dest, tmp, shift); + tcg_gen_shl_reg(dest, tmp, shift); } tcg_temp_free(shift); tcg_temp_free(mask); @@ -2956,7 +3193,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint= 32_t insn, bool is_l) { unsigned n =3D extract32(insn, 1, 1); unsigned b =3D extract32(insn, 21, 5); - target_long disp =3D assemble_17(insn); + target_sreg disp =3D assemble_17(insn); =20 /* unsigned s =3D low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -2971,8 +3208,8 @@ static DisasJumpType trans_be(DisasContext *ctx, uint= 32_t insn, bool is_l) if (b =3D=3D 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } else { - TCGv tmp =3D get_temp(ctx); - tcg_gen_addi_tl(tmp, load_gpr(ctx, b), disp); + TCGv_reg tmp =3D get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } } @@ -2982,7 +3219,7 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint= 32_t insn, { unsigned n =3D extract32(insn, 1, 1); unsigned link =3D extract32(insn, 21, 5); - target_long disp =3D assemble_17(insn); + target_sreg disp =3D assemble_17(insn); =20 return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } @@ -2991,7 +3228,7 @@ static DisasJumpType trans_bl_long(DisasContext *ctx,= uint32_t insn, const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); - target_long disp =3D assemble_22(insn); + target_sreg disp =3D assemble_22(insn); =20 return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n); } @@ -3002,10 +3239,10 @@ static DisasJumpType trans_blr(DisasContext *ctx, u= int32_t insn, unsigned n =3D extract32(insn, 1, 1); unsigned rx =3D extract32(insn, 16, 5); unsigned link =3D extract32(insn, 21, 5); - TCGv tmp =3D get_temp(ctx); + TCGv_reg tmp =3D get_temp(ctx); =20 - tcg_gen_shli_tl(tmp, load_gpr(ctx, rx), 3); - tcg_gen_addi_tl(tmp, tmp, ctx->iaoq_f + 8); + tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); + tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); return do_ibranch(ctx, tmp, link, n); } =20 @@ -3015,14 +3252,14 @@ static DisasJumpType trans_bv(DisasContext *ctx, ui= nt32_t insn, unsigned n =3D extract32(insn, 1, 1); unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; =20 if (rx =3D=3D 0) { dest =3D load_gpr(ctx, rb); } else { dest =3D get_temp(ctx); - tcg_gen_shli_tl(dest, load_gpr(ctx, rx), 3); - tcg_gen_add_tl(dest, dest, load_gpr(ctx, rb)); + tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); + tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } return do_ibranch(ctx, dest, 0, n); } @@ -3242,13 +3479,13 @@ static DisasJumpType trans_ftest_t(DisasContext *ct= x, uint32_t insn, { unsigned y =3D extract32(insn, 13, 3); unsigned cbit =3D (y ^ 1) - 1; - TCGv t; + TCGv_reg t; =20 nullify_over(ctx); =20 t =3D tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); - tcg_gen_extract_tl(t, t, 21 - cbit, 1); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_extract_reg(t, t, 21 - cbit, 1); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); tcg_temp_free(t); =20 @@ -3261,16 +3498,16 @@ static DisasJumpType trans_ftest_q(DisasContext *ct= x, uint32_t insn, unsigned c =3D extract32(insn, 0, 5); int mask; bool inv =3D false; - TCGv t; + TCGv_reg t; =20 nullify_over(ctx); =20 t =3D tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); =20 switch (c) { case 0: /* simple */ - tcg_gen_andi_tl(t, t, 0x4000000); + tcg_gen_andi_reg(t, t, 0x4000000); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ @@ -3298,11 +3535,11 @@ static DisasJumpType trans_ftest_q(DisasContext *ct= x, uint32_t insn, return gen_illegal(ctx); } if (inv) { - TCGv c =3D load_const(ctx, mask); - tcg_gen_or_tl(t, t, c); + TCGv_reg c =3D load_const(ctx, mask); + tcg_gen_or_reg(t, t, c); ctx->null_cond =3D cond_make(TCG_COND_EQ, t, c); } else { - tcg_gen_andi_tl(t, t, mask); + tcg_gen_andi_reg(t, t, mask); ctx->null_cond =3D cond_make_0(TCG_COND_EQ, t); } done: @@ -3805,7 +4042,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D get_temp(ctx); - tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; ctx->iaoq_n_var =3D NULL; @@ -3849,12 +4086,12 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) return; } if (ctx->iaoq_f =3D=3D -1) { - tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); nullify_save(ctx); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b =3D=3D -1) { - tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var); + tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); } } =20 @@ -3889,8 +4126,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) =20 static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - TranslationBlock *tb =3D dcbase->tb; - target_ulong pc =3D tb->pc; + target_ureg pc =3D dcbase->pc_first; =20 #ifdef CONFIG_USER_ONLY switch (pc) { @@ -3910,7 +4146,7 @@ static void hppa_tr_disas_log(const DisasContextBase = *dcbase, CPUState *cs) #endif =20 qemu_log("IN: %s\n", lookup_symbol(pc)); - log_target_disas(cs, pc, tb->size); + log_target_disas(cs, pc, dcbase->tb->size); } =20 static const TranslatorOps hppa_tr_ops =3D { --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 06/45] target/hppa: Implement mmu_idx from IA privilege level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 19 +++++++++++++---- target/hppa/cpu.c | 2 +- target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++---------------= ---- 3 files changed, 50 insertions(+), 26 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1524ef91b6..805c93db9c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,8 +36,10 @@ #define TARGET_PAGE_BITS 12 =20 #define ALIGNED_ONLY -#define NB_MMU_MODES 1 -#define MMU_USER_IDX 0 +#define NB_MMU_MODES 5 +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 /* Hardware exceptions, interupts, faults, and traps. */ @@ -195,7 +197,14 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *= env) =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { - return 0; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return env->iaoq_f & 3; + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif } =20 void hppa_translate_init(void); @@ -210,7 +219,9 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, { *pc =3D env->iaoq_f; *cs_base =3D env->iaoq_b; - *pflags =3D env->psw_n; + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + *pflags =3D (env->psw & (PSW_W | PSW_C | PSW_D)) + | env->psw_n * PSW_N; } =20 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f6d92de972..9962ab71ee 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -39,7 +39,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) =20 cpu->env.iaoq_f =3D tb->pc; cpu->env.iaoq_b =3D tb->cs_base; - cpu->env.psw_n =3D tb->flags & 1; + cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dd96147bf1..33605a2d15 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -282,6 +282,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + int mmu_idx; + int privilege; bool psw_n_nonzero; } DisasContext; =20 @@ -1299,10 +1301,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 = dest, unsigned rb, } =20 if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i32(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1329,10 +1331,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 = dest, unsigned rb, } =20 if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i64(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1358,7 +1360,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } =20 - tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); + tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); =20 if (modify !=3D 0) { save_gpr(ctx, rb, addr); @@ -1386,7 +1388,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } =20 - tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); + tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); =20 if (modify !=3D 0) { save_gpr(ctx, rb, addr); @@ -2497,7 +2499,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, ui= nt32_t insn, =20 zero =3D tcg_const_reg(0); tcg_gen_atomic_xchg_reg(dest, (modify <=3D 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero, ctx->mmu_idx, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -3971,30 +3973,43 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs, int max_insns) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - TranslationBlock *tb =3D ctx->base.tb; int bound; =20 ctx->cs =3D cs; - ctx->iaoq_f =3D tb->pc; - ctx->iaoq_b =3D tb->cs_base; + +#ifdef CONFIG_USER_ONLY + ctx->privilege =3D MMU_USER_IDX; + ctx->mmu_idx =3D MMU_USER_IDX; +#else + ctx->privilege =3D ctx->base.pc_first & 3; + ctx->mmu_idx =3D (ctx->base.tb->flags & PSW_D + ? ctx->privilege : MMU_PHYS_IDX); +#endif + ctx->iaoq_f =3D ctx->base.pc_first; + ctx->iaoq_b =3D ctx->base.tb->cs_base; + ctx->base.pc_first &=3D -4; + ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 + /* Bound the number of instructions by those left on the page. */ + bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + bound =3D MIN(max_insns, bound); + ctx->ntemps =3D 0; memset(ctx->temps, 0, sizeof(ctx->temps)); =20 - bound =3D -(tb->pc | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + return bound; } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. = */ + /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. = */ ctx->null_cond =3D cond_make_f(); ctx->psw_n_nonzero =3D false; - if (ctx->base.tb->flags & 1) { + if (ctx->base.tb->flags & PSW_N) { ctx->null_cond.c =3D TCG_COND_ALWAYS; ctx->psw_n_nonzero =3D true; } @@ -4014,7 +4029,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cs, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next =3D ctx->iaoq_f + 4; + ctx->base.pc_next =3D (ctx->iaoq_f & -4) + 4; return true; } =20 @@ -4035,7 +4050,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f); + uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f & -4); =20 /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4064,10 +4079,8 @@ static void hppa_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) } ctx->ntemps =3D 0; =20 - /* Advance the insn queue. */ - /* ??? The non-linear instruction restriction is purely due to - the debugging dump. Otherwise we *could* follow unconditional - branches within the same page. */ + /* Advance the insn queue. Note that this check also detects + a priority change within the instruction queue. */ if (ret =3D=3D DISAS_NEXT && ctx->iaoq_b !=3D ctx->iaoq_f + 4) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER || ctx->null_cond.c =3D=3D TCG_COND_ALWAYS) { @@ -4121,7 +4134,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) =20 /* We don't actually use this during normal translation, but we should interact with the generic main loop. */ - ctx->base.pc_next =3D ctx->base.tb->pc + 4 * ctx->base.num_insns; + ctx->base.pc_next =3D ctx->base.pc_first + 4 * ctx->base.num_insns; } =20 static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151683726302263.78599710067283; Wed, 24 Jan 2018 15:41:03 -0800 (PST) Received: from localhost ([::1]:54540 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUf8-0007E2-95 for importer@patchew.org; Wed, 24 Jan 2018 18:41:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURJ-0004SU-CD for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURE-0001dQ-Gj for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:45 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33730) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURE-0001d8-7x for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:40 -0500 Received: by mail-pf0-x243.google.com with SMTP id t5so4371297pfi.0 for ; Wed, 24 Jan 2018 15:26:40 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=+6dDGlU5G4pqOu3+fCXuYTnali05S0or37iI2x6SAAg=; b=ATR8z3xjwWJG4XyJQGgN0opnsiYQ62tH0HJzAdIvZ3PxtBkxVxQ5pM5EDvpAjk2EaV fkwr5ca4JzWp8Kva3EF/1Ly3jKBeq8rBhovlEVNqhvvM+83+nxBenP+PuOgl9b5lh6mY zQ8NA1Nu4J891OVvV/hEgodsbqS9g9MnN5zy0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=+6dDGlU5G4pqOu3+fCXuYTnali05S0or37iI2x6SAAg=; b=D7z3GvcXNvsZn/agSdrgHdjtTLlrfFYcwxiwTQ81uNOYSNA2ZUxv0R18F4tngPpEn1 LbJva95YloSYwpHPMD5vfyl0C84Qxt4BJT7eRi28Str0Ic4XiYr4wdPsoZRRVsYwSb+Z eSuybJwT8uyzH1AaCcJwo5kSBQHmUKa/c0Znd/6H/gblOPMHOTqUfX6jpuwmEt3lJn8t Y3O029g0A35/IbnaQbXCZnI8nBgu2yzrZ1iSebfLU6693yMcToY1POah0SLglc5dSXxT 0+iO72XOusQ929eaLBOb/HJ5oRs3SAFcWNx9J9THxMjKTXHXfGV3k5Bpr5ZgQpVRtgoK VD9Q== X-Gm-Message-State: AKwxyteBAdFY2n3EGTxbDb1WI/Ohw2WrnbRZLBYJig9hTahF5v2EHoIB nlvLM0q6nCneHuljOrCYGKPnrKUqtjI= X-Google-Smtp-Source: AH8x224ud4C6O0bw1MJMmwifD/SntB/U74DZ4PJLsG4qh0+gkxfnnVi7T5/AkcXuKS74LUS2ANTCeg== X-Received: by 10.99.66.68 with SMTP id p65mr11418734pga.384.1516836398879; Wed, 24 Jan 2018 15:26:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:47 -0800 Message-Id: <20180124232625.30105-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 07/45] target/hppa: Implement the system mask instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 4 +++ target/hppa/op_helper.c | 14 ++++++++ target/hppa/translate.c | 96 +++++++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 113 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c720de523b..254a4da133 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -76,3 +76,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_s, TCG_CALL_NO_RWG, i32, env,= i32, i32, i32) DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +#endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 479bfc0fdf..1c3e043cc0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -601,3 +601,17 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64= a, float64 b, float64 c) update_fr0_op(env, GETPC()); return ret; } + +#ifndef CONFIG_USER_ONLY +target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +{ + target_ulong psw =3D env->psw; + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (nsm & ~psw & PSW_Q) { + dynexcp(env, EXCP_ILL, GETPC()); + } + env->psw =3D (psw & ~PSW_SM) | (nsm & PSW_SM); + return psw & PSW_SM; +} +#endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 33605a2d15..088031e7f3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -299,6 +299,10 @@ typedef struct DisasContext { updated the iaq for the next instruction to be executed. */ #define DISAS_IAQ_N_STALE DISAS_TARGET_1 =20 +/* Similarly, but we want to return to the main loop immediately + to recognize unmasked interrupts. */ +#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 + typedef struct DisasInsn { uint32_t insn, mask; DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, @@ -697,6 +701,14 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } =20 +#define CHECK_MOST_PRIVILEGED(EXCP) \ + do { \ + if (ctx->privilege !=3D 0) { \ + nullify_over(ctx); \ + return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + } \ + } while (0) + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ @@ -1982,6 +1994,79 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, = uint32_t insn, return DISAS_NEXT; } =20 +#ifndef CONFIG_USER_ONLY +/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ +static target_ureg extract_sm_imm(uint32_t insn) +{ + target_ureg val =3D extract32(insn, 16, 10); + + if (val & PSW_SM_E) { + val =3D (val & ~PSW_SM_E) | PSW_E; + } + if (val & PSW_SM_W) { + val =3D (val & ~PSW_SM_W) | PSW_W; + } + return val; +} + +static DisasJumpType trans_rsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt =3D extract32(insn, 0, 5); + target_ureg sm =3D extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp =3D get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_reg(tmp, tmp, ~sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_ssm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt =3D extract32(insn, 0, 5); + target_ureg sm =3D extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp =3D get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_reg(tmp, tmp, sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr =3D extract32(insn, 16, 5); + TCGv_reg tmp, reg; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + reg =3D load_gpr(ctx, rr); + tmp =3D get_temp(ctx); + gen_helper_swap_system_mask(tmp, cpu_env, reg); + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_system[] =3D { { 0x00000000u, 0xfc001fe0u, trans_break }, /* We don't implement space register, so MTSP is a nop. */ @@ -1993,6 +2078,11 @@ static const DisasInsn table_system[] =3D { { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, +#ifndef CONFIG_USER_ONLY + { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, + { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, + { 0x00001860u, 0xffe0ffffu, trans_mtsm }, +#endif }; =20 static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, @@ -4111,12 +4201,14 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp =3D ctx->base.is_jmp; =20 - switch (ctx->base.is_jmp) { + switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); @@ -4124,6 +4216,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); + } else if (is_jmp =3D=3D DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); } --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837432659515.4859466531904; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Zc2caYK/EPpTetfoJcguGXYP9cMfmLKiBoS/RjrLVto=; b=agjvr/N3UR4UM2ZE3tU2UDIbCGsCnY5wtmMHu9OlD+i0t8F7O8vg9Gm98gcZEuBR43 dphS8s/u2FCnpVVF6YIOg0OSxY6HsLZrQf76GaN3ZPRZcmloHLVLhvP3+MAgpSk7sOSP zJL8wGYejYGga08/DzzVJR34CiYk3kjRGP4XQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Zc2caYK/EPpTetfoJcguGXYP9cMfmLKiBoS/RjrLVto=; b=RW4/JC/yBycIjHg7uDUE+byiHE8Z101Bj+CP8MxbMOtZS7mmV/ONGhjdJ2hxm0gKj8 hbBeW/cW99ZGIjNRbEykdRH1Sgaf6b2AnEHpngJK5mkarn5DfOVTGZhAwm/gv3c5LxoS UuYYFvcUavmI4/XPbUy1wUO5HNZLJYQ4u3ZVFDs2vY+G71v63Qx1ZwP7QPsHmrT/tTSl sWHUXT7hIjPTj3PP02XN30bdtq2P8a7JxdWbSYATzbiOieFIcnCluZlLHaWgpt/GZqZx brt0tVG7H+EjrRnoPrIRPKgCMARCpi8kRT599UcDATg0K/ujN1gpMLLA30R5qBeWZ9Z2 +s8g== X-Gm-Message-State: AKwxyteEZs/6DcZDY/XZjvhPzb7KAxxYdY0cnwa1zVzPIOuDYFS2pea+ yW4EFC9U3xAJS/VNbdaJzN+QlbBcHBc= X-Google-Smtp-Source: AH8x225tItoasVjwQCxZH+XdD/nFGbZr6oNyczLVQLnit4K+6bIYJW3s0Btcj8tJrNFmeHuscrDs/Q== X-Received: by 10.99.110.3 with SMTP id j3mr11943283pgc.85.1516836400242; Wed, 24 Jan 2018 15:26:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:48 -0800 Message-Id: <20180124232625.30105-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 08/45] target/hppa: Add space registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.c | 14 ++++++---- target/hppa/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++= ---- 3 files changed, 77 insertions(+), 11 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 805c93db9c..24c728c0d2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -140,6 +140,7 @@ typedef int64_t target_sreg; struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; + uint64_t sr[8]; /* stored shifted into place for gva */ =20 target_ureg sar; target_ureg cr26; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b6521f61fc..48ac80cb2d 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -168,12 +168,16 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw, psw_cb, psw_c); =20 for (i =3D 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); - if ((i % 4) =3D=3D 3) { - cpu_fprintf(f, "\n"); - } + cpu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + (i & 3) =3D=3D 3 ? '\n' : ' '); + } +#ifndef CONFIG_USER_ONLY + for (i =3D 0; i < 8; i++) { + cpu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), + (i & 3) =3D=3D 3 ? '\n' : ' '); } - cpu_fprintf(f, "\n"); +#endif + cpu_fprintf(f, "\n"); =20 /* ??? FR */ } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 088031e7f3..50d41b0c63 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -320,6 +320,7 @@ typedef struct DisasInsn { =20 /* global register indexes */ static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_reg cpu_sar; @@ -358,6 +359,10 @@ void hppa_translate_init(void) "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; + /* SR[4-7] are not global registers so that we can index them. */ + static const char sr_names[4][4] =3D { + "sr0", "sr1", "sr2", "sr3" + }; =20 int i; =20 @@ -367,6 +372,11 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, gr[i]), gr_names[i]); } + for (i =3D 0; i < 4; i++) { + cpu_sr[i] =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[i]), + sr_names[i]); + } =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; @@ -571,6 +581,19 @@ static void save_frd(unsigned rt, TCGv_i64 val) tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); } =20 +static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) +{ +#ifdef CONFIG_USER_ONLY + tcg_gen_movi_i64(dest, 0); +#else + if (reg < 4) { + tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else { + tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); + } +#endif +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -785,6 +808,13 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } =20 +static unsigned assemble_sr3(uint32_t insn) +{ + unsigned s2 =3D extract32(insn, 13, 1); + unsigned s0 =3D extract32(insn, 14, 2); + return s2 * 4 + s0; +} + static target_sreg assemble_12(uint32_t insn) { target_ureg x =3D -(target_ureg)(insn & 1); @@ -1894,11 +1924,17 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, = uint32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tmp =3D dest_gpr(ctx, rt); + unsigned rs =3D assemble_sr3(insn); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_reg t1 =3D tcg_temp_new(); =20 - /* ??? We don't implement space registers. */ - tcg_gen_movi_reg(tmp, 0); - save_gpr(ctx, rt, tmp); + load_spr(ctx, t0, rs); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(t1, t0); + + save_gpr(ctx, rt, t1); + tcg_temp_free(t1); + tcg_temp_free_i64(t0); =20 cond_free(&ctx->null_cond); return DISAS_NEXT; @@ -1944,6 +1980,32 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, = uint32_t insn, return DISAS_NEXT; } =20 +static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr =3D extract32(insn, 16, 5); + unsigned rs =3D assemble_sr3(insn); + TCGv_i64 t64; + + if (rs >=3D 5) { + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + } + nullify_over(ctx); + + t64 =3D tcg_temp_new_i64(); + tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); + tcg_gen_shli_i64(t64, t64, 32); + + if (rs >=3D 4) { + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + } else { + tcg_gen_mov_i64(cpu_sr[rs], t64); + } + tcg_temp_free_i64(t64); + + return nullify_end(ctx, DISAS_NEXT); +} + static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -2069,8 +2131,7 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, ui= nt32_t insn, =20 static const DisasInsn table_system[] =3D { { 0x00000000u, 0xfc001fe0u, trans_break }, - /* We don't implement space register, so MTSP is a nop. */ - { 0x00001820u, 0xffe01fffu, trans_nop }, + { 0x00001820u, 0xffe01fffu, trans_mtsp }, { 0x00001840u, 0xfc00ffffu, trans_mtctl }, { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837598214936.8571208789475; Wed, 24 Jan 2018 15:46:38 -0800 (PST) Received: from localhost ([::1]:54577 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUkX-0003gI-Du for importer@patchew.org; Wed, 24 Jan 2018 18:46:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURJ-0004SS-C2 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURH-0001eC-AO for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:45 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:43925) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURH-0001dt-2e for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:43 -0500 Received: by mail-pg0-x242.google.com with SMTP id n17so3805629pgf.10 for ; Wed, 24 Jan 2018 15:26:42 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=zEJIyNNEFcvSLly3Po8WRqqswnEmq+LgGLaXt/hERiA=; b=iVxK7pVSXFNluLdzIx2kOvxh7zDz6B8mF3Af+IB0Zmd2YYd1Oy28Jic45yV0oPe7YM tckOI/k0inGEbBCXjdH0aV4SzhErMo9Pf/CqSRHy+LlAywSxhDl1nR7zj7S/Lg293nMO jlb6msViJHMJsnX/3D37QEmatQrAewoo8Yhkw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=zEJIyNNEFcvSLly3Po8WRqqswnEmq+LgGLaXt/hERiA=; b=DpOOB2LJhE9G+oPX6lzTWw37mNzRl/vdbG8bfa/KCMnPUYBgpneBtC72R0TgUQpF4Z 9yQ7b+ORfFdU2rpTJv4oEjAgbOi5ipPNE3FV8P805EO1uOj7rIMDfBGbbXSOQ67IASbV fOXAL3NN0KZXwzo0ZaGaUG4a1INgM/QsMI/aIOg7tHI28SkGRYXbVBbhxjrFNg4Nesp5 WCdqYyP0xttwZut7Rz3mQrBa5eqjo77I9xW5f0UjqQDY47Xj8b41mcskcZV5EJJ7P4o3 UiXorjqEHBiuaMig6AxbyVyE8DZ6MZCRJeQ4kWCpoNlR+OFTeB2Bp0YIwafr4bA7Wh36 pfKA== X-Gm-Message-State: AKwxytf2JLzRfNDPwZ7K4lkQGfVMajcUwzxwR6TPPltD/L7hX13Yuj2E 2hbCaNSaUK+N8NabkOO0caO08nzul+c= X-Google-Smtp-Source: AH8x226NTh/n85uCQWptaGFfgVYnurHuI0blGutgwACEwJ7Rbe9nKZUeT7Cfjduyu+HL5ofZzhqzAg== X-Received: by 10.99.127.24 with SMTP id a24mr11757899pgd.225.1516836401687; Wed, 24 Jan 2018 15:26:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:49 -0800 Message-Id: <20180124232625.30105-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 09/45] target/hppa: Add control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/hppa/target_cpu.h | 2 +- target/hppa/cpu.h | 23 +++++++++++---- linux-user/main.c | 4 +-- linux-user/signal.c | 4 +-- target/hppa/gdbstub.c | 12 ++++---- target/hppa/mem_helper.c | 2 +- target/hppa/translate.c | 70 ++++++++++++++++++++++++++++++----------= ---- 7 files changed, 77 insertions(+), 40 deletions(-) diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index e50522eae9..7b78bbea80 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -33,7 +33,7 @@ static inline void cpu_clone_regs(CPUHPPAState *env, targ= et_ulong newsp) =20 static inline void cpu_set_tls(CPUHPPAState *env, target_ulong newtls) { - env->cr27 =3D newtls; + env->cr[27] =3D newtls; } =20 #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 24c728c0d2..c92c564a7f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -123,6 +123,20 @@ #define PSW_SM_W 0 #endif =20 +#define CR_RC 0 +#define CR_SCRCCR 10 +#define CR_SAR 11 +#define CR_IVA 14 +#define CR_EIEM 15 +#define CR_IT 16 +#define CR_IIASQ 17 +#define CR_IIAOQ 18 +#define CR_IIR 19 +#define CR_ISR 20 +#define CR_IOR 21 +#define CR_IPSW 22 +#define CR_EIRR 23 + typedef struct CPUHPPAState CPUHPPAState; =20 #if TARGET_REGISTER_BITS =3D=3D 32 @@ -142,10 +156,6 @@ struct CPUHPPAState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ =20 - target_ureg sar; - target_ureg cr26; - target_ureg cr27; - target_ureg psw; /* All psw bits except the following: */ target_ureg psw_n; /* boolean */ target_sreg psw_v; /* in most significant bit */ @@ -163,11 +173,12 @@ struct CPUHPPAState { target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ =20 - target_ureg ior; /* interrupt offset register */ - uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; =20 + target_ureg cr[32]; /* control registers */ + target_ureg cr_back[2]; /* back of cr17/cr18 */ + /* Those resources are used only in QEMU core */ CPU_COMMON }; diff --git a/linux-user/main.c b/linux-user/main.c index 42f4c66ce6..90ae447368 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3781,14 +3781,14 @@ void cpu_loop(CPUHPPAState *env) info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->ior; + info._sifields._sigfault._addr =3D env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->ior; + info._sifields._sigfault._addr =3D env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_ILL: diff --git a/linux-user/signal.c b/linux-user/signal.c index f85f0dd780..40d5d849f0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -6440,7 +6440,7 @@ static void setup_sigcontext(struct target_sigcontext= *sc, CPUArchState *env) __put_user(env->fr[i], &sc->sc_fr[i]); } =20 - __put_user(env->sar, &sc->sc_sar); + __put_user(env->cr[CR_SAR], &sc->sc_sar); } =20 static void restore_sigcontext(CPUArchState *env, struct target_sigcontext= *sc) @@ -6461,7 +6461,7 @@ static void restore_sigcontext(CPUArchState *env, str= uct target_sigcontext *sc) =20 __get_user(env->iaoq_f, &sc->sc_iaoq[0]); __get_user(env->iaoq_b, &sc->sc_iaoq[1]); - __get_user(env->sar, &sc->sc_sar); + __get_user(env->cr[CR_SAR], &sc->sc_sar); } =20 /* No, this doesn't look right, but it's copied straight from the kernel. = */ diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 228d282fe9..fc27aec073 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -36,7 +36,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem= _buf, int n) val =3D env->gr[n]; break; case 32: - val =3D env->sar; + val =3D env->cr[CR_SAR]; break; case 33: val =3D env->iaoq_f; @@ -45,10 +45,10 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *m= em_buf, int n) val =3D env->iaoq_b; break; case 59: - val =3D env->cr26; + val =3D env->cr[26]; break; case 60: - val =3D env->cr27; + val =3D env->cr[27]; break; case 64 ... 127: val =3D extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); @@ -89,7 +89,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->gr[n] =3D val; break; case 32: - env->sar =3D val; + env->cr[CR_SAR] =3D val; break; case 33: env->iaoq_f =3D val; @@ -98,10 +98,10 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) env->iaoq_b =3D val; break; case 59: - env->cr26 =3D val; + env->cr[26] =3D val; break; case 60: - env->cr27 =3D val; + env->cr[27] =3D val; break; case 64: env->fr[0] =3D deposit64(env->fr[0], 32, 32, val); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2901f3e29c..1afaf89539 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -32,7 +32,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* ??? Test between data page fault and data memory protection trap, which would affect si_code. */ cs->exception_index =3D EXCP_DMP; - cpu->env.ior =3D address; + cpu->env.cr[CR_IOR] =3D address; return 1; } #else diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 50d41b0c63..89b336c2c4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -328,8 +328,6 @@ static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; static TCGv_reg cpu_psw_cb; static TCGv_reg cpu_psw_cb_msb; -static TCGv_reg cpu_cr26; -static TCGv_reg cpu_cr27; =20 #include "exec/gen-icount.h" =20 @@ -339,9 +337,7 @@ void hppa_translate_init(void) =20 typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] =3D { - DEF_VAR(sar), - DEF_VAR(cr26), - DEF_VAR(cr27), + { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, DEF_VAR(psw_n), DEF_VAR(psw_v), DEF_VAR(psw_cb), @@ -1867,7 +1863,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])= ); tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; @@ -1948,34 +1944,39 @@ static DisasJumpType trans_mfctl(DisasContext *ctx,= uint32_t insn, TCGv_reg tmp; =20 switch (ctl) { - case 11: /* SAR */ + case CR_SAR: #ifdef TARGET_HPPA64 if (extract32(insn, 14, 1) =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); - break; + goto done; } #endif save_gpr(ctx, rt, cpu_sar); - break; - case 16: /* Interval Timer */ + goto done; + case CR_IT: /* Interval Timer */ + /* FIXME: Respect PSW_S bit. */ + nullify_over(ctx); tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, 0); /* FIXME */ + tcg_gen_movi_reg(tmp, 0); /* FIXME */ save_gpr(ctx, rt, tmp); break; case 26: - save_gpr(ctx, rt, cpu_cr26); - break; case 27: - save_gpr(ctx, rt, cpu_cr27); break; default: /* All other control registers are privileged. */ - return gen_illegal(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + break; } =20 + tmp =3D get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + save_gpr(ctx, rt, tmp); + + done: cond_free(&ctx->null_cond); return DISAS_NEXT; } @@ -2011,20 +2012,45 @@ static DisasJumpType trans_mtctl(DisasContext *ctx,= uint32_t insn, { unsigned rin =3D extract32(insn, 16, 5); unsigned ctl =3D extract32(insn, 21, 5); + TCGv_reg reg =3D load_gpr(ctx, rin); TCGv_reg tmp; =20 - if (ctl =3D=3D 11) { /* SAR */ + if (ctl =3D=3D CR_SAR) { tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1= ); + tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); - } else { - /* All other control registers are privileged or read-only. */ - return gen_illegal(ctx); + + cond_free(&ctx->null_cond); + return DISAS_NEXT; } =20 - cond_free(&ctx->null_cond); - return DISAS_NEXT; + /* All other control registers are privileged or read-only. */ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + + nullify_over(ctx); + switch (ctl) { + case CR_IT: + /* ??? modify interval timer offset */ + break; + + case CR_IIASQ: + case CR_IIAOQ: + /* FIXME: Respect PSW_Q bit */ + /* The write advances the queue and stores to the back element. */ + tmp =3D get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + break; + + default: + tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + break; + } + return nullify_end(ctx, DISAS_NEXT); } =20 static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836914449356.80804946612454; Wed, 24 Jan 2018 15:35:14 -0800 (PST) Received: from localhost ([::1]:54497 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUZV-0002M1-KG for importer@patchew.org; Wed, 24 Jan 2018 18:35:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURJ-0004SV-Cf for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURI-0001eS-Go for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:45 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:39455) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURI-0001eJ-Aw for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:44 -0500 Received: by mail-pf0-x241.google.com with SMTP id e11so4363624pff.6 for ; Wed, 24 Jan 2018 15:26:44 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=4cqttb91gExKzUzwYTJJ0VdaDdFF9NoJxDPY3zpOHAU=; b=brH+ZW3KgjpkLfSyZV9/OwYXslUi3ei9J67bZmFcf/DtWwPPxRcfbP7BnjcDaU7uqe BsQTKEEbbmRve8Kn3rfcJ0/aRcquzUJtT4WKppa10/NBaukcvxOe0GT/3Z/kz3fLg5ps aHk+X1avtV4Kwblr3GQOHtcUpglMiBsHnuiXw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4cqttb91gExKzUzwYTJJ0VdaDdFF9NoJxDPY3zpOHAU=; b=M3pYiT744y2V51zfzsdtv649AqP1YO1C82mr0CH64fY8UaZGBOTPfl6Jw61AiccB6s r3j5YdaV+1+pyvH2MCXBrEahjzFaBsb97URI4p8Vwy32nsm07MlPlAeUj/6R0992d+gR xROL5hoLf7r907N1C1t7p/I1PYRBI1FfoaKAsdEvHyEhXWWyV4Cy5EZttXt/GzPP/GeZ MeTk1SWfxQ+4vT6Xco6cypJ+DnCRQ9raAG48IzH7OTvB7bTi9FEPEC9PrI5QRxROzQpc 2thzex1UjceCg3+yXBlS/EO1hh539CUBgRxdwJzcpewrTzGfaeHSxnsDzqfxLiYJLgTd Lz2Q== X-Gm-Message-State: AKwxytdxVJu1A4paHfBbkpierZjqCx8RvETxjkkeu2okNBUmgaojz6GF s8/1tfzrRkW8wCNHuIinPMcZixH/vBA= X-Google-Smtp-Source: AH8x224t5AAt7MJ2XJqnWMRwllhq9xM2rN7reXXjneYfNC0LjWVsH1rdUc+Kmqf5dqk/d1ADofTzsA== X-Received: by 10.99.127.90 with SMTP id p26mr11583846pgn.343.1516836403172; Wed, 24 Jan 2018 15:26:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:50 -0800 Message-Id: <20180124232625.30105-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 10/45] target/hppa: Adjust insn mask for mfctl, w X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 89b336c2c4..8ca58f3df3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2162,7 +2162,7 @@ static const DisasInsn table_system[] =3D { { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, - { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, + { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151683653808758.58848746501383; Wed, 24 Jan 2018 15:28:58 -0800 (PST) Received: from localhost ([::1]:54459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUTR-0005wa-99 for importer@patchew.org; Wed, 24 Jan 2018 18:28:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURL-0004UN-5T for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURK-0001fA-0D for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:47 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:38591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURJ-0001eg-RS for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:45 -0500 Received: by mail-pg0-x243.google.com with SMTP id y27so3814880pgc.5 for ; Wed, 24 Jan 2018 15:26:45 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=PebevTPJ54h7rXLum6cMnnkXuvReOv6VdVnhmLEjzeE=; b=cTmXzzGxhDwnRjllr8bHXvffJxhvp2LgGpP6+hMkA6MoQfz+vrDdas16mCzLY8aGh0 Ft0SZRxOKGJb9p6DCGvhvqJ1n7BSBWkiB0Fp5Mh6jy/rcrApAog103BIgc7j+7j1NhjR kRLf/WRSDIfy6I89cdzEeYLY2pHX1mKLF04TA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PebevTPJ54h7rXLum6cMnnkXuvReOv6VdVnhmLEjzeE=; b=BTUVn1ivMcfOJAyvBSHBsbmh8AFy0P68juMHvC5Jk1mw7xCfy+blY4XMPvnmOeaIEP LbscVl1X/SUFQkt/uGJjMfAx/oxzebtbdGEZPuXGTv9UFwml6qkNqxUJ6qrcaKTMhzzG TgSUImb70ee+bn+8dHYa+G1ug8LShGcQ/aLdKVOZXmj0bh/bnkG4BtHWR0u6KkPuiu1V ritgYUyJh+TpkId61pPR4HvqcL2n7LXDJyu+E47Cl+p7T8pc8Ch5Y0XPS5yab+AkAGRo uyF8CumFvwGzd2SB5ts2cg8DBcQ+dEAnWvIvOIPPHyUs6v+/tXDmcLlUJFGB0zfzTLun 4Ndg== X-Gm-Message-State: AKwxytc0OiHYo6naTq9syOxb3aY/CA5oBom812JBVCcqX2i0Mkm6/noq bfYR3PvyA2ykvatd7Cz32pdW3Gpw4A0= X-Google-Smtp-Source: AH8x225ccw7VTp+anE18l6/QoZCHK6x9LkdDTcfMs5wI/OYW+1Bw7VqiSRMkBZ6TK5v/SO8iDi7n4g== X-Received: by 10.99.159.2 with SMTP id g2mr7212388pge.156.1516836404629; Wed, 24 Jan 2018 15:26:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:51 -0800 Message-Id: <20180124232625.30105-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 11/45] target/hppa: Implement rfi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 24 ++++++++++++++++++++++++ target/hppa/translate.c | 30 ++++++++++++++++++++++++++++-- 4 files changed, 55 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c92c564a7f..6ec3430ae3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -178,6 +178,7 @@ struct CPUHPPAState { =20 target_ureg cr[32]; /* control registers */ target_ureg cr_back[2]; /* back of cr17/cr18 */ + target_ureg shadow[7]; /* shadow registers */ =20 /* Those resources are used only in QEMU core */ CPU_COMMON diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 254a4da133..79d22ae486 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -78,5 +78,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env,= i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1c3e043cc0..3f5dcbbca0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -614,4 +614,28 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env= , target_ureg nsm) env->psw =3D (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; } + +void HELPER(rfi)(CPUHPPAState *env) +{ + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (env->psw & (PSW_I | PSW_R | PSW_Q)) { + helper_excp(env, EXCP_ILL); + } + env->iaoq_f =3D env->cr[CR_IIAOQ]; + env->iaoq_b =3D env->cr_back[1]; + cpu_hppa_put_psw(env, env->cr[CR_IPSW]); +} + +void HELPER(rfi_r)(CPUHPPAState *env) +{ + env->gr[1] =3D env->shadow[0]; + env->gr[8] =3D env->shadow[1]; + env->gr[9] =3D env->shadow[2]; + env->gr[16] =3D env->shadow[3]; + env->gr[17] =3D env->shadow[4]; + env->gr[24] =3D env->shadow[5]; + env->gr[25] =3D env->shadow[6]; + helper_rfi(env); +} #endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8ca58f3df3..df0bb04907 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -655,6 +655,10 @@ static DisasJumpType nullify_end(DisasContext *ctx, Di= sasJumpType status) { TCGLabel *null_lab =3D ctx->null_lab; =20 + /* For NEXT, NORETURN, STALE, we can easily continue (or exit). + For UPDATED, we cannot update on the nullified path. */ + assert(status !=3D DISAS_IAQ_N_UPDATED); + if (likely(null_lab =3D=3D NULL)) { /* The current insn wasn't conditional or handled the condition applied to it without a branch, so the (new) setting of @@ -676,8 +680,6 @@ static DisasJumpType nullify_end(DisasContext *ctx, Dis= asJumpType status) gen_set_label(null_lab); ctx->null_cond =3D cond_make_n(); } - - assert(status !=3D DISAS_NORETURN && status !=3D DISAS_IAQ_N_UPDATED); if (status =3D=3D DISAS_NORETURN) { status =3D DISAS_NEXT; } @@ -2153,6 +2155,29 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, u= int32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); } + +static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned comp =3D extract32(insn, 5, 4); + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + if (comp =3D=3D 5) { + gen_helper_rfi_r(cpu_env); + } else { + gen_helper_rfi(cpu_env); + } + if (ctx->base.singlestep_enabled) { + gen_excp_1(EXCP_DEBUG); + } else { + tcg_gen_exit_tb(0); + } + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_system[] =3D { @@ -2169,6 +2194,7 @@ static const DisasInsn table_system[] =3D { { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, { 0x00001860u, 0xffe0ffffu, trans_mtsm }, + { 0x00000c00u, 0xfffffe1fu, trans_rfi }, #endif }; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15168371002991006.6169860394803; Wed, 24 Jan 2018 15:38:20 -0800 (PST) Received: from localhost ([::1]:54520 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUcT-0004oj-QL for importer@patchew.org; Wed, 24 Jan 2018 18:38:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURN-0004X1-SL for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURL-0001g3-R0 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:49 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:38597) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURL-0001fl-Ir for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:47 -0500 Received: by mail-pf0-x244.google.com with SMTP id k19so4359966pfj.5 for ; Wed, 24 Jan 2018 15:26:47 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=ehRh7IpYE9aUdFX+lvwLZUNe4Qev1gs40Bf4m1i72VM=; b=B69WmBR9/SXfZHNQegMn+pkTxGReQJO1KwzPyaxv/AjCmiRmWu2SDEEa99nZPTzaGi gucK1rJFJKzLwEUDhJGn6OZrAMTz2HWyDGG8futEuLRWoVz9Xyw/XYRyirvq1MHrH5zC itti4HbjWT5XUQTiciJq/zkNNPcRjNEz/8FSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=ehRh7IpYE9aUdFX+lvwLZUNe4Qev1gs40Bf4m1i72VM=; b=hisO2tlC8vCHli4mDw3sgs9VLS0GKNW182jfmmzUj+gV7VPzDkMVE3PH/swA3bDUAk G0IcyL/yEDxUyrGV9WZRdPInuWz8VaGABksjGDEYfVkRDO//ZNchSRrnLPlQq6qyLEty Yb1BqNi2XIch0qux9c9hjSPyTWe4GrBaoDUsCSSKy9ZQnrVIOHRNkaRcClwzQssidt8u pmAkj2FJEuyFEFBUVMMWVCnq0FMXR1IWSawumNHoNjJfOiiy5rmDbNU0fAW/6AzMRxZw bvRDbXT8YtnU5NmIM9XBgicbgle6y4rzdO1xtNIMi94dnLZ8ZqvnF0f6IqAoTjXaj5YX gjMg== X-Gm-Message-State: AKwxytdAL28mRZ3ps5Wt0boDBlMtTvQk8IGjKTzdYZNOI4xJnWbxhRdD zYwqKj4unGl9d78PSvdfUX+nGPMk95s= X-Google-Smtp-Source: AH8x226sVp9WElDDGd8+wqYTb7n+Uq0Uk5p8SEaFQ0V6eKEI9DL/HdlLWmvafw9D2f617R39jGCo+A== X-Received: by 10.99.172.25 with SMTP id v25mr11809411pge.148.1516836406147; Wed, 24 Jan 2018 15:26:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:52 -0800 Message-Id: <20180124232625.30105-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 12/45] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 2 + target/hppa/helper.c | 63 ----------------- target/hppa/int_helper.c | 176 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/translate.c | 16 ++++- target/hppa/Makefile.objs | 1 + 5 files changed, 192 insertions(+), 66 deletions(-) create mode 100644 target/hppa/int_helper.c diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9962ab71ee..ca619578dd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,8 +106,10 @@ static void hppa_cpu_initfn(Object *obj) CPUHPPAState *env =3D &cpu->env; =20 cs->env_ptr =3D env; + cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); set_snan_bit_is_one(true, &env->fp_status); + cpu_hppa_put_psw(env, PSW_W); } =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 48ac80cb2d..6e8758f82c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -67,69 +67,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_cb =3D cb; } =20 -void hppa_cpu_do_interrupt(CPUState *cs) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - int i =3D cs->exception_index; - - if (qemu_loglevel_mask(CPU_LOG_INT)) { - static const char * const names[] =3D { - [EXCP_HPMC] =3D "high priority machine check", - [EXCP_POWER_FAIL] =3D "power fail interrupt", - [EXCP_RC] =3D "recovery counter trap", - [EXCP_EXT_INTERRUPT] =3D "external interrupt", - [EXCP_LPMC] =3D "low priority machine check", - [EXCP_ITLB_MISS] =3D "instruction tlb miss fault", - [EXCP_IMP] =3D "instruction memory protection trap", - [EXCP_ILL] =3D "illegal instruction trap", - [EXCP_BREAK] =3D "break instruction trap", - [EXCP_PRIV_OPR] =3D "privileged operation trap", - [EXCP_PRIV_REG] =3D "privileged register trap", - [EXCP_OVERFLOW] =3D "overflow trap", - [EXCP_COND] =3D "conditional trap", - [EXCP_ASSIST] =3D "assist exception trap", - [EXCP_DTLB_MISS] =3D "data tlb miss fault", - [EXCP_NA_ITLB_MISS] =3D "non-access instruction tlb miss", - [EXCP_NA_DTLB_MISS] =3D "non-access data tlb miss", - [EXCP_DMP] =3D "data memory protection trap", - [EXCP_DMB] =3D "data memory break trap", - [EXCP_TLB_DIRTY] =3D "tlb dirty bit trap", - [EXCP_PAGE_REF] =3D "page reference trap", - [EXCP_ASSIST_EMU] =3D "assist emulation trap", - [EXCP_HPT] =3D "high-privilege transfer trap", - [EXCP_LPT] =3D "low-privilege transfer trap", - [EXCP_TB] =3D "taken branch trap", - [EXCP_DMAR] =3D "data memory access rights trap", - [EXCP_DMPI] =3D "data memory protection id trap", - [EXCP_UNALIGN] =3D "unaligned data reference trap", - [EXCP_PER_INTERRUPT] =3D "performance monitor interrupt", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_SYSCALL_LWS] =3D "syscall-lws", - }; - static int count; - const char *name =3D NULL; - - if (i >=3D 0 && i < ARRAY_SIZE(names)) { - name =3D names[i]; - } - if (name) { - qemu_log("INT %6d: %s ia_f=3D" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); - } else { - qemu_log("INT %6d: unknown %d ia_f=3D" TARGET_FMT_lx "\n", - ++count, i, env->iaoq_f); - } - } - cs->exception_index =3D -1; -} - -bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - abort(); - return false; -} - void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c new file mode 100644 index 0000000000..a59aae1189 --- /dev/null +++ b/target/hppa/int_helper.c @@ -0,0 +1,176 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + + +void hppa_cpu_do_interrupt(CPUState *cs) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + int i =3D cs->exception_index; + target_ureg iaoq_f =3D env->iaoq_f; + target_ureg iaoq_b =3D env->iaoq_b; + +#ifndef CONFIG_USER_ONLY + target_ureg old_psw; + + /* As documented in pa2.0 -- interruption handling. */ + /* step 1 */ + env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); + + /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ + cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + + /* step 3 */ + env->cr[CR_IIAOQ] =3D iaoq_f; + env->cr_back[1] =3D iaoq_b; + + if (old_psw & PSW_Q) { + /* step 5 */ + /* ISR and IOR will be set elsewhere. */ + switch (i) { + case EXCP_ILL: + case EXCP_BREAK: + case EXCP_PRIV_REG: + case EXCP_PRIV_OPR: + /* IIR set via translate.c. */ + break; + + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_DMAR: + case EXCP_DMPI: + case EXCP_UNALIGN: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_TLB_DIRTY: + case EXCP_PAGE_REF: + case EXCP_ASSIST_EMU: + { + /* Avoid reading directly from the virtual address, lest we + raise another exception from some sort of TLB issue. */ + vaddr vaddr; + hwaddr paddr; + + paddr =3D vaddr =3D iaoq_f & -4; + env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); + } + break; + + default: + /* Other exceptions do not set IIR. */ + break; + } + + /* step 6 */ + env->shadow[0] =3D env->gr[1]; + env->shadow[1] =3D env->gr[8]; + env->shadow[2] =3D env->gr[9]; + env->shadow[3] =3D env->gr[16]; + env->shadow[4] =3D env->gr[17]; + env->shadow[5] =3D env->gr[24]; + env->shadow[6] =3D env->gr[25]; + } + + /* step 7 */ + env->iaoq_f =3D env->cr[CR_IVA] + 32 * i; + env->iaoq_b =3D env->iaoq_f + 4; +#endif + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] =3D { + [EXCP_HPMC] =3D "high priority machine check", + [EXCP_POWER_FAIL] =3D "power fail interrupt", + [EXCP_RC] =3D "recovery counter trap", + [EXCP_EXT_INTERRUPT] =3D "external interrupt", + [EXCP_LPMC] =3D "low priority machine check", + [EXCP_ITLB_MISS] =3D "instruction tlb miss fault", + [EXCP_IMP] =3D "instruction memory protection trap", + [EXCP_ILL] =3D "illegal instruction trap", + [EXCP_BREAK] =3D "break instruction trap", + [EXCP_PRIV_OPR] =3D "privileged operation trap", + [EXCP_PRIV_REG] =3D "privileged register trap", + [EXCP_OVERFLOW] =3D "overflow trap", + [EXCP_COND] =3D "conditional trap", + [EXCP_ASSIST] =3D "assist exception trap", + [EXCP_DTLB_MISS] =3D "data tlb miss fault", + [EXCP_NA_ITLB_MISS] =3D "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] =3D "non-access data tlb miss", + [EXCP_DMP] =3D "data memory protection trap", + [EXCP_DMB] =3D "data memory break trap", + [EXCP_TLB_DIRTY] =3D "tlb dirty bit trap", + [EXCP_PAGE_REF] =3D "page reference trap", + [EXCP_ASSIST_EMU] =3D "assist emulation trap", + [EXCP_HPT] =3D "high-privilege transfer trap", + [EXCP_LPT] =3D "low-privilege transfer trap", + [EXCP_TB] =3D "taken branch trap", + [EXCP_DMAR] =3D "data memory access rights trap", + [EXCP_DMPI] =3D "data memory protection id trap", + [EXCP_UNALIGN] =3D "unaligned data reference trap", + [EXCP_PER_INTERRUPT] =3D "performance monitor interrupt", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_SYSCALL_LWS] =3D "syscall-lws", + }; + static int count; + const char *name =3D NULL; + char unknown[16]; + + if (i >=3D 0 && i < ARRAY_SIZE(names)) { + name =3D names[i]; + } + if (!name) { + snprintf(unknown, sizeof(unknown), "unknown %d", i); + name =3D unknown; + } + qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx + " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + ++count, name, + (target_ulong)iaoq_f, + (target_ulong)iaoq_b, + env->iaoq_f, + (target_ulong)env->cr[CR_IOR]); + } + cs->exception_index =3D -1; +} + +bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ +#ifndef CONFIG_USER_ONLY + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + + /* If interrupts are requested and enabled, raise them. */ + if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + cs->exception_index =3D EXCP_EXT_INTERRUPT; + hppa_cpu_do_interrupt(cs); + return true; + } +#endif + return false; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index df0bb04907..34b999fb2c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -282,6 +282,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + uint32_t insn; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -716,17 +717,25 @@ static DisasJumpType gen_excp(DisasContext *ctx, int = exception) return DISAS_NORETURN; } =20 +static DisasJumpType gen_excp_iir(DisasContext *ctx, int exc) +{ + TCGv_reg tmp =3D tcg_const_reg(ctx->insn); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); + tcg_temp_free(tmp); + return gen_excp(ctx, exc); +} + static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_ILL)); } =20 #define CHECK_MOST_PRIVILEGED(EXCP) \ do { \ if (ctx->privilege !=3D 0) { \ nullify_over(ctx); \ - return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + return nullify_end(ctx, gen_excp_iir(ctx, EXCP)); \ } \ } while (0) =20 @@ -1893,7 +1902,7 @@ static DisasJumpType trans_break(DisasContext *ctx, u= int32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_BREAK)); } =20 static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, @@ -4270,6 +4279,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ctx->null_cond.c =3D TCG_COND_NEVER; ret =3D DISAS_NEXT; } else { + ctx->insn =3D insn; ret =3D translate_one(ctx, insn); assert(ctx->null_lab =3D=3D NULL); } diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index d89285307b..dcd60a6839 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1,2 @@ obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o +obj-y +=3D int_helper.o --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 13/45] target/hppa: Implement unaligned access trap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ca619578dd..4d0b760baa 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,6 +48,23 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disass= emble_info *info) info->print_insn =3D print_insn_hppa; } =20 +static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + + cs->exception_index =3D EXCP_UNALIGN; + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] =3D addr; + env->cr[CR_ISR] =3D addr >> 32; + } + + cpu_loop_exit_restore(cs, retaddr); +} + static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -139,7 +156,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #else cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; #endif - + cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->tcg_initialize =3D hppa_translate_init; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837772680708.8179674141378; Wed, 24 Jan 2018 15:49:32 -0800 (PST) Received: from localhost ([::1]:54614 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUnJ-00065Y-UT for importer@patchew.org; Wed, 24 Jan 2018 18:49:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURU-0004dg-95 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURP-0001iL-8P for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:56 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURO-0001hL-VB for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:51 -0500 Received: by mail-pg0-x242.google.com with SMTP id r19so3820933pgn.1 for ; Wed, 24 Jan 2018 15:26:50 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=CJugC0HTqccstHjqeSWo1FHBhIo7Tmfaw+q9yecCg08=; b=ZFZQbIOJtdExq5g2WnVrUYdIcv90WhVaSqai1Pd8Ai4BcMI4H2lyp/YMUcle8zAMuV EE87bKTaA2joOQ+NN8Tixii/jpPqo1gPsDL01A9Nrhn7HSk2ECp1gia8Sn6wEoqkOg4N /3Cf3jdVARqJKJ//w4SHq0rrI8lCWvH5lApSE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=CJugC0HTqccstHjqeSWo1FHBhIo7Tmfaw+q9yecCg08=; b=K9CRa6SR22mJPofB5dOyt4fyACXEgoOY5Te76ztTDAW4ybrK0T+RCIQVa8UrggB1Gl nUBEZHgstbfj4um1fjA9JHRUK/isWZt3cUQB2kYcWC9+tseLa63mJPVLu5NOOencQxDG j79kI0hNd/PcFb7UMe/CmVkHCTVcav9tafTbCuZ1G2+Lm8ec4T/izQqY5t5hzFTwyn2G dJaNJMrYdBIDQ1D59tKCqI29AfZBQUGWkZ4kN2QfAHpocJnmCyzp68hLfnCvRWi4Ivje rfn/0stq4/9BtJtDkUgc1nUZQzz6dqRLA3hkOPEYcTf6hNiYPRUFmwqlsmcs3sd6dTNG SjXg== X-Gm-Message-State: AKwxytehVgbGgQ8JxuOGSHv4040pzja0NlNfzJGPLS7oR3/nOYUFXKE6 q5GZdsATChgT6WosVkWJCJD/B9138Rc= X-Google-Smtp-Source: AH8x226JxVhVibHoeaRMi4ebektqi3psjl0ya0oB/UMtzjCf8PmkISIAkvAkRJ69TybCh6x6Fdub+Q== X-Received: by 2002:a17:902:e83:: with SMTP id 3-v6mr3731412plx.274.1516836409263; Wed, 24 Jan 2018 15:26:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:54 -0800 Message-Id: <20180124232625.30105-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 14/45] target/hppa: Use space registers in data operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 14 ++ target/hppa/translate.c | 334 +++++++++++++++++++++++++++-----------------= ---- 2 files changed, 201 insertions(+), 147 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6ec3430ae3..94f9c8ca2b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,24 @@ #include "qemu-common.h" #include "cpu-qom.h" =20 +#ifdef TARGET_HPPA64 +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) #define TARGET_LONG_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_REGISTER_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* In order to form the GVA from space:offset, + we need a 64-bit virtual address space. */ +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif =20 #define CPUArchState struct CPUHPPAState =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 34b999fb2c..6be9e0c3ff 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -276,8 +276,9 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; =20 - int ntemps; - TCGv_reg temps[8]; + int ntempr, ntempl; + TCGv_reg tempr[4]; + TCGv_tl templ[4]; =20 DisasCond null_cond; TCGLabel *null_lab; @@ -458,11 +459,20 @@ static void cond_free(DisasCond *cond) =20 static TCGv_reg get_temp(DisasContext *ctx) { - unsigned i =3D ctx->ntemps++; - g_assert(i < ARRAY_SIZE(ctx->temps)); - return ctx->temps[i] =3D tcg_temp_new(); + unsigned i =3D ctx->ntempr++; + g_assert(i < ARRAY_SIZE(ctx->tempr)); + return ctx->tempr[i] =3D tcg_temp_new(); } =20 +#ifndef CONFIG_USER_ONLY +static TCGv_tl get_temp_tl(DisasContext *ctx) +{ + unsigned i =3D ctx->ntempl++; + g_assert(i < ARRAY_SIZE(ctx->templ)); + return ctx->templ[i] =3D tcg_temp_new_tl(); +} +#endif + static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t =3D get_temp(ctx); @@ -1324,6 +1334,70 @@ static DisasJumpType do_unit(DisasContext *ctx, unsi= gned rt, TCGv_reg in1, return DISAS_NEXT; } =20 +#ifndef CONFIG_USER_ONLY +/* Top 2 bits of the base register select sp[4-7]. */ +static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) +{ + TCGv_ptr ptr; + TCGv_reg tmp; + TCGv_i64 spc; + + if (sp !=3D 0) { + return cpu_sr[sp]; + } + + ptr =3D tcg_temp_new_ptr(); + tmp =3D tcg_temp_new(); + spc =3D get_temp_tl(ctx); + + tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + tcg_gen_andi_reg(tmp, tmp, 030); + tcg_gen_trunc_reg_ptr(ptr, tmp); + tcg_temp_free(tmp); + + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); + tcg_temp_free_ptr(ptr); + + return spc; +} +#endif + +static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, + unsigned rb, unsigned rx, int scale, target_sreg disp, + unsigned sp, int modify, bool is_phys) +{ + TCGv_reg base =3D load_gpr(ctx, rb); + TCGv_reg ofs; + + /* Note that RX is mutually exclusive with DISP. */ + if (rx) { + ofs =3D get_temp(ctx); + tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); + tcg_gen_add_reg(ofs, ofs, base); + } else if (disp || modify) { + ofs =3D get_temp(ctx); + tcg_gen_addi_reg(ofs, base, disp); + } else { + ofs =3D base; + } + + *pofs =3D ofs; +#ifdef CONFIG_USER_ONLY + *pgva =3D (modify <=3D 0 ? ofs : base); +#else + TCGv_tl addr =3D get_temp_tl(ctx); + tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); + if (ctx->base.tb->flags & PSW_W) { + tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); + } + if (!is_phys) { + tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); + } + *pgva =3D addr; +#endif +} + /* Emit a memory load. The modify parameter should be * < 0 for pre-modify, * > 0 for post-modify, @@ -1331,118 +1405,74 @@ static DisasJumpType do_unit(DisasContext *ctx, un= signed rt, TCGv_reg in1, */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 - addr =3D tcg_temp_new(); - base =3D load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } =20 static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 - addr =3D tcg_temp_new(); - base =3D load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } =20 static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 - addr =3D tcg_temp_new(); - base =3D load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); - - if (modify !=3D 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } =20 static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 - addr =3D tcg_temp_new(); - base =3D load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); - - if (modify !=3D 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } =20 #if TARGET_REGISTER_BITS =3D=3D 64 @@ -1455,7 +1485,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, =20 static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { TCGv_reg dest; =20 @@ -1468,7 +1498,7 @@ static DisasJumpType do_load(DisasContext *ctx, unsig= ned rt, unsigned rb, /* Make sure if RT =3D=3D RB, we see the result of the load. */ dest =3D get_temp(ctx); } - do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); =20 return nullify_end(ctx, DISAS_NEXT); @@ -1476,14 +1506,14 @@ static DisasJumpType do_load(DisasContext *ctx, uns= igned rt, unsigned rb, =20 static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new_i32(); - do_load_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); save_frw_i32(rt, tmp); tcg_temp_free_i32(tmp); =20 @@ -1496,14 +1526,14 @@ static DisasJumpType do_floadw(DisasContext *ctx, u= nsigned rt, unsigned rb, =20 static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new_i64(); - do_load_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); save_frd(rt, tmp); tcg_temp_free_i64(tmp); =20 @@ -1515,23 +1545,24 @@ static DisasJumpType do_floadd(DisasContext *ctx, u= nsigned rt, unsigned rb, } =20 static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_sreg disp, int modify, TCGMemOp mop) + target_sreg disp, unsigned sp, + int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } =20 static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned r= b, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; =20 nullify_over(ctx); =20 tmp =3D load_frw_i32(rt); - do_store_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); tcg_temp_free_i32(tmp); =20 return nullify_end(ctx, DISAS_NEXT); @@ -1539,14 +1570,14 @@ static DisasJumpType do_fstorew(DisasContext *ctx, = unsigned rt, unsigned rb, =20 static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned r= b, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D load_frd(rt); - do_store_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); tcg_temp_free_i64(tmp); =20 return nullify_end(ctx, DISAS_NEXT); @@ -2228,18 +2259,21 @@ static DisasJumpType trans_probe(DisasContext *ctx,= uint32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); + unsigned sp =3D extract32(insn, 14, 2); unsigned rb =3D extract32(insn, 21, 5); unsigned is_write =3D extract32(insn, 6, 1); - TCGv_reg dest; + TCGv_reg dest, ofs; + TCGv_tl addr; =20 nullify_over(ctx); =20 /* ??? Do something with priv level operand. */ dest =3D dest_gpr(ctx, rt); + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); if (is_write) { - gen_helper_probe_w(dest, load_gpr(ctx, rb)); + gen_helper_probe_w(dest, addr); } else { - gen_helper_probe_r(dest, load_gpr(ctx, rb)); + gen_helper_probe_r(dest, addr); } save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); @@ -2628,12 +2662,13 @@ static DisasJumpType trans_ld_idx_i(DisasContext *c= tx, uint32_t insn, unsigned m =3D extract32(insn, 5, 1); unsigned sz =3D extract32(insn, 6, 2); unsigned a =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); int disp =3D low_sextract(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); int modify =3D (m ? (a ? -1 : 1) : 0); TCGMemOp mop =3D MO_TE | sz; =20 - return do_load(ctx, rt, rb, 0, 0, disp, modify, mop); + return do_load(ctx, rt, rb, 0, 0, disp, sp, modify, mop); } =20 static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, @@ -2643,11 +2678,12 @@ static DisasJumpType trans_ld_idx_x(DisasContext *c= tx, uint32_t insn, unsigned m =3D extract32(insn, 5, 1); unsigned sz =3D extract32(insn, 6, 2); unsigned u =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); TCGMemOp mop =3D MO_TE | sz; =20 - return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, m, mop); + return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, sp, m, mop); } =20 static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, @@ -2657,12 +2693,13 @@ static DisasJumpType trans_st_idx_i(DisasContext *c= tx, uint32_t insn, unsigned m =3D extract32(insn, 5, 1); unsigned sz =3D extract32(insn, 6, 2); unsigned a =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rr =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); int modify =3D (m ? (a ? -1 : 1) : 0); TCGMemOp mop =3D MO_TE | sz; =20 - return do_store(ctx, rr, rb, disp, modify, mop); + return do_store(ctx, rr, rb, disp, sp, modify, mop); } =20 static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, @@ -2672,16 +2709,16 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, = uint32_t insn, unsigned m =3D extract32(insn, 5, 1); unsigned i =3D extract32(insn, 12, 1); unsigned au =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); TCGMemOp mop =3D MO_TEUL | MO_ALIGN_16; - TCGv_reg zero, addr, base, dest; + TCGv_reg zero, dest, ofs; + TCGv_tl addr; int modify, disp =3D 0, scale =3D 0; =20 nullify_over(ctx); =20 - /* ??? Share more code with do_load and do_load_{32,64}. */ - if (i) { modify =3D (m ? (au ? -1 : 1) : 0); disp =3D low_sextract(rx, 0, 5); @@ -2693,27 +2730,19 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, = uint32_t insn, } } if (modify) { - /* Base register modification. Make sure if RT =3D=3D RB, we see - the result of the load. */ + /* Base register modification. Make sure if RT =3D=3D RB, + we see the result of the load. */ dest =3D get_temp(ctx); } else { dest =3D dest_gpr(ctx, rt); } =20 - addr =3D tcg_temp_new(); - base =3D load_gpr(ctx, rb); - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); zero =3D tcg_const_reg(0); - tcg_gen_atomic_xchg_reg(dest, (modify <=3D 0 ? addr : base), - zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); if (modify) { - save_gpr(ctx, rb, addr); + save_gpr(ctx, rb, ofs); } save_gpr(ctx, rt, dest); =20 @@ -2726,20 +2755,17 @@ static DisasJumpType trans_stby(DisasContext *ctx, = uint32_t insn, target_sreg disp =3D low_sextract(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); unsigned a =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rt =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); - TCGv_reg addr, val; + TCGv_reg ofs, val; + TCGv_tl addr; =20 nullify_over(ctx); =20 - addr =3D tcg_temp_new(); - if (m || disp =3D=3D 0) { - tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); - } else { - tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); - } + form_gva(ctx, &addr, &ofs, rb, 0, 0, disp, sp, m, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); val =3D load_gpr(ctx, rt); - if (a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { gen_helper_stby_e_parallel(cpu_env, addr, val); @@ -2755,11 +2781,9 @@ static DisasJumpType trans_stby(DisasContext *ctx, u= int32_t insn, } =20 if (m) { - tcg_gen_addi_reg(addr, addr, disp); - tcg_gen_andi_reg(addr, addr, ~3); - save_gpr(ctx, rb, addr); + tcg_gen_andi_reg(ofs, ofs, ~3); + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); =20 return nullify_end(ctx, DISAS_NEXT); } @@ -2824,15 +2848,18 @@ static DisasJumpType trans_load(DisasContext *ctx, = uint32_t insn, { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); + unsigned sp =3D extract32(insn, 14, 2); target_sreg i =3D assemble_16(insn); =20 - return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mo= p); + return do_load(ctx, rt, rb, 0, 0, i, sp, + is_mod ? (i < 0 ? -1 : 1) : 0, mop); } =20 static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); + unsigned sp =3D extract32(insn, 14, 2); target_sreg i =3D assemble_16a(insn); unsigned ext2 =3D extract32(insn, 1, 2); =20 @@ -2840,11 +2867,11 @@ static DisasJumpType trans_load_w(DisasContext *ctx= , uint32_t insn) case 0: case 1: /* FLDW without modification. */ - return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. Note that the sign of I selects post-dec vs pre-inc. */ - return do_load(ctx, rt, rb, 0, 0, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_load(ctx, rt, rb, 0, 0, i, sp, (i < 0 ? 1 : -1), MO_TEUL= ); default: return gen_illegal(ctx); } @@ -2855,11 +2882,12 @@ static DisasJumpType trans_fload_mod(DisasContext *= ctx, uint32_t insn) target_sreg i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); unsigned a =3D extract32(insn, 2, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned t0 =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); =20 /* FLDW with modification. */ - return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } =20 static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, @@ -2867,15 +2895,17 @@ static DisasJumpType trans_store(DisasContext *ctx,= uint32_t insn, { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); + unsigned sp =3D extract32(insn, 14, 2); target_sreg i =3D assemble_16(insn); =20 - return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); + return do_store(ctx, rt, rb, i, sp, is_mod ? (i < 0 ? -1 : 1) : 0, mop= ); } =20 static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); + unsigned sp =3D extract32(insn, 14, 2); target_sreg i =3D assemble_16a(insn); unsigned ext2 =3D extract32(insn, 1, 2); =20 @@ -2883,10 +2913,10 @@ static DisasJumpType trans_store_w(DisasContext *ct= x, uint32_t insn) case 0: case 1: /* FSTW without modification. */ - return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. */ - return do_store(ctx, rt, rb, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); } @@ -2897,11 +2927,12 @@ static DisasJumpType trans_fstore_mod(DisasContext = *ctx, uint32_t insn) target_sreg i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); unsigned a =3D extract32(insn, 2, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned t0 =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); =20 /* FSTW with modification. */ - return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } =20 static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) @@ -2913,6 +2944,7 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, = uint32_t insn) /* unsigned cc =3D extract32(insn, 10, 2); */ unsigned i =3D extract32(insn, 12, 1); unsigned ua =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D t1 * 32 + t0; @@ -2932,9 +2964,9 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, = uint32_t insn) =20 switch (ext3) { case 0: /* FLDW */ - return do_floadw(ctx, rt, rb, rx, scale, disp, modify); + return do_floadw(ctx, rt, rb, rx, scale, disp, sp, modify); case 4: /* FSTW */ - return do_fstorew(ctx, rt, rb, rx, scale, disp, modify); + return do_fstorew(ctx, rt, rb, rx, scale, disp, sp, modify); } return gen_illegal(ctx); } @@ -2947,6 +2979,7 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx,= uint32_t insn) /* unsigned cc =3D extract32(insn, 10, 2); */ unsigned i =3D extract32(insn, 12, 1); unsigned ua =3D extract32(insn, 13, 1); + unsigned sp =3D extract32(insn, 14, 2); unsigned rx =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); int modify =3D (m ? (ua ? -1 : 1) : 0); @@ -2965,9 +2998,9 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx,= uint32_t insn) =20 switch (ext4) { case 0: /* FLDD */ - return do_floadd(ctx, rt, rb, rx, scale, disp, modify); + return do_floadd(ctx, rt, rb, rx, scale, disp, sp, modify); case 8: /* FSTD */ - return do_fstored(ctx, rt, rb, rx, scale, disp, modify); + return do_fstored(ctx, rt, rb, rx, scale, disp, sp, modify); default: return gen_illegal(ctx); } @@ -4208,8 +4241,10 @@ static int hppa_tr_init_disas_context(DisasContextBa= se *dcbase, bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound =3D MIN(max_insns, bound); =20 - ctx->ntemps =3D 0; - memset(ctx->temps, 0, sizeof(ctx->temps)); + ctx->ntempr =3D 0; + ctx->ntempl =3D 0; + memset(ctx->tempr, 0, sizeof(ctx->tempr)); + memset(ctx->templ, 0, sizeof(ctx->templ)); =20 return bound; } @@ -4286,11 +4321,16 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) } =20 /* Free any temporaries allocated. */ - for (i =3D 0, n =3D ctx->ntemps; i < n; ++i) { - tcg_temp_free(ctx->temps[i]); - ctx->temps[i] =3D NULL; + for (i =3D 0, n =3D ctx->ntempr; i < n; ++i) { + tcg_temp_free(ctx->tempr[i]); + ctx->tempr[i] =3D NULL; + } + for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { + tcg_temp_free_tl(ctx->templ[i]); + ctx->templ[i] =3D NULL; } - ctx->ntemps =3D 0; + ctx->ntempr =3D 0; + ctx->ntempl =3D 0; =20 /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ @@ -4400,7 +4440,7 @@ void restore_state_to_opc(CPUHPPAState *env, Translat= ionBlock *tb, target_ulong *data) { env->iaoq_f =3D data[0]; - if (data[1] !=3D -1) { + if (data[1] !=3D (target_ureg)-1) { env->iaoq_b =3D data[1]; } /* Since we were executing the instruction at IAOQ_F, and took some --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837458666964.5999455689297; Wed, 24 Jan 2018 15:44:18 -0800 (PST) Received: from localhost ([::1]:54560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUiH-0001aj-R2 for importer@patchew.org; Wed, 24 Jan 2018 18:44:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURU-0004dh-9H for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURQ-0001jN-4f for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:56 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURP-0001iY-V8 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:52 -0500 Received: by mail-pg0-x244.google.com with SMTP id k68so3819217pga.3 for ; Wed, 24 Jan 2018 15:26:51 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 15/45] target/hppa: Avoid privilege level decrease during branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6be9e0c3ff..4a69f05a91 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1862,6 +1862,40 @@ static DisasJumpType do_ibranch(DisasContext *ctx, T= CGv_reg dest, return DISAS_NEXT; } =20 +/* Implement + * if (IAOQ_Front{30..31} < GR[b]{30..31}) + * IAOQ_Next{30..31} =E2=86=90 GR[b]{30..31}; + * else + * IAOQ_Next{30..31} =E2=86=90 IAOQ_Front{30..31}; + * which keeps the privilege level from being increased. + */ +static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) +{ +#ifdef CONFIG_USER_ONLY + return offset; +#else + TCGv_reg dest; + switch (ctx->privilege) { + case 0: + /* Privilege 0 is maximum and is allowed to decrease. */ + return offset; + case 3: + /* Privilege 3 is minimum and is never allowed increase. */ + dest =3D get_temp(ctx); + tcg_gen_ori_reg(dest, offset, 3); + break; + default: + dest =3D tcg_temp_new(); + tcg_gen_andi_reg(dest, offset, -4); + tcg_gen_ori_reg(dest, dest, ctx->privilege); + tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset= ); + tcg_temp_free(dest); + break; + } + return dest; +#endif +} + #ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific @@ -3441,6 +3475,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint= 32_t insn, bool is_l) unsigned n =3D extract32(insn, 1, 1); unsigned b =3D extract32(insn, 21, 5); target_sreg disp =3D assemble_17(insn); + TCGv_reg tmp; =20 /* unsigned s =3D low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -3449,16 +3484,19 @@ static DisasJumpType trans_be(DisasContext *ctx, ui= nt32_t insn, bool is_l) manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ =20 +#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we c= an goto_tb to the TB containing the syscall. */ if (b =3D=3D 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); - } else { - TCGv_reg tmp =3D get_temp(ctx); - tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); - return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } +#endif + + tmp =3D get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); + tmp =3D do_ibranch_priv(ctx, tmp); + return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } =20 static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3490,6 +3528,7 @@ static DisasJumpType trans_blr(DisasContext *ctx, uin= t32_t insn, =20 tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + /* The computation here never changes privilege level. */ return do_ibranch(ctx, tmp, link, n); } =20 @@ -3508,6 +3547,7 @@ static DisasJumpType trans_bv(DisasContext *ctx, uint= 32_t insn, tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } + dest =3D do_ibranch_priv(ctx, dest); return do_ibranch(ctx, dest, 0, n); } =20 @@ -3517,8 +3557,10 @@ static DisasJumpType trans_bve(DisasContext *ctx, ui= nt32_t insn, unsigned n =3D extract32(insn, 1, 1); unsigned rb =3D extract32(insn, 21, 5); unsigned link =3D extract32(insn, 13, 1) ? 2 : 0; + TCGv_reg dest; =20 - return do_ibranch(ctx, load_gpr(ctx, rb), link, n); + dest =3D do_ibranch_priv(ctx, load_gpr(ctx, rb)); + return do_ibranch(ctx, dest, link, n); } =20 static const DisasInsn table_branch[] =3D { --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836735143517.885829169852; Wed, 24 Jan 2018 15:32:15 -0800 (PST) Received: from localhost ([::1]:54482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUWW-0008RF-9E for importer@patchew.org; Wed, 24 Jan 2018 18:32:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51086) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURU-0004de-8b for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURS-0001lY-0u for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:56 -0500 Received: from mail-pg0-x231.google.com ([2607:f8b0:400e:c05::231]:45020) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURR-0001kY-Of for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:53 -0500 Received: by mail-pg0-x231.google.com with SMTP id m20so3808955pgc.11 for ; Wed, 24 Jan 2018 15:26:53 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=p+QD+b6Cw+XW39YAD69NZNQ9QvIBR9apORbL4Kd/U/Y=; b=HI1pPunDNFbWoUCVe5uwPIkELGJkHMsPYQooMaHo40lnOTg78inOLyNrQyYPOo6Ptb yrPrDYrW6uWNoetqN0pkIQMSUl3UqZnjm2kJSrx5ABEly3fDL5x3MImHpNufd40MPgAa UFRT6gX5ORVztMCO7mzB/rK0gq3vgILXKoA+U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=p+QD+b6Cw+XW39YAD69NZNQ9QvIBR9apORbL4Kd/U/Y=; b=C3x7+9we/qNb4ErLtEy1ORWiEAy97yhCGnq5H+YmGRFqpARqQsmOudAK+8M24LV/Yk SLQcto9NAQFEoENZvWhACLOVtvKfcRJFQBsC9S4h46jbp4IqdbSQZzMoaU8uRmYRpaub t2Juuu8wBrnOpmj4LDcdVQdycJb3EyEXimEjn+fYFfOt6K5f7/am5xI9lWNLVof8H0h3 kd4oz2oSwG1qIzXQ8xSEueI7ACZZUrw0AfTmI+GFHakMsUmLwEc2o48SehvGFKPnegfM OUDOgWQOvhBmPeAHCwmjTdcQ1c7f/lVJUqUx8ocsPTL0t7gG58VLYl3qm7uW8vjcRTRU 7RRw== X-Gm-Message-State: AKwxytdY4qngiGl4j+165Kg1oj+PahXi8eaTwgSTNCJ5clHyPoNg4m91 qK7i+jbwZ2YfVClAIsr+9pAFhEZwHKg= X-Google-Smtp-Source: AH8x226yGAD2hkbI8ha65qMDz5wAzlFe4lwjARMwvWHftSvwnbMGqrGQzvR7QMAyaQu/GMl4BQdBeg== X-Received: by 2002:a17:902:598e:: with SMTP id p14-v6mr9045846pli.289.1516836412108; Wed, 24 Jan 2018 15:26:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:56 -0800 Message-Id: <20180124232625.30105-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PATCH v3 16/45] target/hppa: Implement IASQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 53 ++++++++++++++++++++- target/hppa/cpu.c | 15 ++++++ target/hppa/helper.c | 3 +- target/hppa/int_helper.c | 16 +++++-- target/hppa/op_helper.c | 2 + target/hppa/translate.c | 117 ++++++++++++++++++++++++++++++++++++++-----= ---- 6 files changed, 179 insertions(+), 27 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 94f9c8ca2b..d583ea43dd 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -186,6 +186,8 @@ struct CPUHPPAState { =20 target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ + uint64_t iasq_f; + uint64_t iasq_b; =20 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -240,15 +242,62 @@ void hppa_translate_init(void); =20 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 +static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, + target_ureg off) +{ +#ifdef CONFIG_USER_ONLY + return off; +#else + off &=3D (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + return spc | off; +#endif +} + +static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, + target_ureg off) +{ + return hppa_form_gva_psw(env->psw, spc, off); +} + +/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +#define TB_FLAG_PRIV_SHIFT 8 + static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, uint32_t *pflags) { + uint32_t flags =3D env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu priviledge from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f; *cs_base =3D env->iaoq_b; +#else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ - *pflags =3D (env->psw & (PSW_W | PSW_C | PSW_D)) - | env->psw_n * PSW_N; + flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); + flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc =3D (env->psw & PSW_C + ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) + : env->iaoq_f & -4); + *cs_base =3D env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a p= age. + Failure is indicated by a zero difference. */ + if (env->iasq_f =3D=3D env->iasq_b) { + target_sreg diff =3D env->iaoq_b - env->iaoq_f; + if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { + *cs_base |=3D (uint32_t)diff; + } + } +#endif + + *pflags =3D flags; } =20 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4d0b760baa..2970afd58d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -37,8 +37,23 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, T= ranslationBlock *tb) { HPPACPU *cpu =3D HPPA_CPU(cs); =20 +#ifdef CONFIG_USER_ONLY cpu->env.iaoq_f =3D tb->pc; cpu->env.iaoq_b =3D tb->cs_base; +#else + /* Recover the IAOQ values from the GVA + PRIV. */ + uint32_t priv =3D (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; + target_ulong cs_base =3D tb->cs_base; + target_ulong iasq_f =3D cs_base & ~0xffffffffull; + int32_t diff =3D cs_base; + + cpu->env.iasq_f =3D iasq_f; + cpu->env.iaoq_f =3D (tb->pc & ~iasq_f) + priv; + if (diff) { + cpu->env.iaoq_b =3D cpu->env.iaoq_f + diff; + } +#endif + cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6e8758f82c..858ec205b6 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -78,7 +78,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int i; =20 cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); + hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); =20 psw_c[0] =3D (psw & PSW_W ? 'W' : '-'); psw_c[1] =3D (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a59aae1189..02963b80c6 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -32,6 +32,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i =3D cs->exception_index; target_ureg iaoq_f =3D env->iaoq_f; target_ureg iaoq_b =3D env->iaoq_b; + uint64_t iasq_f =3D env->iasq_f; + uint64_t iasq_b =3D env->iasq_b; =20 #ifndef CONFIG_USER_ONLY target_ureg old_psw; @@ -44,6 +46,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); =20 /* step 3 */ + env->cr[CR_IIASQ] =3D iasq_f >> 32; + env->cr_back[0] =3D iasq_b >> 32; env->cr[CR_IIAOQ] =3D iaoq_f; env->cr_back[1] =3D iaoq_b; =20 @@ -79,6 +83,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) hwaddr paddr; =20 paddr =3D vaddr =3D iaoq_f & -4; + if (old_psw & PSW_C) { + vaddr =3D hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & = -4); + } env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); } break; @@ -101,6 +108,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 7 */ env->iaoq_f =3D env->cr[CR_IVA] + 32 * i; env->iaoq_b =3D env->iaoq_f + 4; + env->iasq_f =3D 0; + env->iasq_b =3D 0; #endif =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -151,10 +160,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, - (target_ulong)iaoq_f, - (target_ulong)iaoq_b, + hppa_form_gva(env, iasq_f, iaoq_f), + hppa_form_gva(env, iasq_b, iaoq_b), env->iaoq_f, - (target_ulong)env->cr[CR_IOR]); + hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, + env->cr[CR_IOR])); } cs->exception_index =3D -1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3f5dcbbca0..1963b2439b 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -622,6 +622,8 @@ void HELPER(rfi)(CPUHPPAState *env) if (env->psw & (PSW_I | PSW_R | PSW_Q)) { helper_excp(env, EXCP_ILL); } + env->iasq_f =3D (uint64_t)env->cr[CR_IIASQ] << 32; + env->iasq_b =3D (uint64_t)env->cr_back[0] << 32; env->iaoq_f =3D env->cr[CR_IIAOQ]; env->iaoq_b =3D env->cr_back[1]; cpu_hppa_put_psw(env, env->cr[CR_IPSW]); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a69f05a91..44abc9006b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -325,6 +325,8 @@ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; +static TCGv_i64 cpu_iasq_f; +static TCGv_i64 cpu_iasq_b; static TCGv_reg cpu_sar; static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; @@ -380,6 +382,13 @@ void hppa_translate_init(void) const GlobalVar *v =3D &vars[i]; *v->var =3D tcg_global_mem_new(cpu_env, v->ofs, v->name); } + + cpu_iasq_f =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_f), + "iasq_f"); + cpu_iasq_b =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_b), + "iasq_b"); } =20 static DisasCond cond_make_f(void) @@ -1760,6 +1769,11 @@ static DisasJumpType do_cbranch(DisasContext *ctx, t= arget_sreg disp, bool is_n, ctx->null_lab =3D NULL; } nullify_set(ctx, n); + if (ctx->iaoq_n =3D=3D -1) { + /* The temporary iaoq_n_var died at the branch above. + Regenerate it here instead of saving it. */ + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } =20 @@ -1801,11 +1815,17 @@ static DisasJumpType do_ibranch(DisasContext *ctx, = TCGv_reg dest, } next =3D get_temp(ctx); tcg_gen_mov_reg(next, dest); - ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D next; if (is_n) { + if (use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, next); + tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + nullify_set(ctx, 0); + return DISAS_IAQ_N_UPDATED; + } ctx->null_cond.c =3D TCG_COND_ALWAYS; } + ctx->iaoq_n =3D -1; + ctx->iaoq_n_var =3D next; } else if (is_n && use_nullify_skip(ctx)) { /* The (conditional) branch, B, nullifies the next insn, N, and we're allowed to skip execution N (no single-step or @@ -3477,26 +3497,55 @@ static DisasJumpType trans_be(DisasContext *ctx, ui= nt32_t insn, bool is_l) target_sreg disp =3D assemble_17(insn); TCGv_reg tmp; =20 - /* unsigned s =3D low_uextract(insn, 13, 3); */ +#ifdef CONFIG_USER_ONLY /* ??? It seems like there should be a good way of using "be disp(sr2, r0)", the canonical gateway entry mechanism to our advantage. But that appears to be inconvenient to manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ - -#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we c= an goto_tb to the TB containing the syscall. */ if (b =3D=3D 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } +#else + int sp =3D assemble_sr3(insn); + nullify_over(ctx); #endif =20 tmp =3D get_temp(ctx); tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); tmp =3D do_ibranch_priv(ctx, tmp); + +#ifdef CONFIG_USER_ONLY return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); +#else + TCGv_i64 new_spc =3D tcg_temp_new_i64(); + + load_spr(ctx, new_spc, sp); + if (is_l) { + copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); + } + if (n && use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, tmp); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_i64(cpu_iasq_f, new_spc); + tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + } else { + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b =3D=3D -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + tcg_gen_mov_reg(cpu_iaoq_b, tmp); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); + nullify_set(ctx, n); + } + tcg_temp_free_i64(new_spc); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } =20 static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3559,8 +3608,26 @@ static DisasJumpType trans_bve(DisasContext *ctx, ui= nt32_t insn, unsigned link =3D extract32(insn, 13, 1) ? 2 : 0; TCGv_reg dest; =20 +#ifdef CONFIG_USER_ONLY dest =3D do_ibranch_priv(ctx, load_gpr(ctx, rb)); return do_ibranch(ctx, dest, link, n); +#else + nullify_over(ctx); + dest =3D do_ibranch_priv(ctx, load_gpr(ctx, rb)); + + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b =3D=3D -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + copy_iaoq_entry(cpu_iaoq_b, -1, dest); + tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + if (link) { + copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + nullify_set(ctx, n); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } =20 static const DisasInsn table_branch[] =3D { @@ -4267,15 +4334,21 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_USER_IDX; ctx->mmu_idx =3D MMU_USER_IDX; + ctx->iaoq_f =3D ctx->base.pc_first; + ctx->iaoq_b =3D ctx->base.tb->cs_base; #else - ctx->privilege =3D ctx->base.pc_first & 3; + ctx->privilege =3D (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->base.tb->flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); -#endif - ctx->iaoq_f =3D ctx->base.pc_first; - ctx->iaoq_b =3D ctx->base.tb->cs_base; - ctx->base.pc_first &=3D -4; =20 + /* Recover the IAOQ values from the GVA + PRIV. */ + uint64_t cs_base =3D ctx->base.tb->cs_base; + uint64_t iasq_f =3D cs_base & ~0xffffffffull; + int32_t diff =3D cs_base; + + ctx->iaoq_f =3D (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_b =3D (diff ? ctx->iaoq_f + diff : -1); +#endif ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 @@ -4318,7 +4391,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cs, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next =3D (ctx->iaoq_f & -4) + 4; + ctx->base.pc_next +=3D 4; return true; } =20 @@ -4331,7 +4404,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) =20 /* Execute one insn. */ #ifdef CONFIG_USER_ONLY - if (ctx->iaoq_f < TARGET_PAGE_SIZE) { + if (ctx->base.pc_next < TARGET_PAGE_SIZE) { ret =3D do_page_zero(ctx); assert(ret !=3D DISAS_NEXT); } else @@ -4339,7 +4412,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f & -4); + uint32_t insn =3D cpu_ldl_code(env, ctx->base.pc_next); =20 /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4377,18 +4450,21 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret =3D=3D DISAS_NEXT && ctx->iaoq_b !=3D ctx->iaoq_f + 4) { - if (ctx->null_cond.c =3D=3D TCG_COND_NEVER - || ctx->null_cond.c =3D=3D TCG_COND_ALWAYS) { + if (ctx->iaoq_b !=3D -1 && ctx->iaoq_n !=3D -1 + && use_goto_tb(ctx, ctx->iaoq_b) + && (ctx->null_cond.c =3D=3D TCG_COND_NEVER + || ctx->null_cond.c =3D=3D TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c =3D=3D TCG_COND_ALWAYS); gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); ret =3D DISAS_NORETURN; } else { ret =3D DISAS_IAQ_N_STALE; - } + } } ctx->iaoq_f =3D ctx->iaoq_b; ctx->iaoq_b =3D ctx->iaoq_n; ctx->base.is_jmp =3D ret; + ctx->base.pc_next +=3D 4; =20 if (ret =3D=3D DISAS_NORETURN || ret =3D=3D DISAS_IAQ_N_UPDATED) { return; @@ -4396,6 +4472,9 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) if (ctx->iaoq_f =3D=3D -1) { tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); +#ifndef CONFIG_USER_ONLY + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); +#endif nullify_save(ctx); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b =3D=3D -1) { @@ -4430,15 +4509,11 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) default: g_assert_not_reached(); } - - /* We don't actually use this during normal translation, - but we should interact with the generic main loop. */ - ctx->base.pc_next =3D ctx->base.pc_first + 4 * ctx->base.num_insns; } =20 static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - target_ureg pc =3D dcbase->pc_first; + target_ulong pc =3D dcbase->pc_first; =20 #ifdef CONFIG_USER_ONLY switch (pc) { --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837627213185.42995286166536; Wed, 24 Jan 2018 15:47:07 -0800 (PST) Received: from localhost ([::1]:54579 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUl0-00044Y-BJ for importer@patchew.org; Wed, 24 Jan 2018 18:47:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURU-0004eB-Pu for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURS-0001n3-To for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:56 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:38598) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURS-0001m1-M5 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:54 -0500 Received: by mail-pf0-x244.google.com with SMTP id k19so4360186pfj.5 for ; Wed, 24 Jan 2018 15:26:54 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=cNMWduwd/imEbozb8k3aw4xPmG54EEtG552lqHT79mQ=; b=K/Kd1IwDo7MruYUuTKUvO1GNRiDwCKcp0Ptt6hxHWwFr5Kt3/WarRLVvj+74jpIfJn rMKl9ZBy6kxTq8RurgbaSWY2TX9yM+2vmCpVTE2RVDBPTaWKhQWp2OJmKRUsNHvCj0zd FYwdEckaqgGdv2+ri3Ku64Glt6Lbb8K4MOa3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=cNMWduwd/imEbozb8k3aw4xPmG54EEtG552lqHT79mQ=; b=UrCl3vflTv549B6cyinUemwoQKwxAWN4ELyEJbk55pe3wifjd6DH3LfP4oicr87kXz lTxnCdDRU/n2d3oyqgPnt8sitwmQ5Om3b2phoqHaiEBgkN70EACnMmiA+BnMOgal6Vt4 MmNehuJyMvZ/4jLj9Y/LqYVZ9swn12pNhAU3C3/BP0tMf9YOfOQ4SCV93IebiYrYf/sZ +wdM/4jfTyqoPwquSewJL8KceowOP7sKwAk35Z09bEpx3Vu/hb/4WM22WbeTCYCVxLcj +NJV7Cg30sET78A8COjiagJWLhwmVsaMVoYizgAk+X/83L8FEePGSEHTae2aFDiI2QkM Sblg== X-Gm-Message-State: AKwxyte3czS3vyJEvdcAm6sEB0RlHGolNrqBKsxIEL7KztJrfPV+GBlP 7VomqlirQWG3PKiEOJ6KeHSRY3yLtng= X-Google-Smtp-Source: AH8x227B8xL4jrd1KtVxW2VIlD9F35hnrt9DRoHQPOkMvYQmcUjcjbix8gjiRpRZKNpr5trDT/aCFA== X-Received: by 2002:a17:902:7f0b:: with SMTP id d11-v6mr5407673plm.70.1516836413291; Wed, 24 Jan 2018 15:26:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:57 -0800 Message-Id: <20180124232625.30105-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 17/45] target/hppa: Implement tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 29 ++++++++- target/hppa/int_helper.c | 15 ++++- target/hppa/mem_helper.c | 151 +++++++++++++++++++++++++++++++++++++++++++= ++-- 3 files changed, 188 insertions(+), 7 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d583ea43dd..c7a2fb5b20 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -165,6 +165,22 @@ typedef int64_t target_sreg; #define TREG_FMT_ld "%"PRId64 #endif =20 +typedef struct { + uint64_t va_b; + uint64_t va_e; + target_ureg pa; + unsigned u : 1; + unsigned t : 1; + unsigned d : 1; + unsigned b : 1; + unsigned page_size : 4; + unsigned ar_type : 3; + unsigned ar_pl1 : 2; + unsigned ar_pl2 : 2; + unsigned entry_valid : 1; + unsigned access_id : 16; +} hppa_tlb_entry; + struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; @@ -198,6 +214,12 @@ struct CPUHPPAState { =20 /* Those resources are used only in QEMU core */ CPU_COMMON + + /* ??? The number of entries isn't specified by the architecture. */ + /* ??? Implement a unified itlb/dtlb for the moment. */ + /* ??? We should use a more intelligent data structure. */ + hppa_tlb_entry tlb[256]; + uint32_t tlb_last; }; =20 /** @@ -307,12 +329,17 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler =20 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mi= dx); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mi= dx); +#else +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *ppro= t); +#endif =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 02963b80c6..5ae5233a96 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -79,12 +79,25 @@ void hppa_cpu_do_interrupt(CPUState *cs) { /* Avoid reading directly from the virtual address, lest we raise another exception from some sort of TLB issue. */ + /* ??? An alternate fool-proof method would be to store the + instruction data into the unwind info. That's probably + a bit too much in the way of extra storage required. */ vaddr vaddr; hwaddr paddr; =20 paddr =3D vaddr =3D iaoq_f & -4; if (old_psw & PSW_C) { - vaddr =3D hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & = -4); + int prot, t; + + vaddr =3D hppa_form_gva_psw(old_psw, iasq_f, vaddr); + t =3D hppa_get_physical_address(env, vaddr, 0, + MMU_INST_FETCH, + &paddr, &prot); + if (t >=3D 0) { + /* We can't re-load the instruction. */ + env->cr[CR_IIR] =3D 0; + break; + } } env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 1afaf89539..08ab19aacf 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -36,18 +36,159 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, return 1; } #else +static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent =3D &env->tlb[i]; + if (ent->va_b <=3D addr && addr <=3D ent->va_e && ent->entry_valid= ) { + return ent; + } + } + return NULL; +} + +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *ppro= t) +{ + hwaddr phys; + int prot, ret, r_prot, w_prot, x_prot, a_prot; + bool ifetch =3D type =3D=3D MMU_INST_FETCH; + hppa_tlb_entry *ent; + + /* Virtual translation disabled. Direct map virtual to physical. */ + if (mmu_idx =3D=3D MMU_PHYS_IDX) { + phys =3D addr; + prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + ret =3D -1; + goto egress; + } + + /* Find a valid tlb entry that matches the virtual address. */ + ent =3D hppa_find_tlb(env, addr); + if (ent =3D=3D NULL) { + phys =3D 0; + prot =3D 0; + ret =3D (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + goto egress; + } + + /* We now know the physical address. */ + phys =3D ent->pa + (addr & ~TARGET_PAGE_MASK); + + /* Map TLB access_rights field to QEMU protection. */ + r_prot =3D (mmu_idx <=3D ent->ar_pl1 ? PROT_READ : 0); + w_prot =3D (mmu_idx <=3D ent->ar_pl2 ? PROT_WRITE : 0); + x_prot =3D (ent->ar_pl2 <=3D mmu_idx && mmu_idx <=3D ent->ar_pl1 ? PRO= T_EXEC : 0); + switch (ent->ar_type) { + case 0: /* read-only: data page */ + prot =3D r_prot; + break; + case 1: /* read/write: dynamic data page */ + prot =3D r_prot | w_prot; + break; + case 2: /* read/execute: normal code page */ + prot =3D r_prot | x_prot; + break; + case 3: /* read/write/execute: dynamic code page */ + prot =3D r_prot | w_prot | x_prot; + break; + default: /* execute: promote to privilege level type & 3 */ + prot =3D x_prot; + } + + /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. = */ + + /* Map MMUAccessType to QEMU protection. */ + if (ifetch) { + a_prot =3D PROT_EXEC; + } else if (type =3D=3D MMU_DATA_STORE) { + a_prot =3D PROT_WRITE; + } else { + a_prot =3D PROT_READ; + } + + if (unlikely(!(prot & a_prot))) { + /* The access isn't allowed -- Inst/Data Memory Protection Fault. = */ + ret =3D (ifetch ? EXCP_IMP : EXCP_DMP); + goto egress; + } + + /* In reverse priority order, check for conditions which raise faults. + As we go, remove PROT bits that cover the condition we want to chec= k. + In this way, the resulting PROT will force a re-check of the + architectural TLB entry for the next access. */ + ret =3D -1; + if (unlikely(!ent->d)) { + if (type =3D=3D MMU_DATA_STORE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret =3D EXCP_TLB_DIRTY; + } + prot &=3D PROT_READ | PROT_EXEC; + } + if (unlikely(ent->b)) { + if (type =3D=3D MMU_DATA_STORE) { + /* The B bit is set -- Data Memory Break Fault. */ + ret =3D EXCP_DMB; + } + prot &=3D PROT_READ | PROT_EXEC; + } + if (unlikely(ent->t)) { + if (!ifetch) { + /* The T bit is set -- Page Reference Fault. */ + ret =3D EXCP_PAGE_REF; + } + prot &=3D PROT_EXEC; + } + + egress: + *pphys =3D phys; + *pprot =3D prot; + return ret; +} + hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - /* Stub */ - return addr; + HPPACPU *cpu =3D HPPA_CPU(cs); + hwaddr phys; + int prot, excp; + + /* If the (data) mmu is disabled, bypass translation. */ + /* ??? We really ought to know if the code mmu is disabled too, + in order to get the correct debugging dumps. */ + if (!(cpu->env.psw & PSW_D)) { + return addr; + } + + excp =3D hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + + /* Since we're translating for debugging, the only error that is a + hard error is no translation at all. Otherwise, while a real cpu + access might not have permission, the debugger does. */ + return excp =3D=3D EXCP_DTLB_MISS ? -1 : phys; } =20 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, int mmu_idx, uintptr_t retaddr) { - /* Stub */ - int prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - hwaddr phys =3D addr; + HPPACPU *cpu =3D HPPA_CPU(cs); + int prot, excp; + hwaddr phys; + + excp =3D hppa_get_physical_address(&cpu->env, addr, mmu_idx, + type, &phys, &prot); + if (unlikely(excp >=3D 0)) { + /* Failure. Raise the indicated exception. */ + cs->exception_index =3D excp; + if (cpu->env.psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + cpu->env.cr[CR_IOR] =3D addr; + cpu->env.cr[CR_ISR] =3D addr >> 32; + } + cpu_loop_exit_restore(cs, retaddr); + } =20 /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836873755206.43578110367548; Wed, 24 Jan 2018 15:34:33 -0800 (PST) Received: from localhost ([::1]:54495 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUYq-0001k6-Uv for importer@patchew.org; Wed, 24 Jan 2018 18:34:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURV-0004f0-K5 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURU-0001qe-Dj for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:57 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURU-0001on-72 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:56 -0500 Received: by mail-pg0-x243.google.com with SMTP id r19so3821098pgn.1 for ; Wed, 24 Jan 2018 15:26:56 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.53 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=CUfgcA2foVF68I+6bbQG+I5P6I+RV/GKq3qFtasSazM=; b=XxCZ1mVu25SzEYStB70W5mr5o0yVDnjWNkYB/qJwQxO6THwwzQ/wWS72pmk4CzaHCK YJxZuuknCmhsGUH09IpZkBzqh7ubV3yodep0l5SWE8im1Ij2ocbO85mFs4uGelc8cO5l SUl3tIRkmblxlbN/yayLYUm0r1hCc7GRqw9GY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=CUfgcA2foVF68I+6bbQG+I5P6I+RV/GKq3qFtasSazM=; b=fHWhIkXL8wA4OB6u+vBefaS1Lt2y7gmDTYdhdzBqLNWfGrN9bgYSIfNyTHTMeTbjKH HNXiRFEt07ZcajvnnqckCY+G+8QKE5lNXs/dxr+M8FlK6LeN/XlwCbq2Zd7cT9Fc7bQG CAIFLK3earLGhiWAY1cuMGhUhYTwEMWBd8zn4I4i96zTddbLAx56Tw0E3xOCdLNplsZ7 9QMPWASVf+52fZJTviwEvUPQrYDiddNEYYm335CXynXfKDOcW5X0LwbsN5NQc6bXIXj0 lya6lfMJD6WCMpggVe5X05sphOy4S62gjb+gMCHwE1OBPKADysHdQ792dQRG56Un8C8f NhaA== X-Gm-Message-State: AKwxyteIngiG0wvniNKS5EsTBnrsBa4gsrHEoIbWKvu4qWfblwdbYGLh FvrYIJPO8D5wz2doJnizfqIYhFUD2og= X-Google-Smtp-Source: AH8x226N2U7nkMpFu9YuyCP000hFI34gO6mJeBMiqvjsfesvBUZabZ9ftnUAaz5zrXfS6iU+EYJSlg== X-Received: by 2002:a17:902:9306:: with SMTP id bc6-v6mr9383899plb.29.1516836414951; Wed, 24 Jan 2018 15:26:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:58 -0800 Message-Id: <20180124232625.30105-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 18/45] target/hppa: Implement external interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/cpu.c | 6 +++++ target/hppa/int_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/translate.c | 16 ++++++++++++- 5 files changed, 83 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c7a2fb5b20..fc3e62c0af 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -340,6 +340,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int midx); #else int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t); +extern const MemoryRegionOps hppa_io_eir_ops; #endif =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 79d22ae486..535f086ab4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,5 +80,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env= , i64, i64, i64) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2970afd58d..888a48f16d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -57,6 +57,11 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, T= ranslationBlock *tb) cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 +static bool hppa_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach =3D bfd_mach_hppa20; @@ -159,6 +164,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) dc->realize =3D hppa_cpu_realizefn; =20 cc->class_by_name =3D hppa_cpu_class_by_name; + cc->has_work =3D hppa_cpu_has_work; cc->do_interrupt =3D hppa_cpu_do_interrupt; cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 5ae5233a96..249e14a2a1 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -24,6 +24,65 @@ #include "exec/helper-proto.h" #include "qom/cpu.h" =20 +#ifndef CONFIG_USER_ONLY +static void eval_interrupt(HPPACPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus + * can write to this word to raise an external interrupt on the target CPU. + * This includes the system controler (DINO) for regular devices, or + * another CPU for SMP interprocessor interrupts. + */ +static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) +{ + HPPACPU *cpu =3D opaque; + + /* ??? What does a read of this register over the GSC bus do? */ + return cpu->env.cr[CR_EIRR]; +} + +static void io_eir_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + HPPACPU *cpu =3D opaque; + int le_bit =3D ~data & (TARGET_REGISTER_BITS - 1); + + cpu->env.cr[CR_EIRR] |=3D (target_ureg)1 << le_bit; + eval_interrupt(cpu); +} + +const MemoryRegionOps hppa_io_eir_ops =3D { + .read =3D io_eir_read, + .write =3D io_eir_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIRR] &=3D ~val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} + +void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIEM] =3D val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} +#endif /* !CONFIG_USER_ONLY */ =20 void hppa_cpu_do_interrupt(CPUState *cs) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 44abc9006b..d6c65f314b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2124,12 +2124,25 @@ static DisasJumpType trans_mtctl(DisasContext *ctx,= uint32_t insn, /* All other control registers are privileged or read-only. */ CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); =20 +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + DisasJumpType ret =3D DISAS_NEXT; + nullify_over(ctx); switch (ctl) { case CR_IT: /* ??? modify interval timer offset */ break; =20 + case CR_EIRR: + gen_helper_write_eirr(cpu_env, reg); + break; + case CR_EIEM: + gen_helper_write_eiem(cpu_env, reg); + ret =3D DISAS_IAQ_N_STALE_EXIT; + break; + case CR_IIASQ: case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ @@ -2146,7 +2159,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, u= int32_t insn, tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); break; } - return nullify_end(ctx, DISAS_NEXT); + return nullify_end(ctx, ret); +#endif } =20 static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837937063987.3541963300453; Wed, 24 Jan 2018 15:52:17 -0800 (PST) Received: from localhost ([::1]:54995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUq0-00009c-Be for importer@patchew.org; Wed, 24 Jan 2018 18:52:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURX-0004gf-3S for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURV-0001tH-TD for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:59 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:41935) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURV-0001s9-LW for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:57 -0500 Received: by mail-pf0-x241.google.com with SMTP id c6so4359732pfi.8 for ; Wed, 24 Jan 2018 15:26:57 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=3QgQ3aTosAcrqniuf2FzQ9ncn1tfTZjIHIuTzT3AMPw=; b=B3Ud02GCV3RJw4F8OdHaNjP5U6ibt3T1t2Yh7dlPcbRJkKo2d+PjlGEfTm3p0Uz4nC seUOa1Mt4uaEVqaY3aTa2Xobv5hHkROKyeOcf6zYfRfEikXT9gOK6i0OsgCrgPhdA5LI bdQQbOBuXf0p2UzAiNmO0ejsxa1dFCbW+j2uM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=3QgQ3aTosAcrqniuf2FzQ9ncn1tfTZjIHIuTzT3AMPw=; b=c/cAbhB3tBPRa5eeKiEnz6QUKNIg2BEZI3Z1yitM3bS+Z14DYjcp76IXbIX+5GjjP0 mKhrEvRfPtBRXU8Vl0JT3AShKPysQl/F15X/DkDaTlT4Cghqr1SsS4QvpCtf08UxiPgg auTvgQXiEx3xxU2f93teg/GIhqpWwYktGZ8n4z1cw0MVH2gocoaPqJEpKA5kOFto4PQe xxck8RRN6ADDqESZ6IzjjpzIQCaacciQCDpDOwkFVSn8mcmnbmPQVMe7yiEDNLrIUaHm wIog5XvR0u4mShVTfH7GFUD11tl3FngJiVR3bec3rEn+cMT18Jl6ZSrwbKrqrQH6Got9 5vhQ== X-Gm-Message-State: AKwxytfA6smPp6Zd6/VzwJk7nccJewek0i4Q6GrOHKhZK08pc1CpFVvF WaQ7b1sP0dtSw78Hj6S/MXQnzB+JZqY= X-Google-Smtp-Source: AH8x2266wD8vt0g0lXv44EvSFy/4J+uhT8sErktVcQMwa1/azL2rslNllPuVg7NcZEhkaLEU2hJV4w== X-Received: by 2002:a17:902:7244:: with SMTP id c4-v6mr9965185pll.414.1516836416308; Wed, 24 Jan 2018 15:26:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:59 -0800 Message-Id: <20180124232625.30105-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 19/45] target/hppa: Implement the interval timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/helper.h | 3 +++ target/hppa/cpu.c | 8 ++++++++ target/hppa/int_helper.c | 6 ++++++ target/hppa/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++---- 6 files changed, 67 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fc3e62c0af..31a3702684 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -234,6 +234,7 @@ struct HPPACPU { /*< public >*/ =20 CPUHPPAState env; + QEMUTimer *alarm_timer; }; =20 static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) @@ -341,6 +342,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t); extern const MemoryRegionOps hppa_io_eir_ops; +void hppa_cpu_alarm_timer(void *); #endif =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 535f086ab4..744b11cb66 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -77,9 +77,12 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, en= v, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) + #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 888a48f16d..6be6eb0a7b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -99,6 +99,14 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error *= *errp) =20 qemu_init_vcpu(cs); acc->parent_realize(dev, errp); + +#ifndef CONFIG_USER_ONLY + { + HPPACPU *cpu =3D HPPA_CPU(cs); + cpu->alarm_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + hppa_cpu_alarm_timer, cpu); + } +#endif } =20 /* Sort hppabetically by type name. */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 249e14a2a1..d54d830196 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -67,6 +67,12 @@ const MemoryRegionOps hppa_io_eir_ops =3D { .impl.max_access_size =3D 4, }; =20 +void hppa_cpu_alarm_timer(void *opaque) +{ + /* Raise interrupt 0. */ + io_eir_write(opaque, 0, 0, 4); +} + void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIRR] &=3D ~val; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1963b2439b..6d19cab6c9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,8 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "qemu/timer.h" + =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { @@ -602,7 +604,41 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64= a, float64 b, float64 c) return ret; } =20 +target_ureg HELPER(read_interval_timer)(void) +{ +#ifdef CONFIG_USER_ONLY + /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. + Just pass through the host cpu clock ticks. */ + return cpu_get_host_ticks(); +#else + /* In system mode we have access to a decent high-resolution clock. + In order to make OS-level time accounting work with the cr16, + present it with a well-timed clock fixed at 250MHz. */ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; +#endif +} + #ifndef CONFIG_USER_ONLY +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +{ + HPPACPU *cpu =3D hppa_env_get_cpu(env); + uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + /* Even in 64-bit mode, the comparator is always 32-bit. But the + value we expose to the guest is 1/4 of the speed of the clock, + so moosh in 34 bits. */ + timeout =3D deposit64(current, 0, 34, (uint64_t)val << 2); + + /* If the mooshing puts the clock in the past, advance to next round. = */ + if (timeout < current + 1000) { + timeout +=3D 1ULL << 34; + } + + cpu->env.cr[CR_IT] =3D timeout; + timer_mod(cpu->alarm_timer, timeout); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw =3D env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d6c65f314b..1cd57f5a90 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2038,6 +2038,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, u= int32_t insn, unsigned rt =3D extract32(insn, 0, 5); unsigned ctl =3D extract32(insn, 21, 5); TCGv_reg tmp; + DisasJumpType ret; =20 switch (ctl) { case CR_SAR: @@ -2056,9 +2057,17 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, = uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, 0); /* FIXME */ + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + gen_helper_read_interval_timer(tmp); + gen_io_end(); + ret =3D DISAS_IAQ_N_STALE; + } else { + gen_helper_read_interval_timer(tmp); + ret =3D DISAS_NEXT; + } save_gpr(ctx, rt, tmp); - break; + return nullify_end(ctx, ret); case 26: case 27: break; @@ -2132,9 +2141,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, u= int32_t insn, nullify_over(ctx); switch (ctl) { case CR_IT: - /* ??? modify interval timer offset */ + gen_helper_write_interval_timer(cpu_env, reg); break; - case CR_EIRR: gen_helper_write_eirr(cpu_env, reg); break; --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838055155365.31283413772974; Wed, 24 Jan 2018 15:54:15 -0800 (PST) Received: from localhost ([::1]:55334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUrt-0001sp-Ub for importer@patchew.org; Wed, 24 Jan 2018 18:54:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURY-0004i4-5X for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURX-0001v7-De for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:00 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:39193) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURX-0001uf-7a for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:26:59 -0500 Received: by mail-pg0-x241.google.com with SMTP id w17so3810899pgv.6 for ; Wed, 24 Jan 2018 15:26:59 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=8fZcIG/WtHjKUCwfLG506MBVjMxOcPO/hwapVk47rEc=; b=JvXpamxVjpHOskLsndznwnnviS0kKgxDkRW7sotymUkUKxvcvs+ypMaoMSx3MO7fi+ WJ4njlMg4mU9aNqlIF0on7eRHP17CTfqyU1s7Us5n5GXCMnnjQKCvR/HPLO6K53uk8qx D/GYrE3cE729S1SEu/c71pGJiifTGuTdz6pf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8fZcIG/WtHjKUCwfLG506MBVjMxOcPO/hwapVk47rEc=; b=pEitbA26AXZ+naHLQULlw2TQZOQ7B2kG8ygti1KH1rNt0C5RpQJ8T14x6ok7IjeUfh IiBoRl2dbgrv6oQaWpZO7cvU9UFnI8/d5MD/w1TuYo3SqrKbd0faPjW25sv0AJGFgNek CwJSW6q/RqarjjMleReqQzRfX+Y02gIX5DcY3mI44IYXhovP+UxmQvwt/a9t1Yt8G0kz 9pDEia1ji/SG6eFIfeSzbAeEcO6jETTXdoWPdPh2HKFFhIm1cLHvVkBZVb+pY0HUsSNo 2bj0XsZrEPSSNUNbUjBIXb2gH8OzDIBywaRALInGWesfQCoYNCwIQvQf5D1c6krjZMtR jfSQ== X-Gm-Message-State: AKwxytfxMhIyxnLVwosil0yKzRu/TA2w3gSfCCd2cYeKKCsuvt1ZR4MT t54lB1wuGmyqhOvYLTHmGJje7GiEuqU= X-Google-Smtp-Source: AH8x226Dmg3VKYCWjMRc70UDX2cjMrjovpvyQCeEXjtr6aLUXrlL98vuyXx3YWAP3TcUH9DWXtldCA== X-Received: by 2002:a17:902:581a:: with SMTP id m26-v6mr9404286pli.158.1516836417973; Wed, 24 Jan 2018 15:26:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:00 -0800 Message-Id: <20180124232625.30105-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 20/45] target/hppa: Log unimplemented instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1cd57f5a90..6288bb9f67 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4218,6 +4218,8 @@ static DisasJumpType translate_table_int(DisasContext= *ctx, uint32_t insn, return table[i].trans(ctx, insn, &table[i]); } } + qemu_log_mask(LOG_UNIMP, "UNIMP insn %08x @ " TARGET_FMT_lx "\n", + insn, ctx->base.pc_next); return gen_illegal(ctx); } =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838164052293.0862310059822; Wed, 24 Jan 2018 15:56:04 -0800 (PST) Received: from localhost ([::1]:55397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUtf-0003Lg-8p for importer@patchew.org; Wed, 24 Jan 2018 18:56:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51159) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURa-0004l3-Q4 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURZ-0001vn-8O for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:02 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:42713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURY-0001va-W5 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:01 -0500 Received: by mail-pf0-x244.google.com with SMTP id b25so4353424pfd.9 for ; Wed, 24 Jan 2018 15:27:00 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=35pGJnCLY/5W72jYPTV6lM+5a5u4ZQxV/aLV82wAQ+M=; b=Mbnq2Jn0pNbDE8WfTlfGyZB8d2fPlHjlGzbcibMm1Ja+4XU0m9VBbwVUKiOwmlER8b VrvnwhpLda1/1LdDH4wMjEXckt8GXYWbH+RxkFMVvov0Ku50peHnW9nDgt0VKGXVu45s so27TekwjMd/mjdoEhewxo+fNtJ1A0nSvfRs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=35pGJnCLY/5W72jYPTV6lM+5a5u4ZQxV/aLV82wAQ+M=; b=e2da6cn3AuMr0iF22yutvKW2lWVaBS2kxhnKf+bnDSHVytdaDIEOlXkkXhLls/DBCC JH2YH2va3kR/YOg2N869Mu6G48aIzgQ8A3apbgA81E33HmBPTePBEwU9MpuEYbXo/zbo Y/LYGL97bDWPEe5RVE83SY8qi6uAG0DMqm64iZOF8NxkhmRUQbIR0IE7WV+GeBHYw4jy bd21aX7TmPdT398ut6uJfaQiTuF0F+BIG+RDz88eC1VRsxqbhDrm9zXTY9213mVPrPje vyLAPIgwyF39IYqZaA9K6x3h4H8r0PV1HYMMOFEG5djfQJM2U6wXcKsccm9eYH94OZOY V7TQ== X-Gm-Message-State: AKwxytfkWKpc6fLh6aVQacE5JvBPbZz+iGof/YO24BK5QiClSSIiMyxY 5WvOQLxrEjERRArMhg7f6KdGU+8s00w= X-Google-Smtp-Source: AH8x224xgeMkhHf+Iei4vt2sY0RfwdN4bC6R3ZqwWUTo8bOkzOMAR5Pj+zsVZNyuWxjD171yIndVTQ== X-Received: by 2002:a17:902:be09:: with SMTP id r9-v6mr9599970pls.234.1516836419453; Wed, 24 Jan 2018 15:26:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:01 -0800 Message-Id: <20180124232625.30105-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 21/45] target/hppa: Implement I*TLBA and I*TLBP insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++++++= ++-- target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++-- 3 files changed, 132 insertions(+), 4 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 744b11cb66..d412093914 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,4 +86,6 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG,= void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 08ab19aacf..7c3c7d1415 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -42,13 +42,40 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env,= vaddr addr) =20 for (i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent =3D &env->tlb[i]; - if (ent->va_b <=3D addr && addr <=3D ent->va_e && ent->entry_valid= ) { + if (ent->va_b <=3D addr && addr <=3D ent->va_e) { return ent; } } return NULL; } =20 +static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) +{ + CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + unsigned i, n =3D 1 << (2 * ent->page_size); + uint64_t addr =3D ent->va_b; + + for (i =3D 0; i < n; ++i, addr +=3D TARGET_PAGE_SIZE) { + /* Do not flush MMU_PHYS_IDX. */ + tlb_flush_page_by_mmuidx(cs, addr, 0xf); + } + + memset(ent, 0, sizeof(*ent)); + ent->va_b =3D -1; +} + +static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) +{ + hppa_tlb_entry *ent; + uint32_t i =3D env->tlb_last; + + env->tlb_last =3D (i =3D=3D ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1); + ent =3D &env->tlb[i]; + + hppa_flush_tlb_ent(env, ent); + return ent; +} + int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t) { @@ -67,7 +94,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr ad= dr, int mmu_idx, =20 /* Find a valid tlb entry that matches the virtual address. */ ent =3D hppa_find_tlb(env, addr); - if (ent =3D=3D NULL) { + if (ent =3D=3D NULL || !ent->entry_valid) { phys =3D 0; prot =3D 0; ret =3D (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); @@ -194,4 +221,53 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType type, tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); } + +/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ +void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *empty =3D NULL; + int i; + + /* Zap any old entries covering ADDR; notice empty entries on the way.= */ + for (i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent =3D &env->tlb[i]; + if (!ent->entry_valid) { + empty =3D ent; + } else if (ent->va_b <=3D addr && addr <=3D ent->va_e) { + hppa_flush_tlb_ent(env, ent); + empty =3D ent; + } + } + + /* If we didn't see an empty entry, evict one. */ + if (empty =3D=3D NULL) { + empty =3D hppa_alloc_tlb_ent(env); + } + + /* Note that empty->entry_valid =3D=3D 0 already. */ + empty->va_b =3D addr & TARGET_PAGE_MASK; + empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; + empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; +} + +/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ +void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); + + if (unlikely(ent =3D=3D NULL || ent->entry_valid)) { + qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); + return; + } + + ent->access_id =3D extract32(reg, 1, 18); + ent->u =3D extract32(reg, 19, 1); + ent->ar_pl2 =3D extract32(reg, 20, 2); + ent->ar_pl1 =3D extract32(reg, 22, 2); + ent->ar_type =3D extract32(reg, 24, 3); + ent->b =3D extract32(reg, 27, 1); + ent->d =3D extract32(reg, 28, 1); + ent->t =3D extract32(reg, 29, 1); + ent->entry_valid =3D 1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6288bb9f67..c02d107041 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1344,7 +1344,10 @@ static DisasJumpType do_unit(DisasContext *ctx, unsi= gned rt, TCGv_reg in1, } =20 #ifndef CONFIG_USER_ONLY -/* Top 2 bits of the base register select sp[4-7]. */ +/* The "normal" usage is SP >=3D 0, wherein SP =3D=3D 0 selects the space + from the top 2 bits of the base register. There are a few system + instructions that have a 3-bit space specifier, for which SR0 is + not special. To handle this, pass ~SP. */ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) { TCGv_ptr ptr; @@ -1352,7 +1355,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int = sp, TCGv_reg base) TCGv_i64 spc; =20 if (sp !=3D 0) { - return cpu_sr[sp]; + if (sp < 0) { + sp =3D ~sp; + } + spc =3D get_temp_tl(ctx); + load_spr(ctx, spc, sp); + return spc; } =20 ptr =3D tcg_temp_new_ptr(); @@ -2355,6 +2363,42 @@ static DisasJumpType trans_probe(DisasContext *ctx, = uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } =20 +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned sp; + unsigned rr =3D extract32(insn, 16, 5); + unsigned rb =3D extract32(insn, 21, 5); + unsigned is_data =3D insn & 0x1000; + unsigned is_addr =3D insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs, reg; + + if (is_data) { + sp =3D extract32(insn, 14, 2); + } else { + sp =3D ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); + reg =3D load_gpr(ctx, rr); + if (is_addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + + /* Exit TB for ITLB change if mmu is enabled. This *should* not be + the case, since the OS TLB fill handler runs with mmu disabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_mem_mgmt[] =3D { { 0x04003280u, 0xfc003fffu, trans_nop }, /* fdc, disp */ { 0x04001280u, 0xfc003fffu, trans_nop }, /* fdc, index */ @@ -2371,6 +2415,12 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04002720u, 0xfc003fffu, trans_base_idx_mod }, /* pdc, base mod */ { 0x04001180u, 0xfc003fa0u, trans_probe }, /* probe */ { 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */ +#ifndef CONFIG_USER_ONLY + { 0x04000000u, 0xfc001fffu, trans_ixtlbx }, /* iitlbp */ + { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ + { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ + { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ +#endif }; =20 static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516836927038654.2596737205499; Wed, 24 Jan 2018 15:35:27 -0800 (PST) Received: from localhost ([::1]:54498 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUZi-0002Ud-81 for importer@patchew.org; Wed, 24 Jan 2018 18:35:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51188) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURf-0004qq-1h for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURa-0001wK-59 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:07 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:38591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURZ-0001w0-W1 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:02 -0500 Received: by mail-pg0-x242.google.com with SMTP id y27so3815289pgc.5 for ; Wed, 24 Jan 2018 15:27:01 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=syJ0GoJ+f8WMWrwcEiicvHb0HU1xqjyXCwDF8fegEPk=; b=RRSdKFHJ3KtTcB402j5FKgTcsTRSOxWgw6OnEq59VvujFKsp9wggmSMRf8wgFqiXtJ b3JoYb4NmTDiei0OPxEA5O14jdQrnzRtxks5Bb6oxb77Froz5D0WyaEwL8re+beuccrR MCfjzhBcdoNFpLzqKmhVI6iKR4h60wprXK4Jo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=syJ0GoJ+f8WMWrwcEiicvHb0HU1xqjyXCwDF8fegEPk=; b=iOeJed81MS6m0GHBe5Yl9Q45GSHN9XZ4LTBbF8fAsdNVK3Yddkj+F6dokStctbqotI igqbJsd6ni8frCrx8duIUv44xlYojYygyuK/ttHX3Y2nkcoleJIYZMbsoqA3tDOSBu16 Tu7uLXWe090zsRjBwWHeecZC5qA4Mzlnkyi45ZfBgxpUD+SZj36RbopeflOXLWjVjwab ARe7VxMhw1exsuhNAMgcju+YmWjzy7RaFWDfhTjIjZ8eDRPHxsfb6BAEGU8b25QsqRmz Og3YRs/q0SrkmsPjYSqIoKJLkapCK7jwzsxXYvhzufcoRPbym4XoqVIvBqK9aQUIK6+C xJcQ== X-Gm-Message-State: AKwxytfJBdBM+GIqm76+iWXz0OuVRNZ3dFn8C80YqNlU8Drc8zx13OzF s8chIBaXxqzzLzz/xYW3uIxS1oaZKZc= X-Google-Smtp-Source: AH8x2248ynwvyjPJ5LOfQsamug66/31mxnX0+xMqz+7BbqnJEQn3RsMXOryDEz6J426hO0cAA/qljg== X-Received: by 10.99.127.24 with SMTP id a24mr11758319pgd.225.1516836420673; Wed, 24 Jan 2018 15:27:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:02 -0800 Message-Id: <20180124232625.30105-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 22/45] target/hppa: Implement P*TLB and P*TLBE insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index d412093914..f059ddf3b9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -88,4 +88,6 @@ DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env= , tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 7c3c7d1415..2835d890f2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -270,4 +270,41 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) ent->t =3D extract32(reg, 29, 1); ent->entry_valid =3D 1; } + +/* Purge (Insn/Data) TLB. This is explicitly page-based, and is + synchronous across all processors. */ +static void ptlb_work(CPUState *cpu, run_on_cpu_data data) +{ + CPUHPPAState *env =3D cpu->env_ptr; + target_ulong addr =3D (target_ulong) data.target_ptr; + hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); + + if (ent && ent->entry_valid) { + hppa_flush_tlb_ent(env, ent); + } +} + +void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) +{ + CPUState *src =3D CPU(hppa_env_get_cpu(env)); + CPUState *cpu; + run_on_cpu_data data =3D RUN_ON_CPU_TARGET_PTR(addr); + + CPU_FOREACH(cpu) { + if (cpu !=3D src) { + async_run_on_cpu(cpu, ptlb_work, data); + } + } + async_safe_run_on_cpu(src, ptlb_work, data); +} + +/* Purge (Insn/Data) TLB entry. This affects an implementation-defined + number of pages/entries (we choose all), and is local to the cpu. */ +void HELPER(ptlbe)(CPUHPPAState *env) +{ + CPUState *src =3D CPU(hppa_env_get_cpu(env)); + + memset(env->tlb, 0, sizeof(env->tlb)); + tlb_flush_by_mmuidx(src, 0xf); +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c02d107041..5b77688fc0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2397,6 +2397,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx,= uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned m =3D extract32(insn, 5, 1); + unsigned sp; + unsigned rx =3D extract32(insn, 16, 5); + unsigned rb =3D extract32(insn, 21, 5); + unsigned is_data =3D insn & 0x1000; + unsigned is_local =3D insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs; + + if (is_data) { + sp =3D extract32(insn, 14, 2); + } else { + sp =3D ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false); + if (m) { + save_gpr(ctx, rb, ofs); + } + if (is_local) { + gen_helper_ptlbe(cpu_env); + } else { + gen_helper_ptlb(cpu_env, addr); + } + + /* Exit TB for TLB change if mmu is enabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_mem_mgmt[] =3D { @@ -2420,6 +2456,10 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ + { 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */ + { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ + { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ + { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ #endif }; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837789866877.362607727309; Wed, 24 Jan 2018 15:49:49 -0800 (PST) Received: from localhost ([::1]:54615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUnd-0006Q8-5K for importer@patchew.org; Wed, 24 Jan 2018 18:49:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURf-0004qp-0y for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURb-0001ws-E7 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:07 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:41704) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURb-0001wV-8G for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:03 -0500 Received: by mail-pg0-x242.google.com with SMTP id 136so3810326pgd.8 for ; Wed, 24 Jan 2018 15:27:03 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=TlXxIZoHiIplbDXZZDFycXiOKS9HrTW99ifnkcnfjHA=; b=NHSKrktJmIn5wDCzWlD4S32jj54CErVPuQzsBD2fPNAZf5tQe6HM0hm/DvfxUadMZ4 NJFy0kI0t2AV8pX5Jv46sx0eTvbJ7Gh5yOiC/bK8trWNkKz5EP9g506Sa0fypbH7uXvs ncNOzIr1pU8tv6LPH9r3+5qF9eZ3UeuZT5Vo8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=TlXxIZoHiIplbDXZZDFycXiOKS9HrTW99ifnkcnfjHA=; b=AkP/LY5hrBXpFkKQPoHGnsotEWYIThaKC1T63X1u8Zu4D7wNy1s4DsjpA8Q8vhq7+0 RYljxXgVVCFMu3ldu8It7vhDKaL0ZBrSW0WFkBpBzAT+9dO/EFJTyAFeLrv2ajpETpyt bWwvWRej9x14GocNoo9BzYphySH/GtTeeiz/IcwzjmZPIMien/t0P+fIDbTssWsHSDw4 hqVf6R/M3mtxGjUpPfWlSi5xHYdPsJ3Q05ScKjrNM+Vvg8LW65LKuF8kubKXOBdk22T0 VYltJ9Ubmjm0oFYSv2cdW5PzUK1KJWVGIUmGaup04CgHCSuacP6Q/sDtpmngHX2QeaKO Obqg== X-Gm-Message-State: AKwxytezEe0uAScPTgx/V9YeU9knPEWN41ivv5RYX3HCt6r8vHPcrMBc S1EJ/4cjmWlJrOIKd3ZjKTXtbejSF6w= X-Google-Smtp-Source: AH8x224WZxdt3GjkuYF6gSUWFvPXzj5RaXpPS8pLVHgxupS6N3SGrgyItwFFQIZjc6WQ0Bwb0e9phA== X-Received: by 2002:a17:902:2823:: with SMTP id e32-v6mr7419512plb.44.1516836422003; Wed, 24 Jan 2018 15:27:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:03 -0800 Message-Id: <20180124232625.30105-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 23/45] target/hppa: Implement LDWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b77688fc0..3d441ef4ac 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2954,12 +2954,50 @@ static DisasJumpType trans_stby(DisasContext *ctx, = uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } =20 +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ldwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx =3D ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx =3D MMU_PHYS_IDX; + ret =3D trans_ld_idx_i(ctx, insn, di); + ctx->mmu_idx =3D hold_mmu_idx; + return ret; +} + +static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx =3D ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx =3D MMU_PHYS_IDX; + ret =3D trans_ld_idx_x(ctx, insn, di); + ctx->mmu_idx =3D hold_mmu_idx; + return ret; +} +#endif + static const DisasInsn table_index_mem[] =3D { { 0x0c001000u, 0xfc001300, trans_ld_idx_i }, /* LD[BHWD], im */ { 0x0c000000u, 0xfc001300, trans_ld_idx_x }, /* LD[BHWD], rx */ { 0x0c001200u, 0xfc001300, trans_st_idx_i }, /* ST[BHWD] */ { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, +#ifndef CONFIG_USER_ONLY + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ +#endif }; =20 static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837056434479.4094520906377; Wed, 24 Jan 2018 15:37:36 -0800 (PST) Received: from localhost ([::1]:54518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUbj-0004Ey-FD for importer@patchew.org; Wed, 24 Jan 2018 18:37:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURg-0004qt-7Z for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURe-0001xu-RQ for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:08 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:42674) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURe-0001xd-Iw for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:06 -0500 Received: by mail-pg0-x244.google.com with SMTP id q67so3809276pga.9 for ; Wed, 24 Jan 2018 15:27:06 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=l90A/DY5v8SNLXxNLjiu4jsgTj01n2M44ta48kw+zYE=; b=UchfsvBqej7XmP1Uj4dsEX+OBvdelsZWAA8alJibtJvDSnCRLZTOwke3WhTCAowZJ1 ZbZsUtk/g7+uIWbZaoF7PjFGRXJqMjkk1uIa4xgqIcECZokcMMA4b4PtyHPeOnkB0rRG E13VUkY5BgpAM7e9jijdWZTByDAhPKGLSv8R4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=l90A/DY5v8SNLXxNLjiu4jsgTj01n2M44ta48kw+zYE=; b=DAFr7cwysWBG6277kwAdwH7YwPIrB13GN3WM0UPGqBFKI2zD8F3v2D6h0LTcezt0tB o+5aFqh48rIqv5MtIz/hrp5yDhjT/ygBRlI/xxHPCtoc+0GzM2EJs9/hgOTYR1gVjfPV 6IH0xQl+puhfxHFqn2F7kTXSaquc8/lE2HzhhGQXeqKcJp824OM6rcEhCtTC04pjsrbJ adqZpyLN42N7kYNvN00uXGnijHvqDtmpAJVIgLTE+5RlzO++QgIp/7pgFL1W1OJgUK01 rPqssuAX+k2P1/m5ji0CTwIjriQ5AJwK+IzQXLHgHXiLn8v1zcLLHKggGbWAo5yGIRUH MpPg== X-Gm-Message-State: AKwxytfB9lo+AYtg8+QAFfxGbKnKszXfHWiEDeOtQQMN/6HvlhOukgHW L9UB6o++e+VXq5Zq99rtRW1KayxjaUQ= X-Google-Smtp-Source: AH8x224cRavDW8s8J6/YCWvWn0US2OVOLxSSgcvsXYA8XsFl0W1UsSWrWXROq8InrjDUCFtVbxdHNQ== X-Received: by 2002:a17:902:62:: with SMTP id 89-v6mr9284626pla.284.1516836425305; Wed, 24 Jan 2018 15:27:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:04 -0800 Message-Id: <20180124232625.30105-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 24/45] target/hppa: Implement LPA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 21 +++++++++++++++++++++ target/hppa/op_helper.c | 10 +++++----- target/hppa/translate.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 58 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 31a3702684..a6e4091b6a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -344,5 +344,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; void hppa_cpu_alarm_timer(void *); #endif +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra); =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index f059ddf3b9..1e733b7926 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -90,4 +90,5 @@ DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl,= tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2835d890f2..fbe2e19d5d 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -307,4 +307,25 @@ void HELPER(ptlbe)(CPUHPPAState *env) memset(env->tlb, 0, sizeof(env->tlb)); tlb_flush_by_mmuidx(src, 0xf); } + +target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) +{ + hwaddr phys; + int prot, excp; + + excp =3D hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + if (excp >=3D 0) { + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] =3D addr; + env->cr[CR_ISR] =3D addr >> 32; + } + if (excp =3D=3D EXCP_DTLB_MISS) { + excp =3D EXCP_NA_DTLB_MISS; + } + hppa_dynamic_excp(env, excp, GETPC()); + } + return phys; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6d19cab6c9..d270f94e31 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -34,7 +34,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int ex= cp) cpu_loop_exit(cs); } =20 -static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t r= a) +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra) { HPPACPU *cpu =3D hppa_env_get_cpu(env); CPUState *cs =3D CPU(cpu); @@ -46,14 +46,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, in= t excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { if (unlikely((target_sreg)cond < 0)) { - dynexcp(env, EXCP_OVERFLOW, GETPC()); + hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); } } =20 void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_COND, GETPC()); + hppa_dynamic_excp(env, EXCP_COND, GETPC()); } } =20 @@ -237,7 +237,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t = ra) env->fr[0] =3D (uint64_t)shadow << 32; =20 if (hard_exp & shadow) { - dynexcp(env, EXCP_ASSIST, ra); + hppa_dynamic_excp(env, EXCP_ASSIST, ra); } } =20 @@ -645,7 +645,7 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env,= target_ureg nsm) /* ??? On second reading this condition simply seems to be undefined rather than a diagnosed trap. */ if (nsm & ~psw & PSW_Q) { - dynexcp(env, EXCP_ILL, GETPC()); + hppa_dynamic_excp(env, EXCP_ILL, GETPC()); } env->psw =3D (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3d441ef4ac..082221f450 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2433,6 +2433,35 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx,= uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt =3D extract32(insn, 0, 5); + unsigned m =3D extract32(insn, 5, 1); + unsigned sp =3D extract32(insn, 14, 2); + unsigned rx =3D extract32(insn, 16, 5); + unsigned rb =3D extract32(insn, 21, 5); + TCGv_tl vaddr; + TCGv_reg ofs, paddr; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &vaddr, &ofs, rb, rx, 0, 0, sp, m, false); + + paddr =3D tcg_temp_new(); + gen_helper_lpa(paddr, cpu_env, vaddr); + + /* Note that physical address result overrides base modification. */ + if (m) { + save_gpr(ctx, rb, ofs); + } + save_gpr(ctx, rt, paddr); + tcg_temp_free(paddr); + + return nullify_end(ctx, DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_mem_mgmt[] =3D { @@ -2460,6 +2489,7 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ + { 0x04001340u, 0xfc003fc0u, trans_lpa }, #endif }; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837232335679.2546278604642; Wed, 24 Jan 2018 15:40:32 -0800 (PST) Received: from localhost ([::1]:54533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUeY-0006dB-7o for importer@patchew.org; Wed, 24 Jan 2018 18:40:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURg-0004qv-Vi for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURg-0001yU-3X for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:08 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:35172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURf-0001yB-V7 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:08 -0500 Received: by mail-pg0-x242.google.com with SMTP id o13so3818865pgs.2 for ; Wed, 24 Jan 2018 15:27:07 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=8xzSBqTDqbAsaks2scycjrLsfLpa0BF7CTKM2I7mUds=; b=FJEllaNASdWItq4Lnay5z+4iu9sx5JUOKbP7tasq2U+2sg/pC3dCML9bj7oa8JNtj5 355l6P/X78k7jjWk/NUDx3w5lkT9P5RV1V05fCuYSY2HZ2rf7JGmpS3ZTDOtDl9PMEMu v+bH7jYir4AWjsDjYlYs1UIYz+2vUH+HugApk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8xzSBqTDqbAsaks2scycjrLsfLpa0BF7CTKM2I7mUds=; b=NOq7V0zDZPNt3pQ/3dRnbI3A/+UM+DKXECfd579OKisbtpYNw/oh3Foo84lqAaBXNZ 6ZJ6aeeqTdlL4bTTNI1C9AD1JgjzyBTJ32ifPCem+cYbEeoWlFNLYPFuB9fRsTrbJCHW +gi9nWkd7XbYkWXsXZfPHYNFJf4YH+I+hBpzJwkueQG9xyslQdP1XE74l07oTMdnjeit z90/RUHbq98oE1DZnaG4wKjISf6gUbpzQYWp37LQPQfQrfci3JlGfhS6xWJSniKG61Uq CTkZXQeidqF1HPfF/NHnWCjx/QNOLRRylOfObfHPejyKbsuI4dVHmc4fevaG3OgSg9QG lyuA== X-Gm-Message-State: AKwxytcTG/a8/mPAdradDWDbEv2Co8EehtNX6Z+7QKLALJEpNMaOh4uI hxXZuVUtsVEJccaVdqhIyHJ8Fh/cse8= X-Google-Smtp-Source: AH8x227wcJoA9CheD6PGdgsyXoWuu5apBZA1qbpbnOH23yH81vxXCC44apgtUc6yQRMT4+nsXz91HA== X-Received: by 10.99.160.88 with SMTP id u24mr11811479pgn.122.1516836426718; Wed, 24 Jan 2018 15:27:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:05 -0800 Message-Id: <20180124232625.30105-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 25/45] target/hppa: Implement LCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 082221f450..41e28ff64c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2462,6 +2462,25 @@ static DisasJumpType trans_lpa(DisasContext *ctx, ui= nt32_t insn, =20 return nullify_end(ctx, DISAS_NEXT); } + +static DisasJumpType trans_lci(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt =3D extract32(insn, 0, 5); + TCGv_reg ci; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* The Coherence Index is an implementation-defined function of the + physical address. Two addresses with the same CI have a coherent + view of the cache. Our implementation is to return 0 for all, + since the entire address space is coherent. */ + ci =3D tcg_const_reg(0); + save_gpr(ctx, rt, ci); + tcg_temp_free(ci); + + return DISAS_NEXT; +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_mem_mgmt[] =3D { @@ -2490,6 +2509,7 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ { 0x04001340u, 0xfc003fc0u, trans_lpa }, + { 0x04001300u, 0xfc003fe0u, trans_lci }, #endif }; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837952734786.286759820537; Wed, 24 Jan 2018 15:52:32 -0800 (PST) Received: from localhost ([::1]:55058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUqG-0000Op-2C for importer@patchew.org; Wed, 24 Jan 2018 18:52:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURi-0004rX-1L for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURh-0001yv-B0 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:10 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:46215) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURh-0001yi-4n for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:09 -0500 Received: by mail-pg0-x243.google.com with SMTP id s9so3801844pgq.13 for ; Wed, 24 Jan 2018 15:27:09 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=xTWn9N9mXuKmrdgjJWIw2xv4sCHNU3rpymThFVTj1ak=; b=avyGF9xZfNmWxsLu75EoAOugWjqWP+i8Q+m4baXcpmGiKgD0OXX9o2WwWHNz5lFpWu i6862vu/939buF1oeXHVypmvz+5wSg+X4CpPIO1/JCTrnQbRggTNWaDHt/CbvSB+4hIB MPcw48tGDCfJSG4Mw49ANQayh6t4tAI7k+uJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=xTWn9N9mXuKmrdgjJWIw2xv4sCHNU3rpymThFVTj1ak=; b=dOKNoIlVDdfQTTOXdK8WDDVFj+1T+90Gdl6C9+lsOYDkdgcmIa9Hn0kBWE1Ck4HTgC 7SZBVtgPlhZxj1CIKwxOBm27YLsyil15mz1JRBzZcLvM8cF+q6Zi2evqyeRzDjKiZDTN EH+h6+IXw6F43NBuQlS6EdhQECBForD3OI/QKG54FQajLIf/AQK3MDukSgm1f5CAnpKw z9UEU7ajtHufT9XqS1CBDk2zsTREOsZrtFpJeLbtY7LbkFIB9nH8H+fBboXcq4TEIdwC ZyafBADoi4kkto74hfcRrmO+ogYVJRoQcUBtuN9wXM02ed+p4/Vpi90uP46FV+ltDCUi 1qRg== X-Gm-Message-State: AKwxytdIJVIrQvskAmh2KfYE+d8X6aSn62Ir1zB7Ll9kpESHTuzutsJt kfCIY6Zj9DVqH6COKQEPc6d9GBvEVVw= X-Google-Smtp-Source: AH8x226B2CR7nRse6JPy95z0QYbsHwwQ7gzEpSjX1zxLi604+tJaGtecW/LhFwWyToKRTphjwbdXGg== X-Received: by 10.98.211.204 with SMTP id z73mr14398236pfk.198.1516836427929; Wed, 24 Jan 2018 15:27:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:06 -0800 Message-Id: <20180124232625.30105-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 26/45] target/hppa: Implement SYNCDMA insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 41e28ff64c..f3942b1baf 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2312,7 +2312,8 @@ static const DisasInsn table_system[] =3D { { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, - { 0x00000400u, 0xffffffffu, trans_sync }, + { 0x00000400u, 0xffffffffu, trans_sync }, /* sync */ + { 0x00100400u, 0xffffffffu, trans_sync }, /* syncdma */ { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837105839618.9256091684422; Wed, 24 Jan 2018 15:38:25 -0800 (PST) Received: from localhost ([::1]:54521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUcb-0004xA-47 for importer@patchew.org; Wed, 24 Jan 2018 18:38:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURj-0004tX-VD for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURi-0001zR-Tn for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:11 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:46052) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURi-0001zE-N0 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:10 -0500 Received: by mail-pg0-x241.google.com with SMTP id m136so3804330pga.12 for ; Wed, 24 Jan 2018 15:27:10 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jz9a0SHM1j6sy0TDh85R+Hbc1trXnrF4FvsYuaL1xsE=; b=EmBIVCO8gjKaYgfgg0g9puZ4d5O7z4KpdGf9mjmS0TRMnPN7E4jAs9qbq7kHg8rYVa +4dEsjj+BawbKRu2AvcPmTcnZ9q55zV0txWjz4h5SUNPI0cCmEDKoua22TlxFHnUnEd6 ri90q9R2vi4/aRbo+px4d5wxD/97XmG7daOCE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jz9a0SHM1j6sy0TDh85R+Hbc1trXnrF4FvsYuaL1xsE=; b=NyrR/SzI0NJqvWlKOK7x5RcX1//WXyZ3WsWYLlsy71UzCWU1nl+oXyOoYdn02hrors IS0zU581G2cqggADLcQZ9990jMWym31EtKjyEsNzr3u/v+l19iyma3T/EKNbUYB6i0cN RH0WyCW4ELuyRqgf9b1bnVj1aVVlzKzINyc9v2y9FS3DdznACsakQvaN1AJQJHy6ce/E ILr7QxuiMccxW+9CEKL8PLokrI0RMnItS6Jgs/yT6sA14L0+cS6WVDSzRTTUOdDRpyZT gdP1H0dAQC6f6DtpmULo6DRYSnHwvXSfzTnkDCq1kTtHJf0NHdbpr1lEuDHBhhrKTuT+ emoQ== X-Gm-Message-State: AKwxytfxMAdqBCsqGYYxedJAHYnmil3trun13kM2fg9C5597roWK2qcQ ATZyRtPOR6Nxgj1M/i0NL7JmlOFdNfg= X-Google-Smtp-Source: AH8x227+YBsQuy8B8VEZBcEcFBVTakywpdaElABQ2cDlKCVjmzccAQDsrRlTaZ8YVdiR9CerZ+6nmQ== X-Received: by 2002:a17:902:6c41:: with SMTP id h1-v6mr9452126pln.25.1516836429418; Wed, 24 Jan 2018 15:27:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:07 -0800 Message-Id: <20180124232625.30105-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 27/45] target/hppa: Implement halt and reset instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Helge Deller Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 13 +++++++++++++ target/hppa/translate.c | 25 ++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1e733b7926..31320740da 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,6 +80,8 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env= , i64, i64, i64) DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) =20 #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(shutdown, noreturn, env) +DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d270f94e31..c2eeced0e9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "sysemu/sysemu.h" #include "qemu/timer.h" =20 =20 @@ -639,6 +640,18 @@ void HELPER(write_interval_timer)(CPUHPPAState *env, t= arget_ureg val) timer_mod(cpu->alarm_timer, timeout); } =20 +void HELPER(shutdown)(CPUHPPAState *env) +{ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + helper_excp(env, EXCP_HLT); +} + +void HELPER(reset)(CPUHPPAState *env) +{ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + helper_excp(env, EXCP_HLT); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw =3D env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f3942b1baf..8c1ae4db78 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2302,6 +2302,18 @@ static DisasJumpType trans_rfi(DisasContext *ctx, ui= nt32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_NORETURN); } + +static DisasJumpType gen_hlt(DisasContext *ctx, int reset) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + if (reset) { + gen_helper_reset(cpu_env); + } else { + gen_helper_shutdown(cpu_env); + } + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_system[] =3D { @@ -4519,7 +4531,18 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) case 0x15: /* unassigned */ case 0x1D: /* unassigned */ case 0x37: /* unassigned */ - case 0x3F: /* unassigned */ + break; + case 0x3F: +#ifndef CONFIG_USER_ONLY + /* Unassigned, but use as system-halt. */ + if (insn =3D=3D 0xfffdead0) { + return gen_hlt(ctx, 0); /* halt system */ + } + if (insn =3D=3D 0xfffdead1) { + return gen_hlt(ctx, 1); /* reset system */ + } +#endif + break; default: break; } --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838280767691.2017144652325; Wed, 24 Jan 2018 15:58:00 -0800 (PST) Received: from localhost ([::1]:55467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUvY-0004tG-2a for importer@patchew.org; Wed, 24 Jan 2018 18:58:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURl-0004vL-Hb for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURk-0001zu-Dm for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:13 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:39196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURk-0001zZ-5i for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:12 -0500 Received: by mail-pg0-x244.google.com with SMTP id w17so3811227pgv.6 for ; Wed, 24 Jan 2018 15:27:12 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=W1Ymh+4pKR0f40mVJ3TI2zd9pktGvqRjYsVLc8R5trk=; b=bFA0dOtjhb217eGh4AH7QdNUrfsXH8AUOkOjKhGdYbJdL/RgT7cGFdGWqyebEw6KTd ydTK100C0zn3P9qbumI84XYC9dCTVtZOyoTcYoLY2NzhsqY5ZFDlir4hjzoE5cdIpLEJ Y8Bx0Mi+fYUf+vUYGlCi+l77SWrIQBCsNN9uw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=W1Ymh+4pKR0f40mVJ3TI2zd9pktGvqRjYsVLc8R5trk=; b=mpU4sl0d9Mh48fw8yHd7ItXlt+4CXGUcTyacEUGga/XLRTnMT+WxwjZ9Nerd7ky5BT w6uLMTjZQK8oPHEdwUIr3JQRrKddy4ipNl9PGmGU2BMpz88V9eZOQIHaC4S76/i1tpa4 B0w+a/8AbNJyi3v+W3M70+SgksFVeDAmYgcBdyKK6vddPUf2YM/8jQiy9/fupCI0OxQl tn3TMOxVqyojtuBkgTKPoQzksOiXKi5tINraCMdsiel45+GkdfRMSeTbOAhbafvDX6TQ vJRrRK5vuUIsuK9sEtl78I6SxtWDJX5bfEjPGm0TOaZtssLoMBbdXTipWnLXojeKHAEu w2KA== X-Gm-Message-State: AKwxytdFlLqUXEX+3HmRv/Gz0+MRu+eHUGZas6b93R4GctYtKssAtF8j hAKOJ0I6BbGo+jLnwTwYJ+H69DOBGlg= X-Google-Smtp-Source: AH8x227WiUTDTWAFV7H50jI4hKQnGOxcKcaoElhNiutNfxPUCz6LJeD9bTjK8G6BWdZeax3OXyO99g== X-Received: by 10.98.205.72 with SMTP id o69mr11930138pfg.104.1516836430830; Wed, 24 Jan 2018 15:27:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:08 -0800 Message-Id: <20180124232625.30105-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 28/45] target/hppa: Optimize for flat addressing space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 11 ++++++++++- target/hppa/translate.c | 29 ++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a6e4091b6a..57e0bd6f0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -282,7 +282,11 @@ static inline target_ulong hppa_form_gva(CPUHPPAState = *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. + * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the + * same value. + */ +#define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, @@ -318,6 +322,11 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *= env, target_ulong *pc, *cs_base |=3D (uint32_t)diff; } } + if ((env->sr[4] =3D=3D env->sr[5]) + & (env->sr[4] =3D=3D env->sr[6]) + & (env->sr[4] =3D=3D env->sr[7])) { + flags |=3D TB_FLAG_SR_SAME; + } #endif =20 *pflags =3D flags; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8c1ae4db78..24d357889e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -284,6 +284,7 @@ typedef struct DisasContext { TCGLabel *null_lab; =20 uint32_t insn; + uint32_t tb_flags; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -323,6 +324,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; +static TCGv_i64 cpu_srH; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; @@ -360,8 +362,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; /* SR[4-7] are not global registers so that we can index them. */ - static const char sr_names[4][4] =3D { - "sr0", "sr1", "sr2", "sr3" + static const char sr_names[5][4] =3D { + "sr0", "sr1", "sr2", "sr3", "srH" }; =20 int i; @@ -377,6 +379,9 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, sr[i]), sr_names[i]); } + cpu_srH =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[4]), + sr_names[4]); =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; @@ -604,6 +609,8 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, = unsigned reg) #else if (reg < 4) { tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { + tcg_gen_mov_i64(dest, cpu_srH); } else { tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); } @@ -1362,6 +1369,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) load_spr(ctx, spc, sp); return spc; } + if (ctx->tb_flags & TB_FLAG_SR_SAME) { + return cpu_srH; + } =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); @@ -1405,7 +1415,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, #else TCGv_tl addr =3D get_temp_tl(ctx); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - if (ctx->base.tb->flags & PSW_W) { + if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); } if (!is_phys) { @@ -2112,6 +2122,7 @@ static DisasJumpType trans_mtsp(DisasContext *ctx, ui= nt32_t insn, =20 if (rs >=3D 4) { tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + ctx->tb_flags &=3D ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } @@ -2407,7 +2418,7 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, = uint32_t insn, =20 /* Exit TB for ITLB change if mmu is enabled. This *should* not be the case, since the OS TLB fill handler runs with mmu disabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } =20 @@ -2443,7 +2454,7 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, = uint32_t insn, } =20 /* Exit TB for TLB change if mmu is enabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } =20 @@ -4556,6 +4567,7 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, int bound; =20 ctx->cs =3D cs; + ctx->tb_flags =3D ctx->base.tb->flags; =20 #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_USER_IDX; @@ -4563,9 +4575,8 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, ctx->iaoq_f =3D ctx->base.pc_first; ctx->iaoq_b =3D ctx->base.tb->cs_base; #else - ctx->privilege =3D (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx =3D (ctx->base.tb->flags & PSW_D - ? ctx->privilege : MMU_PHYS_IDX); + ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; + ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); =20 /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base =3D ctx->base.tb->cs_base; @@ -4597,7 +4608,7 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase= , CPUState *cs) /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. = */ ctx->null_cond =3D cond_make_f(); ctx->psw_n_nonzero =3D false; - if (ctx->base.tb->flags & PSW_N) { + if (ctx->tb_flags & PSW_N) { ctx->null_cond.c =3D TCG_COND_ALWAYS; ctx->psw_n_nonzero =3D true; } --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838528840269.6210717830253; Wed, 24 Jan 2018 16:02:08 -0800 (PST) Received: from localhost ([::1]:55586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUzT-0007uB-Vu for importer@patchew.org; Wed, 24 Jan 2018 19:02:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURq-000504-If for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURl-00020L-Pt for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:18 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:34035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURl-000205-Ha for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:13 -0500 Received: by mail-pg0-x241.google.com with SMTP id r19so3821589pgn.1 for ; Wed, 24 Jan 2018 15:27:13 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=mOdt0qcyMnQWoblkB3DI4JREleHkAHQJdcCTlXCiOnM=; b=E43S/vqs1qzvpOeav3kdiJntqAdW+HAhJOqgfT2VmKOUKqt8M9+54LLUCzIoNidSo2 xhe1GzurfMDQnShHL9WCUSxn1Thefv2UFwJUfHl6zcyZQvsuKr0BDCbQ7jeXKFVg0WVV Ya8dIzmwCaN53c2iPw3V9BtBLobE791wVm6uo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=mOdt0qcyMnQWoblkB3DI4JREleHkAHQJdcCTlXCiOnM=; b=H9LIaCDLUZ3D7b+r9WbVRqaoYAbjM4h3W/9DPd87pVLGZa052Emh+x2k882hffAmNi EIprpkAOIcAY/uXHdrGVBZKWGMrlei6FAbVUUV+oCpioY9y8/yM+8m4LF2gWBbw7v7By OpVDk5yNEHfnldsnqtpVs9ahU7AUqxB1A6aLqQgYasW1UmG4InfGT8o18W0ukrymN+c8 paVPWcMWZaFZ26ltck8Xr9YI4bCmkl+JzBI7VryZVzP5ap6Z7qE8ECfWXBawT3dCRsz9 zJldlBS4y2sqkRhEuaEv57K9JPZ5c29lxhGpiY6QiVCCiVz5OLKTJmPicaQIwgJnPR4c Nb1w== X-Gm-Message-State: AKwxytfQvuFbGtLfzOQBhiQYCywLzmapzp48cxwEljAk5955asX5Pwzw t66RU4UWy9/tMLI5lOGGjjvYFoGGqp0= X-Google-Smtp-Source: AH8x225+jWewDb/ksPCIGav8nY9J5vpi7yQUaoml9E5efnaz80Uel7NwkH6Ep2gRvbGbmiG3OsNy8w== X-Received: by 2002:a17:902:bcc5:: with SMTP id o5-v6mr9682676pls.67.1516836432294; Wed, 24 Jan 2018 15:27:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:09 -0800 Message-Id: <20180124232625.30105-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 29/45] target/hppa: Add system registers to gdbstub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index fc27aec073..e2e9c4d77f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -41,15 +41,93 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *m= em_buf, int n) case 33: val =3D env->iaoq_f; break; + case 34: + val =3D env->iasq_f >> 32; + break; case 35: val =3D env->iaoq_b; break; + case 36: + val =3D env->iasq_b >> 32; + break; + case 37: + val =3D env->cr[CR_EIEM]; + break; + case 38: + val =3D env->cr[CR_IIR]; + break; + case 39: + val =3D env->cr[CR_ISR]; + break; + case 40: + val =3D env->cr[CR_IOR]; + break; + case 41: + val =3D env->cr[CR_IPSW]; + break; + case 43: + val =3D env->sr[4] >> 32; + break; + case 44: + val =3D env->sr[0] >> 32; + break; + case 45: + val =3D env->sr[1] >> 32; + break; + case 46: + val =3D env->sr[2] >> 32; + break; + case 47: + val =3D env->sr[3] >> 32; + break; + case 48: + val =3D env->sr[5] >> 32; + break; + case 49: + val =3D env->sr[6] >> 32; + break; + case 50: + val =3D env->sr[7] >> 32; + break; + case 51: + val =3D env->cr[CR_RC]; + break; + case 52: + val =3D env->cr[8]; + break; + case 53: + val =3D env->cr[9]; + break; + case 54: + val =3D env->cr[CR_SCRCCR]; + break; + case 55: + val =3D env->cr[12]; + break; + case 56: + val =3D env->cr[13]; + break; + case 57: + val =3D env->cr[24]; + break; + case 58: + val =3D env->cr[25]; + break; case 59: val =3D env->cr[26]; break; case 60: val =3D env->cr[27]; break; + case 61: + val =3D env->cr[28]; + break; + case 62: + val =3D env->cr[29]; + break; + case 63: + val =3D env->cr[30]; + break; case 64 ... 127: val =3D extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); break; @@ -94,15 +172,93 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) case 33: env->iaoq_f =3D val; break; + case 34: + env->iasq_f =3D (uint64_t)val << 32; + break; case 35: env->iaoq_b =3D val; break; + case 36: + env->iasq_b =3D (uint64_t)val << 32; + break; + case 37: + env->cr[CR_EIEM] =3D val; + break; + case 38: + env->cr[CR_IIR] =3D val; + break; + case 39: + env->cr[CR_ISR] =3D val; + break; + case 40: + env->cr[CR_IOR] =3D val; + break; + case 41: + env->cr[CR_IPSW] =3D val; + break; + case 43: + env->sr[4] =3D (uint64_t)val << 32; + break; + case 44: + env->sr[0] =3D (uint64_t)val << 32; + break; + case 45: + env->sr[1] =3D (uint64_t)val << 32; + break; + case 46: + env->sr[2] =3D (uint64_t)val << 32; + break; + case 47: + env->sr[3] =3D (uint64_t)val << 32; + break; + case 48: + env->sr[5] =3D (uint64_t)val << 32; + break; + case 49: + env->sr[6] =3D (uint64_t)val << 32; + break; + case 50: + env->sr[7] =3D (uint64_t)val << 32; + break; + case 51: + env->cr[CR_RC] =3D val; + break; + case 52: + env->cr[8] =3D val; + break; + case 53: + env->cr[9] =3D val; + break; + case 54: + env->cr[CR_SCRCCR] =3D val; + break; + case 55: + env->cr[12] =3D val; + break; + case 56: + env->cr[13] =3D val; + break; + case 57: + env->cr[24] =3D val; + break; + case 58: + env->cr[25] =3D val; + break; case 59: env->cr[26] =3D val; break; case 60: env->cr[27] =3D val; break; + case 61: + env->cr[28] =3D val; + break; + case 62: + env->cr[29] =3D val; + break; + case 63: + env->cr[30] =3D val; + break; case 64: env->fr[0] =3D deposit64(env->fr[0], 32, 32, val); cpu_hppa_loaded_fr0(env); --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838105747193.91809448408333; Wed, 24 Jan 2018 15:55:05 -0800 (PST) Received: from localhost ([::1]:55362 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUsi-0002bE-Sx for importer@patchew.org; Wed, 24 Jan 2018 18:55:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURq-000505-If for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURn-00021D-4a for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:18 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURm-00020d-TP for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:15 -0500 Received: by mail-pg0-x242.google.com with SMTP id r19so3821628pgn.1 for ; Wed, 24 Jan 2018 15:27:14 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=CGmoeVcqiAmOqDS89hTb5p7XLCN2XOrTKuUeMRPriRM=; b=LNL9Vl7HW//3lryp8GMIRP+rgxshhk7Um2VjAz9Sa4D2CrzH8FWZXtKIAJ/iYf0kt8 8XGbI7RYxG3dCoSR7I8r3/BLZy5+jHFeL6jUX9uJ7eUObXwDW9SOYxs20Yn2vcTCSjVD r7Uc8Q4LxnBIKyLpMjXEjTgzjCfhZhcoknKAw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=CGmoeVcqiAmOqDS89hTb5p7XLCN2XOrTKuUeMRPriRM=; b=nHWwYkFa7Gs7/25i9dPFSVDIkENNq8X9xZ0DJAWnDFmm/TArTlnX3ShNyiMcLtQ6Ov dHF6B3ZUKLGaAzwigskRWJ0E1OlPpUoHRVF2260eeJPRkAGgEak+iQc8e2n1aJMbwogX RwZwpZ726T2Ws0gKX/UhHtijcuZygZkhTkercahPlZNr2W1bwuRhut6Aa8iyqRWC41kN y7nNoQY4OECKjrGYLRp8WhCy34jBFc9jO9mG3z/Uh6MebW6BMPGtbhWafk/CSoUeyVQI mfTLq/BH+ZVjH7sojFttiuqmSS8PN/DeEKlJTJLmM2TMw7e1eaVpzCulrR6xwTSTycBv +zUg== X-Gm-Message-State: AKwxytd1k5OG8aNENaO8m5uwpW4qo/kBgNGSNbmQeCEFJdAmU7dKfIOx XOcIZnPRkX94f1WbfhLaSnyWstJd7U0= X-Google-Smtp-Source: AH8x226fijClibXKTadFZcScyv5Fx7kj8txGqoLEkQ0nRZoyiikMYuTQOmfFnYksxQx1hyPWRhh3Ig== X-Received: by 10.98.253.5 with SMTP id p5mr14415826pfh.132.1516836433587; Wed, 24 Jan 2018 15:27:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:10 -0800 Message-Id: <20180124232625.30105-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 30/45] target/hppa: Add migration for the cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/cpu.c | 1 + target/hppa/machine.c | 181 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/Makefile.objs | 1 + 4 files changed, 184 insertions(+) create mode 100644 target/hppa/machine.c diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 57e0bd6f0e..8a87b8a9b3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,6 +351,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t); extern const MemoryRegionOps hppa_io_eir_ops; +extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6be6eb0a7b..5213347720 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -184,6 +184,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; #else cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_hppa_cpu; #endif cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/hppa/machine.c b/target/hppa/machine.c new file mode 100644 index 0000000000..8e077788c3 --- /dev/null +++ b/target/hppa/machine.c @@ -0,0 +1,181 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "migration/cpu.h" + +#if TARGET_REGISTER_BITS =3D=3D 64 +#define qemu_put_betr qemu_put_be64 +#define qemu_get_betr qemu_get_be64 +#define VMSTATE_UINTTL_V(_f, _s, _v) \ + VMSTATE_UINT64_V(_f, _s, _v) +#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#else +#define qemu_put_betr qemu_put_be32 +#define qemu_get_betr qemu_get_be32 +#define VMSTATE_UINTTR_V(_f, _s, _v) \ + VMSTATE_UINT32_V(_f, _s, _v) +#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#endif + +#define VMSTATE_UINTTR(_f, _s) \ + VMSTATE_UINTTR_V(_f, _s, 0) +#define VMSTATE_UINTTR_ARRAY(_f, _s, _n) \ + VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, 0) + + +static int get_psw(QEMUFile *f, void *opaque, size_t size, VMStateField *f= ield) +{ + CPUHPPAState *env =3D opaque; + cpu_hppa_put_psw(env, qemu_get_betr(f)); + return 0; +} + +static int put_psw(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + CPUHPPAState *env =3D opaque; + qemu_put_betr(f, cpu_hppa_get_psw(env)); + return 0; +} + +static const VMStateInfo vmstate_psw =3D { + .name =3D "psw", + .get =3D get_psw, + .put =3D put_psw, +}; + +/* FIXME: Use the PA2.0 format, which is a superset of the PA1.1 format. = */ +static int get_tlb(QEMUFile *f, void *opaque, size_t size, VMStateField *f= ield) +{ + hppa_tlb_entry *ent =3D opaque; + uint32_t val; + + memset(ent, 0, sizeof(*ent)); + + ent->va_b =3D qemu_get_be64(f); + ent->pa =3D qemu_get_betr(f); + val =3D qemu_get_be32(f); + + ent->entry_valid =3D extract32(val, 0, 1); + ent->access_id =3D extract32(val, 1, 18); + ent->u =3D extract32(val, 19, 1); + ent->ar_pl2 =3D extract32(val, 20, 2); + ent->ar_pl1 =3D extract32(val, 22, 2); + ent->ar_type =3D extract32(val, 24, 3); + ent->b =3D extract32(val, 27, 1); + ent->d =3D extract32(val, 28, 1); + ent->t =3D extract32(val, 29, 1); + + ent->va_e =3D ent->va_b + TARGET_PAGE_SIZE - 1; + return 0; +} + +static int put_tlb(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + hppa_tlb_entry *ent =3D opaque; + uint32_t val =3D 0; + + if (ent->entry_valid) { + val =3D 1; + val =3D deposit32(val, 1, 18, ent->access_id); + val =3D deposit32(val, 19, 1, ent->u); + val =3D deposit32(val, 20, 2, ent->ar_pl2); + val =3D deposit32(val, 22, 2, ent->ar_pl1); + val =3D deposit32(val, 24, 3, ent->ar_type); + val =3D deposit32(val, 27, 1, ent->b); + val =3D deposit32(val, 28, 1, ent->d); + val =3D deposit32(val, 29, 1, ent->t); + } + + qemu_put_be64(f, ent->va_b); + qemu_put_betr(f, ent->pa); + qemu_put_be32(f, val); + return 0; +} + +static const VMStateInfo vmstate_tlb =3D { + .name =3D "tlb entry", + .get =3D get_tlb, + .put =3D put_tlb, +}; + +static VMStateField vmstate_env_fields[] =3D { + VMSTATE_UINTTR_ARRAY(gr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(fr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(sr, CPUHPPAState, 8), + VMSTATE_UINTTR_ARRAY(cr, CPUHPPAState, 32), + VMSTATE_UINTTR_ARRAY(cr_back, CPUHPPAState, 2), + VMSTATE_UINTTR_ARRAY(shadow, CPUHPPAState, 7), + + /* Save the architecture value of the psw, not the internally + expanded version. Since this architecture value does not + exist in memory to be stored, this requires a but of hoop + jumping. We want OFFSET=3D0 so that we effectively pass ENV + to the helper functions, and we need to fill in the name by + hand since there's no field of that name. */ + { + .name =3D "psw", + .version_id =3D 0, + .size =3D sizeof(uint64_t), + .info =3D &vmstate_psw, + .flags =3D VMS_SINGLE, + .offset =3D 0 + }, + + VMSTATE_UINTTR(iaoq_f, CPUHPPAState), + VMSTATE_UINTTR(iaoq_b, CPUHPPAState), + VMSTATE_UINT64(iasq_f, CPUHPPAState), + VMSTATE_UINT64(iasq_b, CPUHPPAState), + + VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + + VMSTATE_ARRAY(tlb, CPUHPPAState, ARRAY_SIZE(((CPUHPPAState *)0)->tlb), + 0, vmstate_tlb, hppa_tlb_entry), + VMSTATE_UINT32(tlb_last, CPUHPPAState), + + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_env =3D { + .name =3D "env", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D vmstate_env_fields, +}; + +static VMStateField vmstate_cpu_fields[] =3D { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, HPPACPU, 1, vmstate_env, CPUHPPAState), + VMSTATE_END_OF_LIST() +}; + +const VMStateDescription vmstate_hppa_cpu =3D { + .name =3D "cpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D vmstate_cpu_fields, +}; diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index dcd60a6839..3359da5341 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1,2 +1,3 @@ obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o obj-y +=3D int_helper.o +obj-$(CONFIG_SOFTMMU) +=3D machine.o --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837397481425.8063431336234; Wed, 24 Jan 2018 15:43:17 -0800 (PST) Received: from localhost ([::1]:54557 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUhI-0000fa-7o for importer@patchew.org; Wed, 24 Jan 2018 18:43:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURq-000503-Hq for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURo-00021g-FQ for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:18 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:39195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURo-00021P-9X for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:16 -0500 Received: by mail-pg0-x242.google.com with SMTP id w17so3811372pgv.6 for ; Wed, 24 Jan 2018 15:27:16 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=lvnCci7iV1I3qKNv3WOKkyQvm2uDS3zDbCwOpT7h1yY=; b=dQmhO3FboENTGOc1gntb7l3eGJ8x4YzMX9Dml8MP0LD8VJuv/QR21z5UOZtBbTHDrf nmZ6xz8wpX5xzkkMnNxtqNbPsKX0AjH1ScqXJtXyDpKkU5uKxYQXTPfkcuH6wMmJi+lb p7JrBxJJvrIl/h9fjPx9ol2wbqwbf3yvxPYPI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lvnCci7iV1I3qKNv3WOKkyQvm2uDS3zDbCwOpT7h1yY=; b=bnjG7xFUBTQW2akCncyfEGvCc3PphrfEQCS7IhM7tM4gz50VDZVMhEIZx+JOC1VCFd CtiC6aos0UsZyk6okYUcKNOaeKjwWoU1mIgWNCH70rcGMHCCvRS7SgEo9Om0N9jMUcOO ZBuVWXWPJ02a4Ab+GAw/kU+4ME4G35flAUtBGNrFCShJ+ujojDVfaDJFQFzwyr8uGHyo 1+0/YTMZKtaPGkWh5+BB2A+SibsQ2C/TaNZSPRiV2+rbG0+DuLiMnFq+M6/r5eUE051j 6C+zhr/L8FdcJO2OK0bzz+E2q3/rLFwUIi6Pi7hEXZFzNjRuhl+7NX6Airwsvkk0TuZo AAdw== X-Gm-Message-State: AKwxytfjmSIkxC/3lN/W//vmOmF0JdKSWBawhaItCrU8jVrH01rBPX/Z xKj69aoEuWcGchkSX3pk5Gr6m/KYv/g= X-Google-Smtp-Source: AH8x225jgOR+hbyGVNaShlT75HV5SUEpNgE8C1Gg/e2tGcrnTWUiTV+1Ag0Vutb8ypHiIXM3ooBK5A== X-Received: by 10.98.42.79 with SMTP id q76mr11209874pfq.23.1516836435037; Wed, 24 Jan 2018 15:27:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:11 -0800 Message-Id: <20180124232625.30105-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 31/45] target/hppa: Implement B,GATE insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 8 ++++++++ target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 57 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8a87b8a9b3..79763b254c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -353,6 +353,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra); =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index fbe2e19d5d..c14317ebef 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -123,6 +123,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, break; default: /* execute: promote to privilege level type & 3 */ prot =3D x_prot; + break; } =20 /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. = */ @@ -328,4 +329,11 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulon= g addr) } return phys; } + +/* Return the ar_type of the TLB at VADDR, or -1. */ +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) +{ + hppa_tlb_entry *ent =3D hppa_find_tlb(env, vaddr); + return ent ? ent->ar_type : -1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 24d357889e..5b7824f065 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3782,6 +3782,53 @@ static DisasJumpType trans_bl(DisasContext *ctx, uin= t32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } =20 +static DisasJumpType trans_b_gate(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned n =3D extract32(insn, 1, 1); + unsigned link =3D extract32(insn, 21, 5); + target_sreg disp =3D assemble_17(insn); + target_ureg dest =3D iaoq_dest(ctx, disp); + + /* Make sure the caller hasn't done something weird with the queue. + * ??? This is not quite the same as the PSW[B] bit, which would be + * expensive to track. Real hardware will trap for + * b gateway + * b gateway+4 (in delay slot of first branch) + * However, checking for a non-sequential instruction queue *will* + * diagnose the security hole + * b gateway + * b evil + * in which instructions at evil would run with increased privs. + */ + if (ctx->iaoq_b =3D=3D -1 || ctx->iaoq_b !=3D ctx->iaoq_f + 4) { + return gen_illegal(ctx); + } + +#ifndef CONFIG_USER_ONLY + if (ctx->tb_flags & PSW_C) { + CPUHPPAState *env =3D ctx->cs->env_ptr; + int type =3D hppa_artype_for_page(env, ctx->base.pc_next); + /* If we could not find a TLB entry, then we need to generate an + ITLB miss exception so the kernel will provide it. + The resulting TLB fill operation will invalidate this TB and + we will re-translate, at which point we *will* be able to find + the TLB entry and determine if this is in fact a gateway page. = */ + if (type < 0) { + return gen_excp(ctx, EXCP_ITLB_MISS); + } + /* No change for non-gateway pages or for priv decrease. */ + if (type >=3D 4 && type - 4 < ctx->privilege) { + dest =3D deposit32(dest, 0, 2, type - 4); + } + } else { + dest &=3D -4; /* priv =3D 0 */ + } +#endif + + return do_dbranch(ctx, dest, link, n); +} + static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -3860,6 +3907,7 @@ static const DisasInsn table_branch[] =3D { { 0xe8004000u, 0xfc00fffdu, trans_blr }, { 0xe800c000u, 0xfc00fffdu, trans_bv }, { 0xe800d000u, 0xfc00dffcu, trans_bve }, + { 0xe8002000u, 0xfc00e000u, trans_b_gate }, }; =20 static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837575431752.2780124529539; Wed, 24 Jan 2018 15:46:15 -0800 (PST) Received: from localhost ([::1]:54576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUjv-0003Bi-Tz for importer@patchew.org; Wed, 24 Jan 2018 18:46:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURq-00050L-OK for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURp-000229-SZ for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:18 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:35174) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURp-00021z-MP for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:17 -0500 Received: by mail-pg0-x244.google.com with SMTP id o13so3819202pgs.2 for ; Wed, 24 Jan 2018 15:27:17 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=LP9OHUOYoiZv6JPSNgAYHzOXuxtIZkBZc9DCBZ38R7g=; b=cczMHoANxL2ZJf3qiYCYKv+QXkaw3zb/v68CTfAnSObryxr3D48XkF/VUwdd82fpfy tXzGLn3OWQZCzDU9TUON+102jDW3M8axHfLW1oCoKZNO93gpao2slgDv3v3akzROT7pC jsRWKLO3sDm++fbIKdrsWD4ZZTCoOktqpFiuw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LP9OHUOYoiZv6JPSNgAYHzOXuxtIZkBZc9DCBZ38R7g=; b=W9//+HtJUIZ4sq9gI2XPH8MnnWMeWe/x3MDEZNHKgBsUzAY6K8zBWjJWtLkUPLeqB2 mqom3y/quppfysOEfgAcsMr1i42FqVu5rKvPy8Sg68m1+m7gRF50v66pOrLibcVl7utr iYZuPPxa8mf7j9/JS91d/2EknZKbwm7cV+saVAh0orm3HqmqG3zu8BWv06jhEeTlm2cQ 07sxDz9DhLI7wmySBaK73u2jPVBGEL/v0BmTo59fNlMQVZjP0bY9rOSw2yusfq2nVLIK fJphb8NYZvKyqe6rbsem7NKDd0W9Kr1neB42pXF0fw9/OAAJh4kjtbqnu04DzEu4kM03 B6Yw== X-Gm-Message-State: AKwxytc8VIMuyd/kc5+bDMmA12aHcw1iUCyHviU/d9NWrmL4l+OECYpK 0MaAYhsvDVOIFWCqcAHfuaw+jWAyoeI= X-Google-Smtp-Source: AH8x224ZrpP+0OZnPfnvlNZc3RYg9Q5Ccd4Nm7WmKEaFNg+UZCOly+5tQKCKAZECSHAkvUxKCx/qwA== X-Received: by 2002:a17:902:507:: with SMTP id 7-v6mr7968298plf.0.1516836436426; Wed, 24 Jan 2018 15:27:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:12 -0800 Message-Id: <20180124232625.30105-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 32/45] target/hppa: Only use EXCP_DTLB_MISS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c14317ebef..81bcbe45db 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -97,7 +97,9 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr ad= dr, int mmu_idx, if (ent =3D=3D NULL || !ent->entry_valid) { phys =3D 0; prot =3D 0; - ret =3D (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + /* ??? Unconditionally report data tlb miss, + even if this is an instruction fetch. */ + ret =3D EXCP_DTLB_MISS; goto egress; } =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838391206169.37071111888145; Wed, 24 Jan 2018 15:59:51 -0800 (PST) Received: from localhost ([::1]:55516 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUxK-0006DR-FY for importer@patchew.org; Wed, 24 Jan 2018 18:59:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURs-000512-7H for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURr-00022k-AK for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:20 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:42674) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURr-00022T-4T for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:19 -0500 Received: by mail-pg0-x242.google.com with SMTP id q67so3809701pga.9 for ; Wed, 24 Jan 2018 15:27:19 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xn4bhEwKxjI4xsJWxskbh4FNSmb1M37z+WdKtA6veJo=; b=DEghSbpF/OXnjX6M4T4dKm6VlYVd6rSWGo1BrfbCIfqKm+rcCMveG2M3fohA+JQlaQ VQpVVSqXBeElCO5bLB4/uyLRtPYRDg/VPL2oy+Ax89dN7o3Xil7wn1p1Y8nVSJpCNgIQ 6Cuz9ghue/aAc2gNp0mYibdVrQ3wHR1N+OAs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xn4bhEwKxjI4xsJWxskbh4FNSmb1M37z+WdKtA6veJo=; b=UmyeNNG31mSoTO+VU1zZyQ5MwXk18OL82l+GJ1vExy5J8eSBbuHEutQxOLrelLx0xr 6OA4ZxWMOhVz41W7wHVKWTuW0vbUBB/yuSt45TObW2qZpDytx6WiS+Sg2mPQZ997HK2J OEaFT9UM/L0Vgeu5dtYu7b/U7rZq0pNT1kRM7XiLd+SPKLBs7ZUaZouH8jOWed1Ra4D1 uG0MdCJk7HO74vhNU8O9COFgWY1KOqX+EWkeXpxsUfgCNwWEGDQikkEt2rUukyPJkdml lDm/5RTXeCm0DUNx3+F3+7SPJdG+vKj8RMZxYlu5cGY9Nqs+6MQyLmNlzDvm0E2q9YLV MBxQ== X-Gm-Message-State: AKwxytegqdjGnEgd30LWyCckyIqcYJe9+F9JVfhC/93+CI2iVx8WEEUL aeyoLOs4SuaM52h8AJytyv+wqKamHG0= X-Google-Smtp-Source: AH8x227iI16qZF/M+weFDJ3KEuK3OXefpw2INPLm5rL3LUiJXyj9u7l5j9zU+nfE7GonYJZJ7mvNQA== X-Received: by 2002:a17:902:b947:: with SMTP id h7-v6mr9523874pls.82.1516836437866; Wed, 24 Jan 2018 15:27:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:13 -0800 Message-Id: <20180124232625.30105-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 33/45] qom: Add MMU_DEBUG_LOAD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This lets us tell bottom levels of virtual memory translation routines that the access is from within QEMU itself and bypass certain tests. Cc: Andreas F=C3=A4rber Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 ++- target/sh4/op_helper.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 93bd546879..6367acca97 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -64,7 +64,8 @@ typedef uint64_t vaddr; typedef enum MMUAccessType { MMU_DATA_LOAD =3D 0, MMU_DATA_STORE =3D 1, - MMU_INST_FETCH =3D 2 + MMU_INST_FETCH =3D 2, + MMU_DEBUG_LOAD =3D 3 } MMUAccessType; =20 typedef struct CPUWatchpoint CPUWatchpoint; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index d798f239cf..8fa7cb6b42 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -36,6 +36,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, case MMU_DATA_STORE: cs->exception_index =3D 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838221813573.3039570611872; Wed, 24 Jan 2018 15:57:01 -0800 (PST) Received: from localhost ([::1]:55433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUuZ-00049L-60 for importer@patchew.org; Wed, 24 Jan 2018 18:56:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURt-000513-L7 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURs-00024i-NB for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:45854) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURs-00023f-H1 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:20 -0500 Received: by mail-pf0-x243.google.com with SMTP id a88so4351197pfe.12 for ; Wed, 24 Jan 2018 15:27:20 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=N3yFY3KLuN7s5EJ+56CkqrbPrG+d6aGgbHxBlCsk0dI=; b=Kwoc938aukh84nXcM0ZPKBJXC+l+NX8hQZq4L0Q/1XEvZf74IoLpYscSNjgoiD+pL0 o9j4CRnysFUU1hubbN7A3ys2D2OhdKDhRoL51ZbYSuVALz/S17itvgScKfCUvjadxitd IbCBcm6YbTJFZWwyTTEu+X/wVKfmms2a7q2Aw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=N3yFY3KLuN7s5EJ+56CkqrbPrG+d6aGgbHxBlCsk0dI=; b=K/hU/tv5oGEY+BBH/DzLip/ZVpacmJ4+OU4wTyflul35OWa2lGb0MUEggRJhXlUJLo aOTDzwZZPB04JLYfi4uLT+ouFZuA29JP+u1G3ZXRPrwHLQEyfRmUSM8NrcPjrCL616i3 DUYs2oOQds3qUp5HzyERjEfem8ZdboFoA/vT4qTLj4nWbrgLjddzSDRNawcap2+LnmDA C7Jo2gpZXiobzYaOzTXwLgLnwJsiXI9s9diGF27fy1hZ5HScZqBTgHiq7LQXQ2ck48xd U6rCY0cviVMv+rncKAY/wmndSDvYr9dPi8mezIA3g4bK8CYNNpsCmxX+JLGZHXKtcYjA kpHQ== X-Gm-Message-State: AKwxyteiia1UhBPMseHHMI/Ayp/JQrzhrZp6PBTziGvccEBBcc+mmouJ eqCt5L49mClHnBFUU2nChDs4eWZMxzA= X-Google-Smtp-Source: AH8x2254CAjWbypU5lFXmq8jFym3RvpyhzVsKvAYsFmfUBBZUzGKLMkDHGcw0YKgC2AnpDv3pYspIQ== X-Received: by 2002:a17:902:4c88:: with SMTP id b8-v6mr7853207ple.233.1516836439313; Wed, 24 Jan 2018 15:27:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:14 -0800 Message-Id: <20180124232625.30105-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 34/45] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Bypass any tlb protection checks, as this is not a "real" access to memory per the architecture. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index d54d830196..1a9bbe268a 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -156,7 +156,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) =20 vaddr =3D hppa_form_gva_psw(old_psw, iasq_f, vaddr); t =3D hppa_get_physical_address(env, vaddr, 0, - MMU_INST_FETCH, + MMU_DEBUG_LOAD, &paddr, &prot); if (t >=3D 0) { /* We can't re-load the instruction. */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 81bcbe45db..4decfca407 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -131,12 +131,21 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. = */ =20 /* Map MMUAccessType to QEMU protection. */ - if (ifetch) { - a_prot =3D PROT_EXEC; - } else if (type =3D=3D MMU_DATA_STORE) { - a_prot =3D PROT_WRITE; - } else { + switch (type) { + case MMU_DATA_LOAD: a_prot =3D PROT_READ; + break; + case MMU_DATA_STORE: + a_prot =3D PROT_WRITE; + break; + case MMU_INST_FETCH: + a_prot =3D PROT_EXEC; + break; + case MMU_DEBUG_LOAD: + ret =3D -1; + goto egress; + default: + g_assert_not_reached(); } =20 if (unlikely(!(prot & a_prot))) { --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837275170275.16207119580633; Wed, 24 Jan 2018 15:41:15 -0800 (PST) Received: from localhost ([::1]:54541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUfK-0007Q9-Bd for importer@patchew.org; Wed, 24 Jan 2018 18:41:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51382) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURu-00052F-KF for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURt-00026c-UB for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:22 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURt-00025a-OQ for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:21 -0500 Received: by mail-pg0-x242.google.com with SMTP id k68so3820075pga.3 for ; Wed, 24 Jan 2018 15:27:21 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=4VkiwsHNT0XZNGRGb4PuM6QAQn0VXnbiBb9LBE57JCc=; b=Pgbr7gm6OBiqMaoSaoKGo4paAPwW5gzuP0/uX91QFLPsePLInHR4dV0nFamUZyUpDR MD8qbJPoWuC0ec2kuwYianeyyEUa3E5UUeHd006HshqwQf9Bg9cy6BcAAjfn8/zAihjL f09xt4wHuCN893qLM+V4D/nfPVOpTElcDoeCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4VkiwsHNT0XZNGRGb4PuM6QAQn0VXnbiBb9LBE57JCc=; b=fFiCNkTlM3HnjgIdP+Caft3zdJgdJZQU+1BvXeGeHtLJw+kbC6F1G9fMeeed8+4rnz zwjPaEHTgLOwE4a5lEtjD4sQVizK1a/6QO8BvDONQ+mdwCNTORsKivD5mk6kRS3gsn0Q F090AQBUeBi7U0xoZiVYRr4q6tNSam25yfB9h5V1tG2lh0OSkkyCdYFehAgoweR820aN PtbyxKqiN9ep5MkgJ2jZyPC6uAVqDDlTjxvDQcYAgFoe0N6cFfi2S9+c0nbjgxsFX8K0 hOKNQFuF1EP7hIAf1jjgwUaQ4x8SPuFxmqiplutkcC80DXjcTdiUE0SR51JIZuF2S4dV YVzA== X-Gm-Message-State: AKwxyteSFMCs4s4oIvGDwm/wR+EHbBFGkdnv1JyWu/trWwdcrbMUlzBo JkLjKm3X6T+gDmcZpFQNvh21iS9N/WA= X-Google-Smtp-Source: AH8x225y6qvvcHZ9c8WOHmbqA0i++NlSZCh+9vwYNxiBjKIrXBj1bYCFK7d6sgrR5Q12cutmbdXc7g== X-Received: by 2002:a17:902:be09:: with SMTP id r9-v6mr9600608pls.234.1516836440531; Wed, 24 Jan 2018 15:27:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:15 -0800 Message-Id: <20180124232625.30105-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 35/45] target/hppa: Increase number of temp regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b7824f065..a93e86c9e3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -277,7 +277,7 @@ typedef struct DisasContext { TCGv_reg iaoq_n_var; =20 int ntempr, ntempl; - TCGv_reg tempr[4]; + TCGv_reg tempr[8]; TCGv_tl templ[4]; =20 DisasCond null_cond; --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151683864839940.359984323546314; Wed, 24 Jan 2018 16:04:08 -0800 (PST) Received: from localhost ([::1]:55672 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeV1T-0000x0-N0 for importer@patchew.org; Wed, 24 Jan 2018 19:04:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeURw-00053o-1k for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURv-00027z-8c for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:24 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42675) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURv-000271-2P for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:23 -0500 Received: by mail-pg0-x243.google.com with SMTP id q67so3809805pga.9 for ; Wed, 24 Jan 2018 15:27:22 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yysuXyU8pp+OJW+iGbsJa3l0BlyzeKUmKw/ticbpINs=; b=NxO41voBlP6G1LHiNQdKK6h6n5x0t6PvroCjWyw0uWeS+oy3MfSGio+NGhCNwHMGTx wGeyxSjd4/pWNOuifNK1JxCexRIM/+5bvuF6eUzN6rLYxWjt9OhDopaNdpothVJkW3mi Cc4iMb2WKaH1vB8EEr4O7Dw3eDAwVT3L6OLEE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yysuXyU8pp+OJW+iGbsJa3l0BlyzeKUmKw/ticbpINs=; b=i1/+d6NNCxEf68SoJdjdIW7v7aEcR03xBX8tnBjKSC0SJz8C31MpbMrGd1oFxC8W8h rBv7WJGIqFGVZeygdaIWC65y7j6TFEQB4BTrgxytiPSXNzjiAKyKIHw14oxQO63IKYLD MxXZAzuWNxvZHmxX58nJMkwFSk70ioFltlbEo9Br5WaQynM7liBlu6S9q4pZiOUJ7e0v u4EMSz/DncGY+uabTRDvVk6l+HFvOpDFnGqfQ5sA/lJ3dwOULHymkq609YJLSaftkwFB V6n4nDlclqZV11+uN5N9eiH/DqeSTJUpaOTZGRoXf7i6wf7v85zvorOcYuKhIuEH19RY qqKw== X-Gm-Message-State: AKwxyteE4VxImYW0h/3aMSCoB1I68MciZjZaFMzK85oODgtPQ55pOg1l gqZ3/Zwcmlzn+owAE9+RQFG4YFDQXGA= X-Google-Smtp-Source: AH8x225KSxaYQp+z3kkmPSWMW1FkNCTjk9gqU7Hu6go/r/2yKs+pXQN4FMwZJ3O0H89G53ZXm9xZUA== X-Received: by 10.99.159.2 with SMTP id g2mr7213210pge.156.1516836441891; Wed, 24 Jan 2018 15:27:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:16 -0800 Message-Id: <20180124232625.30105-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 36/45] target/hppa: Fix comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a93e86c9e3..3327c085ff 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3193,7 +3193,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx,= uint32_t insn) /* FSTW without modification. */ return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: - /* LDW with modification. */ + /* STW with modification. */ return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838451976220.13455395583185; Wed, 24 Jan 2018 16:00:51 -0800 (PST) Received: from localhost ([::1]:55556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUyF-0006zL-PK for importer@patchew.org; Wed, 24 Jan 2018 19:00:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS1-00058z-19 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURx-0002BQ-51 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:43639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURw-0002AM-VR for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:25 -0500 Received: by mail-pf0-x244.google.com with SMTP id y26so4357787pfi.10 for ; Wed, 24 Jan 2018 15:27:24 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=riVkqWj2V4rUtQRTP3OOrzMkWn1EMy0FQkn8R9nvamI=; b=i+pKbjccPIpIHauu+7m4kx4p4RnILmCi6OZWz24xE1YAEzp4NQTxEwkTk8yygJo1bu IanN2f7Ne/J1b1oSe7oeQcbEAf6fjLVOkuTmnoUHGop1eJDqC1gx4HPw/tZChMSn9jtD nWV0rOi+Gm/sd4nC1WURSDIud06zjeqYxttXc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=riVkqWj2V4rUtQRTP3OOrzMkWn1EMy0FQkn8R9nvamI=; b=C3p3E20YxC6/lsTn9Shez8oLtwFTV4r13nXtTpWXha5a/zj9V/UZJ9PGsQ2ioTqYqm /idw/R+RWoBSnWJH7sLhZw7QvXLjUzU7abukEx1XihDgY5187NxwNk4ucdg1ywfCfEGq o7vvfJKljRRJfgOZDtBXoN25VT9icrk8b396xEqU6sxzfVq4ie7PNfyWq2tlKW+Fttu8 DLOv2Yfoi89zm3d1j/7Jnndkd5DmF98BZX7MUCGXwoInQ33aT2rE8/im4XrYiLPTqj9e LJlCKBqiXVHdeZXdv8AVO4Jep6Xdqp1MTiSGtpZayh2z4DNWXMnjKnVy+SNmIKjlc6zu a5Lg== X-Gm-Message-State: AKwxytcCvOKxozX0iFMofDw4XqA9pPCBFyF9RXF/Cs4jdornRvRlFlwD Dixk4Ia93f0HCDvkKhxC0BFRTuJjQsI= X-Google-Smtp-Source: AH8x225ftosszIxEniMtnnCR5FtXH897sCAMyonmdtzV+LJRXw5VpRtOX7weZa7fF7sdnrSRYTVt4A== X-Received: by 10.99.172.25 with SMTP id v25mr11810285pge.148.1516836443622; Wed, 24 Jan 2018 15:27:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:17 -0800 Message-Id: <20180124232625.30105-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 37/45] target/hppa: Implement LDSID for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3327c085ff..cf67ca026e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2211,8 +2211,20 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, = uint32_t insn, unsigned rt =3D extract32(insn, 0, 5); TCGv_reg dest =3D dest_gpr(ctx, rt); =20 - /* Since we don't implement space registers, this returns zero. */ +#ifdef CONFIG_USER_ONLY + /* We don't implement space registers in user mode. */ tcg_gen_movi_reg(dest, 0); +#else + unsigned rb =3D extract32(insn, 21, 5); + unsigned sp =3D extract32(insn, 14, 2); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + + tcg_gen_mov_i64(t0, space_select(ctx, sp, load_gpr(ctx, rb))); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(dest, t0); + + tcg_temp_free_i64(t0); +#endif save_gpr(ctx, rt, dest); =20 cond_free(&ctx->null_cond); --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151683876626914.190302447585282; Wed, 24 Jan 2018 16:06:06 -0800 (PST) Received: from localhost ([::1]:55989 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeV3I-0002MX-GT for importer@patchew.org; Wed, 24 Jan 2018 19:06:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS1-000590-1a for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURy-0002CD-Bf for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:43637) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURy-0002C0-5n for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:26 -0500 Received: by mail-pf0-x241.google.com with SMTP id y26so4357820pfi.10 for ; Wed, 24 Jan 2018 15:27:26 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.23 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=8Kg5OMBfw7BaLTAtWZSwfZCWdsar5dGHF70bimc73J4=; b=S0LFBqBBXm7exoaZHfottzreIpw98m0xcX3r8vjJEZusu1iW6+yWm4dRKoQGNzunh/ CI8uiS7sB/6uKJubLPFt4RP3Yx2zDs+5P0YxjsjTXnLV8Iuoy/fGEUILVeoIiDYOQC4s 6hVwXIbSDNEtvBlZOs4Q6G+2xDqSrVyOmRMlA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8Kg5OMBfw7BaLTAtWZSwfZCWdsar5dGHF70bimc73J4=; b=tWVrqEXe4XfNtf2/JWA8BaCWybYyME0xdw5Mic6SwUW/zcJ+rpj6U7LjIsqWluSPVy 1jzfSWlW9nRwYe4zUxSzqe44mY1PdzaP6co5kqB4iS5nJwgGa/OX3MuCnFQb4XWrcnb5 MVco7EF8oSIJiFfmGHk7Nd1vVqEn9MTePB1q57VpzWS1U/cKq8JEZcFUgMuXyhQgvl3P UV/17HUpQXeC0QdFJaLyVp0SUIYuMVK6IKtP97EhohbJyqURcgQX8zsnEpl/JvXlRKOB LjQ+T3piM5Fj/G8djg4m5Q26kRP3y8rGKNNGHNTBSJDvKY+IVDDOMgXgLRsnwc7QUEeT ectg== X-Gm-Message-State: AKwxytdAlJNTEzDSFdqRk4BPelqUNszk8Jd0qAWwtVt9PAVMvyEeKVbs ScRgcQ8hSZno242qay+hhH7zom8+bBI= X-Google-Smtp-Source: AH8x226KAtwN3DKSd76wFdM1RgoVkHQIsqK02KDAuPn7pG49gg0bsBVsKiGoLNV5Mn96gry0odeUoQ== X-Received: by 10.101.80.72 with SMTP id k8mr10865658pgo.361.1516836444905; Wed, 24 Jan 2018 15:27:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:18 -0800 Message-Id: <20180124232625.30105-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 38/45] target/hppa: Implement a pause instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cf67ca026e..d84090d479 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2826,9 +2826,45 @@ static DisasJumpType trans_ds(DisasContext *ctx, uin= t32_t insn, return nullify_end(ctx, DISAS_NEXT); } =20 +#ifndef CONFIG_USER_ONLY +/* These are QEMU extensions and are nops in the real architecture: + * + * or %r10,%r10,%r10 -- idle loop; wait for interrupt + * or %r31,%r31,%r31 -- death loop; offline cpu + * currently implemented as idle. + */ +static DisasJumpType trans_pause(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + TCGv_i32 tmp; + + /* No need to check for supervisor, as userland can only pause + until the next timer interrupt. */ + nullify_over(ctx); + + /* Advance the instruction queue. */ + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_set(ctx, 0); + + /* Tell the qemu main loop to halt until this cpu has work. */ + tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + gen_excp_1(EXCP_HALTED); + + return nullify_end(ctx, DISAS_NORETURN); +} +#endif + static const DisasInsn table_arith_log[] =3D { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ +#ifndef CONFIG_USER_ONLY + { 0x094a024au, 0xffffffffu, trans_pause }, /* or r10,r10,r10 */ + { 0x0bff025fu, 0xffffffffu, trans_pause }, /* or r31,r31,r31 */ +#endif { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_andc_reg }, { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_and_reg }, { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_or_reg }, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838337254383.8011919084752; Wed, 24 Jan 2018 15:58:57 -0800 (PST) Received: from localhost ([::1]:55489 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUwS-0005Wx-Kz for importer@patchew.org; Wed, 24 Jan 2018 18:58:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS1-000592-2B for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURz-0002Du-GU for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:44785) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURz-0002Cr-At for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:27 -0500 Received: by mail-pf0-x243.google.com with SMTP id m26so4356011pfj.11 for ; Wed, 24 Jan 2018 15:27:27 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=mAVHaLoUOgItDvWDmsq3JGoLZftVOaugLdkVZOQP1t4=; b=Z2pB/5JqIxul3w8lLFro71W4FXVWDkRFejIld6SZDJuSpbImEXCXpV0Nqfu4uBIfG3 ElrpZXIPZyi4olcJ+0DD171hpmHh/ua8qU1u68HnLpp0cFRqVM7lFQ9pN2UJEIjNyFOO rA5RnJVvK08wi92/H5FxGNsDIImjDR5FZAGjc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=mAVHaLoUOgItDvWDmsq3JGoLZftVOaugLdkVZOQP1t4=; b=ZpAP4NQaurzB+PCoYWB0FW3bBAP1P73Xbru5xobjkJLwHQeRi/lCKOdJCUEFSR7ELf QZfBAMzoTPusMjjTOjsk7sDWDVT4fBIPB4vbQSxMBFNBRt0mVs18w5CTlUaxBxaTBzqj hbUqVK/fCf3IJvcDieEc1NFsXVRYcw/auPji0zdXQcNcugkAFW1TD0O2O1tPvOq9BA/3 qcEG6//nk4eiPoRIFf2zAvI1pUjAcGnrHYNYeIcmQRoYqyOK52swgHGqQN9koofVZP7S RGd+sr0LoscFtxl9/setCDeI8YJJLpHiEqQ066CI2otOGI3SnPRZ6eGGWe2XT0/r3FnJ SAcg== X-Gm-Message-State: AKwxytdNmuJVhIbrMtiMlz0x7en5qER2TfKTpeU2RpZV6irb3esSvXHN GLyfW19rvRT/uXCOCd2DbJxq1eZ+ci4= X-Google-Smtp-Source: AH8x226Wxm3W7Qi8rVWP53r9nCPkjlmBbk1SMNWG5TwP6Gjls6zuZb/lxEqT4/VYktLw1SIc8QK6jA== X-Received: by 10.99.56.18 with SMTP id f18mr11621276pga.438.1516836446127; Wed, 24 Jan 2018 15:27:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:19 -0800 Message-Id: <20180124232625.30105-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 39/45] target/hppa: Implement STWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d84090d479..b9b097acc9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3108,6 +3108,22 @@ static DisasJumpType trans_ldwa_idx_x(DisasContext *= ctx, uint32_t insn, ctx->mmu_idx =3D hold_mmu_idx; return ret; } + +static DisasJumpType trans_stwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx =3D ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx =3D MMU_PHYS_IDX; + ret =3D trans_st_idx_i(ctx, insn, di); + ctx->mmu_idx =3D hold_mmu_idx; + return ret; +} #endif =20 static const DisasInsn table_index_mem[] =3D { @@ -3117,8 +3133,9 @@ static const DisasInsn table_index_mem[] =3D { { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, #ifndef CONFIG_USER_ONLY - { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c001380u, 0xfc00d3c0, trans_stwa_idx_i }, /* STWA, im */ #endif }; =20 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837444068298.677626348947; Wed, 24 Jan 2018 15:44:04 -0800 (PST) Received: from localhost ([::1]:54559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUi3-0001OT-BL for importer@patchew.org; Wed, 24 Jan 2018 18:44:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS1-00059q-Rp for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUS0-0002Fi-VP for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:41938) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUS0-0002Es-Pt for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:28 -0500 Received: by mail-pf0-x241.google.com with SMTP id c6so4360608pfi.8 for ; Wed, 24 Jan 2018 15:27:28 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.26 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=quBtnarmfehsLQSA0SyAoxzs5iPyto2pNccU5OZX0IY=; b=RqkWvK6qR79zSncUHo6udiYXWdInOdlgKDUPc9hypmnEPBq8U3kXtXaP54mt/8XFv/ dDwn2yxiZhBG9Iv4YGVz7+TKhzwqtQRpnAkjOON0hMeIFO1nRbw9omiNFaQWrAFTJwyM PEJpwqGvCuSin3H02ZaXJp4TdEyOF+JtaTENE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=quBtnarmfehsLQSA0SyAoxzs5iPyto2pNccU5OZX0IY=; b=Oqggdi2R1+eHmivgLVGHjRHpiS5i36IiNqa6IozJZucZ+u2JVHly0L4SHEK2nqmzus BFAJYIo83iR9JlW9blG5mrzNpH//YlgXZHTN1fbhuIZupq+9VPIkCk3LByuigoVZ17Fl Grkk07hnbnQhEA8Czy9AswXvl2Ydq0DEVrs/Fx4uRwc2sezpRZ9qCv2nUhYZ64RyMAfo Yh3nyZfkzvcYXkyIsnq/akx3eRF23WHjMTHI4EUOShLyJbORzYcldvgWWMGYwzXK5akQ ojJ+i3rRy2h0sylhFp9EthBmLgApVWrmJKDU7VDYUv7FQb90F4XRX7OWqL5hvtWwx1VI xWVQ== X-Gm-Message-State: AKwxytcpg5kT/BCNPNvH+z6p9hdK8FDEBoJdcUKRqGJXnyN4IScCPu+U VIM+vlNENj99nJXfDt7ff5z32ZqOxKA= X-Google-Smtp-Source: AH8x2274xFoeaDReTfsJT3R0SHtHY9032fgC2tbncINY6NecQec/osO6feAG4xBTTjF1lPcbIek1IQ== X-Received: by 2002:a17:902:3124:: with SMTP id w33-v6mr9315436plb.356.1516836447535; Wed, 24 Jan 2018 15:27:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:20 -0800 Message-Id: <20180124232625.30105-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 40/45] target/hppa: Enable MTTCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 6 ++++++ configure | 1 + 2 files changed, 7 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 79763b254c..3df3ebd19d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif =20 +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState =20 #include "exec/cpu-defs.h" diff --git a/configure b/configure index 044c6fafe2..0046135db6 100755 --- a/configure +++ b/configure @@ -6549,6 +6549,7 @@ case "$target_name" in cris) ;; hppa) + mttcg=3D"yes" ;; lm32) ;; --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837738086287.8561595645881; Wed, 24 Jan 2018 15:48:58 -0800 (PST) Received: from localhost ([::1]:54613 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUmj-0005dN-Op for importer@patchew.org; Wed, 24 Jan 2018 18:48:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS6-0005F4-H4 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUS3-0002IF-8V for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:34 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:36261) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUS2-0002HU-Td for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:31 -0500 Received: by mail-pf0-x241.google.com with SMTP id 23so4373065pfp.3 for ; Wed, 24 Jan 2018 15:27:30 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HAkWzbNyq/NWf9wH76fUmDkbv9xXj9EHzXbveFbQb2k=; b=QYYX3emkrARNWWUaFywyTSId8HIFqOWszW8QkH+e7bI073TmiIrdVMollKCe0nZXiN AeOqW/b/J3/5ZbjBCEV6YDTG6/R6qpxl3JW/+54CZ24UqqA8zGs/JXUE4PRBOwlR0Rmx vBQMyLtf9We5RS3Y5i7CrzuiGH78taYiZHCg0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HAkWzbNyq/NWf9wH76fUmDkbv9xXj9EHzXbveFbQb2k=; b=CYab0AtIYj6ZqmCDXuU243evxubcAy9HGK5EV08D+UHu2G/5PXwogI1NVNUs6lfgA0 cNj1iTaese/MrRUQvMcAfh6gp5E6z3NKgu44TJ5CuYkMW9wNmtexl2Ud8ZinYZBVzeXw UviNS13xe69rS4DEOSe3d1+ovEVt6PpdrcRxN+iKMBrZU4/098ep6Ffqs7VLo2ef21SQ o9y3JtR6udoGZ7DKFp8HJPirJUG9GtzajtE5Jep3BCiW74At+UiisCXwXpE6lhKFSQ3A fDyIrDZpe3ASuOnR95RhTBmr7fPHxkJp0FrrPJ1/pgOvaUV7zqhq9YZqkiWpZElNjxy9 FYoQ== X-Gm-Message-State: AKwxytdJ4tR2mey03UAccg/WNatpywgNhM5/LVck+k//LZ3N1DY6sE18 wVRxh9JDDiA1Mk+YYGphYN+TmoodmU0= X-Google-Smtp-Source: AH8x22599kRr3aQ7Wbg8zKF7xQ/UjDLOFJIRDzisuPL3FZmxf30xSLrpdVRPw+jLXYTXWpJwe2B0jw== X-Received: by 2002:a17:902:68cb:: with SMTP id x11-v6mr9410773plm.198.1516836449077; Wed, 24 Jan 2018 15:27:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:21 -0800 Message-Id: <20180124232625.30105-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 41/45] hw/hppa: Implement DINO system board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Helge Deller Now that we have the prerequisites in target/hppa/, implement the hardware for a PA7100LC. This also enables build for hppa-softmmu. Signed-off-by: Helge Deller [rth: Since it is all new code, squashed all branch development withing hw/hppa/ to a single patch.] Signed-off-by: Richard Henderson --- Makefile.objs | 1 + hw/hppa/hppa_hardware.h | 40 +++ hw/hppa/hppa_sys.h | 24 ++ hw/hppa/dino.c | 518 +++++++++++++++++++++++++++++++++++= ++++ hw/hppa/machine.c | 246 ++++++++++++++++++- hw/hppa/pci.c | 90 +++++++ default-configs/hppa-softmmu.mak | 14 ++ hw/hppa/Makefile.objs | 2 +- hw/hppa/trace-events | 4 + 9 files changed, 937 insertions(+), 2 deletions(-) create mode 100644 hw/hppa/hppa_hardware.h create mode 100644 hw/hppa/hppa_sys.h create mode 100644 hw/hppa/dino.c create mode 100644 hw/hppa/pci.c create mode 100644 default-configs/hppa-softmmu.mak create mode 100644 hw/hppa/trace-events diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..c52925133a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -155,6 +155,7 @@ trace-events-subdirs +=3D hw/vfio trace-events-subdirs +=3D hw/acpi trace-events-subdirs +=3D hw/arm trace-events-subdirs +=3D hw/alpha +trace-events-subdirs +=3D hw/hppa trace-events-subdirs +=3D hw/xen trace-events-subdirs +=3D hw/ide trace-events-subdirs +=3D ui diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h new file mode 100644 index 0000000000..2c61b1f77c --- /dev/null +++ b/hw/hppa/hppa_hardware.h @@ -0,0 +1,40 @@ +/* HPPA cores and system support chips. */ + +#define FIRMWARE_START 0xf0000000 +#define FIRMWARE_END 0xf0800000 + +#define DEVICE_HPA_LEN 0x00100000 + +#define GSC_HPA 0xffc00000 +#define DINO_HPA 0xfff80000 +#define DINO_UART_HPA 0xfff83000 +#define DINO_UART_BASE 0xfff83800 +#define DINO_SCSI_HPA 0xfff8c000 +#define LASI_HPA 0xffd00000 +#define LASI_UART_HPA 0xffd05000 +#define LASI_SCSI_HPA 0xffd06000 +#define LASI_LAN_HPA 0xffd07000 +#define LASI_LPT_HPA 0xffd02000 +#define LASI_AUDIO_HPA 0xffd04000 +#define LASI_PS2KBD_HPA 0xffd08000 +#define LASI_PS2MOU_HPA 0xffd08100 +#define LASI_GFX_HPA 0xf8000000 +#define CPU_HPA 0xfff10000 +#define MEMORY_HPA 0xfffbf000 + +#define PCI_HPA DINO_HPA /* PCI bus */ +#define IDE_HPA 0xf9000000 /* Boot disc controller */ + +/* offsets to DINO HPA: */ +#define DINO_PCI_ADDR 0x064 +#define DINO_CONFIG_DATA 0x068 +#define DINO_IO_DATA 0x06c + +#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) +#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) + +#define PORT_SERIAL1 (DINO_UART_HPA + 0x800) +#define PORT_SERIAL2 (LASI_UART_HPA + 0x800) + +#define HPPA_MAX_CPUS 32 /* max. number of SMP CPUs */ +#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h new file mode 100644 index 0000000000..a182d1f34e --- /dev/null +++ b/hw/hppa/hppa_sys.h @@ -0,0 +1,24 @@ +/* HPPA cores and system support chips. */ + +#ifndef HW_HPPA_SYS_H +#define HW_HPPA_SYS_H + +#include "target/hppa/cpu-qom.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_host.h" +#include "hw/ide.h" +#include "hw/i386/pc.h" +#include "hw/irq.h" + +#include "hw/hppa/hppa_hardware.h" + +PCIBus *dino_init(MemoryRegion *, qemu_irq *, qemu_irq *); + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +/* hppa_pci.c. */ +extern const MemoryRegionOps hppa_pci_ignore_ops; +extern const MemoryRegionOps hppa_pci_conf1_ops; +extern const MemoryRegionOps hppa_pci_iack_ops; + +#endif diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c new file mode 100644 index 0000000000..15aefde09c --- /dev/null +++ b/hw/hppa/dino.c @@ -0,0 +1,518 @@ +/* + * HP-PARISC Dino PCI chipset emulation. + * + * (C) 2017 by Helge Deller + * + * This work is licensed under the GNU GPL license version 2 or later. + * + * Documentation available at: + * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf + * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/devices.h" +#include "sysemu/sysemu.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hppa_sys.h" +#include "exec/address-spaces.h" + + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +#define DINO_IAR0 0x004 +#define DINO_IODC 0x008 +#define DINO_IRR0 0x00C /* RO */ +#define DINO_IAR1 0x010 +#define DINO_IRR1 0x014 /* RO */ +#define DINO_IMR 0x018 +#define DINO_IPR 0x01C +#define DINO_TOC_ADDR 0x020 +#define DINO_ICR 0x024 +#define DINO_ILR 0x028 /* RO */ +#define DINO_IO_COMMAND 0x030 /* WO */ +#define DINO_IO_STATUS 0x034 /* RO */ +#define DINO_IO_CONTROL 0x038 +#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ +#define DINO_IO_ERR_INFO 0x044 /* RO */ +#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ +#define DINO_IO_FBB_EN 0x05c +#define DINO_IO_ADDR_EN 0x060 +#define DINO_PCI_CONFIG_ADDR 0x064 +#define DINO_PCI_CONFIG_DATA 0x068 +#define DINO_PCI_IO_DATA 0x06c +#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ +#define DINO_GSC2X_CONFIG 0x7b4 /* RO */ +#define DINO_GMASK 0x800 +#define DINO_PAMR 0x804 +#define DINO_PAPR 0x808 +#define DINO_DAMODE 0x80c +#define DINO_PCICMD 0x810 +#define DINO_PCISTS 0x814 /* R/WC */ +#define DINO_MLTIM 0x81c +#define DINO_BRDG_FEAT 0x820 +#define DINO_PCIROR 0x824 +#define DINO_PCIWOR 0x828 +#define DINO_TLTIM 0x830 + +#define DINO_IRQS 11 /* bits 0-10 are architected */ +#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ +#define DINO_LOCAL_IRQS (DINO_IRQS + 1) +#define DINO_MASK_IRQ(x) (1 << (x)) + +#define PCIINTA 0x001 +#define PCIINTB 0x002 +#define PCIINTC 0x004 +#define PCIINTD 0x008 +#define PCIINTE 0x010 +#define PCIINTF 0x020 +#define GSCEXTINT 0x040 +/* #define xxx 0x080 - bit 7 is "default" */ +/* #define xxx 0x100 - bit 8 not used */ +/* #define xxx 0x200 - bit 9 not used */ +#define RS232INT 0x400 + +#define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */ + +#define DINO_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) + +typedef struct DinoState { + PCIHostState parent_obj; + + /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, + so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ + + uint32_t iar0; + uint32_t iar1; + uint32_t imr; + uint32_t ipr; + uint32_t icr; + uint32_t ilr; + uint32_t io_addr_en; + uint32_t io_control; + + MemoryRegion this_mem; + MemoryRegion pci_mem; + MemoryRegion pci_mem_alias[32]; + + AddressSpace bm_as; + MemoryRegion bm; + MemoryRegion bm_ram_alias; + MemoryRegion bm_pci_alias; + + MemoryRegion cpu0_eir_mem; +} DinoState; + +/* + * Dino can forward memory accesses from the CPU in the range between + * 0xf0800000 and 0xff000000 to the PCI bus. + */ +static void gsc_to_pci_forwarding(DinoState *s) +{ + uint32_t io_addr_en, tmp; + int enabled, i; + + tmp =3D extract32(s->io_control, 7, 2); + enabled =3D (tmp =3D=3D 0x01); + io_addr_en =3D s->io_addr_en; + + memory_region_transaction_begin(); + for (i =3D 1; i < 31; i++) { + MemoryRegion *mem =3D &s->pci_mem_alias[i]; + if (enabled && (io_addr_en & (1U << i))) { + if (!memory_region_is_mapped(mem)) { + uint32_t addr =3D 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + memory_region_add_subregion(get_system_memory(), addr, mem= ); + } + } else if (memory_region_is_mapped(mem)) { + memory_region_del_subregion(get_system_memory(), mem); + } + } + memory_region_transaction_commit(); +} + +static bool dino_chip_mem_valid(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + switch (addr) { + case DINO_IAR0: + case DINO_IAR1: + case DINO_IRR0: + case DINO_IRR1: + case DINO_IMR: + case DINO_IPR: + case DINO_ICR: + case DINO_ILR: + case DINO_IO_CONTROL: + case DINO_IO_ADDR_EN: + case DINO_PCI_IO_DATA: + return true; + case DINO_PCI_IO_DATA + 2: + return size <=3D 2; + case DINO_PCI_IO_DATA + 1: + case DINO_PCI_IO_DATA + 3: + return size =3D=3D 1; + } + return false; +} + +static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s =3D opaque; + MemTxResult ret =3D MEMTX_OK; + AddressSpace *io; + uint16_t ioaddr; + uint32_t val; + + switch (addr) { + case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: + /* Read from PCI IO space. */ + io =3D &address_space_io; + ioaddr =3D s->parent_obj.config_reg; + switch (size) { + case 1: + val =3D address_space_ldub(io, ioaddr, attrs, &ret); + break; + case 2: + val =3D address_space_lduw_be(io, ioaddr, attrs, &ret); + break; + case 4: + val =3D address_space_ldl_be(io, ioaddr, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + break; + + case DINO_IO_ADDR_EN: + val =3D s->io_addr_en; + break; + case DINO_IO_CONTROL: + val =3D s->io_control; + break; + + case DINO_IAR0: + val =3D s->iar0; + break; + case DINO_IAR1: + val =3D s->iar1; + break; + case DINO_IMR: + val =3D s->imr; + break; + case DINO_ICR: + val =3D s->icr; + break; + case DINO_IPR: + val =3D s->ipr; + /* Any read to IPR clears the register. */ + s->ipr =3D 0; + break; + case DINO_ILR: + val =3D s->ilr; + break; + case DINO_IRR0: + val =3D s->ilr & s->imr & ~s->icr; + break; + case DINO_IRR1: + val =3D s->ilr & s->imr & s->icr; + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + + *data =3D val; + return ret; +} + +static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s =3D opaque; + AddressSpace *io; + MemTxResult ret; + uint16_t ioaddr; + + switch (addr) { + case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: + /* Write into PCI IO space. */ + io =3D &address_space_io; + ioaddr =3D s->parent_obj.config_reg; + switch (size) { + case 1: + address_space_stb(io, ioaddr, val, attrs, &ret); + break; + case 2: + address_space_stw_be(io, ioaddr, val, attrs, &ret); + break; + case 4: + address_space_stl_be(io, ioaddr, val, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + return ret; + + case DINO_IO_ADDR_EN: + /* Never allow first (=3Dfirmware) and last (=3DDino) areas. */ + s->io_addr_en =3D val & 0x7ffffffe; + gsc_to_pci_forwarding(s); + break; + case DINO_IO_CONTROL: + s->io_control =3D val; + gsc_to_pci_forwarding(s); + break; + + case DINO_IAR0: + s->iar0 =3D val; + break; + case DINO_IAR1: + s->iar1 =3D val; + break; + case DINO_IMR: + s->imr =3D val; + break; + case DINO_ICR: + s->icr =3D val; + break; + case DINO_IPR: + /* Any write to IPR clears the register. */ + s->ipr =3D 0; + break; + + case DINO_ILR: + case DINO_IRR0: + case DINO_IRR1: + /* These registers are read-only. */ + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + return MEMTX_OK; +} + +static const MemoryRegionOps dino_chip_ops =3D { + .read_with_attrs =3D dino_chip_read_with_attrs, + .write_with_attrs =3D dino_chip_write_with_attrs, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .accepts =3D dino_chip_mem_valid, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static const VMStateDescription vmstate_dino =3D { + .name =3D "Dino", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(iar0, DinoState), + VMSTATE_UINT32(iar1, DinoState), + VMSTATE_UINT32(imr, DinoState), + VMSTATE_UINT32(ipr, DinoState), + VMSTATE_UINT32(icr, DinoState), + VMSTATE_UINT32(ilr, DinoState), + VMSTATE_UINT32(io_addr_en, DinoState), + VMSTATE_UINT32(io_control, DinoState), + VMSTATE_END_OF_LIST() + } +}; + + +/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ + +static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned = len) +{ + PCIHostState *s =3D opaque; + return pci_data_read(s->bus, s->config_reg | (addr & 3), len); +} + +static void dino_config_data_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) +{ + PCIHostState *s =3D opaque; + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); +} + +static const MemoryRegionOps dino_config_data_ops =3D { + .read =3D dino_config_data_read, + .write =3D dino_config_data_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + DinoState *s =3D opaque; + + return &s->bm_as; +} + +/* + * Dino interrupts are connected as shown on Page 78, Table 23 + * (Little-endian bit numbers) + * 0 PCI INTA + * 1 PCI INTB + * 2 PCI INTC + * 3 PCI INTD + * 4 PCI INTE + * 5 PCI INTF + * 6 GSC External Interrupt + * 7 Bus Error for "less than fatal" mode + * 8 PS2 + * 9 Unused + * 10 RS232 + */ + +static void dino_set_irq(void *opaque, int irq, int level) +{ + DinoState *s =3D opaque; + uint32_t bit =3D 1u << irq; + uint32_t old_ilr =3D s->ilr; + + if (level) { + uint32_t ena =3D bit & ~old_ilr; + s->ipr |=3D ena; + s->ilr =3D old_ilr | bit; + if (ena & s->imr) { + uint32_t iar =3D (ena & s->icr ? s->iar1 : s->iar0); + stl_be_phys(&address_space_memory, iar & -32, iar & 31); + } + } else { + s->ilr =3D old_ilr & ~bit; + } +} + +static int dino_pci_map_irq(PCIDevice *d, int irq_num) +{ + int slot =3D d->devfn >> 3; + int local_irq; + + assert(irq_num >=3D 0 && irq_num <=3D 3); + + local_irq =3D slot & 0x03; + + return local_irq; +} + +static void dino_set_timer_irq(void *opaque, int irq, int level) +{ + /* ??? Not connected. */ +} + +static void dino_set_serial_irq(void *opaque, int irq, int level) +{ + dino_set_irq(opaque, 10, level); +} + +PCIBus *dino_init(MemoryRegion *addr_space, + qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq) +{ + DeviceState *dev; + DinoState *s; + PCIBus *b; + int i; + + dev =3D qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); + s =3D DINO_PCI_HOST_BRIDGE(dev); + + /* Dino PCI access from main memory. */ + memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, + s, "dino", 4096); + memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem); + + /* Dino PCI config. */ + memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), + &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); + memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), + &dino_config_data_ops, dev, "pci-conf-data", 4); + memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, + &s->parent_obj.conf_mem); + memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA, + &s->parent_obj.data_mem); + + /* Dino PCI bus memory. */ + memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32); + + b =3D pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq= , s, + &s->pci_mem, get_system_io(), + PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); + s->parent_obj.bus =3D b; + qdev_init_nofail(dev); + + /* Set up windows into PCI bus memory. */ + for (i =3D 1; i < 31; i++) { + uint32_t addr =3D 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + char *name =3D g_strdup_printf("PCI Outbound Window %d", i); + memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s), + name, &s->pci_mem, addr, + DINO_MEM_CHUNK_SIZE); + } + + /* Set up PCI view of memory: Bus master address space. */ + memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32); + memory_region_init_alias(&s->bm_ram_alias, OBJECT(s), + "bm-system", addr_space, 0, + 0xf0000000 + DINO_MEM_CHUNK_SIZE); + memory_region_init_alias(&s->bm_pci_alias, OBJECT(s), + "bm-pci", &s->pci_mem, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + 31 * DINO_MEM_CHUNK_SIZE); + memory_region_add_subregion(&s->bm, 0, + &s->bm_ram_alias); + memory_region_add_subregion(&s->bm, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + &s->bm_pci_alias); + address_space_init(&s->bm_as, &s->bm, "pci-bm"); + pci_setup_iommu(b, dino_pcihost_set_iommu, s); + + *p_rtc_irq =3D qemu_allocate_irq(dino_set_timer_irq, s, 0); + *p_ser_irq =3D qemu_allocate_irq(dino_set_serial_irq, s, 0); + + return b; +} + +static int dino_pcihost_init(SysBusDevice *dev) +{ + return 0; +} + +static void dino_pcihost_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + k->init =3D dino_pcihost_init; + dc->vmsd =3D &vmstate_dino; +} + +static const TypeInfo dino_pcihost_info =3D { + .name =3D TYPE_DINO_PCI_HOST_BRIDGE, + .parent =3D TYPE_PCI_HOST_BRIDGE, + .instance_size =3D sizeof(DinoState), + .class_init =3D dino_pcihost_class_init, +}; + +static void dino_register_types(void) +{ + type_register_static(&dino_pcihost_info); +} + +type_init(dino_register_types) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 79958da18f..2b66298af5 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -16,20 +16,264 @@ #include "hw/ide.h" #include "hw/timer/i8254.h" #include "hw/char/serial.h" +#include "hw/hppa/hppa_sys.h" #include "qemu/cutils.h" #include "qapi/error.h" =20 +#define MAX_IDE_BUS 2 + +static ISABus *hppa_isa_bus(void) +{ + ISABus *isa_bus; + qemu_irq *isa_irqs; + MemoryRegion *isa_region; + + isa_region =3D g_new(MemoryRegion, 1); + memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, + NULL, "isa-io", 0x800); + memory_region_add_subregion(get_system_memory(), IDE_HPA, + isa_region); + + isa_bus =3D isa_bus_new(NULL, get_system_memory(), isa_region, + &error_abort); + isa_irqs =3D i8259_init(isa_bus, + /* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */ + NULL); + isa_bus_irqs(isa_bus, isa_irqs); + + return isa_bus; +} + +static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) +{ + addr &=3D (0x10000000 - 1); + return addr; +} + +static HPPACPU *cpu[HPPA_MAX_CPUS]; +static uint64_t firmware_entry; =20 static void machine_hppa_init(MachineState *machine) { + const char *kernel_filename =3D machine->kernel_filename; + const char *kernel_cmdline =3D machine->kernel_cmdline; + const char *initrd_filename =3D machine->initrd_filename; + PCIBus *pci_bus; + ISABus *isa_bus; + qemu_irq rtc_irq, serial_irq; + char *firmware_filename; + uint64_t firmware_low, firmware_high; + long size; + uint64_t kernel_entry =3D 0, kernel_low, kernel_high; + MemoryRegion *addr_space =3D get_system_memory(); + MemoryRegion *rom_region; + MemoryRegion *ram_region; + MemoryRegion *cpu_region; + long i; + + ram_size =3D machine->ram_size; + + /* Create CPUs. */ + for (i =3D 0; i < smp_cpus; i++) { + cpu[i] =3D HPPA_CPU(cpu_create(machine->cpu_type)); + + cpu_region =3D g_new(MemoryRegion, 1); + memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, + cpu[i], g_strdup_printf("cpu%ld-io-eir", i),= 4); + memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000, + cpu_region); + } + + /* Limit main memory. */ + if (ram_size > FIRMWARE_START) { + machine->ram_size =3D ram_size =3D FIRMWARE_START; + } + + /* Main memory region. */ + ram_region =3D g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(ram_region, OBJECT(machine), + "ram", ram_size); + memory_region_add_subregion(addr_space, 0, ram_region); + + /* Init Dino (PCI host bus chip). */ + pci_bus =3D dino_init(addr_space, &rtc_irq, &serial_irq); + assert(pci_bus); + + /* Create ISA bus. */ + isa_bus =3D hppa_isa_bus(); + assert(isa_bus); + + /* Realtime clock, used by firmware for PDC_TOD call. */ + mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + /* Serial code setup. */ + if (serial_hds[0]) { + uint32_t addr =3D DINO_UART_HPA + 0x800; + serial_mm_init(addr_space, addr, 0, serial_irq, + 115200, serial_hds[0], DEVICE_BIG_ENDIAN); + fprintf(stderr, "Serial port created at 0x%x\n", addr); + } + + /* SCSI disk setup. */ + lsi53c895a_create(pci_bus); + + /* Network setup. e1000 is good enough, failing Tulip support. */ + for (i =3D 0; i < nb_nics; i++) { + pci_nic_init_nofail(&nd_table[i], pci_bus, "e1000", NULL); + } + + /* Load firmware. Given that this is not "real" firmware, + but one explicitly written for the emulation, we might as + well load it directly from an ELF image. */ + firmware_filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, + bios_name ? bios_name : + "hppa-firmware.img"); + if (firmware_filename =3D=3D NULL) { + error_report("no firmware provided"); + exit(1); + } + + size =3D load_elf(firmware_filename, NULL, + NULL, &firmware_entry, &firmware_low, &firmware_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + firmware_entry =3D (target_ureg)firmware_entry; + firmware_low =3D (target_ureg)firmware_low; + firmware_high =3D (target_ureg)firmware_high; + + if (size < 0) { + error_report("could not load firmware '%s'", firmware_filename); + exit(1); + } + fprintf(stderr, "Firmware loaded at 0x%08lx-0x%08lx, entry at 0x%08lx.= \n", + firmware_low, firmware_high, firmware_entry); + if (firmware_low < ram_size || firmware_high >=3D FIRMWARE_END) { + error_report("Firmware overlaps with memory or IO space"); + exit(1); + } + g_free(firmware_filename); + + rom_region =3D g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(rom_region, OBJECT(machine), + "firmware", + (FIRMWARE_END - FIRMWARE_START)); + memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); + + /* Load kernel */ + if (kernel_filename) { + fprintf(stderr, "LOADING kernel '%s'\n", kernel_filename); + size =3D load_elf(kernel_filename, &cpu_hppa_to_phys, + NULL, &kernel_entry, &kernel_low, &kernel_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + kernel_entry =3D (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry= ); + kernel_low =3D (target_ureg)kernel_low; + kernel_high =3D (target_ureg)kernel_high; + + if (size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + + fprintf(stderr, "Kernel loaded at 0x%08lx-0x%08lx, entry at 0x%08l= x, " + "size %ld kB.\n", + kernel_low, kernel_high, kernel_entry, size / 1024); + + if (kernel_cmdline) { + cpu[0]->env.gr[24] =3D 0x4000; + pstrcpy_targphys("cmdline", cpu[0]->env.gr[24], + TARGET_PAGE_SIZE, kernel_cmdline); + } + + if (initrd_filename) { + ram_addr_t initrd_base; + long initrd_size; + + initrd_size =3D get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + /* Load the initrd image high in memory. + Mirror the algorithm used by palo: + (1) Due to sign-extension problems and PDC, + put the initrd no higher than 1G. + (2) Reserve 64k for stack. */ + initrd_base =3D MIN(ram_size, 1024 * 1024 * 1024); + initrd_base =3D initrd_base - 64 * 1024; + initrd_base =3D (initrd_base - initrd_size) & TARGET_PAGE_MASK; + + if (initrd_base < kernel_high) { + error_report("kernel and initial ram disk too large!"); + exit(1); + } + + load_image_targphys(initrd_filename, initrd_base, initrd_size); + cpu[0]->env.gr[23] =3D initrd_base; + cpu[0]->env.gr[22] =3D initrd_base + initrd_size; + } + } + + if (!kernel_entry) { + /* When booting via firmware, tell firmware if we want interactive + * mode (kernel_entry=3D1), and to boot from CD (gr[24]=3D'd') + * or hard disc * (gr[24]=3D'c'). + */ + kernel_entry =3D boot_menu ? 1 : 0; + cpu[0]->env.gr[24] =3D machine->boot_order[0]; + } + + /* We jump to the firmware entry routine and pass the + * various parameters in registers. After firmware initialization, + * firmware will start the Linux kernel with ramdisk and cmdline. + */ + cpu[0]->env.gr[26] =3D ram_size; + cpu[0]->env.gr[25] =3D kernel_entry; + + /* tell firmware how many SMP CPUs to present in inventory table */ + cpu[0]->env.gr[21] =3D smp_cpus; } =20 +static void hppa_machine_reset(void) +{ + int i; + + qemu_devices_reset(); + + /* Start all CPUs at the firmware entry point. + * Monarch CPU will initialize firmware, secondary CPUs + * will enter a small idle look and wait for rendevouz. */ + for (i =3D 0; i < smp_cpus; i++) { + cpu_set_pc(CPU(cpu[i]), firmware_entry); + cpu[i]->env.gr[5] =3D CPU_HPA + i * 0x1000; + } + + /* already initialized by machine_hppa_init()? */ + if (cpu[0]->env.gr[26] =3D=3D ram_size) { + return; + } + + cpu[0]->env.gr[26] =3D ram_size; + cpu[0]->env.gr[25] =3D 0; /* no firmware boot menu */ + cpu[0]->env.gr[24] =3D 'c'; + /* gr22/gr23 unused, no initrd while reboot. */ + cpu[0]->env.gr[21] =3D smp_cpus; +} + + static void machine_hppa_machine_init(MachineClass *mc) { mc->desc =3D "HPPA generic machine"; + mc->default_cpu_type =3D TYPE_HPPA_CPU; mc->init =3D machine_hppa_init; + mc->reset =3D hppa_machine_reset; mc->block_default_type =3D IF_SCSI; - mc->max_cpus =3D 1; + mc->max_cpus =3D HPPA_MAX_CPUS; + mc->default_cpus =3D 1; mc->is_default =3D 1; mc->default_ram_size =3D 512 * M_BYTE; mc->default_boot_order =3D "cd"; diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c new file mode 100644 index 0000000000..766420254e --- /dev/null +++ b/hw/hppa/pci.c @@ -0,0 +1,90 @@ +/* + * QEMU HP-PARISC PCI support functions. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hppa_sys.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" +#include "trace.h" + + +/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ + +static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned s= ize) +{ +} + +const MemoryRegionOps hppa_pci_ignore_ops =3D { + .read =3D ignore_read, + .write =3D ignore_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + + +/* PCI config space reads/writes, to byte-word addressable memory. */ +static uint64_t bw_conf1_read(void *opaque, hwaddr addr, + unsigned size) +{ + PCIBus *b =3D opaque; + return pci_data_read(b, addr, size); +} + +static void bw_conf1_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PCIBus *b =3D opaque; + pci_data_write(b, addr, val, size); +} + +const MemoryRegionOps hppa_pci_conf1_ops =3D { + .read =3D bw_conf1_read, + .write =3D bw_conf1_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +/* PCI/EISA Interrupt Acknowledge Cycle. */ + +static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) +{ + return pic_read_irq(isa_pic); +} + +static void special_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + trace_hppa_pci_iack_write(); +} + +const MemoryRegionOps hppa_pci_iack_ops =3D { + .read =3D iack_read, + .write =3D special_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; diff --git a/default-configs/hppa-softmmu.mak b/default-configs/hppa-softmm= u.mak new file mode 100644 index 0000000000..013e5f046f --- /dev/null +++ b/default-configs/hppa-softmmu.mak @@ -0,0 +1,14 @@ +include pci.mak +include usb.mak +CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy +CONFIG_ISA_BUS=3Dy +CONFIG_I8259=3Dy +CONFIG_VIRTIO_PCI=3D$(CONFIG_PCI) +CONFIG_VIRTIO=3Dy +CONFIG_E1000_PCI=3Dy +CONFIG_IDE_ISA=3Dy +CONFIG_IDE_CMD646=3Dy +# CONFIG_IDE_MMIO=3Dy +CONFIG_VIRTIO_VGA=3Dy +CONFIG_MC146818RTC=3Dy diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs index 46b2ae18de..bef241ed25 100644 --- a/hw/hppa/Makefile.objs +++ b/hw/hppa/Makefile.objs @@ -1 +1 @@ -obj-y +=3D machine.o +obj-y +=3D machine.o pci.o dino.o diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events new file mode 100644 index 0000000000..14c67937e1 --- /dev/null +++ b/hw/hppa/trace-events @@ -0,0 +1,4 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/hppa/pci.c +hppa_pci_iack_write(void) "" --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837809477255.73983342659994; Wed, 24 Jan 2018 15:50:09 -0800 (PST) Received: from localhost ([::1]:54616 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUnw-0006Ws-Bb for importer@patchew.org; Wed, 24 Jan 2018 18:50:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51792) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUSk-0005sb-Uw for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:28:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUSB-0002Pv-5m for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:28:14 -0500 Received: from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:45019) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUSA-0002PE-BW for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:39 -0500 Received: by mail-pg0-x22e.google.com with SMTP id m20so3810196pgc.11 for ; Wed, 24 Jan 2018 15:27:38 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=3qlGn/Cev9ZRnJ42AuM8l715MDL3FQWxgHiylJ1qML4=; b=j1zTjPHHnH1TYDNU93bnpVBN2RY2jbNptHDUpY/M+/cCEdFrkNkejLpapndKwl0fJI wiI37P3G84WsGcgtAGKTiaXpZYZuW40m5JWwwt7CfvD0cjn+R9iDFFrUnAvprDEiOHu/ GbeOGq6CTEVPuS26LScDgoAimok9MloriTlAs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=3qlGn/Cev9ZRnJ42AuM8l715MDL3FQWxgHiylJ1qML4=; b=ePSGPpSgGjUBUw0PAyCzw2WylUrfXD/8/1jPdsVsew5jD3UmrvVl0Poo+dT/sBFxVX Bs4hkr5VofnFpz/VTkOW7EtoFzO3SJqOPtMplUuxnqo2TyzHPLg1Gox8q39n6RL8RD2T +3TUf49UGI5Xh1aD+onUT61nBWYX9AqEovF8Qo9K3MTeTxcg6Neon6g+p3UiirSYXlhp LoZ6QGZS0fg32TxL/TKFDXmnZttnBBvM3no/3m4nKCFwGIkgRTa9A+1wSIxpsDwHjhEa L43UwN352TZnePGQmrxWzl2gxT63wPU1TaFy6U2yA2BFQFAkZxd3vOnX2HWB5bDcxJDJ WOow== X-Gm-Message-State: AKwxytcr9P4n7haASg5U0pyOhxR8ll8UCdjnpOswHbnFruH9OJVkV10b oVhcqCVG0jzl3mr4xRrA6rWukoA4Zz8= X-Google-Smtp-Source: AH8x227uLgwxQtpUT9V+S5rlDup2NNzmMBnR9EzYRB1kjnPqcdlIPV9XtjbBHUoqNUmOZDmZj8IKVA== X-Received: by 10.99.125.74 with SMTP id m10mr12175117pgn.354.1516836451419; Wed, 24 Jan 2018 15:27:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:22 -0800 Message-Id: <20180124232625.30105-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH v3 42/45] pc-bios: Add hppa-firmware.img and git submodule X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- Makefile | 3 ++- .gitmodules | 3 +++ pc-bios/hppa-firmware.img | Bin 0 -> 461352 bytes roms/seabios-hppa | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) create mode 100755 pc-bios/hppa-firmware.img create mode 160000 roms/seabios-hppa diff --git a/Makefile b/Makefile index d835bb92e7..5ffb7ed57f 100644 --- a/Makefile +++ b/Makefile @@ -649,7 +649,8 @@ s390-ccw.img s390-netboot.img \ spapr-rtas.bin slof.bin skiboot.lid \ palcode-clipper \ u-boot.e500 \ -qemu_vga.ndrv +qemu_vga.ndrv \ +hppa-firmware.img else BLOBS=3D endif diff --git a/.gitmodules b/.gitmodules index 1500579638..7a8282df46 100644 --- a/.gitmodules +++ b/.gitmodules @@ -40,3 +40,6 @@ [submodule "capstone"] path =3D capstone url =3D git://git.qemu.org/capstone.git +[submodule "roms/seabios-hppa"] + path =3D roms/seabios-hppa + url =3D git://github.com/hdeller/seabios-hppa.git diff --git a/pc-bios/hppa-firmware.img b/pc-bios/hppa-firmware.img new file mode 100755 index 0000000000000000000000000000000000000000..ae833437a73cb0955491b95f03c= d42132d8d2e9c GIT binary patch literal 461352 zcmeFae|VJTo$vq5R zPuLD5K=3D>tKpanP7w3l>o&$_2QN>_XETdbm}wG9M_bhV{FwA1?SwRl>u#{GhPU+;Tn zFk0Q+v)})|*U5F|x}Uk9`{(EW+@Ig~{d{fKjk8^DSB{nab6bTxy3SixH)+%=3D$m_Q( zx0k1g<+5t6N-L!I{3j`6>ECkwgU@ou#`9Fbf1LmS@Lwt%{&UK*{@1+e*W5a1e&b&? z&6_tpGH+&MWcHn3x%;n|eq}|ZcK(W`Gv?epKXUs$U+EZctz5Ha)#|B#^;dV?xn|{k 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literal 0 HcmV?d00001 diff --git a/roms/seabios-hppa b/roms/seabios-hppa new file mode 160000 index 0000000000..8fa4ca9935 --- /dev/null +++ b/roms/seabios-hppa @@ -0,0 +1 @@ +Subproject commit 8fa4ca9935669414a824ecda24f6e70c36e8dc94 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838586798947.8002429188548; Wed, 24 Jan 2018 16:03:06 -0800 (PST) Received: from localhost ([::1]:55627 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 43/45] hw/hppa: Add MAINTAINERS entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 753e7996ce..bee6b2bec7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,6 +133,7 @@ HPPA (PA-RISC) M: Richard Henderson S: Maintained F: target/hppa/ +F: hw/hppa/ F: disas/hppa.c =20 LM32 --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516838874748567.9412291403789; Wed, 24 Jan 2018 16:07:54 -0800 (PST) Received: from localhost ([::1]:56053 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeV58-0003cb-2d for importer@patchew.org; Wed, 24 Jan 2018 19:07:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUSB-0005KX-Up for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUS7-0002Np-BN for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:39 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:40649) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUS7-0002NE-63 for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:35 -0500 Received: by mail-pg0-x243.google.com with SMTP id g16so3813329pgn.7 for ; Wed, 24 Jan 2018 15:27:35 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 44/45] target/hppa: Fix 32-bit operand masks for 0E FCVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b9b097acc9..c62ee72615 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4381,34 +4381,34 @@ static const DisasInsn table_float_0e[] =3D { /* floating point class one */ /* float/float */ { 0x38000a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_s }, - { 0x38002200, 0xfc1fffc0, FOP_DEW =3D gen_helper_fcnv_s_d }, + { 0x38002200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_d }, /* int/float */ - { 0x38008200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_w_s }, + { 0x38008200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_w_s }, { 0x38008a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_dw_s }, { 0x3800a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_w_d }, { 0x3800aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_dw_d }, /* float/int */ - { 0x38010200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_s_w }, + { 0x38010200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_s_w }, { 0x38010a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_w }, { 0x38012200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_dw }, { 0x38012a00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_d_dw }, /* float/int truncate */ - { 0x38018200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_t_s_w }, + { 0x38018200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_t_s_w }, { 0x38018a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_t_d_w }, { 0x3801a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_t_s_dw }, { 0x3801aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_t_d_dw }, /* uint/float */ - { 0x38028200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_uw_s }, + { 0x38028200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_uw_s }, { 0x38028a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_udw_s }, { 0x3802a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_uw_d }, { 0x3802aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_udw_d }, /* float/uint */ - { 0x38030200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_s_uw }, + { 0x38030200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_s_uw }, { 0x38030a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_uw }, { 0x38032200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_udw }, { 0x38032a00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_d_udw }, /* float/uint truncate */ - { 0x38038200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_t_s_uw }, + { 0x38038200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_t_s_uw }, { 0x38038a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_t_d_uw }, { 0x3803a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_t_s_udw }, { 0x3803aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_t_d_udw }, --=20 2.14.3 From nobody Thu May 2 22:34:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516837609906611.1107916693869; Wed, 24 Jan 2018 15:46:49 -0800 (PST) Received: from localhost ([::1]:54578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUkj-0003sh-5V for importer@patchew.org; Wed, 24 Jan 2018 18:46:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUSB-0005KS-UO for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeUS8-0002Oa-QS for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:39 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:39198) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeUS8-0002ON-Kr for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:36 -0500 Received: by mail-pg0-x244.google.com with SMTP id w17so3811916pgv.6 for ; Wed, 24 Jan 2018 15:27:36 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=bou4vMWC6c1I5NQcTnWp5K8e3ECnbVkjzlF5uw1WvYY=; b=QPieKmJzxwEhk1Pbz/VSjtAjleaZXObRzmT2/kGtmq//TLXCvP7zmUVB8pBKLQtRFf sgIWYOCHjgzM7nbNRRRK5e+ztAFTSPIYr66J24AQEa3HhkJIH2kgeft6wSbYO4ALKFFv dr0XF2gWdenctjo54ihLeXqpbH3RGWgccSzdE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=bou4vMWC6c1I5NQcTnWp5K8e3ECnbVkjzlF5uw1WvYY=; b=ON9L9NP0juKw+bCMyf6wmTitPNJ3SFYJr86RSONkr9/9HtBLl4sD429K9JXq4CtBSj 1/gaBuWC3dM5T7hP7ElvCuy2Mj4wBr+xFdSDATtmSQoAh7UynBFWo9Rb06yRcbY22zPl CpNUNnsnDOMo0124sbK4NionwYAjSoojnF3Z86YxLZDux+TK559XTO/I5bIWKNj1jW/j n5OjOvTN7jrKLTpCn0Gg1EZrqY7dJukimGg6a0vWrX59nkhjKHedRokmfy/6Ti5gXBtT Ay5nh3KIOEOmOzU1N4pcBShMt/3pQojbILJxYn8PmtBjtzg5oFBaJGFvNlTzWDu3w/eQ 5BhA== X-Gm-Message-State: AKwxyteyN0DcRNPeLea6DQlgy5593qfh39G0KAACZZ0VGIXuPKfflY9z AZJn6pqQYeAfvELw5IMwFeWZh6JOy+s= X-Google-Smtp-Source: AH8x2269XRGJS/pOkEGWWaYEL8flvc7xzeG+CmW+IC8AOMMfuv3ovsFVQat1c7jDPkM0+qMhgJavhg== X-Received: by 2002:a17:902:6c41:: with SMTP id h1-v6mr9452941pln.25.1516836455349; Wed, 24 Jan 2018 15:27:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:25 -0800 Message-Id: <20180124232625.30105-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 45/45] target/hppa: Implement PROBE for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 3 +-- target/hppa/op_helper.c | 36 +++++++++++++++++++++++++----------- target/hppa/translate.c | 20 ++++++++++++++++---- 3 files changed, 42 insertions(+), 17 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 31320740da..51dc3f8b09 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -17,8 +17,7 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void,= env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) =20 -DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tr, tl) -DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tr, tl) +DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index c2eeced0e9..b386394bdf 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -160,21 +160,35 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, targe= t_ulong addr, do_stby_e(env, addr, val, true); } =20 -target_ureg HELPER(probe_r)(target_ulong addr) +target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr, + uint32_t level, uint32_t want) { #ifdef CONFIG_USER_ONLY - return page_check_range(addr, 1, PAGE_READ); + return page_check_range(addr, 1, want); #else - return 1; /* FIXME */ -#endif -} + int prot, excp; + hwaddr phys; =20 -target_ureg HELPER(probe_w)(target_ulong addr) -{ -#ifdef CONFIG_USER_ONLY - return page_check_range(addr, 1, PAGE_WRITE); -#else - return 1; /* FIXME */ + /* Fail if the requested privilege level is higher than current. */ + if (level < (env->iaoq_f & 3)) { + return 0; + } + + /* Use MMU_DEBUG_LOAD to bypass TLB D/B/T bit checks. */ + excp =3D hppa_get_physical_address(env, addr, level, MMU_DEBUG_LOAD, + &phys, &prot); + if (excp >=3D 0) { + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] =3D addr; + env->cr[CR_ISR] =3D addr >> 32; + } + if (excp =3D=3D EXCP_DTLB_MISS) { + excp =3D EXCP_NA_DTLB_MISS; + } + hppa_dynamic_excp(env, excp, GETPC()); + } + return (want & prot) !=3D 0; #endif } =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c62ee72615..7c45b1706c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2380,21 +2380,33 @@ static DisasJumpType trans_probe(DisasContext *ctx,= uint32_t insn, { unsigned rt =3D extract32(insn, 0, 5); unsigned sp =3D extract32(insn, 14, 2); + unsigned rr =3D extract32(insn, 16, 5); unsigned rb =3D extract32(insn, 21, 5); unsigned is_write =3D extract32(insn, 6, 1); + unsigned is_imm =3D extract32(insn, 13, 1); TCGv_reg dest, ofs; + TCGv_i32 level, want; TCGv_tl addr; =20 nullify_over(ctx); =20 - /* ??? Do something with priv level operand. */ dest =3D dest_gpr(ctx, rt); form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); - if (is_write) { - gen_helper_probe_w(dest, addr); + + if (is_imm) { + level =3D tcg_const_i32(extract32(insn, 16, 2)); } else { - gen_helper_probe_r(dest, addr); + level =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(level, load_gpr(ctx, rr)); + tcg_gen_andi_i32(level, level, 3); } + want =3D tcg_const_i32(is_write ? PROT_WRITE : PROT_READ); + + gen_helper_probe(dest, cpu_env, addr, level, want); + + tcg_temp_free_i32(want); + tcg_temp_free_i32(level); + save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); } --=20 2.14.3