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[213.113.116.203]) by smtp.gmail.com with ESMTPSA id m25sm245424lfc.38.2018.01.23.14.59.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2018 14:59:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=/QyF1Vwm+8svLryma+BP+Cu5HUfQ0Y0t6jE8PwDRlv4=; b=Zaq8L+l6RUnWShSpYClwuN3mQZKvOAq+jTqI3/ALM1h2CmJig6Mj5G3mYL1pQF7u7c V3FcO4NMcYR+KrKQCttZBobqxphSp3HoPZbHoU7mwNqALeiHpaBXwaXNq0ngJ40oNDry PMR4p09UEkHmufabz1itNIs/oy/MUaHOSA2tk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/QyF1Vwm+8svLryma+BP+Cu5HUfQ0Y0t6jE8PwDRlv4=; b=gXwqFRZ+md8vas1fyyZTvszTmQD0S4MYuR7Tk9uAfK0jO89LZxnDzdxocF+JCdX78C lx3HU6R4iLK/NnOyBhX2yUXH4A0IXr00fJErOALTACntJED9NwDt4EGo+fim8J3XNYEg MLn/cHSRPAboQ4vLsxKAF6iuXWS5P3U2KmXzMZwgltUMIj9FwfHBSTaZg1HnDaITEAo8 rL2oOD0ipgWup9WY8gCsKTaMmStIarSWi0I4TptFZErQDlrUPhGdUpfNrdvMLPb/9WdT OzZyzGn277+cI+XIWLC9v4+8jYUJ13cfjIyKu7CnsAsjJrmt/tybLYns+2QD7U8cyfgy eWuA== X-Gm-Message-State: AKwxytc2c9rqPDwdWtLLLmQWuYmNvUzB+ZX5Hvq8zq4yebfKhdLqDjPF lnsfua5Lp1p+b7iegwFAWzHZA2xXWpY= X-Google-Smtp-Source: AH8x225xiEKntxadi2dFIMzArJdhGcqg5sBPeAqSaPqQtzYFIaJLnKOjZEgO3JaKFaxqIuiDhBXvPA== X-Received: by 10.25.56.13 with SMTP id f13mr2118489lfa.16.1516748341815; Tue, 23 Jan 2018 14:59:01 -0800 (PST) From: Linus Walleij To: qemu-devel@nongnu.org Date: Tue, 23 Jan 2018 23:56:54 +0100 Message-Id: <20180123225654.5764-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH] pl110: Implement vertical compare/next base interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Linus Walleij , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements rudimentary support for interrupt generation on the PL110. I am working on a new DRI/KMS driver for Linux and since that uses the blanking interrupt, we need something to fire here. Without any interrupt support Linux waits for a while and then gives ugly messages about the vblank not working in the console (it does not hang perpetually or anything though, DRI is pretty forgiving). I solved it for now by setting up a timer to fire at 60Hz and pull the interrupts for "vertical compare" and "next memory base" at this interval. This works fine and fires roughly the same number of IRQs on QEMU as on the hardware and leaves the console clean and nice. People who want to create more accurate emulation can probably work on top of this if need be. It is certainly closer to the hardware behaviour than what we have today anyway. Cc: Peter Maydell Signed-off-by: Linus Walleij --- hw/display/pl110.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 8c7dcc6f0a69..777bb3f44503 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -12,6 +12,7 @@ #include "ui/console.h" #include "framebuffer.h" #include "ui/pixel_ops.h" +#include "qemu/timer.h" #include "qemu/log.h" =20 #define PL110_CR_EN 0x001 @@ -19,6 +20,8 @@ #define PL110_CR_BEBO 0x200 #define PL110_CR_BEPO 0x400 #define PL110_CR_PWR 0x800 +#define PL110_IE_NB 0x004 +#define PL110_IE_VC 0x008 =20 enum pl110_bppmode { @@ -50,6 +53,7 @@ typedef struct PL110State { MemoryRegion iomem; MemoryRegionSection fbsection; QemuConsole *con; + QEMUTimer *vblank_timer; =20 int version; uint32_t timing[4]; @@ -320,7 +324,23 @@ static void pl110_resize(PL110State *s, int width, int= height) /* Update interrupts. */ static void pl110_update(PL110State *s) { - /* TODO: Implement interrupts. */ + /* Raise IRQ if enabled and any status bit is 1 */ + if (s->int_status & s->int_mask) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static void pl110_vblank_interrupt(void *opaque) +{ + PL110State *s =3D opaque; + + /* Fire the vertical compare and next base IRQs and re-arm */ + s->int_status |=3D (PL110_IE_NB | PL110_IE_VC); + timer_mod(s->vblank_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + NANOSECONDS_PER_SECO= ND / 60); + pl110_update(s); } =20 static uint64_t pl110_read(void *opaque, hwaddr offset, @@ -429,6 +449,10 @@ static void pl110_write(void *opaque, hwaddr offset, s->bpp =3D (val >> 1) & 7; if (pl110_enabled(s)) { qemu_console_resize(s->con, s->cols, s->rows); + timer_mod(s->vblank_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + NANOSECONDS_= PER_SECOND / 60); + } else { + timer_del(s->vblank_timer); } break; case 10: /* LCDICR */ @@ -474,6 +498,7 @@ static void pl110_realize(DeviceState *dev, Error **err= p) memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + s->vblank_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, pl110_vblank_inte= rrupt, s); qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); s->con =3D graphic_console_init(dev, 0, &pl110_gfx_ops, s); } --=20 2.14.3