From nobody Sun May 5 01:40:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516679767851462.19519646294304; Mon, 22 Jan 2018 19:56:07 -0800 (PST) Received: from localhost ([::1]:60730 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpgl-0003BY-K7 for importer@patchew.org; Mon, 22 Jan 2018 22:55:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpen-0001sg-QY for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edpel-00044r-Vq for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:57 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34644) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edpel-00043u-Mj for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:55 -0500 Received: by mail-pg0-x242.google.com with SMTP id r19so8779200pgn.1 for ; Mon, 22 Jan 2018 19:53:55 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ALs+5LNCOW2HM0Ze3ARm/rJDwNfbOfdrpeBVt29uKZ0=; b=Y0ysfKUuAjVLno29vP6kzVagc+wW2eFH8ZTgI76KCxRN20Bc+1c4Cs2Bod6ndDaIQj 1tKaEfo41K9g4VQNWNulTETnbge6qUcA4YgQBWq61wti+ItCIC9V7dglY/aaSefyv/go 6tY6VmejEYEHSR5TbXmHDX1Xo2rD7ACvn2d08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ALs+5LNCOW2HM0Ze3ARm/rJDwNfbOfdrpeBVt29uKZ0=; b=KEp15D+5sUtrlos+Wgtx3I24lAYParpBoZj0T4wjtUgLf3VlhHO1fYKu6seURa6xtq 2mn8uxUEjkp7RfL4m/uSm94yMfVaiDQmF5Je0F0ga9ElTdJBRuTWKlULKZERw8MgsUIu GA184PXd7IpW0zOBsQ5iNaE7hxNsY0zbcn6zAW3MoVd465V7kDG9V/25TqiLQiIHiZTi wY4CzdNZ1Mv6Do+cLcJ/Urt+a4qFSmUDtQzYUzVDajLnuYVNUzYJjGDDz9YAozde/DtB /ErvOGwqdEfyq1/Ah3vm4jbu7nzosGmo52ndIg4UbV+5f7mnTSb77GY5gqKUOjeNSsro q2VQ== X-Gm-Message-State: AKwxytc9gxzFkPLb7TAjTRMH0+Jsv3wF3S6uAaM7SdBet1qn4N8MDRz6 ZCr4E2asFRXf5wMjnGKFMGlsf/4y27M= X-Google-Smtp-Source: AH8x227ynbM0Pbv8CX+se0ZNWAHQ4V2iGjyfqfY3yZtOGFEfhENDuc9NHu4AImuVHw28ghoUT9NvSQ== X-Received: by 10.99.167.75 with SMTP id w11mr8164144pgo.215.1516679634206; Mon, 22 Jan 2018 19:53:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:45 -0800 Message-Id: <20180123035349.24538-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 1/5] target/arm: Expand vector registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg. The previous patches have made the change in representation relatively painless. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 59 +++++++++++++++++++++++++++++++-----------= ---- target/arm/machine.c | 35 ++++++++++++++++++++++++++- target/arm/translate-a64.c | 8 +++---- target/arm/translate.c | 7 +++--- 4 files changed, 81 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d2bb59eded..1854fe51a8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -153,6 +153,42 @@ typedef struct { uint32_t base_mask; } TCR; =20 +/* Define a maximum sized vector register. + * For 32-bit, this is a 128-bit NEON/AdvSIMD register. + * For 64-bit, this is a 2048-bit SVE register. + * + * Note that the mapping between S, D, and Q views of the register bank + * differs between AArch64 and AArch32. + * In AArch32: + * Qn =3D regs[n].d[1]:regs[n].d[0] + * Dn =3D regs[n / 2].d[n & 1] + * Sn =3D regs[n / 4].d[n % 4 / 2], + * bits 31..0 for even n, and bits 63..32 for odd n + * (and regs[16] to regs[31] are inaccessible) + * In AArch64: + * Zn =3D regs[n].d[*] + * Qn =3D regs[n].d[1]:regs[n].d[0] + * Dn =3D regs[n].d[0] + * Sn =3D regs[n].d[0] bits 31..0 + * + * This corresponds to the architecturally defined mapping between + * the two execution states, and means we do not need to explicitly + * map these registers when changing states. + * + * Align the data for use with TCG host vector operations. + */ + +#ifdef TARGET_AARCH64 +# define ARM_MAX_VQ 16 +#else +# define ARM_MAX_VQ 1 +#endif + +typedef struct ARMVectorReg { + uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); +} ARMVectorReg; + + typedef struct CPUARMState { /* Regs for current mode. */ uint32_t regs[16]; @@ -477,22 +513,7 @@ typedef struct CPUARMState { =20 /* VFP coprocessor state. */ struct { - /* VFP/Neon register state. Note that the mapping between S, D and= Q - * views of the register bank differs between AArch64 and AArch32: - * In AArch32: - * Qn =3D regs[2n+1]:regs[2n] - * Dn =3D regs[n] - * Sn =3D regs[n/2] bits 31..0 for even n, and bits 63..32 for od= d n - * (and regs[32] to regs[63] are inaccessible) - * In AArch64: - * Qn =3D regs[2n+1]:regs[2n] - * Dn =3D regs[2n] - * Sn =3D regs[2n] bits 31..0 - * This corresponds to the architecturally defined mapping between - * the two execution states, and means we do not need to explicitly - * map these registers when changing states. - */ - uint64_t regs[64]; + ARMVectorReg zregs[32]; =20 uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ @@ -2769,7 +2790,7 @@ static inline void *arm_get_el_change_hook_opaque(ARM= CPU *cpu) */ static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[regno]; + return &env->vfp.zregs[regno >> 1].d[regno & 1]; } =20 /** @@ -2778,7 +2799,7 @@ static inline uint64_t *aa32_vfp_dreg(CPUARMState *en= v, unsigned regno) */ static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[2 * regno]; + return &env->vfp.zregs[regno].d[0]; } =20 /** @@ -2787,7 +2808,7 @@ static inline uint64_t *aa32_vfp_qreg(CPUARMState *en= v, unsigned regno) */ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[2 * regno]; + return &env->vfp.zregs[regno].d[0]; } =20 #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index a85c2430d3..cb0e1c92bb 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -50,7 +50,40 @@ static const VMStateDescription vmstate_vfp =3D { .minimum_version_id =3D 3, .needed =3D vfp_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64), + /* For compatibility, store Qn out of Zn here. */ + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), + /* The xregs array is a little awkward because element 1 (FPSCR) * requires a specific accessor, so we have to split it up in * the vmstate: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eed64c73e5..10eef870fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -517,8 +517,8 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, { int offs =3D 0; #ifdef HOST_WORDS_BIGENDIAN - /* This is complicated slightly because vfp.regs[2n] is - * still the low half and vfp.regs[2n+1] the high half + /* This is complicated slightly because vfp.zregs[n].d[0] is + * still the low half and vfp.zregs[n].d[1] the high half * of the 128 bit vector, even on big endian systems. * Calculate the offset assuming a fully bigendian 128 bits, * then XOR to account for the order of the two 64 bit halves. @@ -528,7 +528,7 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, #else offs +=3D element * (1 << size); #endif - offs +=3D offsetof(CPUARMState, vfp.regs[regno * 2]); + offs +=3D offsetof(CPUARMState, vfp.zregs[regno]); assert_fp_access_checked(s); return offs; } @@ -537,7 +537,7 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, static inline int vec_full_reg_offset(DisasContext *s, int regno) { assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2]); + return offsetof(CPUARMState, vfp.zregs[regno]); } =20 /* Return a newly allocated pointer to the vector register. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 55826b7e5a..a8c13d3758 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1512,13 +1512,12 @@ static inline void gen_vfp_st(DisasContext *s, int = dp, TCGv_i32 addr) } } =20 -static inline long -vfp_reg_offset (int dp, int reg) +static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { - return offsetof(CPUARMState, vfp.regs[reg]); + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); } else { - long ofs =3D offsetof(CPUARMState, vfp.regs[reg >> 1]); + long ofs =3D offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1= ) & 1]); if (reg & 1) { ofs +=3D offsetof(CPU_DoubleU, l.upper); } else { --=20 2.14.3 From nobody Sun May 5 01:40:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516679767905423.0010274227126; Mon, 22 Jan 2018 19:56:07 -0800 (PST) Received: from localhost ([::1]:60729 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpgl-0003Az-Pp for importer@patchew.org; Mon, 22 Jan 2018 22:55:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpeo-0001si-3h for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edpen-000469-AG for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:58 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:34287) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edpen-00045T-3y for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:57 -0500 Received: by mail-pf0-x243.google.com with SMTP id e76so8775074pfk.1 for ; Mon, 22 Jan 2018 19:53:56 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j5ZzFe9v1seJM10ejjq7LnkqZkzsXk5giC+K0+xGnVc=; b=Ed8LJlk6PR/1hL3FhoAdyYapJn0blJ8/Mj8TPSnIgrDwvJPkF1Dt8oYicvaOHD8lJb iLt2nUHUQix4IJqCt1AjvU4Kj332USpPxVWnskNtkSM2tDbvUM8X05uQuTBwyolAk+No Nr7nHCMrNCV+/hmDmDgYnJN+tpHMsSKPlM+p4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j5ZzFe9v1seJM10ejjq7LnkqZkzsXk5giC+K0+xGnVc=; b=uMFwoR/VyRT6NL0Caqg/WvLFecmsm1O0iMVs0I5P1EF8Pn+/LifmOR6DgtkkTZ/Jsq 9osxSbddsftB1awiawV85BXycpb4oWOSgAQ4tF+dQpcxyPLgdyQR/EMv3Cs5x1TjxLvN c/e2ZdgTi9MQFbCTEg5YvMRObx1DAVXu+RjQxEBYFHnIYxgo9VctnkrTCJ4LXZc8w5D8 8cmyjK7qi5FQq+Xw0iezIkHVJXg7Wjcwsy1QUWQnmLjJtLtMGi+OLrWyov7sqzzyc8HG 8QBNKJABXht2YmiTUVImhivn2PlQvLNzvPzjzZtOo3bV0JN6nBumUc/VBxhh+G+xPg8F a0hg== X-Gm-Message-State: AKwxytcq5sqcIekyuB2MYnmUFtgbVzNpNPEq1/3qEZ+PKkXd2Pm8DWkF upO3hDRm94bea7oZYSQYJpuIY3ZHwVk= X-Google-Smtp-Source: AH8x224Ba0yqrIYGFp+jJYSajPHNTPFPMSod+CSTUm1LUcXi9IASQXX24P2r4eSqZUGHgZVl5jF64Q== X-Received: by 2002:a17:902:f:: with SMTP id 15-v6mr4474291pla.419.1516679635543; Mon, 22 Jan 2018 19:53:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:46 -0800 Message-Id: <20180123035349.24538-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: Add predicate registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1854fe51a8..3f4f6b6144 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 +/* In AArch32 mode, predicate registers do not exist at all. */ +#ifdef TARGET_AARCH64 +typedef struct ARMPredicateReg { + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +} ARMPredicateReg; +#endif + =20 typedef struct CPUARMState { /* Regs for current mode. */ @@ -515,6 +522,11 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; =20 +#ifdef TARGET_AARCH64 + /* Store FFR as pregs[16] to make it easier to treat as any other.= */ + ARMPredicateReg pregs[17]; +#endif + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; --=20 2.14.3 From nobody Sun May 5 01:40:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516679886087439.1016074793355; Mon, 22 Jan 2018 19:58:06 -0800 (PST) Received: from localhost ([::1]:60828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpin-0005Bp-Fk for importer@patchew.org; Mon, 22 Jan 2018 22:58:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpep-0001t2-Dd for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edpeo-00047V-G4 for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:59 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42916) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edpeo-00046l-Aq for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:58 -0500 Received: by mail-pg0-x243.google.com with SMTP id q67so8762871pga.9 for ; Mon, 22 Jan 2018 19:53:58 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=PKa2a16/TMZ8XwergD5sZp/vzIA7Cjb4+OArfZMAjiVPkX2RW6mS0+Onie2u3XK2YB RBQ5yzKrMxLWZbFndOS/9X2F+nmDrqQRyLxrXKuLfvT1KMDDWcMAdJR3r97vpy66UAHO DAMsVEx04lO1WmRFPZGnKPROiq122dDchZaW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=hctbg4tehkLSlPHAIfbJcjfb5KyvEkhQgfZ7IbjR2LbawWG3fB319hBQgt85D843iV 6zW0n1NBmYzXMFzxBGBql3bC+pLYgtHuaQQq/avWZl1VwC4tLJLUDQAW3ZR9/G+Z52YA y4H6J+yXL9TIIyetWEQ8LKXgdOfMbHR/eqSRAGY/EwGkNWLEqI1mZzaAHO9du4zhYHoi QXLvamYeZ2w8PLnMLSMDqSDiqn0wYX0cCAszuSxuxA+eHpjOSUiEnCyBD+Xv2MW1x7aT yUwMGgDVGSYd3ftQ+gVDaT+lPXzOLYO2V0pNKsrbqrJhSbLK7/IHLGX6AhUG9/qeJ4E/ qeAQ== X-Gm-Message-State: AKwxyteW6dJ/MpoZra0FEp/KTdSMnLf5zLUQ04jDBBI2BbWzv6Cnsfoy /wadHjBxEdca/GxEarSMmKYjd8t5FBc= X-Google-Smtp-Source: AH8x226t27zZA7SHbv+NC322xOxuTBnwWobJLJnTnbWPYkUb6IMNgrypYkzAiVx8gxvacegixnOFkw== X-Received: by 10.99.112.81 with SMTP id a17mr8201317pgn.293.1516679636953; Mon, 22 Jan 2018 19:53:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:47 -0800 Message-Id: <20180123035349.24538-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 3/5] target/arm: Add SVE to migration state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index cb0e1c92bb..2c8b43062f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt =3D { } }; =20 +#ifdef TARGET_AARCH64 +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, + * and ARMPredicateReg is actively empty. This triggers errors + * in the expansion of the VMSTATE macros. + */ + +static bool sve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_SVE); +} + +/* The first two words of each Zreg is stored in VFP state. */ +static const VMStateDescription vmstate_zreg_hi_reg =3D { + .name =3D "cpu/sve/zreg_hi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_preg_reg =3D { + .name =3D "cpu/sve/preg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_sve =3D { + .name =3D "cpu/sve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, + vmstate_zreg_hi_reg, ARMVectorReg), + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, + vmstate_preg_reg, ARMPredicateReg), + VMSTATE_END_OF_LIST() + } +}; +#endif /* AARCH64 */ + static bool m_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, +#ifdef TARGET_AARCH64 + &vmstate_sve, +#endif NULL } }; --=20 2.14.3 From nobody Sun May 5 01:40:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151667976795466.3847974546236; Mon, 22 Jan 2018 19:56:07 -0800 (PST) Received: from localhost ([::1]:60731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpgp-0003Fl-CC for importer@patchew.org; Mon, 22 Jan 2018 22:56:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edper-0001tt-4x for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edpep-00049X-UQ for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:01 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:42050) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edpep-00048T-LS for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:53:59 -0500 Received: by mail-pf0-x243.google.com with SMTP id b25so8755872pfd.9 for ; Mon, 22 Jan 2018 19:53:59 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=deRFjHrW5yt+nLGpFx/cXpvMsC03NLZLiLHoyaTRKKg=; b=Q9LJQcXpkQV2btUCDOqRcpZ4bnr8pugKpUW1Y+NhFkRnGT+ku3vMhQ9BUBm2HTi5s9 MlVdTFKGau16RBoJA/FgNSDDZyu6/es5GYHl/hqCMl0AmrGMJBAMFAadVRTsrT9QghyS vRIs96tRZ7J6SS+VwM3EuEX3MpGoSQuzf+e68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=deRFjHrW5yt+nLGpFx/cXpvMsC03NLZLiLHoyaTRKKg=; b=fQ+6lfMWHUCZtTxAKPOtZtIcLBKiyc6vD0XvZXLikj1ZyM3cGT94e8w9Bbv9OjVcC9 TlOzwG2MohYixcIgC/Y1Ko1Q8j2CcnO3Simv+cFzIJQhv/t0p74MQp4fPZSPYXmcD/pI o3AZUkoT+yjs/lpTC+l6Uhy5TuKugNyWglcSv99xy7YaZMCjqfgahbsQ6y+e1fLlsxAx KSBt1JUuJkd/1m3oZEFowc+HtdSF6ISku8m3qTjkoJS4KCVkkgCxHat1TTg2BHYVPl16 OCPGcQce/HJr0GgOlP+0tudit2ugIimNYMyIhs4X/myFa4w+r2PIIxUUbi4pDfHNSsz5 knnQ== X-Gm-Message-State: AKwxytd7ayezJvvNPhAeRbI1haK9ZaccE8JhjAbzsmNcW55zl1rIKbkd m1RywIhGRRyV5F75Wf9CF5AyWpRhtZY= X-Google-Smtp-Source: AH8x224wb9UXhPUgjt+oBXE+Ou45H9iYKWNvZjWEQfLBuyw5Ui4xstZyBVs4y8oMCn/Rk8LgA6DrjA== X-Received: by 10.101.67.193 with SMTP id n1mr7989282pgp.116.1516679638301; Mon, 22 Jan 2018 19:53:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:48 -0800 Message-Id: <20180123035349.24538-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 4/5] target/arm: Add ZCR_ELx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define ZCR_EL[1-3]. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 ++ target/arm/helper.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 136 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3f4f6b6144..17955ad3ef 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -549,6 +549,9 @@ typedef struct CPUARMState { */ float_status fp_status; float_status standard_fp_status; + + /* ZCR_EL[1-3] */ + uint64_t zcr_el[4]; } vfp; uint64_t exclusive_addr; uint64_t exclusive_val; @@ -923,6 +926,8 @@ void pmccntr_sync(CPUARMState *env); #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) #define CPTR_TFP (1U << 10) +#define CPTR_TZ (1U << 8) /* CPTR_EL2 */ +#define CPTR_EZ (1U << 8) /* CPTR_EL3 */ =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) diff --git a/target/arm/helper.c b/target/arm/helper.c index bfce09643b..db67e8ac72 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4266,6 +4266,125 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { REGINFO_SENTINEL }; =20 +/* Return the exception level to which SVE-disabled exceptions should + * be taken, or 0 if SVE is enabled. + */ +static int sve_exception_el(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + unsigned current_el =3D arm_current_el(env); + + /* The CPACR.ZEN controls traps to EL1: + * 0, 2 : trap EL0 and EL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + switch (extract32(env->cp15.cpacr_el1, 16, 2)) { + default: + if (current_el <=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + break; + case 1: + if (current_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; + } + + /* Similarly for CPACR.FPEN, after having checked ZEN. */ + switch (extract32(env->cp15.cpacr_el1, 20, 2)) { + default: + if (current_el <=3D 1) { + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + break; + case 1: + if (current_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; + } + + /* CPTR_EL2. Check both TZ and TFP. */ + if (current_el <=3D 2 + && (env->cp15.cptr_el[2] & (CPTR_TFP | CPTR_TZ)) + && !arm_is_secure_below_el3(env)) { + return 2; + } + + /* CPTR_EL3. Check both EZ and TFP. */ + if (!(env->cp15.cptr_el[3] & CPTR_EZ) + || (env->cp15.cptr_el[3] & CPTR_TFP)) { + return 3; + } +#endif + return 0; +} + +static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + switch (sve_exception_el(env)) { + case 3: + return CP_ACCESS_TRAP_EL3; + case 2: + return CP_ACCESS_TRAP_EL2; + case 1: + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Bits other than [3:0] are RAZ/WI. */ + raw_write(env, ri, value & 0xf); +} + +static const ARMCPRegInfo zcr_el1_reginfo =3D { + .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + +static const ARMCPRegInfo zcr_el2_reginfo =3D { + .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + +static const ARMCPRegInfo zcr_no_el2_reginfo =3D { + .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT, + .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore +}; + +static const ARMCPRegInfo zcr_el3_reginfo =3D { + .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; @@ -5332,6 +5451,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_one_arm_cp_reg(cpu, &sctlr); } + + if (arm_feature(env, ARM_FEATURE_SVE)) { + define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); + } else { + define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); + } + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.14.3 From nobody Sun May 5 01:40:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516679884693122.80693607189767; Mon, 22 Jan 2018 19:58:04 -0800 (PST) Received: from localhost ([::1]:60826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpim-0005Ae-1e for importer@patchew.org; Mon, 22 Jan 2018 22:58:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edpes-0001vI-Et for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edper-0004BK-E0 for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:02 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:37286) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edper-0004AW-6T for qemu-devel@nongnu.org; Mon, 22 Jan 2018 22:54:01 -0500 Received: by mail-pg0-x242.google.com with SMTP id z17so8768372pgc.4 for ; Mon, 22 Jan 2018 19:54:01 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aOP5CpWP51onl5Hzyvxgad3yYqWLQMfjilJrKFLiPkU=; b=BdqCt9NhofwJ7TCkTSw1tax0ch18dFc6/if3K4t5ZAi70jElowF5AIb/NllHvBN1TN cOcQwggf2/xGq2j/v9QmX6pF6uVLNjGM19ArKX+FAQJ4HwMywmeURvyc5ArSCcj7v0IX hm7McGVKK6dFmI1tf3zVf02gIJV0kZjo7Z1tk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aOP5CpWP51onl5Hzyvxgad3yYqWLQMfjilJrKFLiPkU=; b=PLLKQhYy9Kkx2CN3/cpg560yCaMdG+Y+7ehVXt2rKFmp3XyDrr8OrAndDhMOoVr6Z6 VD4D41t7DHzf6e5f0yLON0LnHZBQ6M6p0GAlUUX7Pv1ckFDVF0drcIQGm8Dvix9Ul2qG h/4plYRzwC+3lvC17OvTRf83yPj9/fN0vy4JRg1qzz3Q4wfXTLMnNDd+HWjKI6tfhq2r 1H09ov0mwlqmm/JJ/BJ/BnpcyGFgWqX222NFMuPRz9TEOG63W2DfTiwwFHAWcZXBhOB+ Oxp1xpdu/eHkfLCTtCySA3DY0IS4OgfU2L1epGqKmKonKaKWO0QxH68SHAmU9kLhLkPI rC/w== X-Gm-Message-State: AKwxytf3Xf30ilMS7a2ejVjwK4tGPqbpuZMaCr62biAzrQmAVOh8zm3R 9ZzUeVrvW2pM4GjjZfUpHu0HA/KxtHk= X-Google-Smtp-Source: AH8x224W4n+RUMJxZ0QiR7TwG9lffccJR/18TZs1RP0rfh5sA2d7++2+/tiLDUCliNqAkcvcl+p90Q== X-Received: by 10.99.151.2 with SMTP id n2mr5791489pge.87.1516679639854; Mon, 22 Jan 2018 19:53:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:49 -0800 Message-Id: <20180123035349.24538-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 5/5] target/arm: Add SVE state to TB->FLAGS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add both SVE exception state and vector length. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 25 ++++++++++++++++++++++++- target/arm/translate-a64.c | 2 ++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 17955ad3ef..a311d4e327 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2648,6 +2648,10 @@ static inline bool arm_cpu_data_is_big_endian(CPUARM= State *env) #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) +#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 +#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) +#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 +#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) =20 /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -2684,6 +2688,10 @@ static inline bool arm_cpu_data_is_big_endian(CPUARM= State *env) (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) #define ARM_TBFLAG_TBI1(F) \ (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) +#define ARM_TBFLAG_SVEEXC_EL(F) \ + (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) +#define ARM_TBFLAG_ZCR_LEN(F) \ + (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 3f4df91e5e..c47febf99d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -29,6 +29,8 @@ typedef struct DisasContext { bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ + int sve_excp_el; /* SVE exception EL or 0 if enabled */ + int sve_len; /* SVE vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3.= */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index db67e8ac72..d46d3622fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11823,14 +11823,37 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + int fp_el =3D fp_exception_el(env); uint32_t flags; =20 if (is_a64(env)) { + int sve_el =3D sve_exception_el(env); + uint32_t zcr_len; + *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); + flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; + + /* If SVE is disabled, but FP is enabled, + then the effective len is 0. */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + int current_el =3D arm_current_el(env); + + zcr_len =3D env->vfp.zcr_el[current_el <=3D 1 ? 1 : current_el= ]; + zcr_len &=3D 0xf; + if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2= ]); + } + if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3= ]); + } + } + flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } else { *pc =3D env->regs[15]; flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) @@ -11873,7 +11896,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_cpu_data_is_big_endian(env)) { flags |=3D ARM_TBFLAG_BE_DATA_MASK; } - flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |=3D fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 if (arm_v7m_is_handler_mode(env)) { flags |=3D ARM_TBFLAG_HANDLER_MASK; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 10eef870fe..4c1eca7062 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11263,6 +11263,8 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->user =3D (dc->current_el =3D=3D 0); #endif dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->sve_excp_el =3D ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); + dc->sve_len =3D (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.14.3