From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526301536337.2745892548272; Sun, 21 Jan 2018 01:18:21 -0800 (PST) Received: from localhost ([::1]:45021 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBlc-0001k7-O8 for importer@patchew.org; Sun, 21 Jan 2018 04:18:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfq-0006Em-2g for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfn-00037B-5d for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:22 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47976 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfm-0002x8-RR for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:19 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBfo-0005SV-11; Sun, 21 Jan 2018 09:12:22 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:45 +0000 Message-Id: <20180121091154.17426-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 01/10] apb: split simba PCI bridge into hw/pci-bridge/simba.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Mark Cave-Ayland , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Move the QOM type and macros into a new include/hw/pci-bridge/simba.h file, and add a new CONFIG_SIMBA Makefile.objs variable which is enabled for sparc64-softmmu builds only. Signed-off-by: Mark Cave-Ayland CC: Michael S. Tsirkin CC: Marcel Apfelbaum Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- default-configs/sparc64-softmmu.mak | 1 + hw/pci-bridge/Makefile.objs | 2 + hw/pci-bridge/simba.c | 101 ++++++++++++++++++++++++++++++++= ++++ hw/pci-host/apb.c | 62 +--------------------- include/hw/pci-bridge/simba.h | 38 ++++++++++++++ include/hw/pci-host/apb.h | 9 ---- 6 files changed, 143 insertions(+), 70 deletions(-) create mode 100644 hw/pci-bridge/simba.c create mode 100644 include/hw/pci-bridge/simba.h diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-= softmmu.mak index 3e177bbd7b..9b742a7b41 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -12,6 +12,7 @@ CONFIG_FDC=3Dy CONFIG_IDE_ISA=3Dy CONFIG_IDE_CMD646=3Dy CONFIG_PCI_APB=3Dy +CONFIG_SIMBA=3Dy CONFIG_SUNHME=3Dy CONFIG_MC146818RTC=3Dy CONFIG_ISA_TESTDEV=3Dy diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index 1b05023662..47065f87d9 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) +=3D ioh3420.o common-obj-$(CONFIG_I82801B11) +=3D i82801b11.o # NewWorld PowerMac common-obj-$(CONFIG_DEC_PCI) +=3D dec.o +# Sun4u +common-obj-$(CONFIG_SIMBA) +=3D simba.o diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c new file mode 100644 index 0000000000..05ba6f0f34 --- /dev/null +++ b/hw/pci-bridge/simba.c @@ -0,0 +1,101 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/simba.h" + +/* + * Chipset docs: + * APB: "Advanced PCI Bridge (APB) User's Manual", + * http://www.sun.com/processors/manuals/805-1251.pdf + */ + +static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) +{ + /* + * command register: + * According to PCI bridge spec, after reset + * bus master bit is off + * memory space enable bit is off + * According to manual (805-1251.pdf). + * the reset value should be zero unless the boot pin is tied high + * (which is true) and thus it should be PCI_COMMAND_MEMORY. + */ + PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); + + pci_bridge_initfn(dev, TYPE_PCI_BUS); + + pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_set_word(dev->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + + /* Allow 32-bit IO addresses */ + pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); + pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); + + pci_bridge_update_mappings(PCI_BRIDGE(br)); +} + +static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D apb_pci_bridge_realize; + k->exit =3D pci_bridge_exitfn; + k->vendor_id =3D PCI_VENDOR_ID_SUN; + k->device_id =3D PCI_DEVICE_ID_SUN_SIMBA; + k->revision =3D 0x11; + k->config_write =3D pci_bridge_write_config; + k->is_bridge =3D 1; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->reset =3D pci_bridge_reset; + dc->vmsd =3D &vmstate_pci_device; +} + +static const TypeInfo pbm_pci_bridge_info =3D { + .name =3D TYPE_PBM_PCI_BRIDGE, + .parent =3D TYPE_PCI_BRIDGE, + .class_init =3D pbm_pci_bridge_class_init, + .instance_size =3D sizeof(PBMPCIBridge), + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void pbm_register_types(void) +{ + type_register_static(&pbm_pci_bridge_info); +} + +type_init(pbm_register_types) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index ec676f94b6..3a5c046794 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -33,6 +33,7 @@ #include "hw/pci/pci_host.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/simba.h" #include "hw/pci-host/apb.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" @@ -53,9 +54,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", * http://www.sun.com/processors/manuals/805-0087.pdf - * - * APB: "Advanced PCI Bridge (APB) User's Manual", - * http://www.sun.com/processors/manuals/805-1251.pdf */ =20 #define PBM_PCI_IMR_MASK 0x7fffffff @@ -348,35 +346,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num,= int level) } } =20 -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) -{ - /* - * command register: - * According to PCI bridge spec, after reset - * bus master bit is off - * memory space enable bit is off - * According to manual (805-1251.pdf). - * the reset value should be zero unless the boot pin is tied high - * (which is true) and thus it should be PCI_COMMAND_MEMORY. - */ - PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); - - pci_bridge_initfn(dev, TYPE_PCI_BUS); - - pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); - pci_set_word(dev->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | - PCI_STATUS_DEVSEL_MEDIUM); - - /* Allow 32-bit IO addresses */ - pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); - pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); - - pci_bridge_update_mappings(PCI_BRIDGE(br)); -} - static void pci_pbm_reset(DeviceState *d) { APBState *s =3D APB_DEVICE(d); @@ -564,39 +533,10 @@ static const TypeInfo pbm_host_info =3D { .class_init =3D pbm_host_class_init, }; =20 -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->realize =3D apb_pci_bridge_realize; - k->exit =3D pci_bridge_exitfn; - k->vendor_id =3D PCI_VENDOR_ID_SUN; - k->device_id =3D PCI_DEVICE_ID_SUN_SIMBA; - k->revision =3D 0x11; - k->config_write =3D pci_bridge_write_config; - k->is_bridge =3D 1; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset =3D pci_bridge_reset; - dc->vmsd =3D &vmstate_pci_device; -} - -static const TypeInfo pbm_pci_bridge_info =3D { - .name =3D TYPE_PBM_PCI_BRIDGE, - .parent =3D TYPE_PCI_BRIDGE, - .class_init =3D pbm_pci_bridge_class_init, - .instance_size =3D sizeof(PBMPCIBridge), - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - static void pbm_register_types(void) { type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); - type_register_static(&pbm_pci_bridge_info); } =20 type_init(pbm_register_types) diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h new file mode 100644 index 0000000000..5ab1330236 --- /dev/null +++ b/include/hw/pci-bridge/simba.h @@ -0,0 +1,38 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci_bridge.h" + + +typedef struct PBMPCIBridge { + /*< private >*/ + PCIBridge parent_obj; +} PBMPCIBridge; + +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" +#define PBM_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 604d899b1e..5e28f3e1f3 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -42,13 +42,4 @@ typedef struct APBState { unsigned int nr_resets; } APBState; =20 -typedef struct PBMPCIBridge { - /*< private >*/ - PCIBridge parent_obj; -} PBMPCIBridge; - -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -#define PBM_PCI_BRIDGE(obj) \ - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) - #endif --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526094721385.5148154444678; Sun, 21 Jan 2018 01:14:54 -0800 (PST) Received: from localhost ([::1]:44978 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBiB-0007bD-7M for importer@patchew.org; Sun, 21 Jan 2018 04:14:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfq-0006Ej-2b for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfn-00038V-VM for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:22 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47979 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfn-0002yS-Oe for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:19 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBfq-0005SV-GM; Sun, 21 Jan 2018 09:12:23 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:46 +0000 Message-Id: <20180121091154.17426-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 02/10] simba: rename PBMPCIBridge and QOM types to reflect simba naming X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Here we rename PBMPCIBridge to SimbaPCIBridge and the QOM type from TYPE_PBM_PCI_BRIDGE to TYPE_SIMBA_PCI_BRIDGE in improve the clarity of the device name. Also touch up the relevant spots in apb.c and various other function names as appropriate. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/pci-bridge/simba.c | 22 +++++++++++----------- hw/pci-host/apb.c | 12 ++++++------ include/hw/pci-bridge/simba.h | 10 +++++----- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c index 05ba6f0f34..dea4c8c5e7 100644 --- a/hw/pci-bridge/simba.c +++ b/hw/pci-bridge/simba.c @@ -36,7 +36,7 @@ * http://www.sun.com/processors/manuals/805-1251.pdf */ =20 -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) +static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp) { /* * command register: @@ -47,7 +47,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error = **errp) * the reset value should be zero unless the boot pin is tied high * (which is true) and thus it should be PCI_COMMAND_MEMORY. */ - PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); + SimbaPCIBridge *br =3D SIMBA_PCI_BRIDGE(dev); =20 pci_bridge_initfn(dev, TYPE_PCI_BUS); =20 @@ -65,12 +65,12 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Erro= r **errp) pci_bridge_update_mappings(PCI_BRIDGE(br)); } =20 -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) +static void simba_pci_bridge_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->realize =3D apb_pci_bridge_realize; + k->realize =3D simba_pci_bridge_realize; k->exit =3D pci_bridge_exitfn; k->vendor_id =3D PCI_VENDOR_ID_SUN; k->device_id =3D PCI_DEVICE_ID_SUN_SIMBA; @@ -82,20 +82,20 @@ static void pbm_pci_bridge_class_init(ObjectClass *klas= s, void *data) dc->vmsd =3D &vmstate_pci_device; } =20 -static const TypeInfo pbm_pci_bridge_info =3D { - .name =3D TYPE_PBM_PCI_BRIDGE, +static const TypeInfo simba_pci_bridge_info =3D { + .name =3D TYPE_SIMBA_PCI_BRIDGE, .parent =3D TYPE_PCI_BRIDGE, - .class_init =3D pbm_pci_bridge_class_init, - .instance_size =3D sizeof(PBMPCIBridge), + .class_init =3D simba_pci_bridge_class_init, + .instance_size =3D sizeof(SimbaPCIBridge), .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, }, }; =20 -static void pbm_register_types(void) +static void simba_register_types(void) { - type_register_static(&pbm_pci_bridge_info); + type_register_static(&simba_pci_bridge_info); } =20 -type_init(pbm_register_types) +type_init(simba_register_types) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 3a5c046794..43ee42d170 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -293,7 +293,7 @@ static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_= num) return irq_num; } =20 -static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) { /* The on-board devices have fixed (legacy) OBIO intnos */ switch (PCI_SLOT(pci_dev->devfn)) { @@ -311,7 +311,7 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq= _num) return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } =20 -static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) { return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } @@ -417,15 +417,15 @@ static void pci_pbm_realize(DeviceState *dev, Error *= *errp) =20 /* APB secondary busses */ pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeB =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq); + pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); qdev_init_nofail(&pci_dev->qdev); =20 pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeA =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq); + pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); qdev_init_nofail(&pci_dev->qdev); } =20 diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h index 5ab1330236..fac56ab1cf 100644 --- a/include/hw/pci-bridge/simba.h +++ b/include/hw/pci-bridge/simba.h @@ -28,11 +28,11 @@ #include "hw/pci/pci_bridge.h" =20 =20 -typedef struct PBMPCIBridge { +typedef struct SimbaPCIBridge { /*< private >*/ PCIBridge parent_obj; -} PBMPCIBridge; +} SimbaPCIBridge; =20 -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -#define PBM_PCI_BRIDGE(obj) \ - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) +#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge" +#define SIMBA_PCI_BRIDGE(obj) \ + OBJECT_CHECK(SimbaPCIBridge, (obj), TYPE_SIMBA_PCI_BRIDGE) --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526479641939.4470888546979; Sun, 21 Jan 2018 01:21:19 -0800 (PST) Received: from localhost ([::1]:45181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBoM-00042q-SP for importer@patchew.org; Sun, 21 Jan 2018 04:21:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfr-0006F8-2j for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfp-00039Z-2b for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47983 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfo-00030p-PQ for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:21 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBfs-0005SV-6K; Sun, 21 Jan 2018 09:12:26 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:47 +0000 Message-Id: <20180121091154.17426-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 03/10] apb: rename APB functions to use sabre prefix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 As hinted in the comment at the top of the file, the naming convention for = the APB types/QOM functions isn't correct. As a starting point we can at least rename the APB type and related functions to improve the readability of apb= .c. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 109 +++++++++++++++++++++++-------------------= ---- include/hw/pci-host/apb.h | 1 - 2 files changed, 54 insertions(+), 56 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 43ee42d170..d5c459a2df 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) =20 #define NO_IRQ_REQUEST (MAX_IVEC + 1) =20 -static inline void pbm_set_request(APBState *s, unsigned int irq_num) +static inline void sabre_set_request(APBState *s, unsigned int irq_num) { APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); =20 @@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigne= d int irq_num) qemu_set_irq(s->ivec_irqs[irq_num], 1); } =20 -static inline void pbm_check_irqs(APBState *s) +static inline void sabre_check_irqs(APBState *s) { - unsigned int i; =20 /* Previous request is not acknowledged, resubmit */ if (s->irq_request !=3D NO_IRQ_REQUEST) { - pbm_set_request(s, s->irq_request); + sabre_set_request(s, s->irq_request); return; } /* no request pending */ @@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s) for (i =3D 0; i < 32; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); return; } } @@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s) for (i =3D 32; i < 64; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); break; } } } } =20 -static inline void pbm_clear_request(APBState *s, unsigned int irq_num) +static inline void sabre_clear_request(APBState *s, unsigned int irq_num) { APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request =3D NO_IRQ_REQUEST; } =20 -static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devf= n) +static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int de= vfn) { IOMMUState *is =3D opaque; =20 return &is->iommu_as; } =20 -static void apb_config_writel (void *opaque, hwaddr addr, +static void sabre_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { APBState *s =3D opaque; @@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr add= r, s->pci_irq_map[ino] &=3D PBM_PCI_IMR_MASK; s->pci_irq_map[ino] |=3D val & ~PBM_PCI_IMR_MASK; if ((s->irq_request =3D=3D ino) && !(val & ~PBM_PCI_IMR_MASK))= { - pbm_clear_request(s, ino); + sabre_clear_request(s, ino); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1000 ... 0x107f: /* OBIO interrupt control */ @@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr a= ddr, s->obio_irq_map[ino] |=3D val & ~PBM_PCI_IMR_MASK; if ((s->irq_request =3D=3D (ino | 0x20)) && !(val & ~PBM_PCI_IMR_MASK)) { - pbm_clear_request(s, ino | 0x20); + sabre_clear_request(s, ino | 0x20); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1400 ... 0x14ff: /* PCI interrupt clear */ if (addr & 4) { unsigned int ino =3D (addr & 0xff) >> 5; if ((s->irq_request / 4) =3D=3D ino) { - pbm_clear_request(s, s->irq_request); - pbm_check_irqs(s); + sabre_clear_request(s, s->irq_request); + sabre_check_irqs(s); } } break; @@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr add= r, if (addr & 4) { unsigned int ino =3D ((addr & 0xff) >> 3) | 0x20; if (s->irq_request =3D=3D ino) { - pbm_clear_request(s, ino); - pbm_check_irqs(s); + sabre_clear_request(s, ino); + sabre_check_irqs(s); } } break; @@ -202,7 +201,7 @@ static void apb_config_writel (void *opaque, hwaddr add= r, } } =20 -static uint64_t apb_config_readl (void *opaque, +static uint64_t sabre_config_read(void *opaque, hwaddr addr, unsigned size) { APBState *s =3D opaque; @@ -258,14 +257,14 @@ static uint64_t apb_config_readl (void *opaque, return val; } =20 -static const MemoryRegionOps apb_config_ops =3D { - .read =3D apb_config_readl, - .write =3D apb_config_writel, +static const MemoryRegionOps sabre_config_ops =3D { + .read =3D sabre_config_read, + .write =3D sabre_config_write, .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void apb_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void sabre_pci_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { APBState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); @@ -274,8 +273,8 @@ static void apb_pci_config_write(void *opaque, hwaddr a= ddr, pci_data_write(phb->bus, addr, val, size); } =20 -static uint64_t apb_pci_config_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, + unsigned size) { uint32_t ret; APBState *s =3D opaque; @@ -286,8 +285,8 @@ static uint64_t apb_pci_config_read(void *opaque, hwadd= r addr, return ret; } =20 -/* The APB host has an IRQ line for each IRQ line of each slot. */ -static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) +/* The sabre host has an IRQ line for each IRQ line of each slot. */ +static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { /* Return the irq as swizzled by the PBM */ return irq_num; @@ -316,7 +315,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int i= rq_num) return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } =20 -static void pci_apb_set_irq(void *opaque, int irq_num, int level) +static void pci_sabre_set_irq(void *opaque, int irq_num, int level) { APBState *s =3D opaque; =20 @@ -326,7 +325,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, = int level) if (level) { s->pci_irq_in |=3D 1ULL << irq_num; if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &=3D ~(1ULL << irq_num); @@ -338,7 +337,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, = int level) s->pci_irq_in |=3D 1ULL << irq_num; if ((s->irq_request =3D=3D NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &=3D ~(1ULL << irq_num); @@ -346,7 +345,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, = int level) } } =20 -static void pci_pbm_reset(DeviceState *d) +static void sabre_reset(DeviceState *d) { APBState *s =3D APB_DEVICE(d); PCIDevice *pci_dev; @@ -379,12 +378,12 @@ static void pci_pbm_reset(DeviceState *d) } =20 static const MemoryRegionOps pci_config_ops =3D { - .read =3D apb_pci_config_read, - .write =3D apb_pci_config_write, + .read =3D sabre_pci_config_read, + .write =3D sabre_pci_config_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static void pci_pbm_realize(DeviceState *dev, Error **errp) +static void sabre_realize(DeviceState *dev, Error **errp) { APBState *s =3D APB_DEVICE(dev); PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); @@ -403,17 +402,17 @@ static void pci_pbm_realize(DeviceState *dev, Error *= *errp) &s->pci_mmio); =20 phb->bus =3D pci_register_root_bus(dev, "pci", - pci_apb_set_irq, pci_apb_map_irq, s, + pci_sabre_set_irq, pci_sabre_map_irq,= s, &s->pci_mmio, &s->pci_ioport, 0, 32, TYPE_PCI_BUS); =20 pci_create_simple(phb->bus, 0, "pbm-pci"); =20 - /* APB IOMMU */ + /* IOMMU */ memory_region_add_subregion_overlap(&s->apb_config, 0x200, sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1= ); - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu); + pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); =20 /* APB secondary busses */ pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, @@ -429,7 +428,7 @@ static void pci_pbm_realize(DeviceState *dev, Error **e= rrp) qdev_init_nofail(&pci_dev->qdev); } =20 -static void pci_pbm_init(Object *obj) +static void sabre_init(Object *obj) { APBState *s =3D APB_DEVICE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); @@ -444,7 +443,7 @@ static void pci_pbm_init(Object *obj) for (i =3D 0; i < 32; i++) { s->obio_irq_map[i] =3D ((0x1f << 6) | 0x20) + i; } - qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVE= C); + qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_I= VEC); qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC= ); s->irq_request =3D NO_IRQ_REQUEST; s->pci_irq_in =3D 0ULL; @@ -456,7 +455,7 @@ static void pci_pbm_init(Object *obj) 0, NULL); =20 /* apb_config */ - memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s, + memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s, "apb-config", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->apb_config); @@ -473,7 +472,7 @@ static void pci_pbm_init(Object *obj) sysbus_init_mmio(sbd, &s->pci_ioport); } =20 -static void pbm_pci_host_realize(PCIDevice *d, Error **errp) +static void sabre_pci_host_realize(PCIDevice *d, Error **errp) { pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -482,12 +481,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error = **errp) PCI_STATUS_DEVSEL_MEDIUM); } =20 -static void pbm_pci_host_class_init(ObjectClass *klass, void *data) +static void sabre_pci_host_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - k->realize =3D pbm_pci_host_realize; + k->realize =3D sabre_pci_host_realize; k->vendor_id =3D PCI_VENDOR_ID_SUN; k->device_id =3D PCI_DEVICE_ID_SUN_SABRE; k->class_id =3D PCI_CLASS_BRIDGE_HOST; @@ -502,41 +501,41 @@ static const TypeInfo pbm_pci_host_info =3D { .name =3D "pbm-pci", .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PCIDevice), - .class_init =3D pbm_pci_host_class_init, + .class_init =3D sabre_pci_host_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, }, }; =20 -static Property pbm_pci_host_properties[] =3D { +static Property sabre_properties[] =3D { DEFINE_PROP_UINT64("special-base", APBState, special_base, 0), DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0), DEFINE_PROP_END_OF_LIST(), }; =20 -static void pbm_host_class_init(ObjectClass *klass, void *data) +static void sabre_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - dc->realize =3D pci_pbm_realize; - dc->reset =3D pci_pbm_reset; - dc->props =3D pbm_pci_host_properties; + dc->realize =3D sabre_realize; + dc->reset =3D sabre_reset; + dc->props =3D sabre_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } =20 -static const TypeInfo pbm_host_info =3D { +static const TypeInfo sabre_info =3D { .name =3D TYPE_APB, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(APBState), - .instance_init =3D pci_pbm_init, - .class_init =3D pbm_host_class_init, + .instance_init =3D sabre_init, + .class_init =3D sabre_class_init, }; =20 -static void pbm_register_types(void) +static void sabre_register_types(void) { - type_register_static(&pbm_host_info); + type_register_static(&sabre_info); type_register_static(&pbm_pci_host_info); } =20 -type_init(pbm_register_types) +type_init(sabre_register_types) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 5e28f3e1f3..41de012396 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -15,7 +15,6 @@ #define OBIO_SER_IRQ 0x2b =20 #define TYPE_APB "pbm" - #define APB_DEVICE(obj) \ OBJECT_CHECK(APBState, (obj), TYPE_APB) =20 --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526094182646.3833627689539; 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Sun, 21 Jan 2018 09:12:27 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:48 +0000 Message-Id: <20180121091154.17426-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 04/10] apb: change pbm_pci_host prefix functions to use sabre_pci prefix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is the proper name for the PBM host bridge as referenced in the Sun documentation. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index d5c459a2df..98c5f344f7 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -472,7 +472,7 @@ static void sabre_init(Object *obj) sysbus_init_mmio(sbd, &s->pci_ioport); } =20 -static void sabre_pci_host_realize(PCIDevice *d, Error **errp) +static void sabre_pci_realize(PCIDevice *d, Error **errp) { pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -481,12 +481,12 @@ static void sabre_pci_host_realize(PCIDevice *d, Erro= r **errp) PCI_STATUS_DEVSEL_MEDIUM); } =20 -static void sabre_pci_host_class_init(ObjectClass *klass, void *data) +static void sabre_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - k->realize =3D sabre_pci_host_realize; + k->realize =3D sabre_pci_realize; k->vendor_id =3D PCI_VENDOR_ID_SUN; k->device_id =3D PCI_DEVICE_ID_SUN_SABRE; k->class_id =3D PCI_CLASS_BRIDGE_HOST; @@ -497,11 +497,11 @@ static void sabre_pci_host_class_init(ObjectClass *kl= ass, void *data) dc->user_creatable =3D false; } =20 -static const TypeInfo pbm_pci_host_info =3D { +static const TypeInfo sabre_pci_info =3D { .name =3D "pbm-pci", .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PCIDevice), - .class_init =3D sabre_pci_host_class_init, + .class_init =3D sabre_pci_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, @@ -535,7 +535,7 @@ static const TypeInfo sabre_info =3D { static void sabre_register_types(void) { type_register_static(&sabre_info); - type_register_static(&pbm_pci_host_info); + type_register_static(&sabre_pci_info); } =20 type_init(sabre_register_types) --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526092821142.29823324954543; Sun, 21 Jan 2018 01:14:52 -0800 (PST) Received: from localhost ([::1]:44977 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBi8-0007Yy-6n for importer@patchew.org; Sun, 21 Jan 2018 04:14:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfq-0006En-3M for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfl-00035J-P8 for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:22 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47988 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfl-00033y-I4 for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:17 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBfv-0005SV-Qw; Sun, 21 Jan 2018 09:12:28 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:49 +0000 Message-Id: <20180121091154.17426-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 05/10] apb: QOMify sabre PCI host bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 6 +++--- include/hw/pci-host/apb.h | 14 +++++++++++--- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 98c5f344f7..36c6251816 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -407,7 +407,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) &s->pci_ioport, 0, 32, TYPE_PCI_BUS); =20 - pci_create_simple(phb->bus, 0, "pbm-pci"); + pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); =20 /* IOMMU */ memory_region_add_subregion_overlap(&s->apb_config, 0x200, @@ -498,9 +498,9 @@ static void sabre_pci_class_init(ObjectClass *klass, vo= id *data) } =20 static const TypeInfo sabre_pci_info =3D { - .name =3D "pbm-pci", + .name =3D TYPE_SABRE_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIDevice), + .instance_size =3D sizeof(SabrePCIState), .class_init =3D sabre_pci_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 41de012396..470863639a 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -14,9 +14,13 @@ #define OBIO_MSE_IRQ 0x2a #define OBIO_SER_IRQ 0x2b =20 -#define TYPE_APB "pbm" -#define APB_DEVICE(obj) \ - OBJECT_CHECK(APBState, (obj), TYPE_APB) +typedef struct SabrePCIState { + PCIDevice parent_obj; +} SabrePCIState; + +#define TYPE_SABRE_PCI_DEVICE "sabre-pci" +#define SABRE_PCI_DEVICE(obj) \ + OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE) =20 typedef struct APBState { PCIHostState parent_obj; @@ -41,4 +45,8 @@ typedef struct APBState { unsigned int nr_resets; } APBState; =20 +#define TYPE_APB "apb" +#define APB_DEVICE(obj) \ + OBJECT_CHECK(APBState, (obj), TYPE_APB) + #endif --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526480245859.8949540081086; Sun, 21 Jan 2018 01:21:20 -0800 (PST) Received: from localhost ([::1]:45180 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBoM-00042V-2q for importer@patchew.org; Sun, 21 Jan 2018 04:21:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfq-0006Ei-1M for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfn-000389-NY for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:22 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47991 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfn-00036d-DD for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:19 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBfx-0005SV-0a; Sun, 21 Jan 2018 09:12:30 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:50 +0000 Message-Id: <20180121091154.17426-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 06/10] apb: rename QOM type from TYPE_APB to TYPE_SABRE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Similarly rename the corresponding APBState typedef to SabreState. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 30 +++++++++++++++--------------- hw/sparc64/sun4u.c | 6 +++--- include/hw/pci-host/apb.h | 10 +++++----- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 36c6251816..f6c5dbd469 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) =20 #define NO_IRQ_REQUEST (MAX_IVEC + 1) =20 -static inline void sabre_set_request(APBState *s, unsigned int irq_num) +static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); =20 @@ -78,7 +78,7 @@ static inline void sabre_set_request(APBState *s, unsigne= d int irq_num) qemu_set_irq(s->ivec_irqs[irq_num], 1); } =20 -static inline void sabre_check_irqs(APBState *s) +static inline void sabre_check_irqs(SabreState *s) { unsigned int i; =20 @@ -109,7 +109,7 @@ static inline void sabre_check_irqs(APBState *s) } } =20 -static inline void sabre_clear_request(APBState *s, unsigned int irq_num) +static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); @@ -126,7 +126,7 @@ static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, v= oid *opaque, int devfn) static void sabre_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - APBState *s =3D opaque; + SabreState *s =3D opaque; =20 APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); =20 @@ -204,7 +204,7 @@ static void sabre_config_write(void *opaque, hwaddr add= r, static uint64_t sabre_config_read(void *opaque, hwaddr addr, unsigned size) { - APBState *s =3D opaque; + SabreState *s =3D opaque; uint32_t val; =20 switch (addr & 0xffff) { @@ -266,7 +266,7 @@ static const MemoryRegionOps sabre_config_ops =3D { static void sabre_pci_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - APBState *s =3D opaque; + SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); @@ -277,7 +277,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwa= ddr addr, unsigned size) { uint32_t ret; - APBState *s =3D opaque; + SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 ret =3D pci_data_read(phb->bus, addr, size); @@ -317,7 +317,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int i= rq_num) =20 static void pci_sabre_set_irq(void *opaque, int irq_num, int level) { - APBState *s =3D opaque; + SabreState *s =3D opaque; =20 APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); /* PCI IRQ map onto the first 32 INO. */ @@ -347,7 +347,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) =20 static void sabre_reset(DeviceState *d) { - APBState *s =3D APB_DEVICE(d); + SabreState *s =3D SABRE_DEVICE(d); PCIDevice *pci_dev; unsigned int i; uint16_t cmd; @@ -385,7 +385,7 @@ static const MemoryRegionOps pci_config_ops =3D { =20 static void sabre_realize(DeviceState *dev, Error **errp) { - APBState *s =3D APB_DEVICE(dev); + SabreState *s =3D SABRE_DEVICE(dev); PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); PCIDevice *pci_dev; @@ -430,7 +430,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) =20 static void sabre_init(Object *obj) { - APBState *s =3D APB_DEVICE(obj); + SabreState *s =3D SABRE_DEVICE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); unsigned int i; =20 @@ -509,8 +509,8 @@ static const TypeInfo sabre_pci_info =3D { }; =20 static Property sabre_properties[] =3D { - DEFINE_PROP_UINT64("special-base", APBState, special_base, 0), - DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0), + DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), + DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -525,9 +525,9 @@ static void sabre_class_init(ObjectClass *klass, void *= data) } =20 static const TypeInfo sabre_info =3D { - .name =3D TYPE_APB, + .name =3D TYPE_SABRE, .parent =3D TYPE_PCI_HOST_BRIDGE, - .instance_size =3D sizeof(APBState), + .instance_size =3D sizeof(SabreState), .instance_init =3D sabre_init, .class_init =3D sabre_class_init, }; diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index ec45ec2801..b8f685847a 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, Nvram *nvram; unsigned int i; uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_en= try; - APBState *apb; + SabreState *apb; PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; @@ -488,8 +488,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem, =20 prom_init(hwdef->prom_addr, bios_name); =20 - /* Init APB (PCI host bridge) */ - apb =3D APB_DEVICE(qdev_create(NULL, TYPE_APB)); + /* Init sabre (PCI host bridge) */ + apb =3D SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_a= bort); diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 470863639a..2552f3c984 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -22,7 +22,7 @@ typedef struct SabrePCIState { #define SABRE_PCI_DEVICE(obj) \ OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE) =20 -typedef struct APBState { +typedef struct SabreState { PCIHostState parent_obj; =20 hwaddr special_base; @@ -43,10 +43,10 @@ typedef struct APBState { unsigned int irq_request; uint32_t reset_control; unsigned int nr_resets; -} APBState; +} SabreState; =20 -#define TYPE_APB "apb" -#define APB_DEVICE(obj) \ - OBJECT_CHECK(APBState, (obj), TYPE_APB) +#define TYPE_SABRE "sabre" +#define SABRE_DEVICE(obj) \ + OBJECT_CHECK(SabreState, (obj), TYPE_SABRE) =20 #endif --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526093124951.6687972387468; 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Sun, 21 Jan 2018 09:12:32 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:51 +0000 Message-Id: <20180121091154.17426-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 07/10] sun4u: rename apb variables and constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In order to reflect the previous change of TYPE_APB to TYPE_SABRE, update the corresponding variable names to keep the terminology consistent. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/sparc64/sun4u.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index b8f685847a..fb18afaaa6 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -55,9 +55,9 @@ #define CMDLINE_ADDR 0x003ff000 #define PROM_SIZE_MAX (4 * 1024 * 1024) #define PROM_VADDR 0x000ffd00000ULL -#define APB_SPECIAL_BASE 0x1fe00000000ULL -#define APB_MEM_BASE 0x1ff00000000ULL -#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) +#define PBM_SPECIAL_BASE 0x1fe00000000ULL +#define PBM_MEM_BASE 0x1ff00000000ULL +#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) #define PROM_FILENAME "openbios-sparc64" #define NVRAM_SIZE 0x2000 #define MAX_IDE_BUS 2 @@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, Nvram *nvram; unsigned int i; uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_en= try; - SabreState *apb; + SabreState *sabre; PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; @@ -489,23 +489,24 @@ static void sun4uv_init(MemoryRegion *address_space_m= em, prom_init(hwdef->prom_addr, bios_name); =20 /* Init sabre (PCI host bridge) */ - apb =3D SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); - qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); - qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); - object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_a= bort); - qdev_init_nofail(DEVICE(apb)); + sabre =3D SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); + qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); + qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); + object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", + &error_abort); + qdev_init_nofail(DEVICE(sabre)); =20 /* Wire up PCI interrupts to CPU */ for (i =3D 0; i < IVEC_MAX; i++) { - qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, + qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); } =20 - pci_bus =3D PCI_HOST_BRIDGE(apb)->bus; - pci_busA =3D pci_bridge_get_sec_bus(apb->bridgeA); - pci_busB =3D pci_bridge_get_sec_bus(apb->bridgeB); + pci_bus =3D PCI_HOST_BRIDGE(sabre)->bus; + pci_busA =3D pci_bridge_get_sec_bus(sabre->bridgeA); + pci_busB =3D pci_bridge_get_sec_bus(sabre->bridgeB); =20 - /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA = is + /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA = is reserved (leaving no slots free after on-board devices) however slo= ts 0-3 are free on busB */ pci_bus->slot_reserved_mask =3D 0xfffffffc; @@ -517,17 +518,17 @@ static void sun4uv_init(MemoryRegion *address_space_m= em, hwdef->console_serial_base); qdev_init_nofail(DEVICE(ebus)); =20 - /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */ + /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); =20 pci_dev =3D pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); =20 --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526307367663.0225070661677; Sun, 21 Jan 2018 01:18:27 -0800 (PST) Received: from localhost ([::1]:45023 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBli-0001ny-Hy for importer@patchew.org; Sun, 21 Jan 2018 04:18:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBft-0006Ge-6k for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfr-0003DB-MI for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:25 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47998 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfr-0003C0-Cz for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBg0-0005SV-KH; Sun, 21 Jan 2018 09:12:34 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:52 +0000 Message-Id: <20180121091154.17426-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 08/10] apb: rename apb.c to sabre.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is the final stage in correcting the naming convention with respect to sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c along with touching up a few constants to remove the remaining references to APB. Note that as part of the rename process the configuration variable CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- default-configs/sparc64-softmmu.mak | 2 +- hw/pci-host/Makefile.objs | 2 +- hw/pci-host/{apb.c =3D> sabre.c} | 57 +++++++++++++++++-----------= ------ hw/sparc64/sun4u.c | 2 +- include/hw/pci-host/{apb.h =3D> sabre.h} | 2 +- 5 files changed, 33 insertions(+), 32 deletions(-) rename hw/pci-host/{apb.c =3D> sabre.c} (91%) rename include/hw/pci-host/{apb.h =3D> sabre.h} (97%) diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-= softmmu.mak index 9b742a7b41..52edafe547 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -11,7 +11,7 @@ CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy CONFIG_IDE_ISA=3Dy CONFIG_IDE_CMD646=3Dy -CONFIG_PCI_APB=3Dy +CONFIG_PCI_SABRE=3Dy CONFIG_SIMBA=3Dy CONFIG_SUNHME=3Dy CONFIG_MC146818RTC=3Dy diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index 9c7909cf44..4b69f737b5 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) +=3D ppce500.o # ARM devices common-obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o =20 -common-obj-$(CONFIG_PCI_APB) +=3D apb.o +common-obj-$(CONFIG_PCI_SABRE) +=3D sabre.o common-obj-$(CONFIG_FULONG) +=3D bonito.o common-obj-$(CONFIG_PCI_PIIX) +=3D piix.o common-obj-$(CONFIG_PCI_Q35) +=3D q35.o diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c similarity index 91% rename from hw/pci-host/apb.c rename to hw/pci-host/sabre.c index f6c5dbd469..4054c17598 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/sabre.c @@ -1,8 +1,9 @@ /* - * QEMU Ultrasparc APB PCI host + * QEMU Ultrasparc Sabre PCI host (PBM) * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -23,10 +24,6 @@ * THE SOFTWARE. */ =20 -/* XXX This file and most of its contents are somewhat misnamed. The - Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is - the secondary PCI bridge. */ - #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" @@ -34,20 +31,20 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci-bridge/simba.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-host/sabre.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" =20 -/* debug APB */ -//#define DEBUG_APB +/* debug sabre */ +//#define DEBUG_SABRE =20 -#ifdef DEBUG_APB -#define APB_DPRINTF(fmt, ...) \ -do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) +#ifdef DEBUG_SABRE +#define SABRE_DPRINTF(fmt, ...) \ +do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) #else -#define APB_DPRINTF(fmt, ...) +#define SABRE_DPRINTF(fmt, ...) #endif =20 /* @@ -72,7 +69,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) =20 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); + SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num); =20 s->irq_request =3D irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); @@ -111,7 +108,7 @@ static inline void sabre_check_irqs(SabreState *s) =20 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request =3D NO_IRQ_REQUEST; } @@ -128,7 +125,8 @@ static void sabre_config_write(void *opaque, hwaddr add= r, { SabreState *s =3D opaque; =20 - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, + addr, val); =20 switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -252,7 +250,7 @@ static uint64_t sabre_config_read(void *opaque, val =3D 0; break; } - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val= ); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, v= al); =20 return val; } @@ -269,7 +267,8 @@ static void sabre_pci_config_write(void *opaque, hwaddr= addr, SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, + addr, val); pci_data_write(phb->bus, addr, val, size); } =20 @@ -281,7 +280,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwa= ddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 ret =3D pci_data_read(phb->bus, addr, size); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret= ); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, r= et); return ret; } =20 @@ -319,7 +318,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) { SabreState *s =3D opaque; =20 - APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); + SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level= ); /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { @@ -333,7 +332,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, le= vel); + SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, + level); s->pci_irq_in |=3D 1ULL << irq_num; if ((s->irq_request =3D=3D NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { @@ -390,7 +390,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); PCIDevice *pci_dev; =20 - /* apb_config */ + /* sabre_config */ sysbus_mmio_map(sbd, 0, s->special_base); /* PCI configuration space */ sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); @@ -410,7 +410,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); =20 /* IOMMU */ - memory_region_add_subregion_overlap(&s->apb_config, 0x200, + memory_region_add_subregion_overlap(&s->sabre_config, 0x200, sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1= ); pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); =20 @@ -454,19 +454,20 @@ static void sabre_init(Object *obj) qdev_prop_allow_set_link_before_realize, 0, NULL); =20 - /* apb_config */ - memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s, - "apb-config", 0x10000); + /* sabre_config */ + memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, = s, + "sabre-config", 0x10000); /* at region 0 */ - sysbus_init_mmio(sbd, &s->apb_config); + sysbus_init_mmio(sbd, &s->sabre_config); =20 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "apb-pci-config", 0x1000000); + "sabre-pci-config", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); =20 /* pci_ioport */ - memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000= 000); + memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", + 0x1000000); =20 /* at region 2 */ sysbus_init_mmio(sbd, &s->pci_ioport); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index fb18afaaa6..c4eff6bea2 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -30,7 +30,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-host/sabre.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" #include "hw/timer/m48t59.h" diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/sabre.h similarity index 97% rename from include/hw/pci-host/apb.h rename to include/hw/pci-host/sabre.h index 2552f3c984..0f2ccc01c6 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/sabre.h @@ -27,7 +27,7 @@ typedef struct SabreState { =20 hwaddr special_base; hwaddr mem_base; - MemoryRegion apb_config; + MemoryRegion sabre_config; MemoryRegion pci_config; MemoryRegion pci_mmio; MemoryRegion pci_ioport; --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526600277794.7773987765897; Sun, 21 Jan 2018 01:23:20 -0800 (PST) Received: from localhost ([::1]:45286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBqR-0005Rh-IS for importer@patchew.org; Sun, 21 Jan 2018 04:23:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfw-0006HP-8X for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBft-0003Dw-CW for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:26 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48000 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBft-0003De-5V for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:25 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBg2-0005SV-Ue; Sun, 21 Jan 2018 09:12:36 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:53 +0000 Message-Id: <20180121091154.17426-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 09/10] sabre: convert from SABRE_DPRINTF macro to trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Mark Cave-Ayland , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mark Cave-Ayland CC: Michael S. Tsirkin CC: Marcel Apfelbaum Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko [for addition of trace-events to hw/pci-host] Acked-by: Michael S. Tsirkin --- Makefile.objs | 1 + hw/pci-host/sabre.c | 32 ++++++++++---------------------- hw/pci-host/trace-events | 11 +++++++++++ 3 files changed, 22 insertions(+), 22 deletions(-) create mode 100644 hw/pci-host/trace-events diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..323ef12384 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -150,6 +150,7 @@ trace-events-subdirs +=3D hw/i386/xen trace-events-subdirs +=3D hw/9pfs trace-events-subdirs +=3D hw/ppc trace-events-subdirs +=3D hw/pci +trace-events-subdirs +=3D hw/pci-host trace-events-subdirs +=3D hw/s390x trace-events-subdirs +=3D hw/vfio trace-events-subdirs +=3D hw/acpi diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 4054c17598..2268a41dd9 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -36,16 +36,7 @@ #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" - -/* debug sabre */ -//#define DEBUG_SABRE - -#ifdef DEBUG_SABRE -#define SABRE_DPRINTF(fmt, ...) \ -do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) -#else -#define SABRE_DPRINTF(fmt, ...) -#endif +#include "trace.h" =20 /* * Chipset docs: @@ -69,8 +60,7 @@ do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) =20 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num); - + trace_sabre_set_request(irq_num); s->irq_request =3D irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); } @@ -108,7 +98,7 @@ static inline void sabre_check_irqs(SabreState *s) =20 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + trace_sabre_clear_request(irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request =3D NO_IRQ_REQUEST; } @@ -125,8 +115,7 @@ static void sabre_config_write(void *opaque, hwaddr add= r, { SabreState *s =3D opaque; =20 - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, - addr, val); + trace_sabre_config_write(addr, val); =20 switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -250,7 +239,7 @@ static uint64_t sabre_config_read(void *opaque, val =3D 0; break; } - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, v= al); + trace_sabre_config_read(addr, val); =20 return val; } @@ -267,8 +256,7 @@ static void sabre_pci_config_write(void *opaque, hwaddr= addr, SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, - addr, val); + trace_sabre_pci_config_write(addr, val); pci_data_write(phb->bus, addr, val, size); } =20 @@ -280,7 +268,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwa= ddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 ret =3D pci_data_read(phb->bus, addr, size); - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, r= et); + trace_sabre_pci_config_read(addr, ret); return ret; } =20 @@ -318,7 +306,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) { SabreState *s =3D opaque; =20 - SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level= ); + trace_sabre_pci_set_irq(irq_num, level); + /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { @@ -332,8 +321,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, - level); + trace_sabre_pci_set_obio_irq(irq_num, level); s->pci_irq_in |=3D 1ULL << irq_num; if ((s->irq_request =3D=3D NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events new file mode 100644 index 0000000000..32dfc84692 --- /dev/null +++ b/hw/pci-host/trace-events @@ -0,0 +1,11 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/pci-host/sabre.c +sabre_set_request(int irq_num) "request irq %d" +sabre_clear_request(int irq_num) "clear request irq %d" +sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"= PRIx64 +sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"P= RIx64 +sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val = 0x%"PRIx64 +sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0= x%"PRIx64 +sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" +sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" --=20 2.11.0 From nobody Mon Apr 29 09:41:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526605907607.1957826334441; Sun, 21 Jan 2018 01:23:25 -0800 (PST) Received: from localhost ([::1]:45289 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBqV-0005Ut-4t for importer@patchew.org; Sun, 21 Jan 2018 04:23:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBjq-0000xM-Ax for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:16:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBjl-00065A-SA for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:16:30 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48016 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBjl-00063O-Ih for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:16:25 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBg4-0005SV-Jx; Sun, 21 Jan 2018 09:12:38 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:54 +0000 Message-Id: <20180121091154.17426-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 10/10] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- hw/sparc64/sparc64.c | 85 ++++++++++++++++++++-------------------------= ---- hw/sparc64/trace-events | 18 +++++++++++ 2 files changed, 52 insertions(+), 51 deletions(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 95a06f00b2..408388945e 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -28,25 +28,9 @@ #include "hw/char/serial.h" #include "hw/sparc/sparc64.h" #include "qemu/timer.h" +#include "trace.h" =20 =20 -//#define DEBUG_IRQ -//#define DEBUG_TIMER - -#ifdef DEBUG_IRQ -#define CPUIRQ_DPRINTF(fmt, ...) \ - do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) -#else -#define CPUIRQ_DPRINTF(fmt, ...) -#endif - -#ifdef DEBUG_TIMER -#define TIMER_DPRINTF(fmt, ...) \ - do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) -#else -#define TIMER_DPRINTF(fmt, ...) -#endif - #define TICK_MAX 0x7fffffffffffffffULL =20 void cpu_check_irqs(CPUSPARCState *env) @@ -73,8 +57,7 @@ void cpu_check_irqs(CPUSPARCState *env) is (2 << psrpil). */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", - env->interrupt_index); + trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -92,22 +75,21 @@ void cpu_check_irqs(CPUSPARCState *env) =20 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_inter= rupt && ((cpu_tsptr(env)->tt & 0x1f0) =3D=3D TT_EXTINT))) { - CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=3D%d " - "current %x >=3D pending %x\n", - env->tl, cpu_tsptr(env)->tt, new_interr= upt); + trace_sparc64_cpu_check_irqs_noset_irq(env->tl, + cpu_tsptr(env)->tt, + new_interrupt); } else if (old_interrupt !=3D new_interrupt) { env->interrupt_index =3D new_interrupt; - CPUIRQ_DPRINTF("Set CPU IRQ %d old=3D%x new=3D%x\n", i, - old_interrupt, new_interrupt); + trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, + new_interrupt); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } break; } } } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - CPUIRQ_DPRINTF("Interrupts disabled, pil=3D%08x pil_in=3D%08x soft= int=3D%08x " - "current interrupt %x\n", - pil, env->pil_in, env->softint, env->interrupt_inde= x); + trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softi= nt, + env->interrupt_index); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -131,7 +113,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, in= t level) =20 if (level) { if (!(env->ivec_status & 0x20)) { - CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); + trace_sparc64_cpu_ivec_raise_irq(irq); cs =3D CPU(cpu); cs->halted =3D 0; env->interrupt_index =3D TT_IVEC; @@ -143,7 +125,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, in= t level) } } else { if (env->ivec_status & 0x20) { - CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); + trace_sparc64_cpu_ivec_lower_irq(irq); cs =3D CPU(cpu); env->ivec_status &=3D ~0x20; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -216,10 +198,10 @@ static void tick_irq(void *opaque) CPUTimer *timer =3D env->tick; =20 if (timer->disabled) { - CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); + trace_sparc64_cpu_tick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("tick: fire\n"); + trace_sparc64_cpu_tick_irq_fire(); } =20 env->softint |=3D SOFTINT_TIMER; @@ -234,10 +216,10 @@ static void stick_irq(void *opaque) CPUTimer *timer =3D env->stick; =20 if (timer->disabled) { - CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); + trace_sparc64_cpu_stick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("stick: fire\n"); + trace_sparc64_cpu_stick_irq_fire(); } =20 env->softint |=3D SOFTINT_STIMER; @@ -252,10 +234,10 @@ static void hstick_irq(void *opaque) CPUTimer *timer =3D env->hstick; =20 if (timer->disabled) { - CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); + trace_sparc64_cpu_hstick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("hstick: fire\n"); + trace_sparc64_cpu_hstick_irq_fire(); } =20 env->softint |=3D SOFTINT_STIMER; @@ -280,9 +262,9 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count) int64_t vm_clock_offset =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - cpu_to_timer_ticks(real_count, timer->frequency); =20 - TIMER_DPRINTF("%s set_count count=3D0x%016lx (npt %s) p=3D%p\n", - timer->name, real_count, - timer->npt ? "disabled" : "enabled", timer); + trace_sparc64_cpu_tick_set_count(timer->name, real_count, + timer->npt ? "disabled" : "enabled", + timer); =20 timer->npt =3D npt_bit ? 1 : 0; timer->clock_offset =3D vm_clock_offset; @@ -294,9 +276,9 @@ uint64_t cpu_tick_get_count(CPUTimer *timer) qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_o= ffset, timer->frequency); =20 - TIMER_DPRINTF("%s get_count count=3D0x%016lx (npt %s) p=3D%p\n", - timer->name, real_count, - timer->npt ? "disabled" : "enabled", timer); + trace_sparc64_cpu_tick_get_count(timer->name, real_count, + timer->npt ? "disabled" : "enabled", + timer); =20 if (timer->npt) { real_count |=3D timer->npt_mask; @@ -319,18 +301,19 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t lim= it) expires =3D now + 1; } =20 - TIMER_DPRINTF("%s set_limit limit=3D0x%016lx (%s) p=3D%p " - "called with limit=3D0x%016lx at 0x%016lx (delta=3D0x%01= 6lx)\n", - timer->name, real_limit, - timer->disabled ? "disabled" : "enabled", - timer, limit, - timer_to_cpu_ticks(now - timer->clock_offset, - timer->frequency), - timer_to_cpu_ticks(expires - now, timer->frequency)); + trace_sparc64_cpu_tick_set_limit(timer->name, real_limit, + timer->disabled ? "disabled" : "enabl= ed", + timer, limit, + timer_to_cpu_ticks( + now - timer->clock_offset, + timer->frequency + ), + timer_to_cpu_ticks( + expires - now, timer->frequency + )); =20 if (!real_limit) { - TIMER_DPRINTF("%s set_limit limit=3DZERO - not starting timer\n", - timer->name); + trace_sparc64_cpu_tick_set_limit_zero(timer->name); timer_del(timer->qtimer); } else if (timer->disabled) { timer_del(timer->qtimer); diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index 2ee2d75f70..cf0888581d 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -7,3 +7,21 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d lev= el %d" sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRI= x64" val: 0x%"PRIx64" size: %d" sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PR= Ix64" val: 0x%"PRIx64" size: %d" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "x= late 0x%"PRIx64" =3D> pa 0x%"PRIx64" tte: 0x%"PRIx64 + +# hw/sparc64/sparc64.c +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interr= upt 0x%x)" +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not= setting CPU IRQ: TL=3D%d current 0x%x >=3D pending 0x%x" +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU = IRQ %d old=3D0x%x new=3D0x%x" +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t so= ftint, int intno) "Interrupts disabled, pil=3D0x%08x pil_in=3D0x%08x softin= t=3D0x%08x current interrupt 0x%x" +sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" +sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" +sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" +sparc64_cpu_tick_irq_fire(void) "tick_irq: fire" +sparc64_cpu_stick_irq_disabled(void) "stick_irq: softint disabled" +sparc64_cpu_stick_irq_fire(void) "stick_irq: fire" +sparc64_cpu_hstick_irq_disabled(void) "hstick_irq: softint disabled" +sparc64_cpu_hstick_irq_fire(void) "hstick_irq: fire" +sparc64_cpu_tick_set_count(const char *name, uint64_t real_count, const ch= ar *npt, void *p) "%s set_count count=3D0x%016lx (npt %s) p=3D%p" +sparc64_cpu_tick_get_count(const char *name, uint64_t real_count, const ch= ar *npt, void *p) "%s get_count count=3D0x%016lx (npt %s) p=3D%p" +sparc64_cpu_tick_set_limit(const char *name, uint64_t real_limit, const ch= ar *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit li= mit=3D0x%016lx (%s) p=3D%p called with limit=3D0x%016lx at 0x%016lx (delta= =3D0x%016lx)" +sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=3DZE= RO - not starting timer" --=20 2.11.0