From nobody Tue May 14 11:33:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516106272048556.1454720604153; Tue, 16 Jan 2018 04:37:52 -0800 (PST) Received: from localhost ([::1]:33338 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebQUx-0005cD-Ae for importer@patchew.org; Tue, 16 Jan 2018 07:37:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebQTe-0004ut-Hf for qemu-devel@nongnu.org; Tue, 16 Jan 2018 07:36:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebQTa-0004Sr-Ft for qemu-devel@nongnu.org; Tue, 16 Jan 2018 07:36:30 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59998) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ebQTP-0004IT-QQ; Tue, 16 Jan 2018 07:36:16 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 08869C0567A3; Tue, 16 Jan 2018 12:36:08 +0000 (UTC) Received: from localhost.localdomain.com (unknown [10.35.7.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 276EE5D70C; Tue, 16 Jan 2018 12:35:41 +0000 (UTC) From: Yoni Bettan To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 14:34:56 +0200 Message-Id: <20180116123456.32388-1-ybettan@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 16 Jan 2018 12:36:13 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V6] pci: removed the is_express field since a uniform interface was inserted X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Hannes Reinecke , Stefano Stabellini , Fam Zheng , "open list:X86" , "open list:nvme" , "Michael S. Tsirkin" , Yoni Bettan , Alex Williamson , Max Reitz , Keith Busch , Dmitry Fleytman , Paul Burton , Gerd Hoffmann , Anthony Perard , Marcel Apfelbaum , Paolo Bonzini , Jason Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" according to Eduardo Habkost's commit fd3b02c889 all PCIEs now implement INTERFACE_PCIE_DEVICE so we don't need is_express field anymore. Devices that implements only INTERFACE_PCIE_DEVICE (is_express =3D=3D 1) or devices that implements only INTERFACE_CONVENTIONAL_PCI_DEVICE (is_express = =3D=3D 0) where not affected by the change. The only devices that were affected are those that are hybrid and also had (is_express =3D=3D 1) - therefor only: - hw/vfio/pci.c - hw/usb/hcd-xhci.c - hw/xen/xen_pt.c For those 3 I made sure that QEMU_PCI_CAP_EXPRESS is on in instance_init() Reviewed-by: Marcel Apfelbaum Reviewed-by: Eduardo Habkost Signed-off-by: Yoni Bettan --- V5 --> V6 : rebased on Michael S. Tsirkin pci branch as requested. V4 --> V5 : updated the patch to work with a new inserted device hw/xen/xen= _pt.c V3 --> V4 : added a comment on the devices to explain why cap_present is set manually V2 --> V3 : turned the cap_present on in instance_init instead of a pre-reallize function that was created just for that purpose V1 --> V2 : V1 was asked to be ignored docs/pcie_pci_bridge.txt | 2 +- hw/block/nvme.c | 1 - hw/net/e1000e.c | 1 - hw/pci-bridge/pcie_pci_bridge.c | 1 - hw/pci-bridge/pcie_root_port.c | 1 - hw/pci-bridge/xio3130_downstream.c | 1 - hw/pci-bridge/xio3130_upstream.c | 1 - hw/pci-host/xilinx-pcie.c | 1 - hw/pci/pci.c | 8 ++++++-- hw/scsi/megasas.c | 4 ---- hw/usb/hcd-xhci.c | 9 ++++++++- hw/vfio/pci.c | 5 ++++- hw/xen/xen_pt.c | 9 ++++++++- include/hw/pci/pci.h | 3 --- 14 files changed, 27 insertions(+), 20 deletions(-) diff --git a/docs/pcie_pci_bridge.txt b/docs/pcie_pci_bridge.txt index 5a4203f97c..ab35ebf3ca 100644 --- a/docs/pcie_pci_bridge.txt +++ b/docs/pcie_pci_bridge.txt @@ -110,5 +110,5 @@ To enable device hot-plug into the bridge on Linux ther= e're 3 ways: Implementation =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI E= xpress -features as a PCI Express device (is_express=3D1). +features as a PCI Express device. =20 diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1ac356d3a5..c4c7a0a1c5 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1331,7 +1331,6 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0x5845; pc->revision =3D 2; - pc->is_express =3D 1; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc =3D "Non-Volatile Memory Express"; diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 191398a3d5..16a9417a85 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -675,7 +675,6 @@ static void e1000e_class_init(ObjectClass *class, void = *data) c->revision =3D 0; c->romfile =3D "efi-e1000e.rom"; c->class_id =3D PCI_CLASS_NETWORK_ETHERNET; - c->is_express =3D 1; =20 dc->desc =3D "Intel 82574L GbE Controller"; dc->reset =3D e1000e_qdev_reset; diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index a4d827c99d..b7d9ebbec2 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -169,7 +169,6 @@ static void pcie_pci_bridge_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 9b6e4ce512..45f9e8cd4a 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -145,7 +145,6 @@ static void rp_class_init(ObjectClass *klass, void *dat= a) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D rp_write_config; k->realize =3D rp_realize; diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 1e09d2afb7..613a0d6bb7 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -177,7 +177,6 @@ static void xio3130_downstream_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_downstream_write_config; k->realize =3D xio3130_downstream_realize; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 227997ce46..d4645bddee 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -148,7 +148,6 @@ static void xio3130_upstream_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_upstream_write_config; k->realize =3D xio3130_upstream_realize; diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 53b561f81f..044e312dc1 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -297,7 +297,6 @@ static void xilinx_pcie_root_class_init(ObjectClass *kl= ass, void *data) k->device_id =3D 0x7021; k->revision =3D 0; k->class_id =3D PCI_CLASS_BRIDGE_HOST; - k->is_express =3D true; k->is_bridge =3D true; k->realize =3D xilinx_pcie_root_realize; k->exit =3D pci_bridge_exitfn; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e8f9fc1c27..fa918184cf 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2005,11 +2005,15 @@ static void pci_qdev_realize(DeviceState *qdev, Err= or **errp) { PCIDevice *pci_dev =3D (PCIDevice *)qdev; PCIDeviceClass *pc =3D PCI_DEVICE_GET_CLASS(pci_dev); + ObjectClass *klass =3D OBJECT_CLASS(pc); Error *local_err =3D NULL; bool is_default_rom; =20 - /* initialize cap_present for pci_is_express() and pci_config_size() */ - if (pc->is_express) { + /* initialize cap_present for pci_is_express() and pci_config_size(), + * Note that hybrid PCIs are not set automatically and need to manage + * QEMU_PCI_CAP_EXPRESS manually */ + if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && + !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE= )) { pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 3e38e9e8aa..ba1afa3c1e 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2447,7 +2447,6 @@ typedef struct MegasasInfo { uint16_t subsystem_id; int ioport_bar; int mmio_bar; - bool is_express; int osts; const VMStateDescription *vmsd; Property *props; @@ -2465,7 +2464,6 @@ static struct MegasasInfo megasas_devices[] =3D { .ioport_bar =3D 2, .mmio_bar =3D 0, .osts =3D MFI_1078_RM | 1, - .is_express =3D false, .vmsd =3D &vmstate_megasas_gen1, .props =3D megasas_properties_gen1, .interfaces =3D (InterfaceInfo[]) { @@ -2482,7 +2480,6 @@ static struct MegasasInfo megasas_devices[] =3D { .ioport_bar =3D 0, .mmio_bar =3D 1, .osts =3D MFI_GEN2_RM, - .is_express =3D true, .vmsd =3D &vmstate_megasas_gen2, .props =3D megasas_properties_gen2, .interfaces =3D (InterfaceInfo[]) { @@ -2506,7 +2503,6 @@ static void megasas_class_init(ObjectClass *oc, void = *data) pc->subsystem_vendor_id =3D PCI_VENDOR_ID_LSI_LOGIC; pc->subsystem_id =3D info->subsystem_id; pc->class_id =3D PCI_CLASS_STORAGE_RAID; - pc->is_express =3D info->is_express; e->mmio_bar =3D info->mmio_bar; e->ioport_bar =3D info->ioport_bar; e->osts =3D info->osts; diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 228e82b3fb..721beb5486 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3649,6 +3649,13 @@ static Property xhci_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void xhci_instance_init(Object *obj) +{ + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command + * line, therefore, no need to wait to realize like other devices */ + PCI_DEVICE(obj)->cap_present |=3D QEMU_PCI_CAP_EXPRESS; +} + static void xhci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); @@ -3661,7 +3668,6 @@ static void xhci_class_init(ObjectClass *klass, void = *data) k->realize =3D usb_xhci_realize; k->exit =3D usb_xhci_exit; k->class_id =3D PCI_CLASS_SERIAL_USB; - k->is_express =3D 1; } =20 static const TypeInfo xhci_info =3D { @@ -3669,6 +3675,7 @@ static const TypeInfo xhci_info =3D { .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(XHCIState), .class_init =3D xhci_class_init, + .instance_init =3D xhci_instance_init, .abstract =3D true, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_PCIE_DEVICE }, diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 2c71295125..00e76e2aaa 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -2972,6 +2972,10 @@ static void vfio_instance_init(Object *obj) vdev->host.function =3D ~0U; =20 vdev->nv_gpudirect_clique =3D 0xFF; + + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command + * line, therefore, no need to wait to realize like other devices */ + pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 static Property vfio_pci_dev_properties[] =3D { @@ -3026,7 +3030,6 @@ static void vfio_pci_dev_class_init(ObjectClass *klas= s, void *data) pdc->exit =3D vfio_exitfn; pdc->config_read =3D vfio_pci_read_config; pdc->config_write =3D vfio_pci_write_config; - pdc->is_express =3D 1; /* We might be */ } =20 static const TypeInfo vfio_pci_dev_info =3D { diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index f662f30370..9b7a960de1 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -937,6 +937,13 @@ static Property xen_pci_passthrough_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void xen_pci_passthrough_instance_init(Object *obj) +{ + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command + * line, therefore, no need to wait to realize like other devices */ + PCI_DEVICE(obj)->cap_present |=3D QEMU_PCI_CAP_EXPRESS; +} + static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -946,7 +953,6 @@ static void xen_pci_passthrough_class_init(ObjectClass = *klass, void *data) k->exit =3D xen_pt_unregister_device; k->config_read =3D xen_pt_pci_read_config; k->config_write =3D xen_pt_pci_write_config; - k->is_express =3D 1; /* We might be */ set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc =3D "Assign an host PCI device with Xen"; dc->props =3D xen_pci_passthrough_properties; @@ -965,6 +971,7 @@ static const TypeInfo xen_pci_passthrough_info =3D { .instance_size =3D sizeof(XenPCIPassthroughState), .instance_finalize =3D xen_pci_passthrough_finalize, .class_init =3D xen_pci_passthrough_class_init, + .instance_init =3D xen_pci_passthrough_instance_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { INTERFACE_PCIE_DEVICE }, diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 15ced9648c..d8c18c7fa4 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -236,9 +236,6 @@ typedef struct PCIDeviceClass { */ int is_bridge; =20 - /* pcie stuff */ - int is_express; /* is this device pci express? */ - /* rom bar */ const char *romfile; } PCIDeviceClass; --=20 2.14.3