From nobody Thu May 2 17:46:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151589562211366.33150553775295; Sat, 13 Jan 2018 18:07:02 -0800 (PST) Received: from localhost ([::1]:56099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaXhB-0008F8-K9 for importer@patchew.org; Sat, 13 Jan 2018 21:06:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaXfD-00075V-Ip for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaXfA-0006pH-63 for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:47 -0500 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:36254) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eaXfA-0006p5-1z for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:44 -0500 Received: by mail-qt0-x241.google.com with SMTP id a16so10483451qtj.3 for ; Sat, 13 Jan 2018 18:04:43 -0800 (PST) Received: from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id p8sm13333337qki.61.2018.01.13.18.04.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 13 Jan 2018 18:04:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DtTiPZOvQN4aAeS/CGzwffbKmOoY6W+5xdOKjNstNkg=; b=J1sKc/8EDES6vahpe3RD13G6qnz1BS6xc60XOBTIC1/BrrkngVJ5dWxCDpdxJ6/kfd 7h8RQy8gs9zvwhFGc0dS2leBJhj0gkSKRbzYlj649D83ZQZKCOh3WKpH/hFHUqpW5SRc WgH4eqQuMQH2g5WC4Cuiury1fERyScjv/6xJRifKlgvzmgjbR/SerZ9anRYgXp/A0oJT W5hCG4I0dgqTfGAg7amAIdWCH5ivs/ldq5xTzUmmxHYWrnIA0U3+xGKILmk47Z/+/aYi XqfaCiEqq5z8ygFH/gTUZbx3OOIAKHY86Ayb1vVwrqmKwhFz1/s2C2HNmxa8B3J1FllV 2gTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DtTiPZOvQN4aAeS/CGzwffbKmOoY6W+5xdOKjNstNkg=; b=YWlXD2EGZ8Oz0GDLCwYORBG11M/CDNMPakd/zvk3oRy2dXHbvLSzDXx2lfETcAef7o v6aYFStbJqA3vtkhiIldNH/OWLatDv8YsG1JKwhtIrU9XFNSgXYZA9+8tBSGx26gHlo9 pNryZVZQZW8lQd2zfQfgYvtnjkUHvVQbrl/SCti8o3bNzWbXKZZ8oM1bJbrFIUEPheac PgGAwLeay4vI47gcWf+Q+eSc6AdekwCBsTO3Mu/leu8mEwjVpzSqgl3Sawj5/jFZOnhD 3iXOCEweHSCYwFsp+lDTcEBe2bI1SDGY3+hrpZQkC3/MEgHcj38GFCtItNkwq/uFW4NC 78aA== X-Gm-Message-State: AKwxytfKF060ViW1aDPwAJBSZ6nMfIELCEYRJPv9QB+jZmoNhWlBEAzV ir3iRtzNB9vlQxrmGMXgRQY= X-Google-Smtp-Source: ACJfBottWrhr9MOp9xQUKBT4MyKK3EkdjTm2YiHybDCXiMRUwDQMHGCXNriPRJR1m0xreNspdJPkig== X-Received: by 10.200.7.137 with SMTP id l9mr40974029qth.113.1515895483566; Sat, 13 Jan 2018 18:04:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , Marcel Apfelbaum Date: Sat, 13 Jan 2018 23:04:10 -0300 Message-Id: <20180114020412.26160-2-f4bug@amsat.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180114020412.26160-1-f4bug@amsat.org> References: <20180114020412.26160-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [RFC PATCH 1/3] qdev: rename typedef qdev_resetfn() -> DeviceReset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Michael Roth , Markus Armbruster , Paolo Bonzini , "Dr. David Alan Gilbert" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 following the DeviceRealize and DeviceUnrealize typedefs, this unify a bit the new QOM API. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Laurent Vivier --- include/hw/qdev-core.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 0a71bf83f0..83db53b3f5 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -32,9 +32,9 @@ typedef enum DeviceCategory { =20 typedef int (*qdev_initfn)(DeviceState *dev); typedef int (*qdev_event)(DeviceState *dev); -typedef void (*qdev_resetfn)(DeviceState *dev); typedef void (*DeviceRealize)(DeviceState *dev, Error **errp); typedef void (*DeviceUnrealize)(DeviceState *dev, Error **errp); +typedef void (*DeviceReset)(DeviceState *dev); typedef void (*BusRealize)(BusState *bus, Error **errp); typedef void (*BusUnrealize)(BusState *bus, Error **errp); =20 @@ -117,7 +117,7 @@ typedef struct DeviceClass { bool hotpluggable; =20 /* callbacks */ - void (*reset)(DeviceState *dev); + DeviceReset reset; DeviceRealize realize; DeviceUnrealize unrealize; =20 --=20 2.15.1 From nobody Thu May 2 17:46:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515895735822733.8758039123163; Sat, 13 Jan 2018 18:08:55 -0800 (PST) Received: from localhost ([::1]:56254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaXjD-0001SR-2v for importer@patchew.org; Sat, 13 Jan 2018 21:08:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaXfE-00075p-LD for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaXfD-0006sI-Mc for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:48 -0500 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:42880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eaXfD-0006s1-H0 for qemu-devel@nongnu.org; Sat, 13 Jan 2018 21:04:47 -0500 Received: by mail-qk0-x241.google.com with SMTP id q1so13190877qkb.9 for ; Sat, 13 Jan 2018 18:04:47 -0800 (PST) Received: from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id p8sm13333337qki.61.2018.01.13.18.04.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 13 Jan 2018 18:04:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VwpC2BSJkYWjs9/XAE2+QWljRXUqcphSj9hm+mNO7zw=; b=FqUrrIcPRnfnEQ0ihxj+Yicsk6NOwVl3XR3lqhH15TGp/zfBF+o1LZJ3oIDjVWIzQr RC+JGcYvsdS6X43frW99feOUgSueij1+SgdgfmxXhj1oTSOQnjKvIBa0/KuOzYh94t3B YENzPU6F/Cb+HX3h4qpWvKlTfll84E36pvoA6IdBi5aK6336TPz1qqMslboX9ekF5tN+ DA41bk9hY6ZIBZ8nBh3RVSBjCBtNA/iR/cQDwwgqR+YhbmA2aP5BDS7mk3BP3hL08SMU lfuJxSCHuJGKcQWENOXaPvjPAWpFfJ3KZIEeDgvTRM9ExS2BxiPe0PbrK0l0XQjWrt9t SCcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VwpC2BSJkYWjs9/XAE2+QWljRXUqcphSj9hm+mNO7zw=; b=sW5gp2CIKZY1lb6OKmeK0fFVZmakYQKcwJuczPlyScEfuhZu1b1493TZajrMkr9GJx SAJ9x1jCQL7vxOKXa5s9RlVYAUltBw7D19oKEfwPdo4B1oZUylth+y4eUf1TPhONUvGN x/+Xysa3cjZGthtvC/Q330BEIWA71gO7Vz/UsrJQUA6fkbwKZCcBmE96l2FxK+xxKG3v pnZczhi/RpLkPhuvCisWpbenBIwY5c9CHY106GlV6MW70/h0aW5r9d+39RFFMvMU59zr tJmkocqjXD0OHtrLcL1FBOxDp3DyhiDnvFHPJbVFzdz2cf1ua+XDQ8B628GY9UT5GTse AXNg== X-Gm-Message-State: AKwxyte50eKcL31oxTSRzYCbjQGIOp8RiZQRRx3fq8NBbP2SYxr9D+hL /Q995Vz3VJH+ZVn0vudGkBY= X-Google-Smtp-Source: ACJfBou6u8AaA1utCnHkmmvayvejJwRGrtT/+XfYeksG/xy0MCGpQHYeK2X4hsyojW1zVA9NKbzcKQ== X-Received: by 10.55.212.129 with SMTP id s1mr44984584qks.44.1515895487014; Sat, 13 Jan 2018 18:04:47 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , Marcel Apfelbaum Date: Sat, 13 Jan 2018 23:04:11 -0300 Message-Id: <20180114020412.26160-3-f4bug@amsat.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180114020412.26160-1-f4bug@amsat.org> References: <20180114020412.26160-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [RFC PATCH 2/3] qdev: add helpers to be more explicit when using abstract QOM parent functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Michael Roth , Markus Armbruster , Paolo Bonzini , "Dr. David Alan Gilbert" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 QOM API learning curve is quite hard, in particular when devices inherit fr= om abstract parent. To be more explicit about when a device class change the parent hooks, add = few helpers hoping a device class_init() will be easier to understand. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Laurent Vivier --- include/hw/qdev-core.h | 10 ++++++++++ hw/core/qdev.c | 24 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 83db53b3f5..0fc53b33d0 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -381,6 +381,16 @@ void qdev_machine_init(void); */ void device_reset(DeviceState *dev); =20 +void device_class_set_parent_reset(DeviceClass *dc, + DeviceReset dev_reset, + DeviceReset *parent_reset); +void device_class_set_parent_realize(DeviceClass *dc, + DeviceRealize dev_realize, + DeviceRealize *parent_realize); +void device_class_set_parent_unrealize(DeviceClass *dc, + DeviceUnrealize dev_unrealize, + DeviceUnrealize *parent_unrealize); + const struct VMStateDescription *qdev_get_vmsd(DeviceState *dev); =20 const char *qdev_fw_name(DeviceState *dev); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 11112951a5..a71cd264e2 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -1140,6 +1140,30 @@ static void device_class_init(ObjectClass *class, vo= id *data) dc->user_creatable =3D true; } =20 +void device_class_set_parent_reset(DeviceClass *dc, + DeviceReset dev_reset, + DeviceReset *parent_reset) +{ + *parent_reset =3D dc->reset; + dc->reset =3D dev_reset; +} + +void device_class_set_parent_realize(DeviceClass *dc, + DeviceRealize dev_realize, + DeviceRealize *parent_realize) +{ + *parent_realize =3D dc->realize; + dc->realize =3D dev_realize; +} + +void device_class_set_parent_unrealize(DeviceClass *dc, + DeviceUnrealize dev_unrealize, + DeviceUnrealize *parent_unrealize) +{ + *parent_unrealize =3D dc->unrealize; + dc->unrealize =3D dev_unrealize; +} + void device_reset(DeviceState *dev) { DeviceClass *klass =3D DEVICE_GET_CLASS(dev); --=20 2.15.1 From nobody Thu May 2 17:46:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [RFC PATCH 3/3] qdev: use device_class_set_parent_realize/unrealize/reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , Jason Wang , Mark Cave-Ayland , qemu-devel@nongnu.org, Markus Armbruster , Max Filippov , Dmitry Fleytman , "Edgar E. Iglesias" , Guan Xuetao , Yongbok Kim , Marek Vasut , Michael Roth , David Gibson , Anthony Green , Artyom Tarasenko , Fam Zheng , "Dr. David Alan Gilbert" , Alex Williamson , "open list:ARM cores" , Stafford Horne , Richard Henderson , Alexander Graf , "open list:S390" , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Michael Walle , "open list:PowerPC" , Paolo Bonzini , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn =3D dc->realize; ... -dc->realize =3D child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn =3D dc->unrealize; ... -dc->unrealize =3D child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn =3D dc->reset; ... -dc->reset =3D child_fn; ) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Cornelia Huck Acked-by: David Gibson Reviewed-by: Laurent Vivier Reviewed-by: Marcel Apfelbaum --- hw/i386/kvm/i8254.c | 4 ++-- hw/i386/kvm/i8259.c | 3 +-- hw/input/adb-kbd.c | 4 ++-- hw/input/adb-mouse.c | 4 ++-- hw/intc/arm_gic.c | 3 +-- hw/intc/arm_gic_kvm.c | 7 +++---- hw/intc/arm_gicv3.c | 3 +-- hw/intc/arm_gicv3_its_kvm.c | 3 +-- hw/intc/arm_gicv3_kvm.c | 7 +++---- hw/intc/i8259.c | 3 +-- hw/net/vmxnet3.c | 4 ++-- hw/pci-bridge/gen_pcie_root_port.c | 3 +-- hw/scsi/vmw_pvscsi.c | 4 ++-- hw/timer/i8254.c | 3 +-- hw/vfio/amd-xgbe.c | 4 ++-- hw/vfio/calxeda-xgmac.c | 4 ++-- hw/virtio/virtio-pci.c | 4 ++-- target/alpha/cpu.c | 4 ++-- target/arm/cpu.c | 4 ++-- target/cris/cpu.c | 4 ++-- target/hppa/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/lm32/cpu.c | 5 ++--- target/m68k/cpu.c | 5 ++--- target/microblaze/cpu.c | 5 ++--- target/mips/cpu.c | 5 ++--- target/moxie/cpu.c | 5 ++--- target/nios2/cpu.c | 4 ++-- target/openrisc/cpu.c | 5 ++--- target/ppc/translate_init.c | 8 ++++---- target/s390x/cpu.c | 4 ++-- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 4 ++-- target/tilegx/cpu.c | 4 ++-- target/tricore/cpu.c | 4 ++-- target/unicore32/cpu.c | 4 ++-- target/xtensa/cpu.c | 4 ++-- 37 files changed, 73 insertions(+), 88 deletions(-) diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c index 521a58498a..13f20f47d9 100644 --- a/hw/i386/kvm/i8254.c +++ b/hw/i386/kvm/i8254.c @@ -315,8 +315,8 @@ static void kvm_pit_class_init(ObjectClass *klass, void= *data) PITCommonClass *k =3D PIT_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - kpc->parent_realize =3D dc->realize; - dc->realize =3D kvm_pit_realizefn; + device_class_set_parent_realize(dc, kvm_pit_realizefn, + &kpc->parent_realize); k->set_channel_gate =3D kvm_pit_set_gate; k->get_channel_info =3D kvm_pit_get_channel_info; dc->reset =3D kvm_pit_reset; diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index b91e98074e..05394cdb7b 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -142,8 +142,7 @@ static void kvm_i8259_class_init(ObjectClass *klass, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->reset =3D kvm_pic_reset; - kpc->parent_realize =3D dc->realize; - dc->realize =3D kvm_pic_realize; + device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_real= ize); k->pre_save =3D kvm_pic_get; k->post_load =3D kvm_pic_put; } diff --git a/hw/input/adb-kbd.c b/hw/input/adb-kbd.c index 354f56e41e..266aed1b7b 100644 --- a/hw/input/adb-kbd.c +++ b/hw/input/adb-kbd.c @@ -374,8 +374,8 @@ static void adb_kbd_class_init(ObjectClass *oc, void *d= ata) ADBDeviceClass *adc =3D ADB_DEVICE_CLASS(oc); ADBKeyboardClass *akc =3D ADB_KEYBOARD_CLASS(oc); =20 - akc->parent_realize =3D dc->realize; - dc->realize =3D adb_kbd_realizefn; + device_class_set_parent_realize(dc, adb_kbd_realizefn, + &akc->parent_realize); set_bit(DEVICE_CATEGORY_INPUT, dc->categories); =20 adc->devreq =3D adb_kbd_request; diff --git a/hw/input/adb-mouse.c b/hw/input/adb-mouse.c index c9004233b8..47e88faf25 100644 --- a/hw/input/adb-mouse.c +++ b/hw/input/adb-mouse.c @@ -228,8 +228,8 @@ static void adb_mouse_class_init(ObjectClass *oc, void = *data) ADBDeviceClass *adc =3D ADB_DEVICE_CLASS(oc); ADBMouseClass *amc =3D ADB_MOUSE_CLASS(oc); =20 - amc->parent_realize =3D dc->realize; - dc->realize =3D adb_mouse_realizefn; + device_class_set_parent_realize(dc, adb_mouse_realizefn, + &amc->parent_realize); set_bit(DEVICE_CATEGORY_INPUT, dc->categories); =20 adc->devreq =3D adb_mouse_request; diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d701e49ff9..9e0a5ea725 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1444,8 +1444,7 @@ static void arm_gic_class_init(ObjectClass *klass, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(klass); ARMGICClass *agc =3D ARM_GIC_CLASS(klass); =20 - agc->parent_realize =3D dc->realize; - dc->realize =3D arm_gic_realize; + device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } =20 static const TypeInfo arm_gic_info =3D { diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index ae095d08a3..6f467e68a8 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -591,10 +591,9 @@ static void kvm_arm_gic_class_init(ObjectClass *klass,= void *data) =20 agcc->pre_save =3D kvm_arm_gic_get; agcc->post_load =3D kvm_arm_gic_put; - kgc->parent_realize =3D dc->realize; - kgc->parent_reset =3D dc->reset; - dc->realize =3D kvm_arm_gic_realize; - dc->reset =3D kvm_arm_gic_reset; + device_class_set_parent_realize(dc, kvm_arm_gic_realize, + &kgc->parent_realize); + device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_rese= t); } =20 static const TypeInfo kvm_arm_gic_info =3D { diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index f0c967b304..479c66733c 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -385,8 +385,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, vo= id *data) ARMGICv3Class *agc =3D ARM_GICV3_CLASS(klass); =20 agcc->post_load =3D arm_gicv3_post_load; - agc->parent_realize =3D dc->realize; - dc->realize =3D arm_gic_realize; + device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } =20 static const TypeInfo arm_gicv3_info =3D { diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index bf290b8bff..eea6a73df2 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -245,11 +245,10 @@ static void kvm_arm_its_class_init(ObjectClass *klass= , void *data) =20 dc->realize =3D kvm_arm_its_realize; dc->props =3D kvm_arm_its_props; - ic->parent_reset =3D dc->reset; + device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset= ); icc->send_msi =3D kvm_its_send_msi; icc->pre_save =3D kvm_arm_its_pre_save; icc->post_load =3D kvm_arm_its_post_load; - dc->reset =3D kvm_arm_its_reset; } =20 static const TypeInfo kvm_arm_its_info =3D { diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 481fe5405a..ec371772b3 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -795,10 +795,9 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klas= s, void *data) =20 agcc->pre_save =3D kvm_arm_gicv3_get; agcc->post_load =3D kvm_arm_gicv3_put; - kgc->parent_realize =3D dc->realize; - kgc->parent_reset =3D dc->reset; - dc->realize =3D kvm_arm_gicv3_realize; - dc->reset =3D kvm_arm_gicv3_reset; + device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, + &kgc->parent_realize); + device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_re= set); } =20 static const TypeInfo kvm_arm_gicv3_info =3D { diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 1602255a87..76f3d873b8 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -443,8 +443,7 @@ static void i8259_class_init(ObjectClass *klass, void *= data) PICClass *k =3D PIC_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - k->parent_realize =3D dc->realize; - dc->realize =3D pic_realize; + device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); dc->reset =3D pic_reset; } =20 diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 0654d594c1..3648630386 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -2664,8 +2664,8 @@ static void vmxnet3_class_init(ObjectClass *class, vo= id *data) c->class_id =3D PCI_CLASS_NETWORK_ETHERNET; c->subsystem_vendor_id =3D PCI_VENDOR_ID_VMWARE; c->subsystem_id =3D PCI_DEVICE_ID_VMWARE_VMXNET3; - vc->parent_dc_realize =3D dc->realize; - dc->realize =3D vmxnet3_realize; + device_class_set_parent_realize(dc, vmxnet3_realize, + &vc->parent_dc_realize); dc->desc =3D "VMWare Paravirtualized Ethernet v3"; dc->reset =3D vmxnet3_qdev_reset; dc->vmsd =3D &vmstate_vmxnet3; diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index ad4e6aa7ff..4a3b13d02c 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -132,8 +132,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, v= oid *data) dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; =20 - rpc->parent_realize =3D dc->realize; - dc->realize =3D gen_rp_realize; + device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_reali= ze); =20 rpc->aer_vector =3D gen_rp_aer_vector; rpc->interrupts_init =3D gen_rp_interrupts_init; diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 27749c0e42..a3a019e30a 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1284,8 +1284,8 @@ static void pvscsi_class_init(ObjectClass *klass, voi= d *data) k->device_id =3D PCI_DEVICE_ID_VMWARE_PVSCSI; k->class_id =3D PCI_CLASS_STORAGE_SCSI; k->subsystem_id =3D 0x1000; - pvs_k->parent_dc_realize =3D dc->realize; - dc->realize =3D pvscsi_realize; + device_class_set_parent_realize(dc, pvscsi_realize, + &pvs_k->parent_dc_realize); dc->reset =3D pvscsi_reset; dc->vmsd =3D &vmstate_pvscsi; dc->props =3D pvscsi_properties; diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c index dbc4a0baec..1057850808 100644 --- a/hw/timer/i8254.c +++ b/hw/timer/i8254.c @@ -358,8 +358,7 @@ static void pit_class_initfn(ObjectClass *klass, void *= data) PITCommonClass *k =3D PIT_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - pc->parent_realize =3D dc->realize; - dc->realize =3D pit_realizefn; + device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize= ); k->set_channel_gate =3D pit_set_channel_gate; k->get_channel_info =3D pit_get_channel_info_common; k->post_load =3D pit_post_load; diff --git a/hw/vfio/amd-xgbe.c b/hw/vfio/amd-xgbe.c index fab196cebf..0c4ec4ba25 100644 --- a/hw/vfio/amd-xgbe.c +++ b/hw/vfio/amd-xgbe.c @@ -34,8 +34,8 @@ static void vfio_amd_xgbe_class_init(ObjectClass *klass, = void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); VFIOAmdXgbeDeviceClass *vcxc =3D VFIO_AMD_XGBE_DEVICE_CLASS(klass); - vcxc->parent_realize =3D dc->realize; - dc->realize =3D amd_xgbe_realize; + device_class_set_parent_realize(dc, amd_xgbe_realize, + &vcxc->parent_realize); dc->desc =3D "VFIO AMD XGBE"; dc->vmsd =3D &vfio_platform_amd_xgbe_vmstate; /* Supported by TYPE_VIRT_MACHINE */ diff --git a/hw/vfio/calxeda-xgmac.c b/hw/vfio/calxeda-xgmac.c index 7bb17af7ad..24cee6d065 100644 --- a/hw/vfio/calxeda-xgmac.c +++ b/hw/vfio/calxeda-xgmac.c @@ -34,8 +34,8 @@ static void vfio_calxeda_xgmac_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); VFIOCalxedaXgmacDeviceClass *vcxc =3D VFIO_CALXEDA_XGMAC_DEVICE_CLASS(klass); - vcxc->parent_realize =3D dc->realize; - dc->realize =3D calxeda_xgmac_realize; + device_class_set_parent_realize(dc, calxeda_xgmac_realize, + &vcxc->parent_realize); dc->desc =3D "VFIO Calxeda XGMAC"; dc->vmsd =3D &vfio_platform_calxeda_xgmac_vmstate; /* Supported by TYPE_VIRT_MACHINE */ diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 6c75cca88a..3eeb98c4cf 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1907,8 +1907,8 @@ static void virtio_pci_class_init(ObjectClass *klass,= void *data) k->vendor_id =3D PCI_VENDOR_ID_REDHAT_QUMRANET; k->revision =3D VIRTIO_PCI_ABI_VERSION; k->class_id =3D PCI_CLASS_OTHERS; - vpciklass->parent_dc_realize =3D dc->realize; - dc->realize =3D virtio_pci_dc_realize; + device_class_set_parent_realize(dc, virtio_pci_dc_realize, + &vpciklass->parent_dc_realize); dc->reset =3D virtio_pci_reset; } =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d6366bae9..55675ce419 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -233,8 +233,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); AlphaCPUClass *acc =3D ALPHA_CPU_CLASS(oc); =20 - acc->parent_realize =3D dc->realize; - dc->realize =3D alpha_cpu_realizefn; + device_class_set_parent_realize(dc, alpha_cpu_realizefn, + &acc->parent_realize); =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cc1856c32b..2b29747b9f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1722,8 +1722,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(acc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - acc->parent_realize =3D dc->realize; - dc->realize =3D arm_cpu_realizefn; + device_class_set_parent_realize(dc, arm_cpu_realizefn, + &acc->parent_realize); dc->props =3D arm_cpu_properties; =20 acc->parent_reset =3D cc->reset; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 949c7a6e25..db8d0884a1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -260,8 +260,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 - ccc->parent_realize =3D dc->realize; - dc->realize =3D cris_cpu_realizefn; + device_class_set_parent_realize(dc, cris_cpu_realizefn, + &ccc->parent_realize); =20 ccc->parent_reset =3D cc->reset; cc->reset =3D cris_cpu_reset; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9e7b0d4ccb..899464ae87 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -121,8 +121,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) CPUClass *cc =3D CPU_CLASS(oc); HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); =20 - acc->parent_realize =3D dc->realize; - dc->realize =3D hppa_cpu_realizefn; + device_class_set_parent_realize(dc, hppa_cpu_realizefn, + &acc->parent_realize); =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->do_interrupt =3D hppa_cpu_do_interrupt; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3818d72831..3573cfab65 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4216,10 +4216,10 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - xcc->parent_realize =3D dc->realize; - xcc->parent_unrealize =3D dc->unrealize; - dc->realize =3D x86_cpu_realizefn; - dc->unrealize =3D x86_cpu_unrealizefn; + device_class_set_parent_realize(dc, x86_cpu_realizefn, + &xcc->parent_realize); + device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, + &xcc->parent_unrealize); dc->props =3D x86_cpu_properties; =20 xcc->parent_reset =3D cc->reset; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 6f5c14767b..96c2499d0b 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -236,9 +236,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - lcc->parent_realize =3D dc->realize; - dc->realize =3D lm32_cpu_realizefn; - + device_class_set_parent_realize(dc, lm32_cpu_realizefn, + &lcc->parent_realize); lcc->parent_reset =3D cc->reset; cc->reset =3D lm32_cpu_reset; =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 03126ba543..a07c568297 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -255,9 +255,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) CPUClass *cc =3D CPU_CLASS(c); DeviceClass *dc =3D DEVICE_CLASS(c); =20 - mcc->parent_realize =3D dc->realize; - dc->realize =3D m68k_cpu_realizefn; - + device_class_set_parent_realize(dc, m68k_cpu_realizefn, + &mcc->parent_realize); mcc->parent_reset =3D cc->reset; cc->reset =3D m68k_cpu_reset; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5700652e06..d8df2fb07e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -258,9 +258,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) CPUClass *cc =3D CPU_CLASS(oc); MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_CLASS(oc); =20 - mcc->parent_realize =3D dc->realize; - dc->realize =3D mb_cpu_realizefn; - + device_class_set_parent_realize(dc, mb_cpu_realizefn, + &mcc->parent_realize); mcc->parent_reset =3D cc->reset; cc->reset =3D mb_cpu_reset; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 069f93560e..497706b669 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -174,9 +174,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) CPUClass *cc =3D CPU_CLASS(c); DeviceClass *dc =3D DEVICE_CLASS(c); =20 - mcc->parent_realize =3D dc->realize; - dc->realize =3D mips_cpu_realizefn; - + device_class_set_parent_realize(dc, mips_cpu_realizefn, + &mcc->parent_realize); mcc->parent_reset =3D cc->reset; cc->reset =3D mips_cpu_reset; =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index f1389e5097..4170284da6 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -102,9 +102,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); MoxieCPUClass *mcc =3D MOXIE_CPU_CLASS(oc); =20 - mcc->parent_realize =3D dc->realize; - dc->realize =3D moxie_cpu_realizefn; - + device_class_set_parent_realize(dc, moxie_cpu_realizefn, + &mcc->parent_realize); mcc->parent_reset =3D cc->reset; cc->reset =3D moxie_cpu_reset; =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 4742e52c78..fbfaa2ce26 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -187,8 +187,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); Nios2CPUClass *ncc =3D NIOS2_CPU_CLASS(oc); =20 - ncc->parent_realize =3D dc->realize; - dc->realize =3D nios2_cpu_realizefn; + device_class_set_parent_realize(dc, nios2_cpu_realizefn, + &ncc->parent_realize); dc->props =3D nios2_properties; ncc->parent_reset =3D cc->reset; cc->reset =3D nios2_cpu_reset; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e0394b8b06..20b115afae 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -132,9 +132,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) CPUClass *cc =3D CPU_CLASS(occ); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - occ->parent_realize =3D dc->realize; - dc->realize =3D openrisc_cpu_realizefn; - + device_class_set_parent_realize(dc, openrisc_cpu_realizefn, + &occ->parent_realize); occ->parent_reset =3D cc->reset; cc->reset =3D openrisc_cpu_reset; =20 diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 70ff15a51a..566cf552e0 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -10556,12 +10556,12 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - pcc->parent_realize =3D dc->realize; - pcc->parent_unrealize =3D dc->unrealize; + device_class_set_parent_realize(dc, ppc_cpu_realizefn, + &pcc->parent_realize); + device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn, + &pcc->parent_unrealize); pcc->pvr_match =3D ppc_pvr_match_default; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; - dc->realize =3D ppc_cpu_realizefn; - dc->unrealize =3D ppc_cpu_unrealizefn; dc->props =3D ppc_cpu_properties; =20 pcc->parent_reset =3D cc->reset; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index ae3cee91a2..4c068cedff 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -463,8 +463,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) CPUClass *cc =3D CPU_CLASS(scc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - scc->parent_realize =3D dc->realize; - dc->realize =3D s390_cpu_realizefn; + device_class_set_parent_realize(dc, s390_cpu_realizefn, + &scc->parent_realize); dc->props =3D s390x_cpu_properties; dc->user_creatable =3D true; =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e0b99fbc89..e37c187ca2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,8 +236,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) CPUClass *cc =3D CPU_CLASS(oc); SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(oc); =20 - scc->parent_realize =3D dc->realize; - dc->realize =3D superh_cpu_realizefn; + device_class_set_parent_realize(dc, superh_cpu_realizefn, + &scc->parent_realize); =20 scc->parent_reset =3D cc->reset; cc->reset =3D superh_cpu_reset; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c7adc281de..ff6ed91f9a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -858,8 +858,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - scc->parent_realize =3D dc->realize; - dc->realize =3D sparc_cpu_realizefn; + device_class_set_parent_realize(dc, sparc_cpu_realizefn, + &scc->parent_realize); dc->props =3D sparc_cpu_properties; =20 scc->parent_reset =3D cc->reset; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2ef8ea7daa..54b6c50878 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -141,8 +141,8 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) CPUClass *cc =3D CPU_CLASS(oc); TileGXCPUClass *tcc =3D TILEGX_CPU_CLASS(oc); =20 - tcc->parent_realize =3D dc->realize; - dc->realize =3D tilegx_cpu_realizefn; + device_class_set_parent_realize(dc, tilegx_cpu_realizefn, + &tcc->parent_realize); =20 tcc->parent_reset =3D cc->reset; cc->reset =3D tilegx_cpu_reset; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 179c997aa4..2edaef1aef 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -153,8 +153,8 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) CPUClass *cc =3D CPU_CLASS(c); DeviceClass *dc =3D DEVICE_CLASS(c); =20 - mcc->parent_realize =3D dc->realize; - dc->realize =3D tricore_cpu_realizefn; + device_class_set_parent_realize(dc, tricore_cpu_realizefn, + &mcc->parent_realize); =20 mcc->parent_reset =3D cc->reset; cc->reset =3D tricore_cpu_reset; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 17dc1504d7..fb837aab4c 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -132,8 +132,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) CPUClass *cc =3D CPU_CLASS(oc); UniCore32CPUClass *ucc =3D UNICORE32_CPU_CLASS(oc); =20 - ucc->parent_realize =3D dc->realize; - dc->realize =3D uc32_cpu_realizefn; + device_class_set_parent_realize(dc, uc32_cpu_realizefn, + &ucc->parent_realize); =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 1c982a0b2e..4573388a45 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -151,8 +151,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) CPUClass *cc =3D CPU_CLASS(oc); XtensaCPUClass *xcc =3D XTENSA_CPU_CLASS(cc); =20 - xcc->parent_realize =3D dc->realize; - dc->realize =3D xtensa_cpu_realizefn; + device_class_set_parent_realize(dc, xtensa_cpu_realizefn, + &xcc->parent_realize); =20 xcc->parent_reset =3D cc->reset; cc->reset =3D xtensa_cpu_reset; --=20 2.15.1