From nobody Sun Apr 28 19:18:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515611068650852.436276535959; Wed, 10 Jan 2018 11:04:28 -0800 (PST) Received: from localhost ([::1]:60845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLfg-0005KE-8X for importer@patchew.org; Wed, 10 Jan 2018 14:04:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLdV-00047T-QE for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZLdU-0003OD-3R for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:05 -0500 Received: from mx1.redhat.com ([209.132.183.28]:43560) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eZLdT-0003Lx-OZ for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:03 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 87FB77C83C; Wed, 10 Jan 2018 19:01:57 +0000 (UTC) Received: from gimli.home (ovpn-116-14.phx2.redhat.com [10.3.116.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id AEBCC63F94; Wed, 10 Jan 2018 19:01:55 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 12:01:55 -0700 Message-ID: <20180110190155.5389.69659.stgit@gimli.home> In-Reply-To: <20180110190049.5389.12984.stgit@gimli.home> References: <20180110190049.5389.12984.stgit@gimli.home> User-Agent: StGit/0.18 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Wed, 10 Jan 2018 19:01:57 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 1/5] vfio/pci: Fixup VFIOMSIXInfo comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The fields were removed in the referenced commit, but the comment still mentions them. Fixes: 2fb9636ebf24 ("vfio-pci: Remove unused fields from VFIOMSIXInfo") Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Tested-by: Alexey Kardashevskiy Tested-by: Eric Auger --- hw/vfio/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index a8fb3b34222c..3d753222ca4c 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -86,7 +86,7 @@ enum { VFIO_INT_MSIX =3D 3, }; =20 -/* Cache of MSI-X setup plus extra mmap and memory region for split BAR ma= p */ +/* Cache of MSI-X setup */ typedef struct VFIOMSIXInfo { uint8_t table_bar; uint8_t pba_bar; From nobody Sun Apr 28 19:18:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151561107401182.63805830278488; Wed, 10 Jan 2018 11:04:34 -0800 (PST) Received: from localhost ([::1]:60846 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLft-0005ZO-5C for importer@patchew.org; Wed, 10 Jan 2018 14:04:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLda-0004A3-Rl for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZLdZ-0003Wj-EN for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:10 -0500 Received: from mx1.redhat.com ([209.132.183.28]:58802) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eZLdY-0003VB-VA for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:09 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DA56DC0546DE; Wed, 10 Jan 2018 19:02:07 +0000 (UTC) Received: from gimli.home (ovpn-116-14.phx2.redhat.com [10.3.116.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0545867641; Wed, 10 Jan 2018 19:02:02 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 12:02:02 -0700 Message-ID: <20180110190202.5389.39690.stgit@gimli.home> In-Reply-To: <20180110190049.5389.12984.stgit@gimli.home> References: <20180110190049.5389.12984.stgit@gimli.home> User-Agent: StGit/0.18 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 10 Jan 2018 19:02:07 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/5] vfio/pci: Add base BAR MemoryRegion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Add one more layer to our stack of MemoryRegions, this base region allows us to register BARs independently of the vfio region or to extend the size of BARs which do map to a region. This will be useful when we want hypervisor defined BARs or sections of BARs, for purposes such as relocating MSI-X emulation. We therefore call msix_init() based on this new base MemoryRegion, while the quirks, which only modify regions still operate on those sub-MemoryRegions. Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Tested-by: Alexey Kardashevskiy Tested-by: Eric Auger --- hw/vfio/pci.c | 74 ++++++++++++++++++++++++++++++++++++++++++++---------= ---- hw/vfio/pci.h | 3 ++ 2 files changed, 60 insertions(+), 17 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c977ee327f94..46f1e7ed9933 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1440,9 +1440,9 @@ static int vfio_msix_setup(VFIOPCIDevice *vdev, int p= os, Error **errp) vdev->msix->pending =3D g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); ret =3D msix_init(&vdev->pdev, vdev->msix->entries, - vdev->bars[vdev->msix->table_bar].region.mem, + vdev->bars[vdev->msix->table_bar].mr, vdev->msix->table_bar, vdev->msix->table_offset, - vdev->bars[vdev->msix->pba_bar].region.mem, + vdev->bars[vdev->msix->pba_bar].mr, vdev->msix->pba_bar, vdev->msix->pba_offset, pos, &err); if (ret < 0) { @@ -1482,8 +1482,8 @@ static void vfio_teardown_msi(VFIOPCIDevice *vdev) =20 if (vdev->msix) { msix_uninit(&vdev->pdev, - vdev->bars[vdev->msix->table_bar].region.mem, - vdev->bars[vdev->msix->pba_bar].region.mem); + vdev->bars[vdev->msix->table_bar].mr, + vdev->bars[vdev->msix->pba_bar].mr); g_free(vdev->msix->pending); } } @@ -1500,12 +1500,11 @@ static void vfio_mmap_set_enabled(VFIOPCIDevice *vd= ev, bool enabled) } } =20 -static void vfio_bar_setup(VFIOPCIDevice *vdev, int nr) +static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr) { VFIOBAR *bar =3D &vdev->bars[nr]; =20 uint32_t pci_bar; - uint8_t type; int ret; =20 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ @@ -1524,23 +1523,52 @@ static void vfio_bar_setup(VFIOPCIDevice *vdev, int= nr) pci_bar =3D le32_to_cpu(pci_bar); bar->ioport =3D (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); bar->mem64 =3D bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_= 64); - type =3D pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : - ~PCI_BASE_ADDRESS_MEM_MASK); + bar->type =3D pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : + ~PCI_BASE_ADDRESS_MEM_MASK); + bar->size =3D bar->region.size; +} =20 - if (vfio_region_mmap(&bar->region)) { - error_report("Failed to mmap %s BAR %d. Performance may be slow", - vdev->vbasedev.name, nr); +static void vfio_bars_prepare(VFIOPCIDevice *vdev) +{ + int i; + + for (i =3D 0; i < PCI_ROM_SLOT; i++) { + vfio_bar_prepare(vdev, i); } +} =20 - pci_register_bar(&vdev->pdev, nr, type, bar->region.mem); +static void vfio_bar_register(VFIOPCIDevice *vdev, int nr) +{ + VFIOBAR *bar =3D &vdev->bars[nr]; + char *name; + + if (!bar->size) { + return; + } + + bar->mr =3D g_new0(MemoryRegion, 1); + name =3D g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr); + memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->si= ze); + g_free(name); + + if (bar->region.size) { + memory_region_add_subregion(bar->mr, 0, bar->region.mem); + + if (vfio_region_mmap(&bar->region)) { + error_report("Failed to mmap %s BAR %d. Performance may be slo= w", + vdev->vbasedev.name, nr); + } + } + + pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr); } =20 -static void vfio_bars_setup(VFIOPCIDevice *vdev) +static void vfio_bars_register(VFIOPCIDevice *vdev) { int i; =20 for (i =3D 0; i < PCI_ROM_SLOT; i++) { - vfio_bar_setup(vdev, i); + vfio_bar_register(vdev, i); } } =20 @@ -1549,8 +1577,13 @@ static void vfio_bars_exit(VFIOPCIDevice *vdev) int i; =20 for (i =3D 0; i < PCI_ROM_SLOT; i++) { + VFIOBAR *bar =3D &vdev->bars[i]; + vfio_bar_quirk_exit(vdev, i); - vfio_region_exit(&vdev->bars[i].region); + vfio_region_exit(&bar->region); + if (bar->region.size) { + memory_region_del_subregion(bar->mr, bar->region.mem); + } } =20 if (vdev->vga) { @@ -1564,8 +1597,14 @@ static void vfio_bars_finalize(VFIOPCIDevice *vdev) int i; =20 for (i =3D 0; i < PCI_ROM_SLOT; i++) { + VFIOBAR *bar =3D &vdev->bars[i]; + vfio_bar_quirk_finalize(vdev, i); - vfio_region_finalize(&vdev->bars[i].region); + vfio_region_finalize(&bar->region); + if (bar->size) { + object_unparent(OBJECT(bar->mr)); + g_free(bar->mr); + } } =20 if (vdev->vga) { @@ -2810,7 +2849,8 @@ static void vfio_realize(PCIDevice *pdev, Error **err= p) goto error; } =20 - vfio_bars_setup(vdev); + vfio_bars_prepare(vdev); + vfio_bars_register(vdev); =20 ret =3D vfio_add_capabilities(vdev, errp); if (ret) { diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 3d753222ca4c..dcdb1a806769 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -33,6 +33,9 @@ typedef struct VFIOQuirk { =20 typedef struct VFIOBAR { VFIORegion region; + MemoryRegion *mr; + size_t size; + uint8_t type; bool ioport; bool mem64; QLIST_HEAD(, VFIOQuirk) quirks; From nobody Sun Apr 28 19:18:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515611260669164.04439302614026; Wed, 10 Jan 2018 11:07:40 -0800 (PST) Received: from localhost ([::1]:60965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLit-0008CA-Q9 for importer@patchew.org; Wed, 10 Jan 2018 14:07:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLdq-0004KS-Ed for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZLdp-0003tb-NC for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:26 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36730) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eZLdp-0003rn-FT for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:25 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 79F4476541; Wed, 10 Jan 2018 19:02:19 +0000 (UTC) Received: from gimli.home (ovpn-116-14.phx2.redhat.com [10.3.116.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5692817125; Wed, 10 Jan 2018 19:02:13 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 12:02:13 -0700 Message-ID: <20180110190212.5389.67764.stgit@gimli.home> In-Reply-To: <20180110190049.5389.12984.stgit@gimli.home> References: <20180110190049.5389.12984.stgit@gimli.home> User-Agent: StGit/0.18 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 10 Jan 2018 19:02:24 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 3/5] vfio/pci: Emulate BARs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The kernel provides similar emulation of PCI BAR register access to QEMU, so up until now we've used that for things like BAR sizing and storing the BAR address. However, if we intend to resize BARs or add BARs that don't exist on the physical device, we need to switch to the pure QEMU emulation of the BAR. Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Tested-by: Alexey Kardashevskiy Tested-by: Eric Auger --- hw/vfio/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 46f1e7ed9933..20252ea7aeb7 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -2773,6 +2773,8 @@ static void vfio_realize(PCIDevice *pdev, Error **err= p) =20 /* QEMU can choose to expose the ROM or not */ memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); + /* QEMU can also add or extend BARs */ + memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4); =20 /* * The PCI spec reserves vendor ID 0xffff as an invalid value. The From nobody Sun Apr 28 19:18:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515611101274801.2323285848122; Wed, 10 Jan 2018 11:05:01 -0800 (PST) Received: from localhost ([::1]:60847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLgK-0005vX-Hb for importer@patchew.org; Wed, 10 Jan 2018 14:05:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLe2-0004VF-Jp for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZLdx-000468-Mn for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:43860) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eZLdx-00045K-AE for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:33 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 32D94776C0; Wed, 10 Jan 2018 19:02:32 +0000 (UTC) Received: from gimli.home (ovpn-116-14.phx2.redhat.com [10.3.116.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id C6A0287A5; Wed, 10 Jan 2018 19:02:24 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 12:02:24 -0700 Message-ID: <20180110190224.5389.18151.stgit@gimli.home> In-Reply-To: <20180110190049.5389.12984.stgit@gimli.home> References: <20180110190049.5389.12984.stgit@gimli.home> User-Agent: StGit/0.18 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Wed, 10 Jan 2018 19:02:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 4/5] qapi: Create DEFINE_PROP_OFF_AUTO_PCIBAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, eric.auger@redhat.com, Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Add an option which allows the user to specify a PCI BAR number, including an 'off' and 'auto' selection. Cc: Markus Armbruster Cc: Eric Blake Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Reviewed-by: Markus Armbruster Tested-by: Alexey Kardashevskiy Tested-by: Eric Auger --- hw/core/qdev-properties.c | 11 +++++++++++ include/hw/qdev-properties.h | 4 ++++ qapi/common.json | 26 ++++++++++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 1dc80fcea2af..e33184e5a342 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -1256,3 +1256,14 @@ const PropertyInfo qdev_prop_link =3D { .name =3D "link", .create =3D create_link_property, }; + +/* --- OffAutoPCIBAR off/auto/bar0/bar1/bar2/bar3/bar4/bar5 --- */ + +const PropertyInfo qdev_prop_off_auto_pcibar =3D { + .name =3D "OffAutoPCIBAR", + .description =3D "off/auto/bar0/bar1/bar2/bar3/bar4/bar5", + .enum_table =3D &OffAutoPCIBAR_lookup, + .get =3D get_enum, + .set =3D set_enum, + .set_default_value =3D set_default_value_enum, +}; diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 60b42ac561af..e2643f5126c4 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -33,6 +33,7 @@ extern const PropertyInfo qdev_prop_blocksize; extern const PropertyInfo qdev_prop_pci_host_devaddr; extern const PropertyInfo qdev_prop_arraylen; extern const PropertyInfo qdev_prop_link; +extern const PropertyInfo qdev_prop_off_auto_pcibar; =20 #define DEFINE_PROP(_name, _state, _field, _prop, _type) { \ .name =3D (_name), \ @@ -213,6 +214,9 @@ extern const PropertyInfo qdev_prop_link; DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddre= ss) #define DEFINE_PROP_MEMORY_REGION(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, MemoryRegion *) +#define DEFINE_PROP_OFF_AUTO_PCIBAR(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_off_auto_pcibar, \ + OffAutoPCIBAR) =20 #define DEFINE_PROP_END_OF_LIST() \ {} diff --git a/qapi/common.json b/qapi/common.json index 6eb01821ef59..d9b14dd429f3 100644 --- a/qapi/common.json +++ b/qapi/common.json @@ -100,3 +100,29 @@ { 'alternate': 'StrOrNull', 'data': { 's': 'str', 'n': 'null' } } + +## +# @OffAutoPCIBAR: +# +# An enumeration of options for specifying a PCI BAR +# +# @off: The specified feature is disabled +# +# @auto: The PCI BAR for the feature is automatically selected +# +# @bar0: PCI BAR0 is used for the feature +# +# @bar1: PCI BAR1 is used for the feature +# +# @bar2: PCI BAR2 is used for the feature +# +# @bar3: PCI BAR3 is used for the feature +# +# @bar4: PCI BAR4 is used for the feature +# +# @bar5: PCI BAR5 is used for the feature +# +# Since: 2.12 +## +{ 'enum': 'OffAutoPCIBAR', + 'data': [ 'off', 'auto', 'bar0', 'bar1', 'bar2', 'bar3', 'bar4', 'bar5' = ] } From nobody Sun Apr 28 19:18:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515611251781920.8405283706321; Wed, 10 Jan 2018 11:07:31 -0800 (PST) Received: from localhost ([::1]:60963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLik-00084v-Tu for importer@patchew.org; Wed, 10 Jan 2018 14:07:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZLeG-0004fr-Jq for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZLeB-0004Mm-KF for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:52 -0500 Received: from mx1.redhat.com ([209.132.183.28]:43996) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eZLeB-0004ME-4I for qemu-devel@nongnu.org; Wed, 10 Jan 2018 14:02:47 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2DDA5776C0; Wed, 10 Jan 2018 19:02:41 +0000 (UTC) Received: from gimli.home (ovpn-116-14.phx2.redhat.com [10.3.116.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7A9FF80C2; Wed, 10 Jan 2018 19:02:36 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 12:02:36 -0700 Message-ID: <20180110190236.5389.58765.stgit@gimli.home> In-Reply-To: <20180110190049.5389.12984.stgit@gimli.home> References: <20180110190049.5389.12984.stgit@gimli.home> User-Agent: StGit/0.18 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Wed, 10 Jan 2018 19:02:46 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 5/5] vfio/pci: Allow relocating MSI-X MMIO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Recently proposed vfio-pci kernel changes (v4.16) remove the restriction preventing userspace from mmap'ing PCI BARs in areas overlapping the MSI-X vector table. This change is primarily intended to benefit host platforms which make use of system page sizes larger than the PCI spec recommendation for alignment of MSI-X data structures (ie. not x86_64). In the case of POWER systems, the SPAPR spec requires the VM to program MSI-X using hypercalls, rendering the MSI-X vector table unused in the VM view of the device. However, ARM64 platforms also support 64KB pages and rely on QEMU emulation of MSI-X. Regardless of the kernel driver allowing mmaps overlapping the MSI-X vector table, emulation of the MSI-X vector table also prevents direct mapping of device MMIO spaces overlapping this page. Thanks to the fact that PCI devices have a standard self discovery mechanism, we can try to resolve this by relocating the MSI-X data structures, either by creating a new PCI BAR or extending an existing BAR and updating the MSI-X capability for the new location. There's even a very slim chance that this could benefit devices which do not adhere to the PCI spec alignment guidelines on x86_64 systems. This new x-msix-relocation option accepts the following choices: off: Disable MSI-X relocation, use native device config (default) auto: Use a known good combination for the platform/device (none yet) bar0..bar5: Specify the target BAR for MSI-X data structures If compatible, the target BAR will either be created or extended and the new portion will be used for MSI-X emulation. The first obvious user question with this option is how to determine whether a given platform and device might benefit from this option. In most cases, the answer is that it won't, especially on x86_64. Devices often dedicate an entire BAR to MSI-X and therefore no performance sensitive registers overlap the MSI-X area. Take for example: # lspci -vvvs 0a:00.0 0a:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connect= ion ... Region 0: Memory at db680000 (32-bit, non-prefetchable) [size=3D512K] Region 3: Memory at db7f8000 (32-bit, non-prefetchable) [size=3D16K] ... Capabilities: [70] MSI-X: Enable+ Count=3D10 Masked- Vector table: BAR=3D3 offset=3D00000000 PBA: BAR=3D3 offset=3D00002000 This device uses the 16K bar3 for MSI-X with the vector table at offset zero and the pending bits arrary at offset 8K, fully honoring the PCI spec alignment guidance. The data sheet specifically refers to this as an MSI-X BAR. This device would not see a benefit from MSI-X relocation regardless of the platform, regardless of the page size. However, here's another example: # lspci -vvvs 02:00.0 02:00.0 Serial Attached SCSI controller: xxxxxxxx ... Region 0: I/O ports at c000 [size=3D256] Region 1: Memory at ef640000 (64-bit, non-prefetchable) [size=3D64K] Region 3: Memory at ef600000 (64-bit, non-prefetchable) [size=3D256K] ... Capabilities: [c0] MSI-X: Enable+ Count=3D16 Masked- Vector table: BAR=3D1 offset=3D0000e000 PBA: BAR=3D1 offset=3D0000f000 Here the MSI-X data structures are placed on separate 4K pages at the end of a 64KB BAR. If our host page size is 4K, we're likely fine, but at 64KB page size, MSI-X emulation at that location prevents the entire BAR from being directly mapped into the VM address space. Overlapping performance sensitive registers then starts to be a very likely scenario on such a platform. At this point, the user could enable tracing on vfio_region_read and vfio_region_write to determine more conclusively if device accesses are being trapped through QEMU. Upon finding a device and platform in need of MSI-X relocation, the next problem is how to choose target PCI BAR to host the MSI-X data structures. A few key rules to keep in mind for this selection include: * There are only 6 BAR slots, bar0..bar5 * 64-bit BARs occupy two BAR slots, 'lspci -vvv' lists the first slot * PCI BARs are always a power of 2 in size, extending =3D=3D doubling * The maximum size of a 32-bit BAR is 2GB * MSI-X data structures must reside in an MMIO BAR Using these rules, we can evaluate each BAR of the second example device above as follows: bar0: I/O port BAR, incompatible with MSI-X tables bar1: BAR could be extended, incurring another 64KB of MMIO bar2: Unavailable, bar1 is 64-bit, this register is used by bar1 bar3: BAR could be extended, incurring another 256KB of MMIO bar4: Unavailable, bar3 is 64bit, this register is used by bar3 bar5: Available, empty BAR, minimum additional MMIO A secondary optimization we might wish to make in relocating MSI-X is to minimize the additional MMIO required for the device, therefore we might test the available choices in order of preference as bar5, bar1, and finally bar3. The original proposal for this feature included an 'auto' option which would choose bar5 in this case, but various drivers have been found that make assumptions about the properties of the "first" BAR or the size of BARs such that there appears to be no foolproof automatic selection available, requiring known good combinations to be sourced from users. This patch is pre-enabled for an 'auto' selection making use of a validated lookup table, but no entries are yet identified. Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Tested-by: Alexey Kardashevskiy Tested-by: Eric Auger --- hw/vfio/pci.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/vfio/pci.h | 1=20 hw/vfio/trace-events | 2 + 3 files changed, 103 insertions(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 20252ea7aeb7..7171ba18213c 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1352,6 +1352,100 @@ static void vfio_pci_fixup_msix_region(VFIOPCIDevic= e *vdev) } } =20 +static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp) +{ + int target_bar =3D -1; + size_t msix_sz; + + if (!vdev->msix || vdev->msix_relo =3D=3D OFF_AUTOPCIBAR_OFF) { + return; + } + + /* The actual minimum size of MSI-X structures */ + msix_sz =3D (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) + + (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8); + /* Round up to host pages, we don't want to share a page */ + msix_sz =3D REAL_HOST_PAGE_ALIGN(msix_sz); + /* PCI BARs must be a power of 2 */ + msix_sz =3D pow2ceil(msix_sz); + + if (vdev->msix_relo =3D=3D OFF_AUTOPCIBAR_AUTO) { + /* + * TODO: Lookup table for known devices. + * + * Logically we might use an algorithm here to select the BAR addi= ng + * the least additional MMIO space, but we cannot programatically + * predict the driver dependency on BAR ordering or sizing, theref= ore + * 'auto' becomes a lookup for combinations reported to work. + */ + if (target_bar < 0) { + error_setg_errno(errp, EINVAL, "No automatic MSI-X relocation " + "available for device %04x:%04x", + vdev->vendor_id, vdev->device_id); + return; + } + } else { + target_bar =3D (int)(vdev->msix_relo - OFF_AUTOPCIBAR_BAR0); + } + + /* I/O port BARs cannot host MSI-X structures */ + if (vdev->bars[target_bar].ioport) { + error_setg_errno(errp, EINVAL, "Invalid MSI-X relocation BAR %d, " + "I/O port BAR", target_bar); + return; + } + + /* Cannot use a BAR in the "shadow" of a 64-bit BAR */ + if (!vdev->bars[target_bar].size && + target_bar > 0 && vdev->bars[target_bar - 1].mem64) { + error_setg_errno(errp, EINVAL, "Invalid MSI-X relocation BAR %d, " + "consumed by 64-bit BAR %d", target_bar, + target_bar - 1); + return; + } + + /* 2GB max size for 32-bit BARs */ + if (vdev->bars[target_bar].size > (1 * 1024 * 1024 * 1024) && + !vdev->bars[target_bar].mem64) { + error_setg_errno(errp, EINVAL, "Invalid MSI-X relocation BAR %d, " + "no space to extend 32-bit BAR", target_bar); + return; + } + + /* + * If adding a new BAR, test if we can make it 64bit. We make it + * prefetchable since QEMU MSI-X emulation has no read side effects + * and doing so makes mapping more flexible. + */ + if (!vdev->bars[target_bar].size) { + if (target_bar < (PCI_ROM_SLOT - 1) && + !vdev->bars[target_bar + 1].size) { + vdev->bars[target_bar].mem64 =3D true; + vdev->bars[target_bar].type =3D PCI_BASE_ADDRESS_MEM_TYPE_64; + } + vdev->bars[target_bar].type |=3D PCI_BASE_ADDRESS_MEM_PREFETCH; + vdev->bars[target_bar].size =3D msix_sz; + vdev->msix->table_offset =3D 0; + } else { + vdev->bars[target_bar].size =3D MAX(vdev->bars[target_bar].size * = 2, + msix_sz * 2); + /* + * Due to above size calc, MSI-X always starts halfway into the BA= R, + * which will always be a separate host page. + */ + vdev->msix->table_offset =3D vdev->bars[target_bar].size / 2; + } + + vdev->msix->table_bar =3D target_bar; + vdev->msix->pba_bar =3D target_bar; + /* Requires 8-byte alignment, but PCI_MSIX_ENTRY_SIZE guarantees that = */ + vdev->msix->pba_offset =3D vdev->msix->table_offset + + (vdev->msix->entries * PCI_MSIX_ENTRY_SI= ZE); + + trace_vfio_msix_relo(vdev->vbasedev.name, + vdev->msix->table_bar, vdev->msix->table_offset); +} + /* * We don't have any control over how pci_add_capability() inserts * capabilities into the chain. In order to setup MSI-X we need a @@ -1430,6 +1524,8 @@ static void vfio_msix_early_setup(VFIOPCIDevice *vdev= , Error **errp) vdev->msix =3D msix; =20 vfio_pci_fixup_msix_region(vdev); + + vfio_pci_relocate_msix(vdev, errp); } =20 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) @@ -2845,13 +2941,14 @@ static void vfio_realize(PCIDevice *pdev, Error **e= rrp) =20 vfio_pci_size_rom(vdev); =20 + vfio_bars_prepare(vdev); + vfio_msix_early_setup(vdev, &err); if (err) { error_propagate(errp, err); goto error; } =20 - vfio_bars_prepare(vdev); vfio_bars_register(vdev); =20 ret =3D vfio_add_capabilities(vdev, errp); @@ -3041,6 +3138,8 @@ static Property vfio_pci_dev_properties[] =3D { DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice, nv_gpudirect_clique, qdev_prop_nv_gpudirect_clique, uint8_t), + DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_r= elo, + OFF_AUTOPCIBAR_OFF), /* * TODO - support passed fds... is this necessary? * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index dcdb1a806769..588381f201b4 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -135,6 +135,7 @@ typedef struct VFIOPCIDevice { (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT) int32_t bootindex; uint32_t igd_gms; + OffAutoPCIBAR msix_relo; uint8_t pm_cap; uint8_t nv_gpudirect_clique; bool pci_aer; diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index fae096c0724f..437ccdd29053 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -16,6 +16,8 @@ vfio_msix_pba_disable(const char *name) " (%s)" vfio_msix_pba_enable(const char *name) " (%s)" vfio_msix_disable(const char *name) " (%s)" vfio_msix_fixup(const char *name, int bar, uint64_t start, uint64_t end) "= (%s) MSI-X region %d mmap fixup [0x%"PRIx64" - 0x%"PRIx64"]" +vfio_msix_relo_cost(const char *name, int bar, uint64_t cost) " (%s) BAR %= d cost 0x%"PRIx64"" +vfio_msix_relo(const char *name, int bar, uint64_t offset) " (%s) BAR %d o= ffset 0x%"PRIx64"" vfio_msi_enable(const char *name, int nr_vectors) " (%s) Enabled %d MSI ve= ctors" vfio_msi_disable(const char *name) " (%s)" vfio_pci_load_rom(const char *name, unsigned long size, unsigned long offs= et, unsigned long flags) "Device %s ROM:\n size: 0x%lx, offset: 0x%lx, fla= gs: 0x%lx"