From nobody Fri May 3 18:31:20 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151238285921197.36267548450587; Mon, 4 Dec 2017 02:20:59 -0800 (PST) Received: from localhost ([::1]:42042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLnrp-00046V-H2 for importer@patchew.org; Mon, 04 Dec 2017 05:20:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLnqr-0003bz-7w for qemu-devel@nongnu.org; Mon, 04 Dec 2017 05:19:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eLnqp-0000dX-Hg for qemu-devel@nongnu.org; Mon, 04 Dec 2017 05:19:53 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36770) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eLnqj-0000ai-8X; Mon, 04 Dec 2017 05:19:45 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EB53E32DE34; Mon, 4 Dec 2017 10:19:43 +0000 (UTC) Received: from localhost.localdomain.com (unknown [10.35.7.51]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9879E619E0; Mon, 4 Dec 2017 10:19:03 +0000 (UTC) From: Yoni Bettan To: qemu-devel@nongnu.org Date: Mon, 4 Dec 2017 12:18:28 +0200 Message-Id: <20171204101828.24453-1-ybettan@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 04 Dec 2017 10:19:44 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2] pci: removed the is_express field since a uniform interface was inserted X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Hannes Reinecke , "open list:nvme" , "Michael S. Tsirkin" , Yoni Bettan , Alex Williamson , Max Reitz , Keith Busch , Dmitry Fleytman , Paul Burton , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , Jason Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" * according to Eduardo Habkost's commit fd3b02c8896d597dd8b9e053dec579cf0386aee1 * since all PCIEs now implement INTERFACE_PCIE_DEVICE we don't need this field anymore * Devices that where only INTERFACE_PCIE_DEVICE (is_express =3D=3D = 1) or devices that where only INTERFACE_CONVENTIONAL_PCI_DEVICE (is_exp= ress =3D=3D 0) where not affected by the change The only devices that were affected are those that are hybrid and= also had (is_express =3D=3D 1) - therefor only: - hw/vfio/pci.c - hw/usb/hcd-xhci.c For both i made sure that pci_dev->cap_present |=3D QEMU_PCI_CAP_= EXPRESS Signed-off-by: Yoni Bettan --- docs/pcie_pci_bridge.txt | 2 +- hw/block/nvme.c | 1 - hw/net/e1000e.c | 1 - hw/pci-bridge/pcie_pci_bridge.c | 1 - hw/pci-bridge/pcie_root_port.c | 1 - hw/pci-bridge/xio3130_downstream.c | 1 - hw/pci-bridge/xio3130_upstream.c | 1 - hw/pci-host/xilinx-pcie.c | 1 - hw/pci/pci.c | 4 +++- hw/scsi/megasas.c | 4 ---- hw/usb/hcd-xhci.c | 28 ++++++++++++++++++++++++++-- hw/vfio/pci.c | 37 +++++++++++++++++++++++++++++++---= --- include/hw/pci/pci.h | 3 --- include/hw/usb.h | 1 + 14 files changed, 62 insertions(+), 24 deletions(-) diff --git a/docs/pcie_pci_bridge.txt b/docs/pcie_pci_bridge.txt index 5a4203f97c..55f833ec10 100644 --- a/docs/pcie_pci_bridge.txt +++ b/docs/pcie_pci_bridge.txt @@ -110,5 +110,5 @@ To enable device hot-plug into the bridge on Linux ther= e're 3 ways: Implementation =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI E= xpress -features as a PCI Express device (is_express=3D1). +features as a PCI Express device (pci_dev->cap_present & QEMU_PCI_CAP_EXPR= ESS !=3D 0). =20 diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 441e21ed1f..9325bc0911 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1087,7 +1087,6 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0x5845; pc->revision =3D 2; - pc->is_express =3D 1; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc =3D "Non-Volatile Memory Express"; diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index f1af279e8d..c360f0d8c9 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -675,7 +675,6 @@ static void e1000e_class_init(ObjectClass *class, void = *data) c->revision =3D 0; c->romfile =3D "efi-e1000e.rom"; c->class_id =3D PCI_CLASS_NETWORK_ETHERNET; - c->is_express =3D 1; =20 dc->desc =3D "Intel 82574L GbE Controller"; dc->reset =3D e1000e_qdev_reset; diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index a4d827c99d..b7d9ebbec2 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -169,7 +169,6 @@ static void pcie_pci_bridge_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 9b6e4ce512..45f9e8cd4a 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -145,7 +145,6 @@ static void rp_class_init(ObjectClass *klass, void *dat= a) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D rp_write_config; k->realize =3D rp_realize; diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 1e09d2afb7..613a0d6bb7 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -177,7 +177,6 @@ static void xio3130_downstream_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_downstream_write_config; k->realize =3D xio3130_downstream_realize; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 227997ce46..d4645bddee 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -148,7 +148,6 @@ static void xio3130_upstream_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_upstream_write_config; k->realize =3D xio3130_upstream_realize; diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 7659253090..a4ca3ba30f 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -298,7 +298,6 @@ static void xilinx_pcie_root_class_init(ObjectClass *kl= ass, void *data) k->device_id =3D 0x7021; k->revision =3D 0; k->class_id =3D PCI_CLASS_BRIDGE_HOST; - k->is_express =3D true; k->is_bridge =3D true; k->init =3D xilinx_pcie_root_init; k->exit =3D pci_bridge_exitfn; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index b2d139bd9a..6b5676b0f4 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2014,12 +2014,14 @@ static void pci_qdev_realize(DeviceState *qdev, Err= or **errp) { PCIDevice *pci_dev =3D (PCIDevice *)qdev; PCIDeviceClass *pc =3D PCI_DEVICE_GET_CLASS(pci_dev); + ObjectClass *klass =3D OBJECT_CLASS(pc); Error *local_err =3D NULL; PCIBus *bus; bool is_default_rom; =20 /* initialize cap_present for pci_is_express() and pci_config_size() */ - if (pc->is_express) { + if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && + !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE= )) { pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index d5eae6239a..ee51feda59 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2447,7 +2447,6 @@ typedef struct MegasasInfo { uint16_t subsystem_id; int ioport_bar; int mmio_bar; - bool is_express; int osts; const VMStateDescription *vmsd; Property *props; @@ -2465,7 +2464,6 @@ static struct MegasasInfo megasas_devices[] =3D { .ioport_bar =3D 2, .mmio_bar =3D 0, .osts =3D MFI_1078_RM | 1, - .is_express =3D false, .vmsd =3D &vmstate_megasas_gen1, .props =3D megasas_properties_gen1, .interfaces =3D (InterfaceInfo[]) { @@ -2482,7 +2480,6 @@ static struct MegasasInfo megasas_devices[] =3D { .ioport_bar =3D 0, .mmio_bar =3D 1, .osts =3D MFI_GEN2_RM, - .is_express =3D true, .vmsd =3D &vmstate_megasas_gen2, .props =3D megasas_properties_gen2, .interfaces =3D (InterfaceInfo[]) { @@ -2506,7 +2503,6 @@ static void megasas_class_init(ObjectClass *oc, void = *data) pc->subsystem_vendor_id =3D PCI_VENDOR_ID_LSI_LOGIC; pc->subsystem_id =3D info->subsystem_id; pc->class_id =3D PCI_CLASS_STORAGE_RAID; - pc->is_express =3D info->is_express; e->mmio_bar =3D info->mmio_bar; e->ioport_bar =3D info->ioport_bar; e->osts =3D info->osts; diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index af3a9d88de..1524745b3b 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -131,6 +131,17 @@ =20 #define ERDP_EHB (1<<3) =20 +typedef struct XHCIClass { + PCIDeviceClass parent_class; + DeviceRealize parent_dc_realize; +} XHCIClass; + +#define XHCI_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(XHCIClass, (klass), TYPE_XHCI) +#define XHCI_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XHCIClass, (obj), TYPE_XHCI) + + #define TRB_SIZE 16 typedef struct XHCITRB { uint64_t parameter; @@ -3649,11 +3660,24 @@ static Property xhci_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void before_usb_xhci_realize(DeviceState *qdev, Error **errp) +{ + XHCIClass *vc =3D XHCI_DEVICE_GET_CLASS(qdev); + PCIDevice *pci_dev =3D PCI_DEVICE(qdev); + + pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; + + vc->parent_dc_realize(qdev, errp); +} + static void xhci_class_init(ObjectClass *klass, void *data) { - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + XHCIClass *vc =3D XHCI_DEVICE_CLASS(klass); =20 + vc->parent_dc_realize =3D dc->realize; + dc->realize =3D before_usb_xhci_realize; dc->vmsd =3D &vmstate_xhci; dc->props =3D xhci_properties; dc->reset =3D xhci_reset; @@ -3661,12 +3685,12 @@ static void xhci_class_init(ObjectClass *klass, voi= d *data) k->realize =3D usb_xhci_realize; k->exit =3D usb_xhci_exit; k->class_id =3D PCI_CLASS_SERIAL_USB; - k->is_express =3D 1; } =20 static const TypeInfo xhci_info =3D { .name =3D TYPE_XHCI, .parent =3D TYPE_PCI_DEVICE, + .class_size =3D sizeof(XHCIClass), .instance_size =3D sizeof(XHCIState), .class_init =3D xhci_class_init, .abstract =3D true, diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c977ee327f..e330f2c462 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -35,6 +35,18 @@ =20 #define MSIX_CAP_LENGTH 12 =20 +typedef struct VFIOClass { + PCIDeviceClass parent_class; + DeviceRealize parent_dc_realize; +} VFIOClass; + +#define TYPE_VFIOPCI "vfio-pci" + +#define VFIO_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(VFIOClass, (klass), TYPE_VFIOPCI) +#define VFIO_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(VFIOClass, (obj), TYPE_VFIOPCI) + static void vfio_disable_interrupts(VFIOPCIDevice *vdev); static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); =20 @@ -3012,26 +3024,39 @@ static const VMStateDescription vfio_pci_vmstate = =3D { .unmigratable =3D 1, }; =20 +static void before_vfio_realize(DeviceState *qdev, Error **errp) +{ + VFIOClass *vc =3D VFIO_DEVICE_GET_CLASS(qdev); + PCIDevice *pci_dev =3D PCI_DEVICE(qdev); + + pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; + + vc->parent_dc_realize(qdev, errp); +} + static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *pdc =3D PCI_DEVICE_CLASS(klass); + PCIDeviceClass *c =3D PCI_DEVICE_CLASS(klass); + VFIOClass *vc =3D VFIO_DEVICE_CLASS(klass); =20 + vc->parent_dc_realize =3D dc->realize; + dc->realize =3D before_vfio_realize; dc->reset =3D vfio_pci_reset; dc->props =3D vfio_pci_dev_properties; dc->vmsd =3D &vfio_pci_vmstate; dc->desc =3D "VFIO-based PCI device assignment"; set_bit(DEVICE_CATEGORY_MISC, dc->categories); - pdc->realize =3D vfio_realize; - pdc->exit =3D vfio_exitfn; - pdc->config_read =3D vfio_pci_read_config; - pdc->config_write =3D vfio_pci_write_config; - pdc->is_express =3D 1; /* We might be */ + c->realize =3D vfio_realize; + c->exit =3D vfio_exitfn; + c->config_read =3D vfio_pci_read_config; + c->config_write =3D vfio_pci_write_config; } =20 static const TypeInfo vfio_pci_dev_info =3D { .name =3D "vfio-pci", .parent =3D TYPE_PCI_DEVICE, + .class_size =3D sizeof(VFIOClass), .instance_size =3D sizeof(VFIOPCIDevice), .class_init =3D vfio_pci_dev_class_init, .instance_init =3D vfio_instance_init, diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 8d02a0a383..a27be85111 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -236,9 +236,6 @@ typedef struct PCIDeviceClass { */ int is_bridge; =20 - /* pcie stuff */ - int is_express; /* is this device pci express? */ - /* rom bar */ const char *romfile; } PCIDeviceClass; diff --git a/include/hw/usb.h b/include/hw/usb.h index eb28655270..60238bcc32 100644 --- a/include/hw/usb.h +++ b/include/hw/usb.h @@ -275,6 +275,7 @@ typedef void (*USBDeviceUnrealize)(USBDevice *dev, Erro= r **errp); =20 typedef struct USBDeviceClass { DeviceClass parent_class; + DeviceRealize parent_dc_realize; =20 USBDeviceRealize realize; USBDeviceUnrealize unrealize; --=20 2.14.3