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[209.197.184.95]) by smtp.gmail.com with ESMTPSA id n7sm4735347ioi.57.2017.12.02.22.35.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Dec 2017 22:35:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=kA9WZhoMb0nAQ0URmm1ghcsxsIaRlaTtIzo6zAUkv4A=; b=bPPYJnTRprQFHwQgLRbs4nxMkEdjtMsKx9P/1LZjKVRdwlUzUFKQj3n+MMnfuZM3ya PRoWEGC7G0FMvw5/kC/58YH4d+6Q2eEIK3MPCnrExSKAhr+F5We0br8eb92gwYbjhN2L dkWJ0k3i1N5v3z4nn3zGcZCxFLNnB5fLyAv5A9setIg8/XWRjPXQRgOQkqf/62xyUw0P 94yIHv5eEj28CbDoz5fqB5qRik/0z8ikrjSl04cYU6Gd5cOb9XkgFGO01GEIPyTVS6KC ZZ9IBflqIebOl7cXEAR6KdS7XJqRPKBlisoLcdQ9WKK/AL5L7J9U8wQGyKdtVwX0JMso 2OCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=kA9WZhoMb0nAQ0URmm1ghcsxsIaRlaTtIzo6zAUkv4A=; b=fUylPtPMi6bQHpkrWxfn6Kd7HEbZQyTsCHfSpO0G/Sd6t7U2TTlyqXjZN9lqFaLc8D ARc9IR2/8iNz9U16cZHrHkeuutzuC86NpLz5CvYkmdtgwwFbDoo9K2gBhJ5ZjDVtxU61 Ur2TOYSmBbeeoIRupet59UjG0NOQGaI9k1xoCaj5E5RBPP8cFJpGM2pVbMV8+iEzwzdj nLLVfhBJ7+b5m1yDiATCyv2sNZdSNfCoftztVvKbmD09QlAkWNq9K3M+sZTwyiHQvqAO q491zaUVDNF9DTEyTI76U2EZbTtfAIRbg/0ZMCNxkqAPgds9FCsQRaAwUYOYEEz3PBVv LMxQ== X-Gm-Message-State: AJaThX6cLKLUpwyp3Kp6Mkyvco1vnHQjqQl8YjFgl3XNAFW4wJ3RcLjl FtIiMMVm60wEF/ifMXmxytUlr8RX X-Google-Smtp-Source: AGs4zMaUHPFtt2aWm2DP1EFE2P06aA6qbjS8KI+9bC8y2w+Ng54cP5fBJYv5tEu4Tr9l7JCAK7MnXQ== X-Received: by 10.107.47.197 with SMTP id v66mr19454982iov.102.1512282958000; Sat, 02 Dec 2017 22:35:58 -0800 (PST) From: Doug Gale To: qemu-devel@nongnu.org Date: Sun, 3 Dec 2017 01:35:48 -0500 Message-Id: <20171203063548.10297-1-doug16k@gmail.com> X-Mailer: git-send-email 2.14.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [PATCH v2] Add AVX, AVX-512, MPX support to x86_cpu_dump_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Doug Gale , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Doug Gale --- Fix MSB LSB showing when SSE is disabled target/i386/helper.c | 95 +++++++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 83 insertions(+), 12 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index f63eb3d3f4..03812b6e87 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -543,6 +543,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_= function cpu_fprintf, } } cpu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + cpu_fprintf(f, "XCR0=3D%016" PRIx64 "\n", env->xcr0); if (flags & CPU_DUMP_FPU) { int fptag; fptag =3D 0; @@ -565,21 +566,91 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, else cpu_fprintf(f, " "); } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else + + if (env->hflags & HF_CS64_MASK) { + if (env->xcr0 & XSTATE_Hi16_ZMM_MASK) { + /* AVX-512 32 registers enabled */ + nb =3D 32; + } else { + /* 64-bit mode, 16 registers */ + nb =3D 16; + } + } else { + /* 32 bit mode, 8 registers */ nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) + } + + /* sse register width in units of 64 bits */ + int zmm_width; + char zmm_name; + if (env->xcr0 & XSTATE_ZMM_Hi256_MASK) { + /* 512-bit "ZMM" - AVX-512 registers enabled */ + zmm_width =3D 8; + zmm_name =3D 'Z'; + } else if (env->xcr0 & XSTATE_YMM_MASK) { + /* 256-bit "YMM" - AVX enabled */ + zmm_width =3D 4; + zmm_name =3D 'Y'; + } else if (env->cr[4] & CR4_OSFXSR_MASK) { + /* 128-bit "XMM" - SSE enabled */ + zmm_width =3D 2; + zmm_name =3D 'X'; + } else { + /* SSE not enabled */ + zmm_width =3D 0; + zmm_name =3D 0; + } + + if (zmm_width > 0) { + cpu_fprintf(f, " MSB%*sLSB\n", + -(zmm_width * 16 + zmm_width - 7), ""); + } + + for (i =3D 0; i < nb; i++) { + if (zmm_width =3D=3D 0) { + cpu_fprintf(f, "SSE not enabled\n"); + break; + } + + cpu_fprintf(f, "%cMM%02d=3D", zmm_name, i); + int qw; + for (qw =3D zmm_width; qw > 0; qw -=3D 2) { + /* ':' separator every 64 bits */ + cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", + env->xmm_regs[i].ZMM_Q(qw - 1), + env->xmm_regs[i].ZMM_Q(qw - 2), + qw > 2 ? ":" : ""); + } + + /* two registers per line for 128-bit registers */ + if (zmm_width > 2 || (i & 1)) { cpu_fprintf(f, "\n"); - else + } else { cpu_fprintf(f, " "); + } + } + + if (env->xcr0 & XSTATE_OPMASK_MASK) { + /* AVX-512 opmask registers */ + for (i =3D 0; i < 8; ++i) { + cpu_fprintf(f, "K%d=3D%08" PRIx64 "%s", i, env->opmask_reg= s[i], + (i & 3) =3D=3D 3 ? "\n" : " "); + } + } + + if (env->xcr0 & XSTATE_BNDREGS_MASK) { + /* MPX bound registers */ + for (i =3D 0; i < 4; ++i) { + cpu_fprintf(f, "BND%d=3D%016" PRIx64 ":%016" PRIx64 "%s", + i, env->bnd_regs[i].ub, env->bnd_regs[i].lb, + (i & 1) ? "\n" : " "); + } + } + + if (env->xcr0 & XSTATE_BNDCSR_MASK) { + /* MPX bound status/config registers */ + cpu_fprintf(f, "BNDCFGU=3D%016" PRIx64 " BNDSTATUS=3D%016" PRI= x64 "\n", + env->bndcs_regs.cfgu, env->bndcs_regs.sts); } } if (flags & CPU_DUMP_CODE) { --=20 2.14.1