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[90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=znIQ4XuuWniibfGOGqQ0kUF8z+E80+8ODVUVsJCgS+s=; b=HCnH0GTPVBLVtYGLYBNQFIObAIX+5t7jL5VmKjNDj1JR6fsP4naHiFWvNQHwGjpDbk bZbGd3yyuqKBzbnXDfMa5UhzoeY2BYNu37wdvjC2Dw9uG0VonHxsdgzL9sAxVrakjOtx 472tAzV0yXdV8hoYq6GjQd5thrZ6HmV4hCkz+aYTnKXx8WaxgmYyxo1ASJkXMRsxi676 PzpBCg8IRo8FD1SZE1zz3cPK7K65AZOw+3HgW7MwX6yI2yM5cwKa1Ocvr+s9U2RxwBCG FpmR4WKIiLu5DrhTIzoDJUS8ljpDLHC0WV00AJwFsKkO52E/rQQybVrrxI8jNbCe+u/L jEGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=znIQ4XuuWniibfGOGqQ0kUF8z+E80+8ODVUVsJCgS+s=; b=S17+Dc2O4UY+fPNYiiE5T7DDiKe74fCWR12el5XE8tJGTVVCvIYPzlAbhtNTqu8Tng QuTAfei81rfmXJyk0vZM6tLPRUlg69ltxmEmLQ9E98zH6999aeh7yLSF90H+WwfMxBL7 P3V22N50GdSunn/gd/oy1Xy1MR3atKcb3JiRL2CuuQTC1RcsR0jLCKdALzcPfCQl/Tqb rLspg6VkvPy0bwoQpt0/EFT2IjfUqzqgjXpCroqELwbIx/JUPUw7nThGJfVeINJG4pg6 /JhnOMiz0N4NHPXFscblm1MxyBeOPDlALKtr/e7CU6by7kPA238Y+oI2nrb6XKrLuOTa Vssw== X-Gm-Message-State: AJaThX4FJpYwoWa1deMFn0jtKW54UcVxoVWF0svR6uWx4yfOFoYBwYF5 ANFZKY1XYp5bbAP2yh6/xEjsNg== X-Google-Smtp-Source: AGs4zMajgEySRYGqaaT+YO30D15agTAmwEXcWBz9a1km6gKtjvVkn84OL87pcqOyoveUOgVu08ptmA== X-Received: by 10.25.21.74 with SMTP id l71mr11025970lfi.241.1511738200402; Sun, 26 Nov 2017 15:16:40 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:22 +0100 Message-Id: <20171126231634.9531-2-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v9 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice, Eon and Macronix. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/block/m25p80.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a2438b9..d50acc1 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -423,6 +423,7 @@ typedef struct Flash { uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; uint32_t len; uint32_t pos; + bool data_read_loop; uint8_t needed_bytes; uint8_t cmd_in_progress; uint32_t cur_addr; @@ -983,6 +984,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -993,6 +995,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -1133,6 +1136,7 @@ static int m25p80_cs(SSISlave *ss, bool select) s->pos =3D 0; s->state =3D STATE_IDLE; flash_sync_dirty(s, -1); + s->data_read_loop =3D false; } =20 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); @@ -1198,7 +1202,9 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32= _t tx) s->pos++; if (s->pos =3D=3D s->len) { s->pos =3D 0; - s->state =3D STATE_IDLE; + if (!s->data_read_loop) { + s->state =3D STATE_IDLE; + } } break; =20 @@ -1269,11 +1275,38 @@ static Property m25p80_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static int m25p80_pre_load(void *opaque) +{ + Flash *s =3D (Flash *)opaque; + + s->data_read_loop =3D false; + return 0; +} + +static bool m25p80_data_read_loop_needed(void *opaque) +{ + Flash *s =3D (Flash *)opaque; + + return s->data_read_loop; +} + +static const VMStateDescription vmstate_m25p80_data_read_loop =3D { + .name =3D "m25p80/data_read_loop", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D m25p80_data_read_loop_needed, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(data_read_loop, Flash), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m25p80 =3D { .name =3D "m25p80", .version_id =3D 0, .minimum_version_id =3D 0, .pre_save =3D m25p80_pre_save, + .pre_load =3D m25p80_pre_load, .fields =3D (VMStateField[]) { VMSTATE_UINT8(state, Flash), VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), @@ -1295,6 +1328,10 @@ static const VMStateDescription vmstate_m25p80 =3D { VMSTATE_UINT8(spansion_cr3nv, Flash), VMSTATE_UINT8(spansion_cr4nv, Flash), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_m25p80_data_read_loop, + NULL } }; =20 --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738335064942.5539868706783; Sun, 26 Nov 2017 15:18:55 -0800 (PST) Received: from localhost ([::1]:58423 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6CK-000670-86 for importer@patchew.org; Sun, 26 Nov 2017 18:18:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AG-0004Ge-Pw for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AF-0000po-Ra for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:44 -0500 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:34141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AF-0000pM-JN for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:43 -0500 Received: by mail-lf0-x243.google.com with SMTP id i14so30684155lfc.1 for ; Sun, 26 Nov 2017 15:16:43 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xu0+yt3RLda/3XjDZAEzZwWRT0gdVqr5WLY5RIqSepc=; b=m3anlYtpcwHALgmGxsQU4hqPzTywU5zozz6PEfLrx3+AF4HE8xEbX5wwsqkncfALmr n7I6lvkvJLyrXsDQsoL1Rtb+USVJNXDEKB/uiB6bAtXYgE35Aj2xbn+wjIgAMsJWYuBe fcpoa2+DtWSR90WNU7/2QtKdemM9NWydQp3fTA9vvOUIdSPCFflUkX0Z/5W0W+3vuq0n iyZ6hT/nIedSUPnKNCiVV2wKPfld2UOFatpOi1/XQ1qlydc6I35K3hkGk1gn3GALHCsZ plaKj6mrwxz4/4bmxmdCqnkFj9wcDvOQCXqGTgbiZoKAl6i9eeZi1wwsw8TDVk/Vgx8z YTUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xu0+yt3RLda/3XjDZAEzZwWRT0gdVqr5WLY5RIqSepc=; b=kCSGApimAF1TaNw8WbYBjsgPIxsVcFe3mZ7gPVxzdvHeVDMQOMl5NBoJ1/srZGwqwQ LxWqJHZjPwhPpqF1D8/w1k8I+2flapVuxQhf7lXn6ZEBXsOgzE9wiz1Vup7gUjJPiKsS FmE1NhYxjWjzn6O3+i3xu2BoMQEbT9VsJpBYqSGOxmLEaQkgYc4u0vxlOMa2483De6LY h6wU+Exv+zAjP5D23UuUGCtSrs6tqDdgQsl0tltaBSgB+adJcQtoPgfSQoJaE3kgP2Mo kZyfEytpt8OUVF9F+RA1c7KDgvqEqSKjyUEpSMG0dViz96j0+M14JVSYhpHwOQWjW1l6 9iPw== X-Gm-Message-State: AJaThX4gIzLY6eYx7Kkeh49TW2KCEnWafq96w2uKNN0Oyz9qEGSuZgqw IeNWr2FrmZjWN9G4fGKDT/Ot1Q== X-Google-Smtp-Source: AGs4zMYFePngyb55SZbHcSfsd+pcbR6+x5l0vzDnIGed/u/tVOiJb3uMcJ8Q0dFwPX5Uhl5OwgPiaQ== X-Received: by 10.25.168.140 with SMTP id r134mr4206376lfe.65.1511738202025; Sun, 26 Nov 2017 15:16:42 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:23 +0100 Message-Id: <20171126231634.9531-3-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v9 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacturer ID and device ID. Signed-off-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/m25p80.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index d50acc1..092c0c6 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -355,6 +355,8 @@ typedef enum { DPP =3D 0xa2, QPP =3D 0x32, QPP_4 =3D 0x34, + RDID_90 =3D 0x90, + RDID_AB =3D 0xab, =20 ERASE_4K =3D 0x20, ERASE4_4K =3D 0x21, @@ -405,6 +407,7 @@ typedef enum { MAN_MACRONIX, MAN_NUMONYX, MAN_WINBOND, + MAN_SST, MAN_GENERIC, } Manufacturer; =20 @@ -476,6 +479,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_SPANSION; case 0xC2: return MAN_MACRONIX; + case 0xBF: + return MAN_SST; default: return MAN_GENERIC; } @@ -711,6 +716,31 @@ static void complete_collecting_data(Flash *s) case WEVCR: s->enh_volatile_cfg =3D s->data[0]; break; + case RDID_90: + case RDID_AB: + if (get_man(s) =3D=3D MAN_SST) { + if (s->cur_addr <=3D 1) { + if (s->cur_addr) { + s->data[0] =3D s->pi->id[2]; + s->data[1] =3D s->pi->id[0]; + } else { + s->data[0] =3D s->pi->id[0]; + s->data[1] =3D s->pi->id[2]; + } + s->pos =3D 0; + s->len =3D 2; + s->data_read_loop =3D true; + s->state =3D STATE_READING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "M25P80: Invalid read id address\n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "M25P80: Read id (command 0x90/0xAB) is not supp= orted" + " by device\n"); + } + break; default: break; } @@ -926,6 +956,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) case PP4: case PP4_4: case DIE_ERASE: + case RDID_90: + case RDID_AB: s->needed_bytes =3D get_addr_length(s); s->pos =3D 0; s->len =3D 0; --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738512535699.8551412384888; Sun, 26 Nov 2017 15:21:52 -0800 (PST) Received: from localhost ([::1]:58442 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6Ev-0008PP-OF for importer@patchew.org; Sun, 26 Nov 2017 18:21:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AI-0004LR-79 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AH-0000qu-Al for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:46 -0500 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:42954) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AH-0000qD-2w for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:45 -0500 Received: by mail-lf0-x241.google.com with SMTP id m1so30656768lfj.9 for ; Sun, 26 Nov 2017 15:16:45 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nalsezwvEQd9yNPaNCkW6bPlwlSKzg6SUBHCGCdMXY=; b=A0RUH4ZCxyySn27MBUiuoY+9YTd6VoLdB/8AmJIjeLmP12o0wRQ10CHcfkyizjVDzm h5ikGqOOUeIxcpiA+EpAYaLe8HJIS8VKOaVfO6d4zjSD+7QIsdzdaDRaAVgkBsMplT2V x99xJgLrU7mo1FnhXoV+5aMRc1ORrEPsJ7nfvMwkedKApxzawjLNOoUy1ys8GgGVZFrU YpQOFgYzcC7j60xbE6GBxrTkSRZIVZSaAYgn0NPLcHXa+hcOTLM3H4qhFoe5fLAF6eCC RTCS+Kl1NYqm4+CJOYzKUAvEsmc+FJFNnq3kj5D55szV3IEBkNdvAz1t5KRIPtdKIqxC 0fYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3nalsezwvEQd9yNPaNCkW6bPlwlSKzg6SUBHCGCdMXY=; b=sN44sjenjbGdLrcZbMRYgsOqz3avNygEgOx5BiQh7QWNdVoSnW5IxSIyY1wuwF4kqY 76jfUngYwtLPUKM1dWeVA4M8iKkL1ez1/Ew9jlE2eejl/56rmqsmbkn43V+SOun7Vfle ld9+A5qWbgbaU1pzqELvmV7fLTewclThtLYYw50NfHIab+8M1Y+JO1uoDysNzH1B2lGZ V0qIwt+UO0njdUz8v1m9btEbQ0FsLDIeYemSpKA3CtbmkAsb7tjoIpnDAALdr1UwMhIk GcKNYFFTG8CO2QNL50dwCN5ey5JATnkxLTbFxrb/RWh3r8MoZx7PDzGFCv81C91DuwZB FIxw== X-Gm-Message-State: AJaThX7fQZQtDTY0sDAdXSV8bPDB3/jUkuGmsvMV57MQul33BizirpMi 7cpDBP8ypzDLZ0gWzde9GJhn+Q== X-Google-Smtp-Source: AGs4zMair9dktmwkyZOA3BYUE/XYbpDkdBLMf+9lU7mCne8oRISthvz1eL61jV8yolfuSjeHpQD4/w== X-Received: by 10.25.92.204 with SMTP id u73mr8732078lfi.206.1511738203554; Sun, 26 Nov 2017 15:16:43 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:24 +0100 Message-Id: <20171126231634.9531-4-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v9 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/block/m25p80.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 092c0c6..35efdf0 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -331,7 +331,10 @@ typedef enum { WRDI =3D 0x4, RDSR =3D 0x5, WREN =3D 0x6, + BRRD =3D 0x16, + BRWR =3D 0x17, JEDEC_READ =3D 0x9f, + BULK_ERASE_60 =3D 0x60, BULK_ERASE =3D 0xc7, READ_FSR =3D 0x70, RDCR =3D 0x15, @@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s) s->write_enable =3D false; } break; + case BRWR: case EXTEND_ADDR_WRITE: s->ear =3D s->data[0]; break; @@ -1050,6 +1054,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state =3D STATE_READING_DATA; break; =20 + case BULK_ERASE_60: case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); @@ -1067,12 +1072,14 @@ static void decode_new_cmd(Flash *s, uint32_t value) case EX_4BYTE_ADDR: s->four_bytes_address_mode =3D false; break; + case BRRD: case EXTEND_ADDR_READ: s->data[0] =3D s->ear; s->pos =3D 0; s->len =3D 1; s->state =3D STATE_READING_DATA; break; + case BRWR: case EXTEND_ADDR_WRITE: if (s->write_enable) { s->needed_bytes =3D 1; --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738508696464.0155354758534; Sun, 26 Nov 2017 15:21:48 -0800 (PST) Received: from localhost ([::1]:58440 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6Ev-0008OK-AN for importer@patchew.org; Sun, 26 Nov 2017 18:21:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AJ-0004Mz-Ih for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AI-0000rK-O3 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:47 -0500 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:40908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AI-0000r1-GS for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:46 -0500 Received: by mail-lf0-x243.google.com with SMTP id d10so19608973lfj.7 for ; Sun, 26 Nov 2017 15:16:46 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v9 04/13] m25p80: Add support for n25q512a11 and n25q512a13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 35efdf0..ea14216 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -240,6 +240,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, + { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151173862998850.45525631681937; Sun, 26 Nov 2017 15:23:49 -0800 (PST) Received: from localhost ([::1]:58458 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6H2-0002Ul-8x for importer@patchew.org; Sun, 26 Nov 2017 18:23:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AL-0004Rd-CQ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AK-0000rq-AZ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:49 -0500 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:43798) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AK-0000rX-2Z for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:48 -0500 Received: by mail-lf0-x241.google.com with SMTP id 73so30653516lfu.10 for ; Sun, 26 Nov 2017 15:16:48 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QqcpZUqH4Q+uhKeZJ+Daf1++gdeCQOEuV6orauuAWik=; b=AItHx+FJSD1nyNMYjNK7Mjy02TOSXyE/dtp0xUMkrmWwOEEWG3fr3OO7hASV4jq//j L8rBECeg34HlWTwMu+zLEBexJC/c43aY69oSIEkUGjp/Xk/gioyIkYK0uW5Cjl8KyHb4 I2lGZVANtbbo4Mqer+kCGIkVLKj0ZyY9uaUMrELToD6a/P5NtezN8F1wizFjif3hy+4D zHTkMzZUXYVFBuneCUg6wErREFa0RIx7yp4Vb2SY2hbozxydrNF9u1JwDwlAS6bqWrr9 yT6VbnBVnyJzPK0wsT09cLphohgIUaBqq5mIhA+vXb1bOq7fekUDkfnqCIYDvceaVYKZ QOtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QqcpZUqH4Q+uhKeZJ+Daf1++gdeCQOEuV6orauuAWik=; b=ok0ifpu+W6+dl3MOKUlLnfcfov0TZdPnaEZLWEXWA7mmLzmNqn3v7BsM1xTMqemhS/ aNBjrU6FI0W6ealaIWg018ARZKaGaYtoVddGsYH64iiPHQvXRSOaN/PGMPizmMyQQKIX ZwYkE6nqkd3pWIGbo8c5H9yNXT1c3G8G+1/nbMFFiTm0LPNizLIvf/OzQmfaxSbL3ndS j5FNJtYS8kj9gsjSsr5fFBUz5eL5mLfBEhQXcZ65ixcxMemTPICg0sJvEXoKoH9RQtku MevTdijUlrPj0aTb+XrwzI9qzOD6ZpVOd5/inY4sPFTvhXFdcgRMY2ZQtYMoYTzo8tP8 KyNA== X-Gm-Message-State: AJaThX7XZp8v1KZY3NFOPR+GOdZr39ke8M7HQ0quSCUbY71AY+YSpYYe AdJErHZMS5Qz3GsPfI8/X6vdfA== X-Google-Smtp-Source: AGs4zMbsYE0BLhLsms2o/rT2ZYWD55dtleWvFOK415muPOisVUe3DMRvke4nUL5O1Yb7FxyhYUV22A== X-Received: by 10.25.205.77 with SMTP id d74mr2821197lfg.194.1511738206555; Sun, 26 Nov 2017 15:16:46 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:26 +0100 Message-Id: <20171126231634.9531-6-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v9 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency (struct XilinxSPIPS is found there). Also move out a define and remove two double included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 35 ----------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..559fa79 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,44 +114,11 @@ =20 /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 =20 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 =20 -typedef enum { - READ =3D 0x3, - FAST_READ =3D 0xb, - DOR =3D 0x3b, - QOR =3D 0x6b, - DIOR =3D 0xbb, - QIOR =3D 0xeb, - - PP =3D 0x2, - DPP =3D 0xa2, - QPP =3D 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; - static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) =20 +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ =3D 0x3, READ_4 =3D 0x13, + FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, + DOR =3D 0x3b, DOR_4 =3D 0x3c, + QOR =3D 0x6b, QOR_4 =3D 0x6c, + DIOR =3D 0xbb, DIOR_4 =3D 0xbc, + QIOR =3D 0xeb, QIOR_4 =3D 0xec, + + PP =3D 0x2, PP_4 =3D 0x12, + DPP =3D 0xa2, + QPP =3D 0x32, QPP_4 =3D 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; =20 @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; =20 +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" =20 --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738362684929.116401702879; Sun, 26 Nov 2017 15:19:22 -0800 (PST) Received: from localhost ([::1]:58424 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6CX-0006Iq-Ap for importer@patchew.org; Sun, 26 Nov 2017 18:19:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AO-0004Z9-IU for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AL-0000sQ-Ts for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:52 -0500 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:38270) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AL-0000rv-LZ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:49 -0500 Received: by mail-lf0-x244.google.com with SMTP id c188so23160373lfd.5 for ; Sun, 26 Nov 2017 15:16:49 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3wSYmfzEkkrslM6tMYxuIEfNmZ+9NYiFb0ns0uEC1uM=; b=Gcu0ba7h+yhi0AofY0ALqsONBwPoUpbWY28wTuqmGYAAfyla/WCmPICQwMcm1x6zWG J/Wb6Ba8PRVc2T59r0TCo1+dMHuRzTc2xY1bYgKKc1J9+2LvJk64yt919r0466brm22Z JNYitxpsPYavihDY5IC9IKFSzkbA1BIpFwAfuOe5E1abAq49ia+OLsxKJBwLiPWRrL5Z MkwCHV17Ixfe4o7e+Ll/FtyWa0dw4Wg6qs3QaEw9t/WX3jYV/CM0UlunZKfVYXHybFBV iIsilnMW95yVP/0MPPVR4TotQw77OnElNZw+6sFIkle9bo7QMAZtzRgVuaCyY6KMARgf e3QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3wSYmfzEkkrslM6tMYxuIEfNmZ+9NYiFb0ns0uEC1uM=; b=bRkx3p7W/UQjo0ljWRO8UDAXLp+qUFDBtEPCmwttTb9x4xf3Nc0eOgn7dG0edRD9AP LSyJAu90iNAq1QP3UgHasRYoJU+L00OtR05NEPuDTKA03iMWlc1UJeF/nRtf3BqolDKM W/IJa75yXWoHo3Jjtb1rsvg5VTd43WC+4EFdu4CCtSxV5W0dXyrE6ewSVMra7DR3G6RO OJObuzZKE+2zqjFu1Bgf3gCqDqx+wqGIUy2WHAX5SgxuaTio9I7SgSaNC6dXa79h1zKz I/FKHMsnj2/P4TQe3ZCfJygTUyOk/bZlPKOIMzBLS/o0J+G0ukC3CKxD3k7tZPJxHSyN bNVg== X-Gm-Message-State: AJaThX632x5JbmKVpszS4F5+na5Lv28dBdoNlEJmCdKEPqw9imDWujZb xxnMDsK1ZMZVAFPklP1u+bbeHQ== X-Google-Smtp-Source: AGs4zMbv+q85vDZDoYWxOCsbQ3+qcSZmZJxpMIRyMxAiD2BUVVCqhOyTp3ZDZzJNZF5R72IUtiU5kg== X-Received: by 10.46.101.141 with SMTP id e13mr5046981ljf.127.1511738208054; Sun, 26 Nov 2017 15:16:48 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:27 +0100 Message-Id: <20171126231634.9531-7-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v9 06/13] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update striping functionality to be big-endian bit order (as according to the Zynq-7000 Technical Reference Manual). Output thereafter the even bits into the flash memory connected to the lower QSPI bus and the odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 559fa79..231aa5b 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -208,14 +208,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): * - * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { 52hebGDA, }} */ =20 static inline void stripe8(uint8_t *x, int num, bool dir) @@ -223,15 +223,15 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] =3D {0, 0}; - int bit[2] =3D {0, 0}; + int bit[2] =3D {0, 7}; int d =3D dir; =20 for (idx[0] =3D 0; idx[0] < num; ++idx[0]) { - for (bit[0] =3D 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |=3D x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] =3D 7; bit[0] >=3D 0; bit[0]--) { + r[idx[!d]] |=3D x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] =3D (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1]--; } } } @@ -266,8 +266,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { + int bus =3D num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); } =20 --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738733006273.18952487043066; Sun, 26 Nov 2017 15:25:33 -0800 (PST) Received: from localhost ([::1]:58466 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6If-0003dK-3E for importer@patchew.org; Sun, 26 Nov 2017 18:25:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AP-0004Zr-AM for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AN-0000tA-KT for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:53 -0500 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:36817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AN-0000st-86 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:51 -0500 Received: by mail-lf0-x244.google.com with SMTP id k66so30675151lfg.3 for ; Sun, 26 Nov 2017 15:16:51 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5KTvL3yzFhefNBxPweHDGqlsSJG5GWQCqLGGqN9oGLQ=; b=cUE6YN7peiIEfKFcmhvjOgU7835LkNlWx2Cuxd+GBqJkJQYn3xDbjl+FxuI3it9Bj0 I+dIVHVfBfzEzmtaabAug6CmuqzjMMY44CNbSh3mPD+r5LPvAD2UAR/BVSLtiaJZ13WO z7LFX8VWFbLlm/Kv6+l98YanX1BfpW44soCbHK+6NKqPTF5wZbz+nAlxyO5jZqMFQ/Kh 2Kqekm3x07Vwr2/ffw0OVnHL/8ylscvAxsCmpzE4Y2c4/DE5nVqn0nph+t28OrtEpsL/ Vzm5cZkEawhOyKkfyydIsGntcJQWLKIXIXWysNBXVav1zpUWQ8sPIkD2ivG05B+iaclh 7PGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5KTvL3yzFhefNBxPweHDGqlsSJG5GWQCqLGGqN9oGLQ=; b=n22K1c8KPRXbXC/47/Xto+cfc7T9xmyyrVFdO5emzLufrb7yapzMvivDtOxuAmhp5+ OrepUc/KnOQ0f03/LOjh0QSkGyjeStvWX8q2wrSSHzOBbRxjZgsHvgP/FAeHTtZqmIEL HLztbsP1p0k5cQ6UXeHgchO1YSLIxZmTu/gI/qnvVwYTemKDUjeDtY2l3G+yLUpV5UCb CnQqx5T3LpHkGwgoLrJsAyD0H0KUc+1hJZ3pcdSVHwgkDp1MjwGLvZUPRlBTgeVeVM0V rNO8ZENVhXsk7dyb69MLnh6go6gXoieTOjLZrMrivvCNKXe8aHSuHwi13KmB0FOdAKr4 S9QA== X-Gm-Message-State: AJaThX5uGFWJ3Y13LtNOEsF0OrADVic/aseS1Gmm0cwEiGlBC3kwDHBd 4wftpaiBa3nkjzZcWrT+i7veEg== X-Google-Smtp-Source: AGs4zMb85eAKgVE+pgRKi9B3xEfF1aAsmfOadaLjUK+wQHhgcKLEtkloGhl3MxiUaaV/ixf9ftdiPA== X-Received: by 10.46.85.18 with SMTP id j18mr11418155ljb.109.1511738209678; Sun, 26 Nov 2017 15:16:49 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:28 +0100 Message-Id: <20171126231634.9531-8-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v9 07/13] xilinx_spips: Add support for RX discard and RX drain X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 167 +++++++++++++++++++++++++++++++++++++-= ---- include/hw/ssi/xilinx_spips.h | 6 ++ 2 files changed, 155 insertions(+), 18 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 231aa5b..691d48d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -30,6 +30,7 @@ #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" +#include "hw/register.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -100,6 +101,14 @@ #define LQSPI_CFG_DUMMY_SHIFT 8 #define LQSPI_CFG_INST_CODE 0xFF =20 +#define R_CMND (0xc0 / 4) + #define R_CMND_RXFIFO_DRAIN (1 << 19) + FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) +#define R_CMND_EXT_ADD (1 << 15) + FIELD(CMND, RX_DISCARD, 8, 7) + FIELD(CMND, DUMMY_CYCLES, 2, 6) +#define R_CMND_DMA_EN (1 << 1) +#define R_CMND_PUSH_WAIT (1 << 0) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -116,7 +125,8 @@ #define LQSPI_ADDRESS_BITS 24 =20 #define SNOOP_CHECKING 0xFF -#define SNOOP_NONE 0xFE +#define SNOOP_ADDR 0xF0 +#define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 =20 static inline int num_effective_busses(XilinxSPIPS *s) @@ -146,9 +156,14 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT_L(0, "selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); + if (s->cs_lines_state[cs_to_set]) { + s->cs_lines_state[cs_to_set] =3D false; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); + } } else { DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); + s->cs_lines_state[cs_to_set] =3D true; } } if (xilinx_spips_cs_is_set(s, i, field)) { @@ -157,6 +172,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) } if (!found) { s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; DB_PRINT_L(1, "moving to snoop check state\n"); } } @@ -203,7 +222,11 @@ static void xilinx_spips_reset(DeviceState *d) /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] =3D 0x01090106; s->regs[R_LQSPI_CFG] =3D R_LQSPI_CFG_RESET; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -238,14 +261,69 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) +{ + if (!qs) { + /* The SPI device is not a QSPI device */ + return -1; + } + + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 5; + default: + return -1; + } +} + +static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) +{ + switch (cmd) { + case PP_4: + case QPP_4: + case READ_4: + case QIOR_4: + case FAST_READ_4: + case DOR_4: + case QOR_4: + case DIOR_4: + return 4; + default: + return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; + } +} + static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) { int debug_level =3D 0; + XilinxQSPIPS *q =3D (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), + TYPE_XILINX_QSP= IPS); =20 for (;;) { int i; uint8_t tx =3D 0; uint8_t tx_rx[num_effective_busses(s)]; + uint8_t dummy_cycles =3D 0; + uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { @@ -258,54 +336,102 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] =3D fifo8_pop(&s->tx_fifo); } stripe8(tx_rx, num_effective_busses(s), false); - } else { + } else if (s->snoop_state >=3D SNOOP_ADDR) { tx =3D fifo8_pop(&s->tx_fifo); for (i =3D 0; i < num_effective_busses(s); ++i) { tx_rx[i] =3D tx; } + } else { + /* Extract a dummy byte and generate dummy cycles according to= the + * link state */ + tx =3D fifo8_pop(&s->tx_fifo); + dummy_cycles =3D 8 / s->link_state; } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { int bus =3D num_effective_busses(s) - 1 - i; - DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); - DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + if (dummy_cycles) { + int d; + for (d =3D 0; d < dummy_cycles; ++d) { + tx_rx[0] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx= [0]); + } + } else { + DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); + DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + } } =20 - if (fifo8_is_full(&s->rx_fifo)) { + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); + /* Do nothing */ + } else if (s->rx_discard) { + DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); + s->rx_discard -=3D 8 / s->link_state; + } else if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_INTR_STATUS] |=3D IXR_RX_FIFO_OVERFLOW; DB_PRINT_L(0, "rx FIFO overflow"); } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { stripe8(tx_rx, num_effective_busses(s), true); for (i =3D 0; i < num_effective_busses(s); ++i) { fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); + DB_PRINT_L(debug_level, "pushing striped rx byte\n"); } } else { + DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); } =20 + if (s->link_state_next_when) { + s->link_state_next_when--; + if (!s->link_state_next_when) { + s->link_state =3D s->link_state_next; + } + } + DB_PRINT_L(debug_level, "initial snoop state: %x\n", (unsigned)s->snoop_state); switch (s->snoop_state) { case (SNOOP_CHECKING): - switch (tx) { /* new instruction code */ - case READ: /* 3 address bytes, no dummy bytes/cycles */ - case PP: + /* Store the count of dummy bytes in the txfifo */ + s->cmd_dummies =3D xilinx_spips_num_dummies(q, tx); + addr_length =3D get_addr_length(s, tx); + if (s->cmd_dummies < 0) { + s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D SNOOP_ADDR + addr_length - 1; + } + switch (tx) { case DPP: - case QPP: - s->snoop_state =3D 3; - break; - case FAST_READ: /* 3 address bytes, 1 dummy byte */ case DOR: + case DOR_4: + s->link_state_next =3D 2; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case QPP: + case QPP_4: case QOR: - case DIOR: /* FIXME: these vary between vendor - set to spansi= on */ - s->snoop_state =3D 4; + case QOR_4: + s->link_state_next =3D 4; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case DIOR: + case DIOR_4: + s->link_state =3D 2; break; - case QIOR: /* 3 address bytes, 2 dummy bytes */ - s->snoop_state =3D 6; + case QIOR: + case QIOR_4: + s->link_state =3D 4; break; - default: + } + break; + case (SNOOP_ADDR): + /* Address has been transmitted, transmit dummy cycles now if + * needed */ + if (s->cmd_dummies < 0) { s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D s->cmd_dummies; } break; case (SNOOP_STRIPING): @@ -483,6 +609,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, uint64_t value, unsigned size) { XilinxQSPIPS *q =3D XILINX_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(opaque); =20 xilinx_spips_write(opaque, addr, value, size); addr >>=3D 2; @@ -490,6 +617,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, if (addr =3D=3D R_LQSPI_CFG) { xilinx_qspips_invalidate_mmio_ptr(q); } + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + fifo8_reset(&s->rx_fifo); + } } =20 static const MemoryRegionOps qspips_ops =3D { @@ -632,6 +762,7 @@ static void xilinx_spips_realize(DeviceState *dev, Erro= r **errp) } =20 s->cs_lines =3D g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state =3D g_new0(bool, s->num_cs * s->num_busses); for (i =3D 0, cs =3D s->cs_lines; i < s->num_busses; ++i, cs +=3D s->n= um_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7f9e2fc..bac90a5 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -61,13 +61,19 @@ struct XilinxSPIPS { uint8_t num_busses; =20 uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; =20 Fifo8 rx_fifo; Fifo8 tx_fifo; =20 uint8_t num_txrx_bytes; + uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; }; --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738827644995.1702657527122; Sun, 26 Nov 2017 15:27:07 -0800 (PST) Received: from localhost ([::1]:58478 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6K3-0004l3-IW for importer@patchew.org; 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[90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bdrjykzqXzKWm6F6HhMzlVMUTOERVvEewFrJlkNkkwc=; b=AVwhNQsQDoBn1U3LzF39gioM0hQE0LpKosNK9SX8OhvXn/jp8E9AVX520WV79/kUD3 BOMjd+QLGYEn4iNau89/ETJXiJF/+ZS5Oj5bWJw58h0O5as6PMDONMACfUC2EnOaHQJ+ 3Z5jC+dpfGkEfcKNV3AkDfagL6eZrno3ADKWJjZiE8DdyHi2Qc6WIFCR25lO7alPlPuF +UfazILsbL0qux3aggQ9aWgFgN0ruGWfsOm0tEH8SNJ5kzIbc1kOhwpUcE6/zFa+HGCu mAvACrOrKaDTkKATyD/IeKQvPvc0MumkvjAq8RXnfEI3lvwKZd3/leTT56qkde+dUkKX aEig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bdrjykzqXzKWm6F6HhMzlVMUTOERVvEewFrJlkNkkwc=; b=aS0Alw/fmZQ+zmCYYkKZ0sNYuufNldQ9udzsicQ23Xt9PV6+F3XGRZC0+EGrx3zP0s KlFidhBA1VOh3ya+t7OnRmgZe4e/fsbtpg3HcmZFGy4AB94Q2N8OpSZ/WI9TGtfgcAII aWDrOELNPNUcirRkxWyyNGpcG+rp//U/20uJy8qU5hWq3QryU4hpLDBXGZpkgwL/VosZ 9K1x1UEc203bIVAVWgWCLuRPQ3NvkBHhPoJU+DoYnR4QAiqq2tj90dPDKfyzbz/fGP7R Wsqc6tOplhWgjzaOw9B2dooC6r4h8M7h0nPcz97y+CmHghSktk/GsWDB+34jXHGmRmbi gGQA== X-Gm-Message-State: AJaThX7dnQCA+h/aYKGWGPT0U1mw5m9BnHXJezVTUfIbURvmbK0RybDc pjDkqAqlgAt9HDjlJGfMebAdfg== X-Google-Smtp-Source: AGs4zMZyj9NOS3haD8CUOse1EqCES7QKdVL499GizqBvV3aqoekAv9ht/EGhPoiWahpuAxAeIvhTNg== X-Received: by 10.46.2.17 with SMTP id 17mr15175300ljc.67.1511738211186; Sun, 26 Nov 2017 15:16:51 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:29 +0100 Message-Id: <20171126231634.9531-9-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v9 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 64 +++++++++++++++++++++++++++++------------------= ---- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 691d48d..4621dbb 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -450,13 +450,28 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } =20 -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, boo= l be) { int i; + for (i =3D 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<=3D 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>=3D 8; + } + } +} =20 - for (i =3D 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - value[i] =3D fifo8_pop(&s->rx_fifo); +static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) +{ + int i; + + for (i =3D 0; i < max && !fifo8_is_empty(fifo); ++i) { + value[i] =3D fifo8_pop(fifo); } + return max - i; } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -466,6 +481,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, uint32_t mask =3D ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; =20 addr >>=3D 2; switch (addr) { @@ -496,9 +512,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret =3D s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_b= uf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall =3D rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes= ); + ret =3D s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<=3D 8 * shortfall; + } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -509,20 +529,6 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i =3D 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<=3D 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>=3D 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -563,16 +569,20 @@ static void xilinx_spips_write(void *opaque, hwaddr a= ddr, mask =3D 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); @@ -682,11 +692,11 @@ static void lqspi_load_cache(void *opaque, hwaddr add= r) =20 while (cache_entry < LQSPI_CACHE_SIZE) { for (i =3D 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i =3D 0; i < 64; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); + rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1= ); } } =20 --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151173889440823.75353357827703; Sun, 26 Nov 2017 15:28:14 -0800 (PST) Received: from localhost ([::1]:58481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6L9-0005Vb-JQ for importer@patchew.org; Sun, 26 Nov 2017 18:27:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50264) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AR-0004bh-EG for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AQ-0000ue-F0 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:55 -0500 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:40909) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AQ-0000uA-7L for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:54 -0500 Received: by mail-lf0-x242.google.com with SMTP id d10so19609169lfj.7 for ; Sun, 26 Nov 2017 15:16:54 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. 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X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v9 09/13] xilinx_spips: Add support for zero pumping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++---= ---- include/hw/ssi/xilinx_spips.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 4621dbb..878b17e 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ FIELD(CMND, DUMMY_CYCLES, 2, 6) #define R_CMND_DMA_EN (1 << 1) #define R_CMND_PUSH_WAIT (1 << 0) +#define R_TRANSFER_SIZE (0xc4 / 4) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d) s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; + s->man_start_com =3D false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t= value, int num, bool be) } } =20 +static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) +{ + if (!s->regs[R_TRANSFER_SIZE]) { + return; + } + if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT= ) { + return; + } + /* + * The zero pump must never fill tx fifo such that rx overflow is + * possible + */ + while (s->regs[R_TRANSFER_SIZE] && + s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { + /* endianess just doesn't matter when zero pumping */ + tx_data_bytes(&s->tx_fifo, 0, 4, false); + s->regs[R_TRANSFER_SIZE] &=3D ~0x03ull; + s->regs[R_TRANSFER_SIZE] -=3D 4; + } +} + +static void xilinx_spips_check_flush(XilinxSPIPS *s) +{ + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } + if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { + s->man_start_com =3D false; + } + xilinx_spips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, uint64_t value, unsigned size) { int mask =3D ~0; - int man_start_com =3D 0; XilinxSPIPS *s =3D opaque; =20 DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); @@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, switch (addr) { case R_CONFIG: mask =3D ~(R_CONFIG_RSVD | MAN_START_COM); - if (value & MAN_START_COM) { - man_start_com =3D 1; + if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN))= { + s->man_start_com =3D true; } break; case R_INTR_STATUS: @@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr ad= dr, s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: xilinx_spips_update_cs_lines(s); - if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || - (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_= EN)) { - xilinx_spips_flush_txfifo(s); - } + xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index bac90a5..ad2175a 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -76,6 +76,8 @@ struct XilinxSPIPS { uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; =20 typedef struct { --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738972706494.4457540104073; Sun, 26 Nov 2017 15:29:32 -0800 (PST) Received: from localhost ([::1]:58488 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6MO-0006lM-Tk for importer@patchew.org; Sun, 26 Nov 2017 18:29:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AS-0004d9-Q0 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AS-0000vQ-0n for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:56 -0500 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:45062) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AR-0000ul-P7 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:55 -0500 Received: by mail-lf0-x241.google.com with SMTP id f131so22662212lff.12 for ; Sun, 26 Nov 2017 15:16:55 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FyKV9YMaKdDeUyfkAioenF3+YIeH7mO4K/KuYDet/+A=; b=tuqec58XB3+Z5KLKq7BzvYy+GN2fGDBmaahhppnYe/f8T9R1jb1aRu2G9GX3jrZti5 GjpFQs0TRzW8PHh9RPRLQ+PCV8cCLSsEPGdPJYSayPrNKPxijjb4doss0fogdEaYwHKf DqoKjEn0LoVj5RWKd4lEU98gl9l1rhQtjg1uYO9VTVRn/xSwQoCNw6UakzpqniJx9pG8 1rmZrp332umAs+G8A7Ccfu3K96kHy304aebquobE1hTm6SIbsZ+/yicj5poy4lk5DrNC YTATEM7hw3dAjVi8DDerUbDZVc8LrGu3LFIfP0sAoiJZaVigpCXtgV9vqCFm1sq+tz3j CfFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FyKV9YMaKdDeUyfkAioenF3+YIeH7mO4K/KuYDet/+A=; b=CMq3H6PhIJrBzIRVczoKNedqtPGNjEbAdVN6hbq59AhvDatzRGWXEnfTJmWZiBEYtB NZ676TZ+y1CyalpnAa43viHV0VQcI1Y/kxTQa9mK/0sVQXVwKAlMZWXMb6vg8SyB+J6d Czq8+5F65S1ppgVq3T3FSyXSxfLUaacWctUon4fkSgCDC40+BjXgTBC1cxXcurb0SOOn 0WvC5Qa0Ked7zONx0WLRzW2fyaT+hIgIgYX7GbvXvt1tMaXqMPsONQN4t8DhHeJwlkG3 RgT9C4bw5PRdVNjO3w4uqpBcxNCoCugfDE7rVbIZL9yft8otzdS2PRgxB0K9yHpzvZ83 WKHA== X-Gm-Message-State: AJaThX7Dg9AzJlfiSo9HP5aQwK3WYqkJP4YQzZkoXES96rQqC4a/t3HP 9RprNINo5mWp27jImSSpHeUDVw== X-Google-Smtp-Source: AGs4zMZVXj1DPa7sT+kiAv0b2sGxY6GnlmA58hbCfTYWIThkuKL0Jy6Eea6qQeWoTatAI7Vs4Sh0aQ== X-Received: by 10.25.76.68 with SMTP id z65mr4075700lfa.234.1511738214266; Sun, 26 Nov 2017 15:16:54 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:31 +0100 Message-Id: <20171126231634.9531-11-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v9 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 878b17e..ab54da8 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE= ); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738666603645.2358176011458; Sun, 26 Nov 2017 15:24:26 -0800 (PST) Received: from localhost ([::1]:58459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6Hd-0002uG-TW for importer@patchew.org; Sun, 26 Nov 2017 18:24:21 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AU-0004en-9M for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AT-0000xf-FJ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:58 -0500 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:36997) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AT-0000vo-8J for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:57 -0500 Received: by mail-lf0-x241.google.com with SMTP id y2so29735691lfj.4 for ; Sun, 26 Nov 2017 15:16:57 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=URRWU3vGnIRDzJcyY17DgEXkPD90KuVUQjWNDwaLwa8=; b=rWg7cNyyFZQAGypuElJaF7+H8GOFoFYeSRvM5TS/Mx8jiBt664zSSF+HfF1gXLaqlz tuPG52LOBOWnnf+FY6l0bGSVkCanijfgMOeOzUnYqPl92wPPVqJydrwkj07ha+gMB8KU hdKTBNK+rP6NCGeaVb6w+igHPQot478olDjaWTx0xpvwjTCV6Tz9vdFMmL5d5lodAsSy nW9gzOw3v2U1nfWAQpPJjXOKSw33Z2kRuWhEoewME9mBURDz/kPTepU0uh3+V998Nqhw z9SjZRo53QC9YQ0fOfGs8Wz6yaneihGXwqX2BXcnFsQoTwZQUuVh8SSPHn/InR0QJLcq u12A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=URRWU3vGnIRDzJcyY17DgEXkPD90KuVUQjWNDwaLwa8=; b=Ecb/gBhjLls00jgUcYiREyEqekxg8wtJUjvC5rp0PuefYRGjlwiEJRgFTzEy3o5lvF f4AwisRWzNgqIzTOZqGdZVRtxpB8/X36c0MEJCGXNdJ0hjBvfvroUKYRvo0BUk3vak4d 4VPGdFW0vAWeniiv74fUB43BZElPD1qcGJp4YVp+00iGMvQ1ZR91v1TNzkmYdu8H+R43 75q7wD/ArnS6cn23KXzO5YkuFo/+LrXkFfwvQTnp8V/8waLvl5isRNWDJxnUfOs7dEyU If2nc7ukpSW/o1loVxyMAleSW8R7nl4OJywT0tnipf6JON++i/TPfqK8TQN6hW7W1tvb rGtw== X-Gm-Message-State: AJaThX6IvgqNoP9oPYEsHSJlZBxIMJ+CnbtcqsMt73R5JXpXFa5tih2F fHcjgCIpZtQ2kToIOMZQvOlI/Q== X-Google-Smtp-Source: AGs4zMZ+/dvI9TEWxaXOTLn3pUkA/IVpry6QULhAZOXL6+oWXM1BBt4VVVyiPlzJAVmsfjXMlJQiNQ== X-Received: by 10.25.43.84 with SMTP id r81mr3189780lfr.34.1511738215748; Sun, 26 Nov 2017 15:16:55 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:32 +0100 Message-Id: <20171126231634.9531-12-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v9 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ab54da8..3805d8b 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |=3D IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, ret =3D s->regs[addr] & IXR_ALL; s->regs[addr] =3D 0; DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask =3D IXR_ALL; --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738512931958.3469444365799; Sun, 26 Nov 2017 15:21:52 -0800 (PST) Received: from localhost ([::1]:58443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6F6-00005L-Uo for importer@patchew.org; Sun, 26 Nov 2017 18:21:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AY-0004hx-FW for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AV-0000yY-Qw for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:02 -0500 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:46174) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AV-0000y6-A6 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:16:59 -0500 Received: by mail-lf0-x242.google.com with SMTP id g35so30642764lfi.13 for ; Sun, 26 Nov 2017 15:16:59 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. [90.232.123.128]) by smtp.gmail.com with ESMTPSA id j63sm2070285lfg.95.2017.11.26.15.16.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 15:16:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N3aPqe3zod7OtYm4MrYLMpIKy4oTbGCk4qQALP3REKA=; b=DuWnRESCuY9xjJ4eGzs8qKwLACiiwazurvXAYhzsbkc1sve52DIi81uyVQgANFMZIf abXRVibADQ/nBZhQT8SVgb1pp2n6XLV1dDF39GMuKmZ685bLq3RZuUiS1kTuZWlmvagD R53+HtT+oiCbrMaATZ30s4MP8pzK0dlpKNgwD7sbK/Oe+xVA59v8rI1SI0fKsPbQ6rb1 prjlig5ssGKy2PV/TSU91rI+XbER3e8nRSs3LOTT+9J33zqdbd5VufdpsuE92BGS7Y7r 6itmE6Wb7NXTGLbRw4QSyCKtvlClxG896Pzpdn6lRlkHrvl39Z8scYHS0lKHsnIbI0Qi 50Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N3aPqe3zod7OtYm4MrYLMpIKy4oTbGCk4qQALP3REKA=; b=oDGcXzrNepO3qMrL4Zb713S8ilgfxpFSXN3lEkOYMyNt2pqYPttRxf1m8DAW0ZB1ya boDh33tGvNZeaqsKYHyeToQg7OemRoNpP8oKSPGSNfzREQsFlsYl3r22IrXQK/E9vpZ8 6ObmlyLK3PmM770Q7RHBFPNbfcFhGW1xWvRtqe+n6n2AphaTtYZtBDigOfOir5ixiKs0 q9ZA8Vudqjq5QvFIXFh+bDhIhp+p/U0La03K0DT7X6e/9PSp9RShYiqPHJlhAwEiJDN4 wnYNnlDkWoQCR2ETRB1JIJWkWDeQmU5q1LS9cHgTeCiUtNHfzEDPg2ut0+XKad7bzpwI WMqw== X-Gm-Message-State: AJaThX6HIyY47lI/+7nPKi0x5PGFJX7woO27RJJFHOvbE6NCdb4j1FVH retlJmDtE/WmFpihE9rz5azHZw== X-Google-Smtp-Source: AGs4zMayjHtkRs9PvQAXy0JjYmPCBAlCaFTZt+bSSQcUJCvnLrg0JI5W0qXx/7Zo+DhUdE+eeAWECA== X-Received: by 10.46.64.194 with SMTP id r63mr12587233lje.112.1511738217501; Sun, 26 Nov 2017 15:16:57 -0800 (PST) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Mon, 27 Nov 2017 00:16:33 +0100 Message-Id: <20171126231634.9531-13-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171126231634.9531-1-frasse.iglesias@gmail.com> References: <20171126231634.9531-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v9 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- default-configs/arm-softmmu.mak | 2 +- hw/ssi/xilinx_spips.c | 579 ++++++++++++++++++++++++++++++++++++= ---- include/hw/ssi/xilinx_spips.h | 32 ++- 3 files changed, 564 insertions(+), 49 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index d37edc4..b0d6e65 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,5 +130,5 @@ CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy CONFIG_MSF2=3Dy - CONFIG_FW_CFG_DMA=3Dy +CONFIG_XILINX_AXI=3Dy diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 3805d8b..ad1b2ba 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,30 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) =20 #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -116,9 +134,54 @@ =20 #define R_MOD_ID (0xFC / 4) =20 +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) +#define R_GQSPI_GEN_FIFO (0x140 / 4) +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) +#define R_GQSPI_DATA_STS (0x15c / 4) +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) =20 #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -137,42 +200,22 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } =20 -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) -{ - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); -} - -static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) { - int i, j; - bool found =3D false; - int field =3D s->regs[R_CONFIG] >> CS_SHIFT; + int i; =20 for (i =3D 0; i < s->num_cs; i++) { - for (j =3D 0; j < num_effective_busses(s); j++) { - int upage =3D !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set =3D (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - if (s->cs_lines_state[cs_to_set]) { - s->cs_lines_state[cs_to_set] =3D false; - s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); - } - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - s->cs_lines_state[cs_to_set] =3D true; - } - } - if (xilinx_spips_cs_is_set(s, i, field)) { - found =3D true; + bool old_state =3D s->cs_lines_state[i]; + bool new_state =3D field & (1 << i); + + if (old_state !=3D new_state) { + s->cs_lines_state[i] =3D new_state; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de",= i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; s->link_state =3D 1; @@ -182,21 +225,51 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS = *s) } } =20 +static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) +{ + if (s->regs[R_GQSPI_GF_SNAPSHOT]) { + int field =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SE= LECT); + xilinx_spips_update_cs(XILINX_SPIPS(s), field); + } +} + +static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +{ + int field =3D ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) =3D=3D 2) { + /* Single bit chip-select for qspi */ + field &=3D 0x1; + field |=3D field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + field &=3D 0x1; + /* change from CS0 to CS1 */ + field <<=3D 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + field =3D 0; + } + xilinx_spips_update_cs(s, field); +} + static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &=3D ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |=3D + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL := 0); } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &=3D (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERF= LOW | - IXR_TX_FIFO_MODE_FAIL); - /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |=3D - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY := 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); - /* drive external interrupt pin */ int new_irqline =3D !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & IXR_ALL); if (new_irqline !=3D s->irqline) { @@ -205,6 +278,37 @@ static void xilinx_spips_update_ixr(XilinxSPIPS *s) } } =20 +static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) +{ + uint32_t gqspi_int; + int new_irqline; + + s->regs[R_GQSPI_ISR] &=3D ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |=3D + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >=3D s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + /* GQSPI Interrupt Trigger Status */ + gqspi_int =3D (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_I= XR_MASK; + new_irqline =3D !!(gqspi_int & IXR_ALL); + + /* drive external interrupt pin */ + if (new_irqline !=3D s->gqspi_irqline) { + s->gqspi_irqline =3D new_irqline; + qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); + } +} + static void xilinx_spips_reset(DeviceState *d) { XilinxSPIPS *s =3D XILINX_SPIPS(d); @@ -234,6 +338,28 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 +static void xlnx_zynqmp_qspips_reset(DeviceState *d) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(d); + int i; + + xilinx_spips_reset(d); + + for (i =3D 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) { + s->regs[i] =3D 0; + } + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); + s->regs[R_GQSPI_TX_THRESH] =3D 1; + s->regs[R_GQSPI_RX_THRESH] =3D 1; + s->regs[R_GQSPI_GFIFO_THRESH] =3D 1; + s->regs[R_GQSPI_IMR] =3D GQSPI_IXR_MASK; + s->man_start_com_g =3D false; + s->gqspi_irqline =3D 0; + xlnx_zynqmp_qspips_update_ixr(s); +} + /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: @@ -264,6 +390,108 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2] =3D { 0 }; + int num_stripes =3D 1; + uint8_t busses; + int i; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] =3D fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSH= OT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing= "); + continue; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + + imm =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE= _DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)= || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))= { + s->regs[R_GQSPI_DATA_STS] =3D 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] =3D 0; + } + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONE= NT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer to= o" + " long - 2 ^ %" PRId8 " requested\n", im= m); + } + s->regs[R_GQSPI_DATA_STS] =3D 1ul << imm; + } else { + s->regs[R_GQSPI_DATA_STS] =3D imm; + } + } + /* Zero length transfer check */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && + (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { + num_stripes =3D 2; + } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] =3D ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT))= { + for (i =3D 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] =3D fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes =3D=3D 1) { + /* mirror */ + tx_rx[1] =3D tx_rx[0]; + } + busses =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_S= ELECT); + for (i =3D 0; i < 2; ++i) { + DB_PRINT_L(1, "bus %d tx =3D %02x\n", i, tx_rx[i]); + tx_rx[i] =3D ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); + DB_PRINT_L(1, "bus %d rx =3D %02x\n", i, tx_rx[i]); + } + if (s->regs[R_GQSPI_DATA_STS] > 1 && + busses =3D=3D 0x3 && num_stripes =3D=3D 2) { + s->regs[R_GQSPI_DATA_STS] -=3D 2; + } else if (s->regs[R_GQSPI_DATA_STS] > 0) { + s->regs[R_GQSPI_DATA_STS]--; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i =3D 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte =3D %02x\n", i, tx_rx[= i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -499,6 +727,25 @@ static void xilinx_spips_check_flush(XilinxSPIPS *s) xilinx_spips_update_ixr(s); } =20 +static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) +{ + bool gqspi_has_work =3D s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)))= { + xlnx_zynqmp_qspips_flush_fifo_g(s); + } + } else { + xilinx_spips_check_flush(XILINX_SPIPS(s)); + } + if (!gqspi_has_work) { + s->man_start_com_g =3D false; + } + xlnx_zynqmp_qspips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -509,6 +756,53 @@ static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *= value, int max) return max - i; } =20 +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max =3D=3D 0 || max > fifo->num) { + abort(); + } + *num =3D MIN(fifo->capacity - fifo->head, max); + ret =3D &fifo->data[fifo->head]; + fifo->head +=3D *num; + fifo->head %=3D fifo->capacity; + fifo->num -=3D *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) =3D=3D 2)) { + return; + } + recv_fifo =3D &rq->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo =3D &s->rx_fifo; + } + while (recv_fifo->num >=3D 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd =3D pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret =3D stream_push(rq->dma, rq->dma_buf, 4); + assert(ret =3D=3D 4); + xlnx_zynqmp_qspips_check_flush(rq); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -556,6 +850,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, ret <<=3D 8 * shortfall; } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -565,6 +860,43 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 +static uint64_t xlnx_zynqmp_qspips_read(void *opaque, + hwaddr addr, unsigned size) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg =3D addr / 4; + uint32_t ret; + uint8_t rx_buf[4]; + int shortfall; + + if (reg <=3D R_MOD_ID) { + return xilinx_spips_read(opaque, addr, size); + } else { + switch (reg) { + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Read from empty GQSPI RX FIFO\n"); + return 0; + } + memset(rx_buf, 0, sizeof(rx_buf)); + shortfall =3D rx_data_bytes(&s->rx_fifo_g, rx_buf, + XILINX_SPIPS(s)->num_txrx_bytes); + ret =3D ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { + ret <<=3D 8 * shortfall; + } + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_ixr(s); + return ret; + default: + return s->regs[reg]; + } + } +} + static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -664,12 +996,81 @@ static void xilinx_qspips_write(void *opaque, hwaddr = addr, } } =20 +static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg =3D addr / 4; + + if (reg <=3D R_MOD_ID) { + xilinx_qspips_write(opaque, addr, value, size); + } else { + switch (reg) { + case R_GQSPI_CNFG: + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)= ) { + s->man_start_com_g =3D true; + } + s->regs[reg] =3D value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + break; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + break; + case R_GQSPI_FIFO_CTRL: + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |=3D value; + break; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &=3D ~value; + break; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &=3D ~value; + break; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + break; + default: + s->regs[reg] =3D value; + break; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_update_ixr(s); + } + xlnx_zynqmp_qspips_notify(s); +} + static const MemoryRegionOps qspips_ops =3D { .read =3D xilinx_spips_read, .write =3D xilinx_qspips_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static const MemoryRegionOps xlnx_zynqmp_qspips_ops =3D { + .read =3D xlnx_zynqmp_qspips_read, + .write =3D xlnx_zynqmp_qspips_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 =20 static void lqspi_load_cache(void *opaque, hwaddr addr) @@ -818,7 +1219,7 @@ static void xilinx_spips_realize(DeviceState *dev, Err= or **errp) } =20 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, - "spi", XLNX_SPIPS_R_MAX * 4); + "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); sysbus_init_mmio(sbd, &s->iomem); =20 s->irqline =3D -1; @@ -856,6 +1257,28 @@ static void xilinx_qspips_realize(DeviceState *dev, E= rror **errp) } } =20 +static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(dev); + XilinxSPIPSClass *xsc =3D XILINX_SPIPS_GET_CLASS(s); + + xilinx_qspips_realize(dev, errp); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); +} + +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAV= E, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -877,6 +1300,46 @@ static const VMStateDescription vmstate_xilinx_spips = =3D { } }; =20 +static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) +{ + XlnxZynqMPQSPIPS *s =3D (XlnxZynqMPQSPIPS *)opaque; + XilinxSPIPS *qs =3D XILINX_SPIPS(s); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && + fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { + xlnx_zynqmp_qspips_update_ixr(s); + xlnx_zynqmp_qspips_update_cs_lines(s); + } + return 0; +} + +static const VMStateDescription vmstate_xilinx_qspips =3D { + .name =3D "xilinx_qspips", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, + vmstate_xilinx_spips, XilinxSPIPS), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_xlnx_zynqmp_qspips =3D { + .name =3D "xlnx_zynqmp_qspips", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D xlnx_zynqmp_qspips_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, + vmstate_xilinx_qspips, XilinxQSPIPS), + VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_M= AX), + VMSTATE_END_OF_LIST() + } +}; + static Property xilinx_qspips_properties[] =3D { /* We had to turn this off for 2.10 as it is not compatible with migra= tion. * It can be enabled but will prevent the device to be migrated. @@ -921,6 +1384,19 @@ static void xilinx_spips_class_init(ObjectClass *klas= s, void *data) xsc->tx_fifo_size =3D TXFF_A; } =20 +static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + XilinxSPIPSClass *xsc =3D XILINX_SPIPS_CLASS(klass); + + dc->realize =3D xlnx_zynqmp_qspips_realize; + dc->reset =3D xlnx_zynqmp_qspips_reset; + dc->vmsd =3D &vmstate_xlnx_zynqmp_qspips; + xsc->reg_ops =3D &xlnx_zynqmp_qspips_ops; + xsc->rx_fifo_size =3D RXFF_A_Q; + xsc->tx_fifo_size =3D TXFF_A_Q; +} + static const TypeInfo xilinx_spips_info =3D { .name =3D TYPE_XILINX_SPIPS, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -936,10 +1412,19 @@ static const TypeInfo xilinx_qspips_info =3D { .class_init =3D xilinx_qspips_class_init, }; =20 +static const TypeInfo xlnx_zynqmp_qspips_info =3D { + .name =3D TYPE_XLNX_ZYNQMP_QSPIPS, + .parent =3D TYPE_XILINX_QSPIPS, + .instance_size =3D sizeof(XlnxZynqMPQSPIPS), + .instance_init =3D xlnx_zynqmp_qspips_init, + .class_init =3D xlnx_zynqmp_qspips_class_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } =20 type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index ad2175a..75fc94c 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,13 @@ #define XILINX_SPIPS_H =20 #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" =20 typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) =20 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -89,6 +91,30 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; =20 +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; + int gqspi_irqline; + + uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; + + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * At the end of each generic command, misaligned extra bytes are disc= ard + * or padded to tx and rx respectively to round it out (and avoid need= for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; + bool man_start_com_g; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; =20 @@ -100,6 +126,7 @@ typedef struct XilinxSPIPSClass { =20 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" =20 #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -111,4 +138,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) =20 +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ --=20 2.9.3 From nobody Sat Apr 27 14:50:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511738516007536.084870719163; Sun, 26 Nov 2017 15:21:56 -0800 (PST) Received: from localhost ([::1]:58444 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6FD-0000CW-7Q for importer@patchew.org; Sun, 26 Nov 2017 18:21:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ6AY-0004hh-63 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ6AX-0000z2-48 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:02 -0500 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:42954) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ6AW-0000yV-P4 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 18:17:01 -0500 Received: by mail-lf0-x242.google.com with SMTP id m1so30657129lfj.9 for ; Sun, 26 Nov 2017 15:17:00 -0800 (PST) Received: from localhost.localdomain (host-90-232-123-128.mobileonline.telia.com. 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X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v9 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, francisco.iglesias@feimtech.se, f4bug@amsat.org, edgari@xilinx.com, alistai@xilinx.com, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 54 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index bbe7d04..b126cf1 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -151,6 +151,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineSta= te *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + int bus =3D i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name =3D g_strdup_printf("qspi%d", bus); + + spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name= ); + g_free(bus_name); + + flash_dev =3D ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(di= nfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ =20 xlnx_zcu102_binfo.ram_size =3D ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c707c66..3256420 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 =20 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 =20 @@ -171,6 +175,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } =20 + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); =20 @@ -411,6 +418,25 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) g_free(bus_name); } =20 + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + + /* Alias controller SPI bus to the SoC itself */ + bus_name =3D g_strdup_printf("qspi%d", i); + target_bus =3D g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 =20 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; =20 --=20 2.9.3