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Thu, 23 Nov 2017 12:05:39 -0500 Received: from 5.mo3.mail-out.ovh.net ([87.98.178.36]:42064) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eHuwR-00084e-19 for qemu-devel@nongnu.org; Thu, 23 Nov 2017 12:05:35 -0500 Received: from player797.ha.ovh.net (gw6.ovh.net [213.251.189.206]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 8EDBB175AB9 for ; Thu, 23 Nov 2017 18:05:33 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr [90.76.52.173]) (Authenticated sender: clg@kaod.org) by player797.ha.ovh.net (Postfix) with ESMTPSA id 79C122E007A; Thu, 23 Nov 2017 18:05:28 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Date: Thu, 23 Nov 2017 18:05:24 +0100 Message-Id: <20171123170524.3865-1-clg@kaod.org> X-Mailer: git-send-email 2.13.6 MIME-Version: 1.0 X-Ovh-Tracer-Id: 18436610977312836435 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedttddrledtgdejjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.178.36 Subject: [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" and use the value to define precisely the default value of the LPCR in the helper routine cpu_ppc_set_papr() Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu-qom.h | 1 + target/ppc/translate_init.c | 23 +++++++++++------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 429b47f959dc..deaa46a14b2e 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -191,6 +191,7 @@ typedef struct PowerPCCPUClass { uint64_t insns_flags; uint64_t insns_flags2; uint64_t msr_mask; + uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bit= s */ powerpc_mmu_t mmu_model; powerpc_excp_t excp_model; powerpc_input_t bus_model; diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index b9c49c22f29f..828d7e778c3b 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8535,6 +8535,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; + pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; } =20 static void init_proc_POWER8(CPUPPCState *env) @@ -8704,6 +8705,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; + pcc->lpcr_pm =3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; } =20 #ifdef CONFIG_SOFTMMU @@ -8898,11 +8901,13 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; } =20 #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; ppc_spr_t *lpcr =3D &env->spr_cb[SPR_LPCR]; ppc_spr_t *amor =3D &env->spr_cb[SPR_AMOR]; @@ -8932,8 +8937,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHype= rvisor *vhyp) lpcr->default_value &=3D ~LPCR_RMLS; lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; =20 - switch (env->mmu_model) { - case POWERPC_MMU_3_00: + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { /* By default we choose legacy mode and switch to new hash or radix * when a register process table hcall is made. So disable process * tables and guest translation shootdown by default @@ -8947,18 +8951,13 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHy= pervisor *vhyp) } else { lpcr->default_value &=3D ~(LPCR_UPRT | LPCR_GTSE); } - lpcr->default_value |=3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_D= EE | - LPCR_OEE; - break; - default: - /* P7 and P8 has slightly different PECE bits, mostly because P8 a= dds - * bit 47 and 48 which are reserved on P7. Here we set them all, w= hich - * will work as expected for both implementations - */ - lpcr->default_value |=3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_P= ECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; } =20 + /* Also set the power-saving mode bits which depend on the CPU + * family + */ + lpcr->default_value |=3D pcc->lpcr_pm; + /* We should be followed by a CPU reset but update the active value * just in case... */ --=20 2.13.6