From nobody Mon Apr 29 00:12:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15111878544961006.8098815607376; Mon, 20 Nov 2017 06:24:14 -0800 (PST) Received: from localhost ([::1]:57601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGmzN-0000LU-3o for importer@patchew.org; Mon, 20 Nov 2017 09:23:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGmxz-0008Cp-T9 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 09:22:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGmxw-00010I-Oy for qemu-devel@nongnu.org; Mon, 20 Nov 2017 09:22:31 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49584) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGmxw-000102-IT for qemu-devel@nongnu.org; Mon, 20 Nov 2017 09:22:28 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 96A6E7E390; Mon, 20 Nov 2017 14:22:27 +0000 (UTC) Received: from dhcp-1-107.brq.redhat.com (ovpn-204-197.brq.redhat.com [10.40.204.197]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0D9D34DC57; Mon, 20 Nov 2017 14:22:18 +0000 (UTC) From: Ladi Prosek To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 15:22:16 +0100 Message-Id: <20171120142216.17832-1-lprosek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 20 Nov 2017 14:22:27 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] msix: don't mask already masked vectors on reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, geoff@hostfission.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" msix_mask_all() is supposed to invoke the release vector notifier if the st= ate of the respective vector changed from unmasked or masked. The way it's currently c= alled from msix_reset(), though, may result in calling the release notifier even if th= e vector is already masked. 1) msix_reset() clears out the msix_cap field and the msix_table. 2) msix_mask_all() runs with was_masked=3Dfalse for all vectors because of = 1), which results in calling the release notifier on all vectors. 3) if msix_reset() is subsequently called again, it goes through the same s= teps and calls the release notifier on all vectors again. This commit moves msix_mask_all() up so it runs before the device state is = lost. And it adds a call to msix_update_function_masked() so that the device remember= s that MSI-X is masked. This is likely a low impact issue, found while debugging an already broken = device. It is however easy to fix and the expectation that the use and release notifie= r invocations are always balanced is very natural. Signed-off-by: Ladi Prosek --- hw/pci/msix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index c944c02135..34656de9b0 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -500,11 +500,12 @@ void msix_reset(PCIDevice *dev) return; } msix_clear_all_vectors(dev); + msix_mask_all(dev, dev->msix_entries_nr); dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=3D ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE); memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8); - msix_mask_all(dev, dev->msix_entries_nr); + msix_update_function_masked(dev); } =20 /* PCI spec suggests that devices make it possible for software to configu= re --=20 2.13.5