From nobody Mon Apr 29 01:32:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510879380247407.76333563888466; Thu, 16 Nov 2017 16:43:00 -0800 (PST) Received: from localhost ([::1]:43405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eFUju-0003jC-Kv for importer@patchew.org; Thu, 16 Nov 2017 19:42:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eFUj3-00032k-1r for qemu-devel@nongnu.org; Thu, 16 Nov 2017 19:41:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eFUj1-0001HE-UW for qemu-devel@nongnu.org; Thu, 16 Nov 2017 19:41:45 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36184) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eFUix-00019o-56; Thu, 16 Nov 2017 19:41:39 -0500 Received: by mail-pg0-x242.google.com with SMTP id t10so644442pgo.3; Thu, 16 Nov 2017 16:41:39 -0800 (PST) Received: from surajjs1.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id q10sm3740335pgc.84.2017.11.16.16.41.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Nov 2017 16:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=6mF4Iz/zEzwKE9+JaP94l1LOHha3eg0WyzgfSq+Lf3E=; b=kNREGLLMGOEtO4xNncXPaMfigUy9MH8SKBjhRtHag7tpHPDTYxH+sV3rUGztEfmUhs Rf+0a1u0NlCCdXuIe9HgIQfmQpbd2AHCHmJLmOV70tEFyMR4eD3qU0IWqN1w4bg0Ld9R Jq+jMPP3uhKWw5aTb+Pj149rFe38dkVU5ErpuE9iKCa/J1W0YB2mfn8W1sMo0txHU1ZJ /DhxxV93OANRPL/0a5STa+d2WldR1GahguvS3XpRo8IG6jkFY3f5jO+w0xlGasyiWToA EppuYB1rrOiXNk5Tnro2SeBTvmY2jCJ9MRqKrxJrhtN5xZHH45KJ0A+zGiml++893Ni/ e3EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6mF4Iz/zEzwKE9+JaP94l1LOHha3eg0WyzgfSq+Lf3E=; b=LG8BSBlsEi7VtT0G/In0o4bZwrB1kNfhor+q7ajUCtA0CSmUbYfbENjtiCvnvdAsNx u7wqTJJ0MY66cIvFtXwKaepL2o6Lpj5HbrRThL5IudOIMCYhUcv6opt0y9ggAMoKGxgY pjnhedn+YYyVSCJ8J5V49s/QIyPpMF4HGMQwcHiPFGZwCeqzWUO4zRcT+cFJbfbRg510 adiGvJLkeniTF0V/6AHVYJdKjL+/hNJrZAOMzHufSlsfIwfyJoINlHhB77VTaZN9J/OK rrFumqgXGoWByHj0dOVYgkD7cjn2EyMNv1Z05ba891VJwGMmnClROQCpEhopNaPMsiT6 hQOg== X-Gm-Message-State: AJaThX5WTIGNMbGpUR+is90svjJ2DhXQTBd98Wars8ewKxoLVW8NubIx J7oC5Jjpln+h4uxCDmGOoxzVBLbG X-Google-Smtp-Source: AGs4zMaKPLOoyer9h/E6ygyOjmPsDRxi6s15Gp53YFVkMJd0QImFh0mYSuEmxlWi5Nsvq7Wdj3n2bw== X-Received: by 10.84.235.136 with SMTP id p8mr3379697plk.263.1510879297786; Thu, 16 Nov 2017 16:41:37 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 17 Nov 2017 11:40:58 +1100 Message-Id: <20171117004058.32158-1-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.9.5 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2] target/ppc: Update setting of cpu features to account for compat modes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: groug@kaod.org, qemu-devel@nongnu.org, sjitindarsingh@gmail.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The device tree nodes ibm,arch-vec-5-platform-support and ibm,pa-features are used to communicate features of the cpu to the guest operating system. The properties of each of these are determined based on the selected cpu model and the availability of hypervisor features. Currently the compatibility mode of the cpu is not taken into account. The ibm,arch-vec-5-platform-support node is used to communicate the level of support for various ISAv3 processor features to the guest before CAS to inform the guests' request. The available mmu mode should only be hash unless the cpu is a POWER9 which is not in a prePOWER9 compat mode, in which case the available modes depend on the accelerator and the hypervisor capabilities. The ibm,pa-featues node is used to communicate the level of cpu support for various features to the guest os. This should only contain features relevant to the operating mode of the processor, that is the selected cpu model taking into account any compat mode. This means that the compat mode should be taken into account when choosing the properties of ibm,pa-features and they should match the compat mode selected, or the cpu model selected if no compat mode. Update the setting of these cpu features in the device tree as described above to properly take into account any compat mode. Signed-off-by: Suraj Jitindar Singh --- V1 -> V2: - Pass cpu pointer to spapr_populate_pa_features to avoid extracting it back out from env - Slight reword of spapr_dt_ov5_platform_support logic to avoid duplicate case --- hw/ppc/spapr.c | 48 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d682f01..480484a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -44,6 +44,7 @@ #include "migration/register.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" +#include "cpu-models.h" #include "qom/cpu.h" =20 #include "hw/boards.h" @@ -252,9 +253,10 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offs= et, PowerPCCPU *cpu) } =20 /* Populate the "ibm,pa-features" property */ -static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int of= fset, - bool legacy_guest) +static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int off= set, + bool legacy_guest) { + CPUPPCState *env =3D &cpu->env; uint8_t pa_features_206[] =3D { 6, 0, 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; uint8_t pa_features_207[] =3D { 24, 0, @@ -290,16 +292,36 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset, uint8_t *pa_features; size_t pa_size; =20 - switch (POWERPC_MMU_VER(env->mmu_model)) { - case POWERPC_MMU_VER_2_06: + switch (cpu->compat_pvr) { + case 0: + /* If not in a compat mode then determine based on the mmu model */ + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_2_06: + pa_features =3D pa_features_206; + pa_size =3D sizeof(pa_features_206); + break; + case POWERPC_MMU_VER_2_07: + pa_features =3D pa_features_207; + pa_size =3D sizeof(pa_features_207); + break; + case POWERPC_MMU_VER_3_00: + pa_features =3D pa_features_300; + pa_size =3D sizeof(pa_features_300); + break; + default: + return; + } + break; + case CPU_POWERPC_LOGICAL_2_06: + case CPU_POWERPC_LOGICAL_2_06_PLUS: pa_features =3D pa_features_206; pa_size =3D sizeof(pa_features_206); break; - case POWERPC_MMU_VER_2_07: + case CPU_POWERPC_LOGICAL_2_07: pa_features =3D pa_features_207; pa_size =3D sizeof(pa_features_207); break; - case POWERPC_MMU_VER_3_00: + case CPU_POWERPC_LOGICAL_3_00: pa_features =3D pa_features_300; pa_size =3D sizeof(pa_features_300); break; @@ -340,7 +362,6 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) =20 CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; DeviceClass *dc =3D DEVICE_GET_CLASS(cs); int index =3D spapr_vcpu_id(cpu); int compat_smt =3D MIN(smp_threads, ppc_compat_max_threads(cpu)); @@ -384,7 +405,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) return ret; } =20 - spapr_populate_pa_features(env, fdt, offset, + spapr_populate_pa_features(cpu, fdt, offset, spapr->cas_legacy_guest_workaroun= d); } return ret; @@ -579,7 +600,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, page_sizes_prop, page_sizes_prop_size))); } =20 - spapr_populate_pa_features(env, fdt, offset, false); + spapr_populate_pa_features(cpu, fdt, offset, false); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); @@ -941,6 +962,7 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, voi= d *fdt) static void spapr_dt_ov5_platform_support(void *fdt, int chosen) { PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + CPUPPCState *env =3D &first_ppc_cpu->env; =20 char val[2 * 4] =3D { 23, 0x00, /* Xive mode, filled in below. */ @@ -949,7 +971,11 @@ static void spapr_dt_ov5_platform_support(void *fdt, i= nt chosen) 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ }; =20 - if (kvm_enabled()) { + if (first_ppc_cpu->compat_pvr && (first_ppc_cpu->compat_pvr < + CPU_POWERPC_LOGICAL_3_00)) { + /* If we're in a pre POWER9 compat mode then the guest should do h= ash */ + val[3] =3D 0x00; /* Hash */ + } else if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { val[3] =3D 0x80; /* OV5_MMU_BOTH */ } else if (kvmppc_has_cap_mmu_radix()) { @@ -958,7 +984,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, in= t chosen) val[3] =3D 0x00; /* Hash */ } } else { - if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { + if (env->mmu_model & POWERPC_MMU_V3) { /* V3 MMU supports both hash and radix (with dynamic switching= ) */ val[3] =3D 0xC0; } else { --=20 2.9.5