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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [QEMU-PPC] [PATCH] target/ppc: Update setting of cpu features to account for compat modes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sjitindarsingh@gmail.com, qemu-devel@nongnu.org, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The device tree nodes ibm,arch-vec-5-platform-support and ibm,pa-features are used to communicate features of the cpu to the guest operating system. The properties of each of these are determined based on the selected cpu model and the availability of hypervisor features. Currently the compatibility mode of the cpu is not taken into account. The ibm,arch-vec-5-platform-support node is used to communicate the level of support for various ISAv3 processor features to the guest before CAS to inform the guests' request. The available mmu mode should only be hash unless the cpu is a POWER9 which is not in a prePOWER9 compat mode, in which case the available modes depend on the accelerator and the hypervisor capabilities. The ibm,pa-featues node is used to communicate the level of cpu support for various features to the guest os. This should only contain features relevant to the operating mode of the processor, that is the selected cpu model taking into account any compat mode. This means that the compat mode should be taken into account when choosing the properties of ibm,pa-features and they should match the compat mode selected, or the cpu model selected if no compat mode. Update the setting of these cpu features in the device tree as described above to properly take into account any compat mode. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d682f01..0dab6f1 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -44,6 +44,7 @@ #include "migration/register.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" +#include "cpu-models.h" #include "qom/cpu.h" =20 #include "hw/boards.h" @@ -255,6 +256,7 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offse= t, PowerPCCPU *cpu) static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int of= fset, bool legacy_guest) { + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint8_t pa_features_206[] =3D { 6, 0, 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; uint8_t pa_features_207[] =3D { 24, 0, @@ -290,16 +292,36 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset, uint8_t *pa_features; size_t pa_size; =20 - switch (POWERPC_MMU_VER(env->mmu_model)) { - case POWERPC_MMU_VER_2_06: + switch (cpu->compat_pvr) { + case 0: + /* If not in a compat mode then determine based on the mmu model */ + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_2_06: + pa_features =3D pa_features_206; + pa_size =3D sizeof(pa_features_206); + break; + case POWERPC_MMU_VER_2_07: + pa_features =3D pa_features_207; + pa_size =3D sizeof(pa_features_207); + break; + case POWERPC_MMU_VER_3_00: + pa_features =3D pa_features_300; + pa_size =3D sizeof(pa_features_300); + break; + default: + return; + } + break; + case CPU_POWERPC_LOGICAL_2_06: + case CPU_POWERPC_LOGICAL_2_06_PLUS: pa_features =3D pa_features_206; pa_size =3D sizeof(pa_features_206); break; - case POWERPC_MMU_VER_2_07: + case CPU_POWERPC_LOGICAL_2_07: pa_features =3D pa_features_207; pa_size =3D sizeof(pa_features_207); break; - case POWERPC_MMU_VER_3_00: + case CPU_POWERPC_LOGICAL_3_00: pa_features =3D pa_features_300; pa_size =3D sizeof(pa_features_300); break; @@ -941,6 +963,7 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, voi= d *fdt) static void spapr_dt_ov5_platform_support(void *fdt, int chosen) { PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + CPUPPCState *env =3D &first_ppc_cpu->env; =20 char val[2 * 4] =3D { 23, 0x00, /* Xive mode, filled in below. */ @@ -949,7 +972,12 @@ static void spapr_dt_ov5_platform_support(void *fdt, i= nt chosen) 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ }; =20 - if (kvm_enabled()) { + if (POWERPC_MMU_VER(env->mmu_model) !=3D POWERPC_MMU_VER_3_00 || + (first_ppc_cpu->compat_pvr && (first_ppc_cpu->compat_pvr < + CPU_POWERPC_LOGICAL_3_00))) { + /* If we're in a pre POWER9 compat mode then the guest should do h= ash */ + val[3] =3D 0x00; /* Hash */ + } else if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { val[3] =3D 0x80; /* OV5_MMU_BOTH */ } else if (kvmppc_has_cap_mmu_radix()) { --=20 2.9.5