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[37.10.242.18]) by smtp.gmail.com with ESMTPSA id 29sm21828608wrz.77.2017.11.15.04.37.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Nov 2017 04:37:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cAyrpm5zwNK2k5k9wqEc1GoIsoaXxBPiNuQAd01KzFQ=; b=If4prqmRa+ezLs+Ppw21edregSGZj/tWNM7GViw3rEtWDTDq5Q+JMyHrAGPUuQUUT+ 9cwtvcxWrcc3FmOzbU7+eZikMYb0GqGiqPXWXCFA9RcVcvGDzoVwdGv0vmjxQYoUGsOp 6MQCM71DVfoH9FVrNK+720ojhd8CWJnE3XCtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cAyrpm5zwNK2k5k9wqEc1GoIsoaXxBPiNuQAd01KzFQ=; b=cM8sMHlIZ12HDP8bC4uBPXucKvNL9jtGScZQHNhGJwTABnzuNaWwcpB6RLBMy0V5CS rWgZmf5i0zoUHtwit5dja0zeguKVlP/tKXWX+8JYR66y8YpIQKgUNveoB5nPpQikpCke Gl0pctIrhHnIPs3DXJH7ZksgKDVmPjIxhMCR/AMgFh+jrtTg0kLzadhTLHEyYAIewd4d z/r7rb+JPuhxC37cgNy0ZJMfl/mx/9gf5q0O9WwQIgA0O+Xdpj+sy08zVkC9mvZixvA9 9UxPHz2QAAXiresZp2THMtmAfxW8CV9GLbwtAYdSAbc7UopwmXXofn7YwMNeKCqgoJuW nmdQ== X-Gm-Message-State: AJaThX7UBHTzHTT8753X7zqgek2t9zcSyykGyHicQNe3K8vbpuok2bEM AP4YETMJN0S6q2wRK6jaYB3pUXettiM= X-Google-Smtp-Source: AGs4zMaME6AIAeiR/IkOlYPAk9FQ/ZevzuSFkp+A5RdcsEPZm4XYlFnOYO3Pc5+zodnm2yuhixhwJA== X-Received: by 10.223.201.5 with SMTP id m5mr14266710wrh.68.1510749445212; Wed, 15 Nov 2017 04:37:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 15 Nov 2017 13:35:18 +0100 Message-Id: <20171115123520.7464-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171115123520.7464-1-richard.henderson@linaro.org> References: <20171115123520.7464-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PULL for-2.11 1/3] tcg: Record code_gen_buffer address for user-only memory helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 When we handle a signal from a fault within a user-only memory helper, we cannot cpu_restore_state with the PC found within the signal frame. Use a TLS variable, helper_retaddr, to record the unwind start point to find the faulting guest insn. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 32 +++++++++++++---- include/exec/cpu_ldst.h | 2 ++ include/exec/cpu_ldst_useronly_template.h | 14 ++++++-- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++--= ---- 5 files changed, 87 insertions(+), 20 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index b400b2a3d3..1c7c17526c 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -62,7 +62,9 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) { DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; - return atomic_cmpxchg__nocheck(haddr, cmpv, newv); + DATA_TYPE ret =3D atomic_cmpxchg__nocheck(haddr, cmpv, newv); + ATOMIC_MMU_CLEANUP; + return ret; } =20 #if DATA_SIZE >=3D 16 @@ -70,6 +72,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong = addr EXTRA_ARGS) { DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; __atomic_load(haddr, &val, __ATOMIC_RELAXED); + ATOMIC_MMU_CLEANUP; return val; } =20 @@ -78,13 +81,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, { DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; __atomic_store(haddr, &val, __ATOMIC_RELAXED); + ATOMIC_MMU_CLEANUP; } #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; - return atomic_xchg__nocheck(haddr, val); + DATA_TYPE ret =3D atomic_xchg__nocheck(haddr, val); + ATOMIC_MMU_CLEANUP; + return ret; } =20 #define GEN_ATOMIC_HELPER(X) \ @@ -92,8 +98,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong = addr, \ ABI_TYPE val EXTRA_ARGS) \ { \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ - return atomic_##X(haddr, val); \ -} \ + DATA_TYPE ret =3D atomic_##X(haddr, val); \ + ATOMIC_MMU_CLEANUP; \ + return ret; \ +} =20 GEN_ATOMIC_HELPER(fetch_add) GEN_ATOMIC_HELPER(fetch_and) @@ -123,7 +131,9 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) { DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; - return BSWAP(atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv))); + DATA_TYPE ret =3D atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(ne= wv)); + ATOMIC_MMU_CLEANUP; + return BSWAP(ret); } =20 #if DATA_SIZE >=3D 16 @@ -131,6 +141,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr EXTRA_ARGS) { DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; __atomic_load(haddr, &val, __ATOMIC_RELAXED); + ATOMIC_MMU_CLEANUP; return BSWAP(val); } =20 @@ -140,13 +151,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong = addr, DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; val =3D BSWAP(val); __atomic_store(haddr, &val, __ATOMIC_RELAXED); + ATOMIC_MMU_CLEANUP; } #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; - return BSWAP(atomic_xchg__nocheck(haddr, BSWAP(val))); + ABI_TYPE ret =3D atomic_xchg__nocheck(haddr, BSWAP(val)); + ATOMIC_MMU_CLEANUP; + return BSWAP(ret); } =20 #define GEN_ATOMIC_HELPER(X) \ @@ -154,7 +168,9 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ ABI_TYPE val EXTRA_ARGS) \ { \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ - return BSWAP(atomic_##X(haddr, BSWAP(val))); \ + DATA_TYPE ret =3D atomic_##X(haddr, BSWAP(val)); \ + ATOMIC_MMU_CLEANUP; \ + return BSWAP(ret); \ } =20 GEN_ATOMIC_HELPER(fetch_and) @@ -180,6 +196,7 @@ ABI_TYPE ATOMIC_NAME(fetch_add)(CPUArchState *env, targ= et_ulong addr, sto =3D BSWAP(ret + val); ldn =3D atomic_cmpxchg__nocheck(haddr, ldo, sto); if (ldn =3D=3D ldo) { + ATOMIC_MMU_CLEANUP; return ret; } ldo =3D ldn; @@ -198,6 +215,7 @@ ABI_TYPE ATOMIC_NAME(add_fetch)(CPUArchState *env, targ= et_ulong addr, sto =3D BSWAP(ret); ldn =3D atomic_cmpxchg__nocheck(haddr, ldo, sto); if (ldn =3D=3D ldo) { + ATOMIC_MMU_CLEANUP; return ret; } ldo =3D ldn; diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6eb5fe80dc..191f2e962a 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -76,6 +76,8 @@ =20 #if defined(CONFIG_USER_ONLY) =20 +extern __thread uintptr_t helper_retaddr; + /* In user-only mode we provide only the _code and _data accessors. */ =20 #define MEMSUFFIX _data diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_l= dst_useronly_template.h index 7b8c7c506e..c168f31bba 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -73,7 +73,11 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, target_ulong ptr, uintptr_t retaddr) { - return glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr); + RES_TYPE ret; + helper_retaddr =3D retaddr; + ret =3D glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr); + helper_retaddr =3D 0; + return ret; } =20 #if DATA_SIZE <=3D 2 @@ -93,7 +97,11 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, target_ulong ptr, uintptr_t retaddr) { - return glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr); + int ret; + helper_retaddr =3D retaddr; + ret =3D glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr); + helper_retaddr =3D 0; + return ret; } #endif =20 @@ -116,7 +124,9 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, RES_TYPE v, uintptr_t retaddr) { + helper_retaddr =3D retaddr; glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(env, ptr, v); + helper_retaddr =3D 0; } #endif =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a23919c3a8..d071ca4d14 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1041,6 +1041,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, #define ATOMIC_NAME(X) \ HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr) +#define ATOMIC_MMU_CLEANUP do { } while (0) =20 #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 492ea0826c..0324ba8ad1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -39,6 +39,8 @@ #include #endif =20 +__thread uintptr_t helper_retaddr; + //#define DEBUG_SIGNAL =20 /* exit the current TB from a signal handler. The host registers are @@ -62,6 +64,27 @@ static inline int handle_cpu_signal(uintptr_t pc, unsign= ed long address, CPUClass *cc; int ret; =20 + /* We must handle PC addresses from two different sources: + * a call return address and a signal frame address. + * + * Within cpu_restore_state_from_tb we assume the former and adjust + * the address by -GETPC_ADJ so that the address is within the call + * insn so that addr does not accidentally match the beginning of the + * next guest insn. + * + * However, when the PC comes from the signal frame, it points to + * the actual faulting host insn and not a call insn. Subtracting + * GETPC_ADJ in that case may accidentally match the previous guest in= sn. + * + * So for the later case, adjust forward to compensate for what + * will be done later by cpu_restore_state_from_tb. + */ + if (helper_retaddr) { + pc =3D helper_retaddr; + } else { + pc +=3D GETPC_ADJ; + } + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. @@ -84,21 +107,24 @@ static inline int handle_cpu_signal(uintptr_t pc, unsi= gned long address, switch (page_unprotect(h2g(address), pc)) { case 0: /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem + * cached translations, must be the guest binary's problem. */ break; case 1: /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. */ return 1; case 2: /* Fault caused by protection of cached translation, and the * currently executing TB was modified and must be exited - * immediately. + * immediately. Clear helper_retaddr for next execution. */ + helper_retaddr =3D 0; cpu_exit_tb_from_sighandler(cpu, old_set); - g_assert_not_reached(); + /* NORETURN */ + default: g_assert_not_reached(); } @@ -112,17 +138,25 @@ static inline int handle_cpu_signal(uintptr_t pc, uns= igned long address, /* see if it is an MMU fault */ g_assert(cc->handle_mmu_fault); ret =3D cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX); + + if (ret =3D=3D 0) { + /* The MMU fault was handled without causing real CPU fault. + * Retain helper_retaddr for a possible second fault. + */ + return 1; + } + + /* All other paths lead to cpu_exit; clear helper_retaddr + * for next execution. + */ + helper_retaddr =3D 0; + if (ret < 0) { return 0; /* not an MMU fault */ } - if (ret =3D=3D 0) { - return 1; /* the MMU fault was handled without causing real CPU fa= ult */ - } =20 - /* Now we have a real cpu fault. Since this is the exact location of - * the exception, we must undo the adjustment done by cpu_restore_state - * for handling call return addresses. */ - cpu_restore_state(cpu, pc + GETPC_ADJ); + /* Now we have a real cpu fault. */ + cpu_restore_state(cpu, pc); =20 sigprocmask(SIG_SETMASK, old_set, NULL); cpu_loop_exit(cpu); @@ -585,11 +619,13 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); } + helper_retaddr =3D retaddr; return g2h(addr); } =20 /* Macro to call the above, with local variables from the use context. */ #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) +#define ATOMIC_MMU_CLEANUP do { helper_retaddr =3D 0; } while (0) =20 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define EXTRA_ARGS --=20 2.13.6 From nobody Mon Apr 29 15:50:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510749619299279.8264938205516; Wed, 15 Nov 2017 04:40:19 -0800 (PST) Received: from localhost ([::1]:35836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEwz4-0008HN-Bd for importer@patchew.org; Wed, 15 Nov 2017 07:40:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEwwa-0006r5-Tp for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEwwa-0006OM-5Z for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:28 -0500 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:51741) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eEwwZ-0006Nq-Ui for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:28 -0500 Received: by mail-wr0-x244.google.com with SMTP id z14so1554079wrb.8 for ; Wed, 15 Nov 2017 04:37:27 -0800 (PST) Received: from cloudburst.twiddle.net (18.red-37-10-242.dynamicip.rima-tde.net. [37.10.242.18]) by smtp.gmail.com with ESMTPSA id 29sm21828608wrz.77.2017.11.15.04.37.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Nov 2017 04:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aHBaUea/tBedI9wsvw9tO3w8Ii64fxfFEO7kzaNZoMk=; b=N5TZGsNIOoEffPijtjDZ4mRx3t1IJ3DzyRotuYhoViSd9NaW4jowbtyCA9/bbwahYe hSw6TP1MkBt58ABJbThwUlnQ9wSctCgVkr0nXnNh+3aaVaL2BlEpUhlbfmlUTo+Tzkfv pIwTkKFKY7ze8zfVHaWO/hupgjdjMmguJYmAw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aHBaUea/tBedI9wsvw9tO3w8Ii64fxfFEO7kzaNZoMk=; b=jUWSozgYJ68aGUEyvnPvce0FEpkjlCj4K4jyKv7T2CCtQsJf9ChgMjaoyuyQYHSKbq Ev7SLT996EHk1vWdP0eQ8Exqc6eq8e45vROHvpWvXOcMUZ8LPBeoyLfat7yjxQVIDC93 OXKWctfaonXiZGnEhAu/ssYFf2Sjjq79lDB59w+FoAQ1jIgilhUCjg/X/2tcGXahhb75 v6w/Q7GxL/x8kOZdXUC8/KCVBpeNvxrCLgtlho8TATvK3ug3IXpSNcJr6hIjgnSPdgyN uiMrJMyXfAoS9dEsC3KDdcpktanT3+xB5ohyb4MY2y7ivOHsbHbWuOwyqTczeHNyomHt P4Aw== X-Gm-Message-State: AJaThX7zeB4cqosBPk2aElPdWBLcXH5CRivqFxMTn3g31qzSdI9aBQ6f 6M5hFjGxbLFfh7yxGgNBFTSXOJibLOc= X-Google-Smtp-Source: AGs4zMYbmuvAwBa7pQKZK4jutWAQrhK9E/jbXqlwjBIzcYrdvIVMaRR/NOUZ3DEwsHCTrGbQ8DYg3g== X-Received: by 10.223.153.100 with SMTP id x91mr12602715wrb.189.1510749446588; Wed, 15 Nov 2017 04:37:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 15 Nov 2017 13:35:19 +0100 Message-Id: <20171115123520.7464-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171115123520.7464-1-richard.henderson@linaro.org> References: <20171115123520.7464-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PULL for-2.11 2/3] target/arm: Use helper_retaddr in stxp helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We use raw memory primitives along the !parallel_cpus paths in order to simplify the endianness handling. Because of that, we did not benefit from the generic changes to cpu_ldst_user_only_template.h. The simplest fix is to manipulate helper_retaddr here. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d0e435ca4b..96a3ecf707 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -456,6 +456,8 @@ static uint64_t do_paired_cmpxchg64_le(CPUARMState *env= , uint64_t addr, #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ uint64_t *haddr =3D g2h(addr); + + helper_retaddr =3D ra; o0 =3D ldq_le_p(haddr + 0); o1 =3D ldq_le_p(haddr + 1); oldv =3D int128_make128(o0, o1); @@ -465,6 +467,7 @@ static uint64_t do_paired_cmpxchg64_le(CPUARMState *env= , uint64_t addr, stq_le_p(haddr + 0, int128_getlo(newv)); stq_le_p(haddr + 1, int128_gethi(newv)); } + helper_retaddr =3D 0; #else int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -523,6 +526,8 @@ static uint64_t do_paired_cmpxchg64_be(CPUARMState *env= , uint64_t addr, #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ uint64_t *haddr =3D g2h(addr); + + helper_retaddr =3D ra; o1 =3D ldq_be_p(haddr + 0); o0 =3D ldq_be_p(haddr + 1); oldv =3D int128_make128(o0, o1); @@ -532,6 +537,7 @@ static uint64_t do_paired_cmpxchg64_be(CPUARMState *env= , uint64_t addr, stq_be_p(haddr + 0, int128_gethi(newv)); stq_be_p(haddr + 1, int128_getlo(newv)); } + helper_retaddr =3D 0; #else int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); --=20 2.13.6 From nobody Mon Apr 29 15:50:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510749530739847.3339647350742; Wed, 15 Nov 2017 04:38:50 -0800 (PST) Received: from localhost ([::1]:35833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEwxo-0007SD-U0 for importer@patchew.org; Wed, 15 Nov 2017 07:38:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEwwc-0006rE-OS for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEwwb-0006PW-QA for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:30 -0500 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:49235) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eEwwb-0006Ou-KN for qemu-devel@nongnu.org; Wed, 15 Nov 2017 07:37:29 -0500 Received: by mail-wr0-x242.google.com with SMTP id o88so20312517wrb.6 for ; Wed, 15 Nov 2017 04:37:29 -0800 (PST) Received: from cloudburst.twiddle.net (18.red-37-10-242.dynamicip.rima-tde.net. [37.10.242.18]) by smtp.gmail.com with ESMTPSA id 29sm21828608wrz.77.2017.11.15.04.37.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Nov 2017 04:37:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q4cHOET0RjremJACS4BvBGqPid2KGrIo6RRafDt62mw=; b=VYWKkn4v1yXsA+G+eXikdWPoZP2HHOH0zWlfVo9aiv6/Qy79YJTTqGk2XsYfV8FPUC WbQh6/oZj/2yCXo/lkKVB5foxEa/SONEtwinUGU9Lm5PZCrQ5EqLrSDRRCa87jkdGu4m 79i9bK9FkscW7SDVIsqjQHD/pXUe99YQ1DyzY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q4cHOET0RjremJACS4BvBGqPid2KGrIo6RRafDt62mw=; b=VWDxap7weHvsG/FH2PDy2b7pP83wr9Rvs4vT9pf236vF8+xhZfX14+El4X92g9A9L5 XoCXKoFC6la4WnhiS+66wdRetpILOOpgJj/LJxKSXn+pNGb1olN2Q8uLbowvsdLeSMdp oKjalkg/ij3J1tX0BPd88JD2gYBAy/exTErMbH3+z8BniptKDr2mdmGZDubNpmOmJbLH ifTnoqRXete7ZuW+xMjlG0P4ndPVShDQV0TZ1Nr6xaaFT5Wby9BCYvS6q3J3+Pnix1t6 Kbss6bW9VhIn8ngPXuSXoNz43jBd4ZTSUW6ZXGk0bKlXW47blVnlAosQMkiU+Osw0078 9wXg== X-Gm-Message-State: AJaThX4TWBZEkNefeTxFDZlHCQi3vvTv8T8/xttoB+4s3oCVu4kXgiVd oAC5u17efFUY9i4nJ4AiPQP8czv44FU= X-Google-Smtp-Source: AGs4zMYrCZWGh8ZSZMM6VGk5KY0VCGl2obLVdhijoJf1U2uSTe0rTaARnkqIDhEBsU5IumXum0o55A== X-Received: by 10.223.164.206 with SMTP id h14mr9495106wrb.221.1510749448338; Wed, 15 Nov 2017 04:37:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 15 Nov 2017 13:35:20 +0100 Message-Id: <20171115123520.7464-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171115123520.7464-1-richard.henderson@linaro.org> References: <20171115123520.7464-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PULL for-2.11 3/3] target/arm: Fix GETPC usage in do_paired_cmpxchg64_l/be X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Use of GETPC must be restricted to those functions that are directly called from TCG generated code. Reviewed-by: Alex Benn=C3=A9e Fixes: 2399d4e7cec22ecf1c51062d2ebfd45220dbaace Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 96a3ecf707..b84ebcae6e 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -432,9 +432,8 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, = uint32_t bytes) /* Returns 0 on success; 1 otherwise. */ static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi, - bool parallel) + bool parallel, uintptr_t ra) { - uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; bool success; =20 @@ -491,20 +490,19 @@ static uint64_t do_paired_cmpxchg64_le(CPUARMState *e= nv, uint64_t addr, uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t ne= w_hi) { - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false); + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC(= )); } =20 uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, uint64_t new_lo, uint64_t ne= w_hi) { - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true); + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC()= ); } =20 static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi, - bool parallel) + bool parallel, uintptr_t ra) { - uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; bool success; =20 @@ -561,11 +559,11 @@ static uint64_t do_paired_cmpxchg64_be(CPUARMState *e= nv, uint64_t addr, uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false); + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC(= )); } =20 uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, uint64_t new_lo, uint64_t new_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true); + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()= ); } --=20 2.13.6