[Qemu-devel] [PATCH v5 0/8] aspeed: add a witherspoon-bmc machine

Cédric Le Goater posted 8 patches 6 years, 6 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20171019151249.13663-1-clg@kaod.org
Test docker passed
Test s390x passed
There is a newer version of this series
default-configs/arm-softmmu.mak |   1 +
hw/arm/aspeed.c                 | 110 ++++++++++++++++-
hw/i2c/smbus_eeprom.c           |  16 ++-
hw/misc/Makefile.objs           |   1 +
hw/misc/pca9552.c               | 259 ++++++++++++++++++++++++++++++++++++++++
include/hw/i2c/smbus.h          |   1 +
include/hw/misc/pca9552.h       |  33 +++++
tests/Makefile.include          |   2 +
tests/pca9552-test.c            | 131 ++++++++++++++++++++
9 files changed, 544 insertions(+), 10 deletions(-)
create mode 100644 hw/misc/pca9552.c
create mode 100644 include/hw/misc/pca9552.h
create mode 100644 tests/pca9552-test.c
[Qemu-devel] [PATCH v5 0/8] aspeed: add a witherspoon-bmc machine
Posted by Cédric Le Goater 6 years, 6 months ago
Hello,

This series adds a new Aspeed machine to emulate the BMC of a
Witherspoon system. It also extends the other Aspeed machines with I2C
devices and adds a simple model for the pca9552 LED blinker present on
the witherspoon board.

Thanks,

C.

Changes since v4:

 - use a ROM memory region

Changes since v3:

 - introduce a dummy ROM device to catch invalid writes
 - removed 'ignore_memory_transaction_failures' on all Aspeed machines
 - reworked PCA9552 device :
   . simpler I2C handles
   . auto-increment support
   . unit test

Changes since v2:

 - removed comments on the I2C buffer size pf the PCA9552 device.
 - removed 'ignore_memory_transaction_failures' flag on the
   witherspoon machine.
   
Changes since v1:

 - introduced smbus_eeprom_init_one()

Cédric Le Goater (8):
  aspeed: use a ROM memory region to catch invalid writes
  aspeed: remove ignore_memory_transaction_failures all boards
  aspeed: add support for the witherspoon-bmc board
  aspeed: add an I2C RTC device to all machines
  smbus: add a smbus_eeprom_init_one() routine
  aspeed: Add EEPROM I2C devices
  misc: add pca9552 LED blinker model
  aspeed: add the pc9552 chips to the witherspoon machine

 default-configs/arm-softmmu.mak |   1 +
 hw/arm/aspeed.c                 | 110 ++++++++++++++++-
 hw/i2c/smbus_eeprom.c           |  16 ++-
 hw/misc/Makefile.objs           |   1 +
 hw/misc/pca9552.c               | 259 ++++++++++++++++++++++++++++++++++++++++
 include/hw/i2c/smbus.h          |   1 +
 include/hw/misc/pca9552.h       |  33 +++++
 tests/Makefile.include          |   2 +
 tests/pca9552-test.c            | 131 ++++++++++++++++++++
 9 files changed, 544 insertions(+), 10 deletions(-)
 create mode 100644 hw/misc/pca9552.c
 create mode 100644 include/hw/misc/pca9552.h
 create mode 100644 tests/pca9552-test.c

-- 
2.13.6


Re: [Qemu-devel] [PATCH v5 0/8] aspeed: add a witherspoon-bmc machine
Posted by Cédric Le Goater 6 years, 4 months ago
On 10/19/2017 05:12 PM, Cédric Le Goater wrote:
> Hello,
> 
> This series adds a new Aspeed machine to emulate the BMC of a
> Witherspoon system. It also extends the other Aspeed machines with I2C
> devices and adds a simple model for the pca9552 LED blinker present on
> the witherspoon board.
> 
> Thanks,
> 
> C.
> 
> Changes since v4:
> 
>  - use a ROM memory region
> 
> Changes since v3:
> 
>  - introduce a dummy ROM device to catch invalid writes
>  - removed 'ignore_memory_transaction_failures' on all Aspeed machines

So that was a bad idea because old firwmares run load/store loops
beyond the address space to guess how much RAM the SoC has.  

I am wondering if it is possible to model the same behavior with
a MMIO region (of a correct size depending on the max ram size of 
the SoC) and mapped beyond the RAM region to catch such accesses 
and keep 'ignore_memory_transaction_failures' to false. 
  
Thanks,

C.


>  - reworked PCA9552 device :
>    . simpler I2C handles
>    . auto-increment support
>    . unit test
> 
> Changes since v2:
> 
>  - removed comments on the I2C buffer size pf the PCA9552 device.
>  - removed 'ignore_memory_transaction_failures' flag on the
>    witherspoon machine.
>    
> Changes since v1:
> 
>  - introduced smbus_eeprom_init_one()
> 
> Cédric Le Goater (8):
>   aspeed: use a ROM memory region to catch invalid writes
>   aspeed: remove ignore_memory_transaction_failures all boards
>   aspeed: add support for the witherspoon-bmc board
>   aspeed: add an I2C RTC device to all machines
>   smbus: add a smbus_eeprom_init_one() routine
>   aspeed: Add EEPROM I2C devices
>   misc: add pca9552 LED blinker model
>   aspeed: add the pc9552 chips to the witherspoon machine
> 
>  default-configs/arm-softmmu.mak |   1 +
>  hw/arm/aspeed.c                 | 110 ++++++++++++++++-
>  hw/i2c/smbus_eeprom.c           |  16 ++-
>  hw/misc/Makefile.objs           |   1 +
>  hw/misc/pca9552.c               | 259 ++++++++++++++++++++++++++++++++++++++++
>  include/hw/i2c/smbus.h          |   1 +
>  include/hw/misc/pca9552.h       |  33 +++++
>  tests/Makefile.include          |   2 +
>  tests/pca9552-test.c            | 131 ++++++++++++++++++++
>  9 files changed, 544 insertions(+), 10 deletions(-)
>  create mode 100644 hw/misc/pca9552.c
>  create mode 100644 include/hw/misc/pca9552.h
>  create mode 100644 tests/pca9552-test.c
> 


Re: [Qemu-devel] [PATCH v5 0/8] aspeed: add a witherspoon-bmc machine
Posted by Peter Maydell 6 years, 4 months ago
On 29 November 2017 at 09:58, Cédric Le Goater <clg@kaod.org> wrote:
> On 10/19/2017 05:12 PM, Cédric Le Goater wrote:
>>  - introduce a dummy ROM device to catch invalid writes
>>  - removed 'ignore_memory_transaction_failures' on all Aspeed machines
>
> So that was a bad idea because old firwmares run load/store loops
> beyond the address space to guess how much RAM the SoC has.
>
> I am wondering if it is possible to model the same behavior with
> a MMIO region (of a correct size depending on the max ram size of
> the SoC) and mapped beyond the RAM region to catch such accesses
> and keep 'ignore_memory_transaction_failures' to false.

Yeah, if the hardware genuinely ignores accesses to a particular
region of the address space then you can model this with an
appropriate background memory region. You just need to figure
out what range of the address space it should apply to...

thanks
-- PMM