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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zgPU8osK8WOXr6Bfqyrt6MJzS9T+IaVLi64zYa/MXV8=; b=QiGukZDTZTC6YdC7c2eb1M5mn+4KsWEV35fh8dUZ+XQAV84jktNa6O105OXOVqJdlf Ds3eoj7vKl+4ms/wdPKfkGW7KMuNNDkRDb9i9r+u0MxNArA8OnZbRYi+NoUjoaVyQMFY i2nIQzBImNNm/LbwsHQ8vxD0h6pHAYdgYeBzI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zgPU8osK8WOXr6Bfqyrt6MJzS9T+IaVLi64zYa/MXV8=; b=jHiSIzV9JRkaoH1oaqjywTbNYCLIsoVtS82PRMkLAiwPpXUmPM77EivWpoRne9033G h3hm2tGZF1+IkueXceiWEFXTY4+zDbCMPULUXHVa5Gn2zqZWnyZlso0EHTf//V2ikX5O bAZoWOcmByv8z30xjxnhpPqwWU/EOr+gJeHcBpuOMSH0hE4mSJODOrRLGW9rK+Ka75yd Q3lKYrp/Z4LC9c/xW7LiDELW7NNjakC2WxaDFzrFnA+/FjEzHWhWeeq3TIrgqkrhQzwQ C9+boQM7RtZpgF5q3wqvj72FM+3ae0B4M/fEmS6Tmxf6Brwszq3YK6+ErE7+XfUHszg2 iC1w== X-Gm-Message-State: AMCzsaWDzS17hLK9GcrWAilc8puzdf8x4NaAZixZqXgwTE14+5UmnePD dctymtfcKMn+S8bFOx9qcaYILKjeLXY= X-Google-Smtp-Source: AOwi7QCiE4Yj/G+gcbEZfQWKIceom+znKv7goM8glFU5meSiEv5S8Dn0G9vjTC6vvqg9UbYECGD/yg== X-Received: by 10.99.127.67 with SMTP id p3mr8823114pgn.321.1508174774058; Mon, 16 Oct 2017 10:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:20 -0700 Message-Id: <20171016172609.23422-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v6 01/50] tcg: Merge opcode arguments into TCGOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Rather than have a separate buffer of 10*max_ops entries, give each opcode 10 entries. The result is actually a bit smaller and should have slightly more cache locality. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 37 ++++++++++------------ tcg/optimize.c | 6 ++-- tcg/tcg-op.c | 99 +++++++++++++++++++++---------------------------------= ---- tcg/tcg.c | 98 ++++++++++++++++++++++++++----------------------------= --- 4 files changed, 98 insertions(+), 142 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index b2d42e3136..2cefd9f125 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -51,8 +51,6 @@ #define OPC_BUF_SIZE 640 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) =20 -#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) - #define CPU_TEMP_BUF_NLONGS 128 =20 /* Default target word size to pointer size. */ @@ -606,33 +604,33 @@ typedef struct TCGTempSet { #define SYNC_ARG 1 typedef uint16_t TCGLifeData; =20 -/* The layout here is designed to avoid crossing of a 32-bit boundary. - If we do so, gcc adds padding, expanding the size to 12. */ +/* The layout here is designed to avoid a bitfield crossing of + a 32-bit boundary, which would cause GCC to add extra padding. */ typedef struct TCGOp { TCGOpcode opc : 8; /* 8 */ =20 - /* Index of the prev/next op, or 0 for the end of the list. */ - unsigned prev : 10; /* 18 */ - unsigned next : 10; /* 28 */ - /* The number of out and in parameter for a call. */ - unsigned calli : 4; /* 32 */ - unsigned callo : 2; /* 34 */ + unsigned calli : 4; /* 12 */ + unsigned callo : 2; /* 14 */ + unsigned : 2; /* 16 */ =20 - /* Index of the arguments for this op, or 0 for zero-operand ops. */ - unsigned args : 14; /* 48 */ + /* Index of the prev/next op, or 0 for the end of the list. */ + unsigned prev : 16; /* 32 */ + unsigned next : 16; /* 48 */ =20 /* Lifetime data of the operands. */ unsigned life : 16; /* 64 */ + + /* Arguments for the opcode. */ + TCGArg args[MAX_OPC_PARAM]; } TCGOp; =20 +/* Make sure that we don't expand the structure without noticing. */ +QEMU_BUILD_BUG_ON(sizeof(TCGOp) !=3D 8 + sizeof(TCGArg) * MAX_OPC_PARAM); + /* Make sure operands fit in the bitfields above. */ QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); -QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10)); -QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14)); - -/* Make sure that we don't overflow 64 bits without noticing. */ -QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8); +QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16)); =20 struct TCGContext { uint8_t *pool_cur, *pool_end; @@ -682,7 +680,6 @@ struct TCGContext { #endif =20 int gen_next_op_idx; - int gen_next_parm_idx; =20 /* Code generation. Note that we specifically do not use tcg_insn_unit here, because there's too much arithmetic throughout that relies @@ -720,7 +717,6 @@ struct TCGContext { TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; =20 TCGOp gen_op_buf[OPC_BUF_SIZE]; - TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE]; =20 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; @@ -731,8 +727,7 @@ extern bool parallel_cpus; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { - int op_argi =3D tcg_ctx.gen_op_buf[op_idx].args; - tcg_ctx.gen_opparam_buf[op_argi + arg] =3D v; + tcg_ctx.gen_op_buf[op_idx].args[arg] =3D v; } =20 /* The number of opcodes emitted so far. */ diff --git a/tcg/optimize.c b/tcg/optimize.c index adfc56ce62..002aad6bf4 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -576,7 +576,7 @@ void tcg_optimize(TCGContext *s) TCGArg tmp; =20 TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D &s->gen_opparam_buf[op->args]; + TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 @@ -1184,7 +1184,7 @@ void tcg_optimize(TCGContext *s) uint64_t b =3D ((uint64_t)bh << 32) | bl; TCGArg rl, rh; TCGOp *op2 =3D tcg_op_insert_before(s, op, INDEX_op_movi_i= 32, 2); - TCGArg *args2 =3D &s->gen_opparam_buf[op2->args]; + TCGArg *args2 =3D op2->args; =20 if (opc =3D=3D INDEX_op_add2_i32) { a +=3D b; @@ -1210,7 +1210,7 @@ void tcg_optimize(TCGContext *s) uint64_t r =3D (uint64_t)a * b; TCGArg rl, rh; TCGOp *op2 =3D tcg_op_insert_before(s, op, INDEX_op_movi_i= 32, 2); - TCGArg *args2 =3D &s->gen_opparam_buf[op2->args]; + TCGArg *args2 =3D op2->args; =20 rl =3D args[0]; rh =3D args[1]; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index d3c0e4799e..bd84a782e3 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -46,107 +46,78 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); Up to and including filling in the forward link immediately. We'll do proper termination of the end of the list after we finish translation. = */ =20 -static void tcg_emit_op(TCGContext *ctx, TCGOpcode opc, int args) +static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc) { int oi =3D ctx->gen_next_op_idx; int ni =3D oi + 1; int pi =3D oi - 1; + TCGOp *op =3D &ctx->gen_op_buf[oi]; =20 tcg_debug_assert(oi < OPC_BUF_SIZE); ctx->gen_op_buf[0].prev =3D oi; ctx->gen_next_op_idx =3D ni; =20 - ctx->gen_op_buf[oi] =3D (TCGOp){ - .opc =3D opc, - .args =3D args, - .prev =3D pi, - .next =3D ni - }; + memset(op, 0, offsetof(TCGOp, args)); + op->opc =3D opc; + op->prev =3D pi; + op->next =3D ni; + + return op; } =20 void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 1 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 1; - ctx->gen_opparam_buf[pi] =3D a1; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; } =20 void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 2 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 2; - ctx->gen_opparam_buf[pi + 0] =3D a1; - ctx->gen_opparam_buf[pi + 1] =3D a2; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; + op->args[1] =3D a2; } =20 void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 3 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 3; - ctx->gen_opparam_buf[pi + 0] =3D a1; - ctx->gen_opparam_buf[pi + 1] =3D a2; - ctx->gen_opparam_buf[pi + 2] =3D a3; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; + op->args[1] =3D a2; + op->args[2] =3D a3; } =20 void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 4 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 4; - ctx->gen_opparam_buf[pi + 0] =3D a1; - ctx->gen_opparam_buf[pi + 1] =3D a2; - ctx->gen_opparam_buf[pi + 2] =3D a3; - ctx->gen_opparam_buf[pi + 3] =3D a4; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; + op->args[1] =3D a2; + op->args[2] =3D a3; + op->args[3] =3D a4; } =20 void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 5 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 5; - ctx->gen_opparam_buf[pi + 0] =3D a1; - ctx->gen_opparam_buf[pi + 1] =3D a2; - ctx->gen_opparam_buf[pi + 2] =3D a3; - ctx->gen_opparam_buf[pi + 3] =3D a4; - ctx->gen_opparam_buf[pi + 4] =3D a5; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; + op->args[1] =3D a2; + op->args[2] =3D a3; + op->args[3] =3D a4; + op->args[4] =3D a5; } =20 void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6) { - int pi =3D ctx->gen_next_parm_idx; - - tcg_debug_assert(pi + 6 <=3D OPPARAM_BUF_SIZE); - ctx->gen_next_parm_idx =3D pi + 6; - ctx->gen_opparam_buf[pi + 0] =3D a1; - ctx->gen_opparam_buf[pi + 1] =3D a2; - ctx->gen_opparam_buf[pi + 2] =3D a3; - ctx->gen_opparam_buf[pi + 3] =3D a4; - ctx->gen_opparam_buf[pi + 4] =3D a5; - ctx->gen_opparam_buf[pi + 5] =3D a6; - - tcg_emit_op(ctx, opc, pi); + TCGOp *op =3D tcg_emit_op(ctx, opc); + op->args[0] =3D a1; + op->args[1] =3D a2; + op->args[2] =3D a3; + op->args[3] =3D a4; + op->args[4] =3D a5; + op->args[5] =3D a6; } =20 void tcg_gen_mb(TCGBar mb_type) diff --git a/tcg/tcg.c b/tcg/tcg.c index 4492e1eb3f..98673f2190 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -471,7 +471,6 @@ void tcg_func_start(TCGContext *s) s->gen_op_buf[0].next =3D 1; s->gen_op_buf[0].prev =3D 0; s->gen_next_op_idx =3D 1; - s->gen_next_parm_idx =3D 0; } =20 static inline int temp_idx(TCGContext *s, TCGTemp *ts) @@ -980,9 +979,10 @@ bool tcg_op_supported(TCGOpcode op) void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, int nargs, TCGArg *args) { - int i, real_args, nb_rets, pi, pi_first; + int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; + TCGOp *op; =20 info =3D g_hash_table_lookup(helper_table, (gpointer)func); flags =3D info->flags; @@ -995,11 +995,11 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg = ret, int orig_sizemask =3D sizemask; int orig_nargs =3D nargs; TCGv_i64 retl, reth; + TCGArg split_args[MAX_OPC_PARAM]; =20 TCGV_UNUSED_I64(retl); TCGV_UNUSED_I64(reth); if (sizemask !=3D 0) { - TCGArg *split_args =3D __builtin_alloca(sizeof(TCGArg) * nargs * 2= ); for (i =3D real_args =3D 0; i < nargs; ++i) { int is_64bit =3D sizemask & (1 << (i+1)*2); if (is_64bit) { @@ -1034,7 +1034,19 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg= ret, } #endif /* TCG_TARGET_EXTEND_ARGS */ =20 - pi_first =3D pi =3D s->gen_next_parm_idx; + i =3D s->gen_next_op_idx; + tcg_debug_assert(i < OPC_BUF_SIZE); + s->gen_op_buf[0].prev =3D i; + s->gen_next_op_idx =3D i + 1; + op =3D &s->gen_op_buf[i]; + + /* Set links for sequential allocation during translation. */ + memset(op, 0, offsetof(TCGOp, args)); + op->opc =3D INDEX_op_call; + op->prev =3D i - 1; + op->next =3D i + 1; + + pi =3D 0; if (ret !=3D TCG_CALL_DUMMY_ARG) { #if defined(__sparc__) && !defined(__arch64__) \ && !defined(CONFIG_TCG_INTERPRETER) @@ -1044,31 +1056,33 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGAr= g ret, two return temporaries, and reassemble below. */ retl =3D tcg_temp_new_i64(); reth =3D tcg_temp_new_i64(); - s->gen_opparam_buf[pi++] =3D GET_TCGV_I64(reth); - s->gen_opparam_buf[pi++] =3D GET_TCGV_I64(retl); + op->args[pi++] =3D GET_TCGV_I64(reth); + op->args[pi++] =3D GET_TCGV_I64(retl); nb_rets =3D 2; } else { - s->gen_opparam_buf[pi++] =3D ret; + op->args[pi++] =3D ret; nb_rets =3D 1; } #else if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { #ifdef HOST_WORDS_BIGENDIAN - s->gen_opparam_buf[pi++] =3D ret + 1; - s->gen_opparam_buf[pi++] =3D ret; + op->args[pi++] =3D ret + 1; + op->args[pi++] =3D ret; #else - s->gen_opparam_buf[pi++] =3D ret; - s->gen_opparam_buf[pi++] =3D ret + 1; + op->args[pi++] =3D ret; + op->args[pi++] =3D ret + 1; #endif nb_rets =3D 2; } else { - s->gen_opparam_buf[pi++] =3D ret; + op->args[pi++] =3D ret; nb_rets =3D 1; } #endif } else { nb_rets =3D 0; } + op->callo =3D nb_rets; + real_args =3D 0; for (i =3D 0; i < nargs; i++) { int is_64bit =3D sizemask & (1 << (i+1)*2); @@ -1076,7 +1090,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg = ret, #ifdef TCG_TARGET_CALL_ALIGN_ARGS /* some targets want aligned 64 bit args */ if (real_args & 1) { - s->gen_opparam_buf[pi++] =3D TCG_CALL_DUMMY_ARG; + op->args[pi++] =3D TCG_CALL_DUMMY_ARG; real_args++; } #endif @@ -1091,42 +1105,26 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGAr= g ret, have to get more complicated to differentiate between stack arguments and register arguments. */ #if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) - s->gen_opparam_buf[pi++] =3D args[i] + 1; - s->gen_opparam_buf[pi++] =3D args[i]; + op->args[pi++] =3D args[i] + 1; + op->args[pi++] =3D args[i]; #else - s->gen_opparam_buf[pi++] =3D args[i]; - s->gen_opparam_buf[pi++] =3D args[i] + 1; + op->args[pi++] =3D args[i]; + op->args[pi++] =3D args[i] + 1; #endif real_args +=3D 2; continue; } =20 - s->gen_opparam_buf[pi++] =3D args[i]; + op->args[pi++] =3D args[i]; real_args++; } - s->gen_opparam_buf[pi++] =3D (uintptr_t)func; - s->gen_opparam_buf[pi++] =3D flags; + op->args[pi++] =3D (uintptr_t)func; + op->args[pi++] =3D flags; + op->calli =3D real_args; =20 - i =3D s->gen_next_op_idx; - tcg_debug_assert(i < OPC_BUF_SIZE); - tcg_debug_assert(pi <=3D OPPARAM_BUF_SIZE); - - /* Set links for sequential allocation during translation. */ - s->gen_op_buf[i] =3D (TCGOp){ - .opc =3D INDEX_op_call, - .callo =3D nb_rets, - .calli =3D real_args, - .args =3D pi_first, - .prev =3D i - 1, - .next =3D i + 1 - }; - - /* Make sure the calli field didn't overflow. */ - tcg_debug_assert(s->gen_op_buf[i].calli =3D=3D real_args); - - s->gen_op_buf[0].prev =3D i; - s->gen_next_op_idx =3D i + 1; - s->gen_next_parm_idx =3D pi; + /* Make sure the fields didn't overflow. */ + tcg_debug_assert(op->calli =3D=3D real_args); + tcg_debug_assert(pi <=3D ARRAY_SIZE(op->args)); =20 #if defined(__sparc__) && !defined(__arch64__) \ && !defined(CONFIG_TCG_INTERPRETER) @@ -1286,7 +1284,7 @@ void tcg_dump_ops(TCGContext *s) op =3D &s->gen_op_buf[oi]; c =3D op->opc; def =3D &tcg_op_defs[c]; - args =3D &s->gen_opparam_buf[op->args]; + args =3D op->args; =20 if (c =3D=3D INDEX_op_insn_start) { col +=3D qemu_log("%s ----", oi !=3D s->gen_op_buf[0].next ? "= \n" : ""); @@ -1570,20 +1568,16 @@ TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *o= ld_op, TCGOpcode opc, int nargs) { int oi =3D s->gen_next_op_idx; - int pi =3D s->gen_next_parm_idx; int prev =3D old_op->prev; int next =3D old_op - s->gen_op_buf; TCGOp *new_op; =20 tcg_debug_assert(oi < OPC_BUF_SIZE); - tcg_debug_assert(pi + nargs <=3D OPPARAM_BUF_SIZE); s->gen_next_op_idx =3D oi + 1; - s->gen_next_parm_idx =3D pi + nargs; =20 new_op =3D &s->gen_op_buf[oi]; *new_op =3D (TCGOp){ .opc =3D opc, - .args =3D pi, .prev =3D prev, .next =3D next }; @@ -1597,20 +1591,16 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *ol= d_op, TCGOpcode opc, int nargs) { int oi =3D s->gen_next_op_idx; - int pi =3D s->gen_next_parm_idx; int prev =3D old_op - s->gen_op_buf; int next =3D old_op->next; TCGOp *new_op; =20 tcg_debug_assert(oi < OPC_BUF_SIZE); - tcg_debug_assert(pi + nargs <=3D OPPARAM_BUF_SIZE); s->gen_next_op_idx =3D oi + 1; - s->gen_next_parm_idx =3D pi + nargs; =20 new_op =3D &s->gen_op_buf[oi]; *new_op =3D (TCGOp){ .opc =3D opc, - .args =3D pi, .prev =3D prev, .next =3D next }; @@ -1666,7 +1656,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) TCGArg arg; =20 TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D &s->gen_opparam_buf[op->args]; + TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 @@ -1904,7 +1894,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp *op =3D &s->gen_op_buf[oi]; - TCGArg *args =3D &s->gen_opparam_buf[op->args]; + TCGArg *args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; @@ -1947,7 +1937,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) ? INDEX_op_ld_i32 : INDEX_op_ld_i64); TCGOp *lop =3D tcg_op_insert_before(s, op, lopc, 3); - TCGArg *largs =3D &s->gen_opparam_buf[lop->args]; + TCGArg *largs =3D lop->args; =20 largs[0] =3D dir; largs[1] =3D temp_idx(s, its->mem_base); @@ -2019,7 +2009,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) ? INDEX_op_st_i32 : INDEX_op_st_i64); TCGOp *sop =3D tcg_op_insert_after(s, op, sopc, 3); - TCGArg *sargs =3D &s->gen_opparam_buf[sop->args]; + TCGArg *sargs =3D sop->args; =20 sargs[0] =3D dir; sargs[1] =3D temp_idx(s, its->mem_base); @@ -2851,7 +2841,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) num_insns =3D -1; for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D &s->gen_opparam_buf[op->args]; + TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508174916034463.72225189161; Mon, 16 Oct 2017 10:28:36 -0700 (PDT) Received: from localhost ([::1]:34301 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Bi-0003Wx-4G for importer@patchew.org; Mon, 16 Oct 2017 13:28:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499h-0001sd-7I for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499d-0003EE-HC for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:21 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:52165) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499d-0003DA-4K for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:17 -0400 Received: by mail-pg0-x234.google.com with SMTP id p9so2747468pgc.8 for ; Mon, 16 Oct 2017 10:26:17 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v6 02/50] tcg: Propagate args to op->args in optimizer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/optimize.c | 430 ++++++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 227 insertions(+), 203 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 002aad6bf4..1a1c6fb90c 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -166,8 +166,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return false; } =20 -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg = val) { TCGOpcode new_op =3D op_to_movi(op->opc); tcg_target_ulong mask; @@ -184,12 +183,11 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op= , TCGArg *args, } temps[dst].mask =3D mask; =20 - args[0] =3D dst; - args[1] =3D val; + op->args[0] =3D dst; + op->args[1] =3D val; } =20 -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg src) +static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg s= rc) { if (temps_are_copies(dst, src)) { tcg_op_remove(s, op); @@ -218,8 +216,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T= CGArg *args, temps[dst].val =3D temps[src].val; } =20 - args[0] =3D dst; - args[1] =3D src; + op->args[0] =3D dst; + op->args[1] =3D src; } =20 static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) @@ -559,7 +557,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) void tcg_optimize(TCGContext *s) { int oi, oi_next, nb_temps, nb_globals; - TCGArg *prev_mb_args =3D NULL; + TCGOp *prev_mb =3D NULL; =20 /* Array VALS has an element for each temp. If this temp holds a constant then its value is kept in VALS' eleme= nt. @@ -576,7 +574,6 @@ void tcg_optimize(TCGContext *s) TCGArg tmp; =20 TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 @@ -588,7 +585,7 @@ void tcg_optimize(TCGContext *s) nb_oargs =3D op->callo; nb_iargs =3D op->calli; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - tmp =3D args[i]; + tmp =3D op->args[i]; if (tmp !=3D TCG_CALL_DUMMY_ARG) { init_temp_info(tmp); } @@ -597,14 +594,14 @@ void tcg_optimize(TCGContext *s) nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - init_temp_info(args[i]); + init_temp_info(op->args[i]); } } =20 /* Do copy propagation */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - if (temp_is_copy(args[i])) { - args[i] =3D find_better_copy(s, args[i]); + if (temp_is_copy(op->args[i])) { + op->args[i] =3D find_better_copy(s, op->args[i]); } } =20 @@ -620,45 +617,45 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(nor): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - swap_commutative(args[0], &args[1], &args[2]); + swap_commutative(op->args[0], &op->args[1], &op->args[2]); break; CASE_OP_32_64(brcond): - if (swap_commutative(-1, &args[0], &args[1])) { - args[2] =3D tcg_swap_cond(args[2]); + if (swap_commutative(-1, &op->args[0], &op->args[1])) { + op->args[2] =3D tcg_swap_cond(op->args[2]); } break; CASE_OP_32_64(setcond): - if (swap_commutative(args[0], &args[1], &args[2])) { - args[3] =3D tcg_swap_cond(args[3]); + if (swap_commutative(op->args[0], &op->args[1], &op->args[2]))= { + op->args[3] =3D tcg_swap_cond(op->args[3]); } break; CASE_OP_32_64(movcond): - if (swap_commutative(-1, &args[1], &args[2])) { - args[5] =3D tcg_swap_cond(args[5]); + if (swap_commutative(-1, &op->args[1], &op->args[2])) { + op->args[5] =3D tcg_swap_cond(op->args[5]); } /* For movcond, we canonicalize the "false" input reg to match the destination reg so that the tcg backend can implement a "move if true" operation. */ - if (swap_commutative(args[0], &args[4], &args[3])) { - args[5] =3D tcg_invert_cond(args[5]); + if (swap_commutative(op->args[0], &op->args[4], &op->args[3]))= { + op->args[5] =3D tcg_invert_cond(op->args[5]); } break; CASE_OP_32_64(add2): - swap_commutative(args[0], &args[2], &args[4]); - swap_commutative(args[1], &args[3], &args[5]); + swap_commutative(op->args[0], &op->args[2], &op->args[4]); + swap_commutative(op->args[1], &op->args[3], &op->args[5]); break; CASE_OP_32_64(mulu2): CASE_OP_32_64(muls2): - swap_commutative(args[0], &args[2], &args[3]); + swap_commutative(op->args[0], &op->args[2], &op->args[3]); break; case INDEX_op_brcond2_i32: - if (swap_commutative2(&args[0], &args[2])) { - args[4] =3D tcg_swap_cond(args[4]); + if (swap_commutative2(&op->args[0], &op->args[2])) { + op->args[4] =3D tcg_swap_cond(op->args[4]); } break; case INDEX_op_setcond2_i32: - if (swap_commutative2(&args[1], &args[3])) { - args[5] =3D tcg_swap_cond(args[5]); + if (swap_commutative2(&op->args[1], &op->args[3])) { + op->args[5] =3D tcg_swap_cond(op->args[5]); } break; default: @@ -673,8 +670,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(sar): CASE_OP_32_64(rotl): CASE_OP_32_64(rotr): - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temp_is_const(op->args[1]) && temps[op->args[1]].val =3D= =3D 0) { + tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; @@ -683,7 +680,7 @@ void tcg_optimize(TCGContext *s) TCGOpcode neg_op; bool have_neg; =20 - if (temp_is_const(args[2])) { + if (temp_is_const(op->args[2])) { /* Proceed with possible constant folding. */ break; } @@ -697,40 +694,45 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0)= { + if (temp_is_const(op->args[1]) + && temps[op->args[1]].val =3D=3D 0) { op->opc =3D neg_op; - reset_temp(args[0]); - args[1] =3D args[2]; + reset_temp(op->args[0]); + op->args[1] =3D op->args[2]; continue; } } break; CASE_OP_32_64(xor): CASE_OP_32_64(nand): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { + if (!temp_is_const(op->args[1]) + && temp_is_const(op->args[2]) + && temps[op->args[2]].val =3D=3D -1) { i =3D 1; goto try_not; } break; CASE_OP_32_64(nor): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { + if (!temp_is_const(op->args[1]) + && temp_is_const(op->args[2]) + && temps[op->args[2]].val =3D=3D 0) { i =3D 1; goto try_not; } break; CASE_OP_32_64(andc): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D -1)= { + if (!temp_is_const(op->args[2]) + && temp_is_const(op->args[1]) + && temps[op->args[1]].val =3D=3D -1) { i =3D 2; goto try_not; } break; CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { + if (!temp_is_const(op->args[2]) + && temp_is_const(op->args[1]) + && temps[op->args[1]].val =3D=3D 0) { i =3D 2; goto try_not; } @@ -751,8 +753,8 @@ void tcg_optimize(TCGContext *s) break; } op->opc =3D not_op; - reset_temp(args[0]); - args[1] =3D args[i]; + reset_temp(op->args[0]); + op->args[1] =3D op->args[i]; continue; } default: @@ -771,18 +773,20 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(or): CASE_OP_32_64(xor): CASE_OP_32_64(andc): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(op->args[1]) + && temp_is_const(op->args[2]) + && temps[op->args[2]].val =3D=3D 0) { + tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; CASE_OP_32_64(and): CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(op->args[1]) + && temp_is_const(op->args[2]) + && temps[op->args[2]].val =3D=3D -1) { + tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; @@ -796,21 +800,21 @@ void tcg_optimize(TCGContext *s) affected =3D -1; switch (opc) { CASE_OP_32_64(ext8s): - if ((temps[args[1]].mask & 0x80) !=3D 0) { + if ((temps[op->args[1]].mask & 0x80) !=3D 0) { break; } CASE_OP_32_64(ext8u): mask =3D 0xff; goto and_const; CASE_OP_32_64(ext16s): - if ((temps[args[1]].mask & 0x8000) !=3D 0) { + if ((temps[op->args[1]].mask & 0x8000) !=3D 0) { break; } CASE_OP_32_64(ext16u): mask =3D 0xffff; goto and_const; case INDEX_op_ext32s_i64: - if ((temps[args[1]].mask & 0x80000000) !=3D 0) { + if ((temps[op->args[1]].mask & 0x80000000) !=3D 0) { break; } case INDEX_op_ext32u_i64: @@ -818,110 +822,111 @@ void tcg_optimize(TCGContext *s) goto and_const; =20 CASE_OP_32_64(and): - mask =3D temps[args[2]].mask; - if (temp_is_const(args[2])) { + mask =3D temps[op->args[2]].mask; + if (temp_is_const(op->args[2])) { and_const: - affected =3D temps[args[1]].mask & ~mask; + affected =3D temps[op->args[1]].mask & ~mask; } - mask =3D temps[args[1]].mask & mask; + mask =3D temps[op->args[1]].mask & mask; break; =20 case INDEX_op_ext_i32_i64: - if ((temps[args[1]].mask & 0x80000000) !=3D 0) { + if ((temps[op->args[1]].mask & 0x80000000) !=3D 0) { break; } case INDEX_op_extu_i32_i64: /* We do not compute affected as it is a size changing op. */ - mask =3D (uint32_t)temps[args[1]].mask; + mask =3D (uint32_t)temps[op->args[1]].mask; break; =20 CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless - args[2] is constant, we can't infer anything from it. */ - if (temp_is_const(args[2])) { - mask =3D ~temps[args[2]].mask; + op->args[2] is constant, we can't infer anything from it. = */ + if (temp_is_const(op->args[2])) { + mask =3D ~temps[op->args[2]].mask; goto and_const; } - /* But we certainly know nothing outside args[1] may be set. */ - mask =3D temps[args[1]].mask; + /* But we certainly know nothing outside op->args[1] may be se= t. */ + mask =3D temps[op->args[1]].mask; break; =20 case INDEX_op_sar_i32: - if (temp_is_const(args[2])) { - tmp =3D temps[args[2]].val & 31; - mask =3D (int32_t)temps[args[1]].mask >> tmp; + if (temp_is_const(op->args[2])) { + tmp =3D temps[op->args[2]].val & 31; + mask =3D (int32_t)temps[op->args[1]].mask >> tmp; } break; case INDEX_op_sar_i64: - if (temp_is_const(args[2])) { - tmp =3D temps[args[2]].val & 63; - mask =3D (int64_t)temps[args[1]].mask >> tmp; + if (temp_is_const(op->args[2])) { + tmp =3D temps[op->args[2]].val & 63; + mask =3D (int64_t)temps[op->args[1]].mask >> tmp; } break; =20 case INDEX_op_shr_i32: - if (temp_is_const(args[2])) { - tmp =3D temps[args[2]].val & 31; - mask =3D (uint32_t)temps[args[1]].mask >> tmp; + if (temp_is_const(op->args[2])) { + tmp =3D temps[op->args[2]].val & 31; + mask =3D (uint32_t)temps[op->args[1]].mask >> tmp; } break; case INDEX_op_shr_i64: - if (temp_is_const(args[2])) { - tmp =3D temps[args[2]].val & 63; - mask =3D (uint64_t)temps[args[1]].mask >> tmp; + if (temp_is_const(op->args[2])) { + tmp =3D temps[op->args[2]].val & 63; + mask =3D (uint64_t)temps[op->args[1]].mask >> tmp; } break; =20 case INDEX_op_extrl_i64_i32: - mask =3D (uint32_t)temps[args[1]].mask; + mask =3D (uint32_t)temps[op->args[1]].mask; break; case INDEX_op_extrh_i64_i32: - mask =3D (uint64_t)temps[args[1]].mask >> 32; + mask =3D (uint64_t)temps[op->args[1]].mask >> 32; break; =20 CASE_OP_32_64(shl): - if (temp_is_const(args[2])) { - tmp =3D temps[args[2]].val & (TCG_TARGET_REG_BITS - 1); - mask =3D temps[args[1]].mask << tmp; + if (temp_is_const(op->args[2])) { + tmp =3D temps[op->args[2]].val & (TCG_TARGET_REG_BITS - 1); + mask =3D temps[op->args[1]].mask << tmp; } break; =20 CASE_OP_32_64(neg): /* Set to 1 all bits to the left of the rightmost. */ - mask =3D -(temps[args[1]].mask & -temps[args[1]].mask); + mask =3D -(temps[op->args[1]].mask & -temps[op->args[1]].mask); break; =20 CASE_OP_32_64(deposit): - mask =3D deposit64(temps[args[1]].mask, args[3], args[4], - temps[args[2]].mask); + mask =3D deposit64(temps[op->args[1]].mask, op->args[3], + op->args[4], temps[op->args[2]].mask); break; =20 CASE_OP_32_64(extract): - mask =3D extract64(temps[args[1]].mask, args[2], args[3]); - if (args[2] =3D=3D 0) { - affected =3D temps[args[1]].mask & ~mask; + mask =3D extract64(temps[op->args[1]].mask, op->args[2], op->a= rgs[3]); + if (op->args[2] =3D=3D 0) { + affected =3D temps[op->args[1]].mask & ~mask; } break; CASE_OP_32_64(sextract): - mask =3D sextract64(temps[args[1]].mask, args[2], args[3]); - if (args[2] =3D=3D 0 && (tcg_target_long)mask >=3D 0) { - affected =3D temps[args[1]].mask & ~mask; + mask =3D sextract64(temps[op->args[1]].mask, + op->args[2], op->args[3]); + if (op->args[2] =3D=3D 0 && (tcg_target_long)mask >=3D 0) { + affected =3D temps[op->args[1]].mask & ~mask; } break; =20 CASE_OP_32_64(or): CASE_OP_32_64(xor): - mask =3D temps[args[1]].mask | temps[args[2]].mask; + mask =3D temps[op->args[1]].mask | temps[op->args[2]].mask; break; =20 case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - mask =3D temps[args[2]].mask | 31; + mask =3D temps[op->args[2]].mask | 31; break; =20 case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - mask =3D temps[args[2]].mask | 63; + mask =3D temps[op->args[2]].mask | 63; break; =20 case INDEX_op_ctpop_i32: @@ -937,7 +942,7 @@ void tcg_optimize(TCGContext *s) break; =20 CASE_OP_32_64(movcond): - mask =3D temps[args[3]].mask | temps[args[4]].mask; + mask =3D temps[op->args[3]].mask | temps[op->args[4]].mask; break; =20 CASE_OP_32_64(ld8u): @@ -952,7 +957,7 @@ void tcg_optimize(TCGContext *s) =20 CASE_OP_32_64(qemu_ld): { - TCGMemOpIdx oi =3D args[nb_oargs + nb_iargs]; + TCGMemOpIdx oi =3D op->args[nb_oargs + nb_iargs]; TCGMemOp mop =3D get_memop(oi); if (!(mop & MO_SIGN)) { mask =3D (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; @@ -976,12 +981,12 @@ void tcg_optimize(TCGContext *s) =20 if (partmask =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_movi(s, op, args, args[0], 0); + tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } if (affected =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } =20 @@ -991,8 +996,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mul): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - if ((temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0)) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if ((temp_is_const(op->args[2]) && temps[op->args[2]].val =3D= =3D 0)) { + tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; @@ -1004,8 +1009,8 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64(or): CASE_OP_32_64(and): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (temps_are_copies(op->args[1], op->args[2])) { + tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; @@ -1018,8 +1023,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): CASE_OP_32_64(sub): CASE_OP_32_64(xor): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temps_are_copies(op->args[1], op->args[2])) { + tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; @@ -1032,10 +1037,10 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64(mov): - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); break; CASE_OP_32_64(movi): - tcg_opt_gen_movi(s, op, args, args[0], args[1]); + tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); break; =20 CASE_OP_32_64(not): @@ -1051,9 +1056,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - if (temp_is_const(args[1])) { - tmp =3D do_constant_folding(opc, temps[args[1]].val, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + if (temp_is_const(op->args[1])) { + tmp =3D do_constant_folding(opc, temps[op->args[1]].val, 0= ); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; @@ -1080,68 +1085,72 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): CASE_OP_32_64(rem): CASE_OP_32_64(remu): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { - tmp =3D do_constant_folding(opc, temps[args[1]].val, - temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) { + tmp =3D do_constant_folding(opc, temps[op->args[1]].val, + temps[op->args[2]].val); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(clz): CASE_OP_32_64(ctz): - if (temp_is_const(args[1])) { - TCGArg v =3D temps[args[1]].val; + if (temp_is_const(op->args[1])) { + TCGArg v =3D temps[op->args[1]].val; if (v !=3D 0) { tmp =3D do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, op, op->args[0], tmp); } else { - tcg_opt_gen_mov(s, op, args, args[0], args[2]); + tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); } break; } goto do_default; =20 CASE_OP_32_64(deposit): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { - tmp =3D deposit64(temps[args[1]].val, args[3], args[4], - temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) { + tmp =3D deposit64(temps[op->args[1]].val, op->args[3], + op->args[4], temps[op->args[2]].val); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(extract): - if (temp_is_const(args[1])) { - tmp =3D extract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + if (temp_is_const(op->args[1])) { + tmp =3D extract64(temps[op->args[1]].val, + op->args[2], op->args[3]); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(sextract): - if (temp_is_const(args[1])) { - tmp =3D sextract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + if (temp_is_const(op->args[1])) { + tmp =3D sextract64(temps[op->args[1]].val, + op->args[2], op->args[3]); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(setcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[3= ]); + tmp =3D do_constant_folding_cond(opc, op->args[1], + op->args[2], op->args[3]); if (tmp !=3D 2) { - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(brcond): - tmp =3D do_constant_folding_cond(opc, args[0], args[1], args[2= ]); + tmp =3D do_constant_folding_cond(opc, op->args[0], + op->args[1], op->args[2]); if (tmp !=3D 2) { if (tmp) { reset_all_temps(nb_temps); op->opc =3D INDEX_op_br; - args[0] =3D args[3]; + op->args[0] =3D op->args[3]; } else { tcg_op_remove(s, op); } @@ -1150,21 +1159,22 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 CASE_OP_32_64(movcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[5= ]); + tmp =3D do_constant_folding_cond(opc, op->args[1], + op->args[2], op->args[5]); if (tmp !=3D 2) { - tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]); + tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); break; } - if (temp_is_const(args[3]) && temp_is_const(args[4])) { - tcg_target_ulong tv =3D temps[args[3]].val; - tcg_target_ulong fv =3D temps[args[4]].val; - TCGCond cond =3D args[5]; + if (temp_is_const(op->args[3]) && temp_is_const(op->args[4])) { + tcg_target_ulong tv =3D temps[op->args[3]].val; + tcg_target_ulong fv =3D temps[op->args[4]].val; + TCGCond cond =3D op->args[5]; if (fv =3D=3D 1 && tv =3D=3D 0) { cond =3D tcg_invert_cond(cond); } else if (!(tv =3D=3D 1 && fv =3D=3D 0)) { goto do_default; } - args[3] =3D cond; + op->args[3] =3D cond; op->opc =3D opc =3D (opc =3D=3D INDEX_op_movcond_i32 ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64); @@ -1174,17 +1184,16 @@ void tcg_optimize(TCGContext *s) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3]) - && temp_is_const(args[4]) && temp_is_const(args[5])) { - uint32_t al =3D temps[args[2]].val; - uint32_t ah =3D temps[args[3]].val; - uint32_t bl =3D temps[args[4]].val; - uint32_t bh =3D temps[args[5]].val; + if (temp_is_const(op->args[2]) && temp_is_const(op->args[3]) + && temp_is_const(op->args[4]) && temp_is_const(op->args[5]= )) { + uint32_t al =3D temps[op->args[2]].val; + uint32_t ah =3D temps[op->args[3]].val; + uint32_t bl =3D temps[op->args[4]].val; + uint32_t bh =3D temps[op->args[5]].val; uint64_t a =3D ((uint64_t)ah << 32) | al; uint64_t b =3D ((uint64_t)bh << 32) | bl; TCGArg rl, rh; TCGOp *op2 =3D tcg_op_insert_before(s, op, INDEX_op_movi_i= 32, 2); - TCGArg *args2 =3D op2->args; =20 if (opc =3D=3D INDEX_op_add2_i32) { a +=3D b; @@ -1192,10 +1201,10 @@ void tcg_optimize(TCGContext *s) a -=3D b; } =20 - rl =3D args[0]; - rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32)); + rl =3D op->args[0]; + rh =3D op->args[1]; + tcg_opt_gen_movi(s, op, rl, (int32_t)a); + tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1204,18 +1213,17 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_mulu2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3])) { - uint32_t a =3D temps[args[2]].val; - uint32_t b =3D temps[args[3]].val; + if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])) { + uint32_t a =3D temps[op->args[2]].val; + uint32_t b =3D temps[op->args[3]].val; uint64_t r =3D (uint64_t)a * b; TCGArg rl, rh; TCGOp *op2 =3D tcg_op_insert_before(s, op, INDEX_op_movi_i= 32, 2); - TCGArg *args2 =3D op2->args; =20 - rl =3D args[0]; - rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32)); + rl =3D op->args[0]; + rh =3D op->args[1]; + tcg_opt_gen_movi(s, op, rl, (int32_t)r); + tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1224,41 +1232,47 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_brcond2_i32: - tmp =3D do_constant_folding_cond2(&args[0], &args[2], args[4]); + tmp =3D do_constant_folding_cond2(&op->args[0], &op->args[2], + op->args[4]); if (tmp !=3D 2) { if (tmp) { do_brcond_true: reset_all_temps(nb_temps); op->opc =3D INDEX_op_br; - args[0] =3D args[5]; + op->args[0] =3D op->args[5]; } else { do_brcond_false: tcg_op_remove(s, op); } - } else if ((args[4] =3D=3D TCG_COND_LT || args[4] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[2]) && temps[args[2]].val =3D= =3D 0 - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0) { + } else if ((op->args[4] =3D=3D TCG_COND_LT + || op->args[4] =3D=3D TCG_COND_GE) + && temp_is_const(op->args[2]) + && temps[op->args[2]].val =3D=3D 0 + && temp_is_const(op->args[3]) + && temps[op->args[3]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: reset_all_temps(nb_temps); op->opc =3D INDEX_op_brcond_i32; - args[0] =3D args[1]; - args[1] =3D args[3]; - args[2] =3D args[4]; - args[3] =3D args[5]; - } else if (args[4] =3D=3D TCG_COND_EQ) { + op->args[0] =3D op->args[1]; + op->args[1] =3D op->args[3]; + op->args[2] =3D op->args[4]; + op->args[3] =3D op->args[5]; + } else if (op->args[4] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, - args[0], args[2], TCG_COND_= EQ); + op->args[0], op->args[2], + TCG_COND_EQ); if (tmp =3D=3D 0) { goto do_brcond_false; } else if (tmp =3D=3D 1) { goto do_brcond_high; } tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, - args[1], args[3], TCG_COND_= EQ); + op->args[1], op->args[3], + TCG_COND_EQ); if (tmp =3D=3D 0) { goto do_brcond_false; } else if (tmp !=3D 1) { @@ -1267,21 +1281,23 @@ void tcg_optimize(TCGContext *s) do_brcond_low: reset_all_temps(nb_temps); op->opc =3D INDEX_op_brcond_i32; - args[1] =3D args[2]; - args[2] =3D args[4]; - args[3] =3D args[5]; - } else if (args[4] =3D=3D TCG_COND_NE) { + op->args[1] =3D op->args[2]; + op->args[2] =3D op->args[4]; + op->args[3] =3D op->args[5]; + } else if (op->args[4] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, - args[0], args[2], TCG_COND_= NE); + op->args[0], op->args[2], + TCG_COND_NE); if (tmp =3D=3D 0) { goto do_brcond_high; } else if (tmp =3D=3D 1) { goto do_brcond_true; } tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, - args[1], args[3], TCG_COND_= NE); + op->args[1], op->args[3], + TCG_COND_NE); if (tmp =3D=3D 0) { goto do_brcond_low; } else if (tmp =3D=3D 1) { @@ -1294,57 +1310,65 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_setcond2_i32: - tmp =3D do_constant_folding_cond2(&args[1], &args[3], args[5]); + tmp =3D do_constant_folding_cond2(&op->args[1], &op->args[3], + op->args[5]); if (tmp !=3D 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, args, args[0], tmp); - } else if ((args[5] =3D=3D TCG_COND_LT || args[5] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0 - && temp_is_const(args[4]) && temps[args[4]].val =3D= =3D 0) { + tcg_opt_gen_movi(s, op, op->args[0], tmp); + } else if ((op->args[5] =3D=3D TCG_COND_LT + || op->args[5] =3D=3D TCG_COND_GE) + && temp_is_const(op->args[3]) + && temps[op->args[3]].val =3D=3D 0 + && temp_is_const(op->args[4]) + && temps[op->args[4]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: - reset_temp(args[0]); - temps[args[0]].mask =3D 1; + reset_temp(op->args[0]); + temps[op->args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; - args[1] =3D args[2]; - args[2] =3D args[4]; - args[3] =3D args[5]; - } else if (args[5] =3D=3D TCG_COND_EQ) { + op->args[1] =3D op->args[2]; + op->args[2] =3D op->args[4]; + op->args[3] =3D op->args[5]; + } else if (op->args[5] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, - args[1], args[3], TCG_COND_= EQ); + op->args[1], op->args[3], + TCG_COND_EQ); if (tmp =3D=3D 0) { goto do_setcond_const; } else if (tmp =3D=3D 1) { goto do_setcond_high; } tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, - args[2], args[4], TCG_COND_= EQ); + op->args[2], op->args[4], + TCG_COND_EQ); if (tmp =3D=3D 0) { goto do_setcond_high; } else if (tmp !=3D 1) { goto do_default; } do_setcond_low: - reset_temp(args[0]); - temps[args[0]].mask =3D 1; + reset_temp(op->args[0]); + temps[op->args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; - args[2] =3D args[3]; - args[3] =3D args[5]; - } else if (args[5] =3D=3D TCG_COND_NE) { + op->args[2] =3D op->args[3]; + op->args[3] =3D op->args[5]; + } else if (op->args[5] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, - args[1], args[3], TCG_COND_= NE); + op->args[1], op->args[3], + TCG_COND_NE); if (tmp =3D=3D 0) { goto do_setcond_high; } else if (tmp =3D=3D 1) { goto do_setcond_const; } tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, - args[2], args[4], TCG_COND_= NE); + op->args[2], op->args[4], + TCG_COND_NE); if (tmp =3D=3D 0) { goto do_setcond_low; } else if (tmp =3D=3D 1) { @@ -1357,7 +1381,7 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_call: - if (!(args[nb_oargs + nb_iargs + 1] + if (!(op->args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS)= )) { for (i =3D 0; i < nb_globals; i++) { if (test_bit(i, temps_used.l)) { @@ -1379,11 +1403,11 @@ void tcg_optimize(TCGContext *s) } else { do_reset_output: for (i =3D 0; i < nb_oargs; i++) { - reset_temp(args[i]); + reset_temp(op->args[i]); /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). = */ if (i =3D=3D 0) { - temps[args[i]].mask =3D mask; + temps[op->args[i]].mask =3D mask; } } } @@ -1391,7 +1415,7 @@ void tcg_optimize(TCGContext *s) } =20 /* Eliminate duplicate and redundant fence instructions. */ - if (prev_mb_args) { + if (prev_mb) { switch (opc) { case INDEX_op_mb: /* Merge two barriers of the same type into one, @@ -1405,7 +1429,7 @@ void tcg_optimize(TCGContext *s) * barrier. This is stricter than specified but for * the purposes of TCG is better than not optimizing. */ - prev_mb_args[0] |=3D args[0]; + prev_mb->args[0] |=3D op->args[0]; tcg_op_remove(s, op); break; =20 @@ -1421,11 +1445,11 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_st_i64: case INDEX_op_call: /* Opcodes that touch guest memory stop the optimization. = */ - prev_mb_args =3D NULL; + prev_mb =3D NULL; break; } } else if (opc =3D=3D INDEX_op_mb) { - prev_mb_args =3D args; + prev_mb =3D op; } } } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175222289454.1975109328288; Mon, 16 Oct 2017 10:33:42 -0700 (PDT) Received: from localhost ([::1]:34324 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Gf-0008DL-Bx for importer@patchew.org; Mon, 16 Oct 2017 13:33:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499h-0001sW-34 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499f-0003Fs-2M for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:21 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:46993) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499e-0003Es-Pe for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:18 -0400 Received: by mail-pg0-x22f.google.com with SMTP id k7so7341617pga.3 for ; Mon, 16 Oct 2017 10:26:18 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J0VE06SjkV92bZIVIfFBbcIdqedj3gEMQuhX7z2qXFQ=; b=gSymsFJj1Z1pm7t/6j7KEyBB7heWCgExHdxdkI2XxvG6PglJJphAl/XhVgmhYpS9D4 VK4N0oELybJpUvEptLGHVxSvpzQi9pwL0H31rCyrXWMMGFdNo/j+IPb7S+mK8u1k69Zh rFRC63am3eXkvgJam23gQFQ4cCHnLyO8P/jYs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J0VE06SjkV92bZIVIfFBbcIdqedj3gEMQuhX7z2qXFQ=; b=iPs3qyLoK9NYwR7I4RrKE0/5t/TbP7mn3Xax3y9969rvPYZgxaGpXzFxRq7zrJOe9x KS+AHdszj/BkFtRIGaWx6fNcSOuwVCp8wssEMfxliFrW8zEXL8d3zHPcNk1S51tbvzx3 maSQdfHPqnA30jjywxh+JyqPeDHlZYt087L68/m6umxClKKrwmAHEY7WbxitMDKPkxOQ sGWFC4QpB6i32qu16/NfoT0yAUKhdDisoKGjSEbowicOLqDxMxRwS44pe+8WYjQGe2I6 7VpRM0r/6qEg8w1/ozyXhRgyfptd8HFgLvhmqrollo34vAhr1VXmmxXy0DC9zxEibXkP CdWw== X-Gm-Message-State: AMCzsaURGBN8r88fHEC175+ac2Rf7MhfGUmw94usHEj1VnFRxdTc3fgY WAOAn3WzJ9s+jR8ONmDBc82bCYvrczk= X-Google-Smtp-Source: AOwi7QAV9RyDUxw5S9JJGm0A/N/ovcsjJeixG14BUREB89Pd9in6O9WtS4vTNmpydM8tPAxh40JOKg== X-Received: by 10.159.208.2 with SMTP id a2mr9709124plp.370.1508174777078; Mon, 16 Oct 2017 10:26:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:22 -0700 Message-Id: <20171016172609.23422-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v6 03/50] tcg: Propagate args to op->args in tcg.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.c | 121 ++++++++++++++++++++++++++++++----------------------------= ---- 1 file changed, 58 insertions(+), 63 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 98673f2190..4f56077f64 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1277,14 +1277,12 @@ void tcg_dump_ops(TCGContext *s) for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D op->next) { int i, k, nb_oargs, nb_iargs, nb_cargs; const TCGOpDef *def; - const TCGArg *args; TCGOpcode c; int col =3D 0; =20 op =3D &s->gen_op_buf[oi]; c =3D op->opc; def =3D &tcg_op_defs[c]; - args =3D op->args; =20 if (c =3D=3D INDEX_op_insn_start) { col +=3D qemu_log("%s ----", oi !=3D s->gen_op_buf[0].next ? "= \n" : ""); @@ -1292,9 +1290,9 @@ void tcg_dump_ops(TCGContext *s) for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { target_ulong a; #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - a =3D ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2]; + a =3D deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + = 1]); #else - a =3D args[i]; + a =3D op->args[i]; #endif col +=3D qemu_log(" " TARGET_FMT_lx, a); } @@ -1306,14 +1304,14 @@ void tcg_dump_ops(TCGContext *s) =20 /* function name, flags, out args */ col +=3D qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, - tcg_find_helper(s, args[nb_oargs + nb_iargs]), - args[nb_oargs + nb_iargs + 1], nb_oargs); + tcg_find_helper(s, op->args[nb_oargs + nb_iarg= s]), + op->args[nb_oargs + nb_iargs + 1], nb_oargs); for (i =3D 0; i < nb_oargs; i++) { col +=3D qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeo= f(buf), - args[i])); + op->args[i])); } for (i =3D 0; i < nb_iargs; i++) { - TCGArg arg =3D args[nb_oargs + i]; + TCGArg arg =3D op->args[nb_oargs + i]; const char *t =3D ""; if (arg !=3D TCG_CALL_DUMMY_ARG) { t =3D tcg_get_arg_str_idx(s, buf, sizeof(buf), arg); @@ -1333,14 +1331,14 @@ void tcg_dump_ops(TCGContext *s) col +=3D qemu_log(","); } col +=3D qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof= (buf), - args[k++])); + op->args[k++])); } for (i =3D 0; i < nb_iargs; i++) { if (k !=3D 0) { col +=3D qemu_log(","); } col +=3D qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof= (buf), - args[k++])); + op->args[k++])); } switch (c) { case INDEX_op_brcond_i32: @@ -1351,10 +1349,11 @@ void tcg_dump_ops(TCGContext *s) case INDEX_op_brcond_i64: case INDEX_op_setcond_i64: case INDEX_op_movcond_i64: - if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]])= { - col +=3D qemu_log(",%s", cond_name[args[k++]]); + if (op->args[k] < ARRAY_SIZE(cond_name) + && cond_name[op->args[k]]) { + col +=3D qemu_log(",%s", cond_name[op->args[k++]]); } else { - col +=3D qemu_log(",$0x%" TCG_PRIlx, args[k++]); + col +=3D qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); } i =3D 1; break; @@ -1363,7 +1362,7 @@ void tcg_dump_ops(TCGContext *s) case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: { - TCGMemOpIdx oi =3D args[k++]; + TCGMemOpIdx oi =3D op->args[k++]; TCGMemOp op =3D get_memop(oi); unsigned ix =3D get_mmuidx(oi); =20 @@ -1388,14 +1387,15 @@ void tcg_dump_ops(TCGContext *s) case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: case INDEX_op_brcond2_i32: - col +=3D qemu_log("%s$L%d", k ? "," : "", arg_label(args[k= ])->id); + col +=3D qemu_log("%s$L%d", k ? "," : "", + arg_label(op->args[k])->id); i++, k++; break; default: break; } for (; i < nb_cargs; i++, k++) { - col +=3D qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", args[k= ]); + col +=3D qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->ar= gs[k]); } } if (op->life) { @@ -1656,7 +1656,6 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) TCGArg arg; =20 TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 @@ -1669,12 +1668,12 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) =20 nb_oargs =3D op->callo; nb_iargs =3D op->calli; - call_flags =3D args[nb_oargs + nb_iargs + 1]; + call_flags =3D op->args[nb_oargs + nb_iargs + 1]; =20 /* pure functions can be removed if their result is unused= */ if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { for (i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (temp_state[arg] !=3D TS_DEAD) { goto do_not_remove_call; } @@ -1685,7 +1684,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) =20 /* output args are dead */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (temp_state[arg] & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } @@ -1708,7 +1707,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) =20 /* record arguments that die in this helper */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { if (temp_state[arg] & TS_DEAD) { arg_life |=3D DEAD_ARG << i; @@ -1717,7 +1716,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) } /* input arguments are live for preceding opcodes */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { temp_state[arg] &=3D ~TS_DEAD; } @@ -1729,7 +1728,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) break; case INDEX_op_discard: /* mark the temporary as dead */ - temp_state[args[0]] =3D TS_DEAD; + temp_state[op->args[0]] =3D TS_DEAD; break; =20 case INDEX_op_add2_i32: @@ -1750,15 +1749,15 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) the low part. The result can be optimized to a simple add or sub. This happens often for x86_64 guest when the cpu mode is set to 32 bit. */ - if (temp_state[args[1]] =3D=3D TS_DEAD) { - if (temp_state[args[0]] =3D=3D TS_DEAD) { + if (temp_state[op->args[1]] =3D=3D TS_DEAD) { + if (temp_state[op->args[0]] =3D=3D TS_DEAD) { goto do_remove; } /* Replace the opcode and adjust the args in place, leaving 3 unused args at the end. */ op->opc =3D opc =3D opc_new; - args[1] =3D args[2]; - args[2] =3D args[4]; + op->args[1] =3D op->args[2]; + op->args[2] =3D op->args[4]; /* Fall through and mark the single-word operation live. = */ nb_iargs =3D 2; nb_oargs =3D 1; @@ -1788,21 +1787,21 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) do_mul2: nb_iargs =3D 2; nb_oargs =3D 2; - if (temp_state[args[1]] =3D=3D TS_DEAD) { - if (temp_state[args[0]] =3D=3D TS_DEAD) { + if (temp_state[op->args[1]] =3D=3D TS_DEAD) { + if (temp_state[op->args[0]] =3D=3D TS_DEAD) { /* Both parts of the operation are dead. */ goto do_remove; } /* The high part of the operation is dead; generate the lo= w. */ op->opc =3D opc =3D opc_new; - args[1] =3D args[2]; - args[2] =3D args[3]; - } else if (temp_state[args[0]] =3D=3D TS_DEAD && have_opc_new2= ) { + op->args[1] =3D op->args[2]; + op->args[2] =3D op->args[3]; + } else if (temp_state[op->args[0]] =3D=3D TS_DEAD && have_opc_= new2) { /* The low part of the operation is dead; generate the hig= h. */ op->opc =3D opc =3D opc_new2; - args[0] =3D args[1]; - args[1] =3D args[2]; - args[2] =3D args[3]; + op->args[0] =3D op->args[1]; + op->args[1] =3D op->args[2]; + op->args[2] =3D op->args[3]; } else { goto do_not_remove; } @@ -1820,7 +1819,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) implies side effects */ if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs !=3D 0) { for (i =3D 0; i < nb_oargs; i++) { - if (temp_state[args[i]] !=3D TS_DEAD) { + if (temp_state[op->args[i]] !=3D TS_DEAD) { goto do_not_remove; } } @@ -1830,7 +1829,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) do_not_remove: /* output args are dead */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (temp_state[arg] & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } @@ -1852,14 +1851,14 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) =20 /* record arguments that die in this opcode */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (temp_state[arg] & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } } /* input arguments are live for preceding opcodes */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - temp_state[args[i]] &=3D ~TS_DEAD; + temp_state[op->args[i]] &=3D ~TS_DEAD; } } break; @@ -1894,7 +1893,6 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp *op =3D &s->gen_op_buf[oi]; - TCGArg *args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; @@ -1906,7 +1904,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) if (opc =3D=3D INDEX_op_call) { nb_oargs =3D op->callo; nb_iargs =3D op->calli; - call_flags =3D args[nb_oargs + nb_iargs + 1]; + call_flags =3D op->args[nb_oargs + nb_iargs + 1]; } else { nb_iargs =3D def->nb_iargs; nb_oargs =3D def->nb_oargs; @@ -1927,7 +1925,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) =20 /* Make sure that input arguments are available. */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; /* Note this unsigned test catches TCG_CALL_ARG_DUMMY too. */ if (arg < nb_globals) { dir =3D dir_temps[arg]; @@ -1937,11 +1935,10 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) ? INDEX_op_ld_i32 : INDEX_op_ld_i64); TCGOp *lop =3D tcg_op_insert_before(s, op, lopc, 3); - TCGArg *largs =3D lop->args; =20 - largs[0] =3D dir; - largs[1] =3D temp_idx(s, its->mem_base); - largs[2] =3D its->mem_offset; + lop->args[0] =3D dir; + lop->args[1] =3D temp_idx(s, its->mem_base); + lop->args[2] =3D its->mem_offset; =20 /* Loaded, but synced with memory. */ temp_state[arg] =3D TS_MEM; @@ -1953,11 +1950,11 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) No action is required except keeping temp_state up to date so that we reload when needed. */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (arg < nb_globals) { dir =3D dir_temps[arg]; if (dir !=3D 0) { - args[i] =3D dir; + op->args[i] =3D dir; changes =3D true; if (IS_DEAD_ARG(i)) { temp_state[arg] =3D TS_DEAD; @@ -1988,7 +1985,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) =20 /* Outputs become available. */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; if (arg >=3D nb_globals) { continue; } @@ -1996,7 +1993,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) if (dir =3D=3D 0) { continue; } - args[i] =3D dir; + op->args[i] =3D dir; changes =3D true; =20 /* The output is now live and modified. */ @@ -2009,11 +2006,10 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) ? INDEX_op_st_i32 : INDEX_op_st_i64); TCGOp *sop =3D tcg_op_insert_after(s, op, sopc, 3); - TCGArg *sargs =3D sop->args; =20 - sargs[0] =3D dir; - sargs[1] =3D temp_idx(s, its->mem_base); - sargs[2] =3D its->mem_offset; + sop->args[0] =3D dir; + sop->args[1] =3D temp_idx(s, its->mem_base); + sop->args[2] =3D its->mem_offset; =20 temp_state[arg] =3D TS_MEM; } @@ -2841,7 +2837,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) num_insns =3D -1; for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp * const op =3D &s->gen_op_buf[oi]; - TCGArg * const args =3D op->args; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; @@ -2854,11 +2849,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) switch (opc) { case INDEX_op_mov_i32: case INDEX_op_mov_i64: - tcg_reg_alloc_mov(s, def, args, arg_life); + tcg_reg_alloc_mov(s, def, op->args, arg_life); break; case INDEX_op_movi_i32: case INDEX_op_movi_i64: - tcg_reg_alloc_movi(s, args, arg_life); + tcg_reg_alloc_movi(s, op->args, arg_life); break; case INDEX_op_insn_start: if (num_insns >=3D 0) { @@ -2868,22 +2863,22 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { target_ulong a; #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - a =3D ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2]; + a =3D deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + = 1]); #else - a =3D args[i]; + a =3D op->args[i]; #endif s->gen_insn_data[num_insns][i] =3D a; } break; case INDEX_op_discard: - temp_dead(s, &s->temps[args[0]]); + temp_dead(s, &s->temps[op->args[0]]); break; case INDEX_op_set_label: tcg_reg_alloc_bb_end(s, s->reserved_regs); - tcg_out_label(s, arg_label(args[0]), s->code_ptr); + tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); break; case INDEX_op_call: - tcg_reg_alloc_call(s, op->callo, op->calli, args, arg_life); + tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life= ); break; default: /* Sanity check that we've not introduced any unhandled opcode= s. */ @@ -2891,7 +2886,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) /* Note: in order to speed up the code, it would be much faster to have specialized register allocator functions for some common argument patterns */ - tcg_reg_alloc_op(s, def, opc, args, arg_life); + tcg_reg_alloc_op(s, def, opc, op->args, arg_life); break; } #ifdef CONFIG_DEBUG_TCG --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175050594832.286123722052; Mon, 16 Oct 2017 10:30:50 -0700 (PDT) Received: from localhost ([::1]:34313 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Du-0005nD-NN for importer@patchew.org; Mon, 16 Oct 2017 13:30:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499h-0001ss-KN for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499g-0003Gl-46 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:21 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:45355) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499f-0003GA-Rk for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:20 -0400 Received: by mail-pf0-x22f.google.com with SMTP id d28so16306527pfe.2 for ; Mon, 16 Oct 2017 10:26:19 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH v6 04/50] tcg: Propagate TCGOp down to allocators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.c | 78 ++++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 4f56077f64..147b8904d8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2334,25 +2334,24 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TC= GTemp *ots, } } =20 -static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args, - TCGLifeData arg_life) +static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) { - TCGTemp *ots =3D &s->temps[args[0]]; - tcg_target_ulong val =3D args[1]; + TCGTemp *ots =3D &s->temps[op->args[0]]; + tcg_target_ulong val =3D op->args[1]; =20 - tcg_reg_alloc_do_movi(s, ots, val, arg_life); + tcg_reg_alloc_do_movi(s, ots, val, op->life); } =20 -static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, - const TCGArg *args, TCGLifeData arg_life) +static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { + const TCGLifeData arg_life =3D op->life; TCGRegSet allocated_regs; TCGTemp *ts, *ots; TCGType otype, itype; =20 allocated_regs =3D s->reserved_regs; - ots =3D &s->temps[args[0]]; - ts =3D &s->temps[args[1]]; + ots =3D &s->temps[op->args[0]]; + ts =3D &s->temps[op->args[1]]; =20 /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; @@ -2382,7 +2381,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOpDef *def, liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); if (!ots->mem_allocated) { - temp_allocate_frame(s, args[0]); + temp_allocate_frame(s, op->args[0]); } tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); if (IS_DEAD_ARG(1)) { @@ -2416,10 +2415,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOpDef *def, } } =20 -static void tcg_reg_alloc_op(TCGContext *s,=20 - const TCGOpDef *def, TCGOpcode opc, - const TCGArg *args, TCGLifeData arg_life) +static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) { + const TCGLifeData arg_life =3D op->life; + const TCGOpDef * const def =3D &tcg_op_defs[op->opc]; TCGRegSet i_allocated_regs; TCGRegSet o_allocated_regs; int i, k, nb_iargs, nb_oargs; @@ -2430,21 +2429,24 @@ static void tcg_reg_alloc_op(TCGContext *s, TCGArg new_args[TCG_MAX_OP_ARGS]; int const_args[TCG_MAX_OP_ARGS]; =20 + /* Sanity check that we've not introduced any unhandled opcodes. */ + tcg_debug_assert(!(def->flags & TCG_OPF_NOT_PRESENT)); + nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; =20 /* copy constants */ memcpy(new_args + nb_oargs + nb_iargs,=20 - args + nb_oargs + nb_iargs,=20 + op->args + nb_oargs + nb_iargs, sizeof(TCGArg) * def->nb_cargs); =20 i_allocated_regs =3D s->reserved_regs; o_allocated_regs =3D s->reserved_regs; =20 /* satisfy input constraints */=20 - for(k =3D 0; k < nb_iargs; k++) { + for (k =3D 0; k < nb_iargs; k++) { i =3D def->sorted_args[nb_oargs + k]; - arg =3D args[i]; + arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D &s->temps[arg]; =20 @@ -2462,7 +2464,7 @@ static void tcg_reg_alloc_op(TCGContext *s, if (ts->fixed_reg) { /* if fixed register, we must allocate a new register if the alias is not the same register */ - if (arg !=3D args[arg_ct->alias_index]) + if (arg !=3D op->args[arg_ct->alias_index]) goto allocate_in_reg; } else { /* if the input is aliased to an output and if it is @@ -2503,7 +2505,7 @@ static void tcg_reg_alloc_op(TCGContext *s, /* mark dead temporaries and free the associated registers */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[args[i]]); + temp_dead(s, &s->temps[op->args[i]]); } } =20 @@ -2527,7 +2529,7 @@ static void tcg_reg_alloc_op(TCGContext *s, /* satisfy the output constraints */ for(k =3D 0; k < nb_oargs; k++) { i =3D def->sorted_args[k]; - arg =3D args[i]; + arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D &s->temps[arg]; if ((arg_ct->ct & TCG_CT_ALIAS) @@ -2566,11 +2568,11 @@ static void tcg_reg_alloc_op(TCGContext *s, } =20 /* emit instruction */ - tcg_out_op(s, opc, new_args, const_args); + tcg_out_op(s, op->opc, new_args, const_args); =20 /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { - ts =3D &s->temps[args[i]]; + ts =3D &s->temps[op->args[i]]; reg =3D new_args[i]; if (ts->fixed_reg && ts->reg !=3D reg) { tcg_out_mov(s, ts->type, ts->reg, reg); @@ -2589,9 +2591,11 @@ static void tcg_reg_alloc_op(TCGContext *s, #define STACK_DIR(x) (x) #endif =20 -static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, - const TCGArg * const args, TCGLifeData arg_= life) +static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { + const int nb_oargs =3D op->callo; + const int nb_iargs =3D op->calli; + const TCGLifeData arg_life =3D op->life; int flags, nb_regs, i; TCGReg reg; TCGArg arg; @@ -2602,8 +2606,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, int allocate_args; TCGRegSet allocated_regs; =20 - func_addr =3D (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs]; - flags =3D args[nb_oargs + nb_iargs + 1]; + func_addr =3D (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; + flags =3D op->args[nb_oargs + nb_iargs + 1]; =20 nb_regs =3D ARRAY_SIZE(tcg_target_call_iarg_regs); if (nb_regs > nb_iargs) { @@ -2622,8 +2626,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 stack_offset =3D TCG_TARGET_CALL_STACK_OFFSET; - for(i =3D nb_regs; i < nb_iargs; i++) { - arg =3D args[nb_oargs + i]; + for (i =3D nb_regs; i < nb_iargs; i++) { + arg =3D op->args[nb_oargs + i]; #ifdef TCG_TARGET_STACK_GROWSUP stack_offset -=3D sizeof(tcg_target_long); #endif @@ -2640,8 +2644,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 /* assign input registers */ allocated_regs =3D s->reserved_regs; - for(i =3D 0; i < nb_regs; i++) { - arg =3D args[nb_oargs + i]; + for (i =3D 0; i < nb_regs; i++) { + arg =3D op->args[nb_oargs + i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { ts =3D &s->temps[arg]; reg =3D tcg_target_call_iarg_regs[i]; @@ -2663,9 +2667,9 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 /* mark dead temporaries and free the associated registers */ - for(i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { + for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[args[i]]); + temp_dead(s, &s->temps[op->args[i]]); } } =20 @@ -2690,7 +2694,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 /* assign output registers and emit moves if needed */ for(i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; ts =3D &s->temps[arg]; reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); @@ -2838,8 +2842,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp * const op =3D &s->gen_op_buf[oi]; TCGOpcode opc =3D op->opc; - const TCGOpDef *def =3D &tcg_op_defs[opc]; - TCGLifeData arg_life =3D op->life; =20 oi_next =3D op->next; #ifdef CONFIG_PROFILER @@ -2849,11 +2851,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) switch (opc) { case INDEX_op_mov_i32: case INDEX_op_mov_i64: - tcg_reg_alloc_mov(s, def, op->args, arg_life); + tcg_reg_alloc_mov(s, op); break; case INDEX_op_movi_i32: case INDEX_op_movi_i64: - tcg_reg_alloc_movi(s, op->args, arg_life); + tcg_reg_alloc_movi(s, op); break; case INDEX_op_insn_start: if (num_insns >=3D 0) { @@ -2878,7 +2880,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); break; case INDEX_op_call: - tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life= ); + tcg_reg_alloc_call(s, op); break; default: /* Sanity check that we've not introduced any unhandled opcode= s. */ @@ -2886,7 +2888,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) /* Note: in order to speed up the code, it would be much faster to have specialized register allocator functions for some common argument patterns */ - tcg_reg_alloc_op(s, def, opc, op->args, arg_life); + tcg_reg_alloc_op(s, op); break; } #ifdef CONFIG_DEBUG_TCG --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v6 05/50] tcg: Introduce arg_temp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 5 +++++ tcg/optimize.c | 4 ++-- tcg/tcg.c | 51 +++++++++++++++++++++++++-------------------------- 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 2cefd9f125..f06187fd8e 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -725,6 +725,11 @@ struct TCGContext { extern TCGContext tcg_ctx; extern bool parallel_cpus; =20 +static inline TCGTemp *arg_temp(TCGArg a) +{ + return &tcg_ctx.temps[a]; +} + static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { tcg_ctx.gen_op_buf[op_idx].args[arg] =3D v; diff --git a/tcg/optimize.c b/tcg/optimize.c index 1a1c6fb90c..d8c3a7ed56 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -133,7 +133,7 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg te= mp) } =20 /* If it is a temp, search for a temp local. */ - if (!s->temps[temp].temp_local) { + if (!arg_temp(temp)->temp_local) { for (i =3D temps[temp].next_copy ; i !=3D temp ; i =3D temps[i].ne= xt_copy) { if (s->temps[i].temp_local) { return i; @@ -207,7 +207,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T= CGArg dst, TCGArg src) } temps[dst].mask =3D mask; =20 - if (s->temps[src].type =3D=3D s->temps[dst].type) { + if (arg_temp(src)->type =3D=3D arg_temp(dst)->type) { temps[dst].next_copy =3D temps[src].next_copy; temps[dst].prev_copy =3D src; temps[temps[dst].next_copy].prev_copy =3D dst; diff --git a/tcg/tcg.c b/tcg/tcg.c index 147b8904d8..2704aa8a4d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1200,11 +1200,10 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, cha= r *buf, int buf_size, return buf; } =20 -static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, - int buf_size, int idx) +static char *tcg_get_arg_str(TCGContext *s, char *buf, + int buf_size, TCGArg arg) { - tcg_debug_assert(idx >=3D 0 && idx < s->nb_temps); - return tcg_get_arg_str_ptr(s, buf, buf_size, &s->temps[idx]); + return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); } =20 /* Find helper name. */ @@ -1307,14 +1306,14 @@ void tcg_dump_ops(TCGContext *s) tcg_find_helper(s, op->args[nb_oargs + nb_iarg= s]), op->args[nb_oargs + nb_iargs + 1], nb_oargs); for (i =3D 0; i < nb_oargs; i++) { - col +=3D qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeo= f(buf), - op->args[i])); + col +=3D qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(bu= f), + op->args[i])); } for (i =3D 0; i < nb_iargs; i++) { TCGArg arg =3D op->args[nb_oargs + i]; const char *t =3D ""; if (arg !=3D TCG_CALL_DUMMY_ARG) { - t =3D tcg_get_arg_str_idx(s, buf, sizeof(buf), arg); + t =3D tcg_get_arg_str(s, buf, sizeof(buf), arg); } col +=3D qemu_log(",%s", t); } @@ -1330,15 +1329,15 @@ void tcg_dump_ops(TCGContext *s) if (k !=3D 0) { col +=3D qemu_log(","); } - col +=3D qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof= (buf), - op->args[k++])); + col +=3D qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf= ), + op->args[k++])); } for (i =3D 0; i < nb_iargs; i++) { if (k !=3D 0) { col +=3D qemu_log(","); } - col +=3D qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof= (buf), - op->args[k++])); + col +=3D qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf= ), + op->args[k++])); } switch (c) { case INDEX_op_brcond_i32: @@ -1930,7 +1929,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) if (arg < nb_globals) { dir =3D dir_temps[arg]; if (dir !=3D 0 && temp_state[arg] =3D=3D TS_DEAD) { - TCGTemp *its =3D &s->temps[arg]; + TCGTemp *its =3D arg_temp(arg); TCGOpcode lopc =3D (its->type =3D=3D TCG_TYPE_I32 ? INDEX_op_ld_i32 : INDEX_op_ld_i64); @@ -2001,7 +2000,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) =20 /* Sync outputs upon their last write. */ if (NEED_SYNC_ARG(i)) { - TCGTemp *its =3D &s->temps[arg]; + TCGTemp *its =3D arg_temp(arg); TCGOpcode sopc =3D (its->type =3D=3D TCG_TYPE_I32 ? INDEX_op_st_i32 : INDEX_op_st_i64); @@ -2032,7 +2031,7 @@ static void dump_regs(TCGContext *s) =20 for(i =3D 0; i < s->nb_temps; i++) { ts =3D &s->temps[i]; - printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i)); + printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); switch(ts->val_type) { case TEMP_VAL_REG: printf("%s", tcg_target_reg_names[ts->reg]); @@ -2336,7 +2335,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGT= emp *ots, =20 static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) { - TCGTemp *ots =3D &s->temps[op->args[0]]; + TCGTemp *ots =3D arg_temp(op->args[0]); tcg_target_ulong val =3D op->args[1]; =20 tcg_reg_alloc_do_movi(s, ots, val, op->life); @@ -2350,8 +2349,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) TCGType otype, itype; =20 allocated_regs =3D s->reserved_regs; - ots =3D &s->temps[op->args[0]]; - ts =3D &s->temps[op->args[1]]; + ots =3D arg_temp(op->args[0]); + ts =3D arg_temp(op->args[1]); =20 /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; @@ -2448,7 +2447,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) i =3D def->sorted_args[nb_oargs + k]; arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; - ts =3D &s->temps[arg]; + ts =3D arg_temp(arg); =20 if (ts->val_type =3D=3D TEMP_VAL_CONST && tcg_target_const_match(ts->val, ts->type, arg_ct)) { @@ -2505,7 +2504,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) /* mark dead temporaries and free the associated registers */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[op->args[i]]); + temp_dead(s, arg_temp(op->args[i])); } } =20 @@ -2531,7 +2530,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) i =3D def->sorted_args[k]; arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; - ts =3D &s->temps[arg]; + ts =3D arg_temp(arg); if ((arg_ct->ct & TCG_CT_ALIAS) && !const_args[arg_ct->alias_index]) { reg =3D new_args[arg_ct->alias_index]; @@ -2572,7 +2571,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) =20 /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { - ts =3D &s->temps[op->args[i]]; + ts =3D arg_temp(op->args[i]); reg =3D new_args[i]; if (ts->fixed_reg && ts->reg !=3D reg) { tcg_out_mov(s, ts->type, ts->reg, reg); @@ -2632,7 +2631,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) stack_offset -=3D sizeof(tcg_target_long); #endif if (arg !=3D TCG_CALL_DUMMY_ARG) { - ts =3D &s->temps[arg]; + ts =3D arg_temp(arg); temp_load(s, ts, tcg_target_available_regs[ts->type], s->reserved_regs); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_off= set); @@ -2647,7 +2646,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) for (i =3D 0; i < nb_regs; i++) { arg =3D op->args[nb_oargs + i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { - ts =3D &s->temps[arg]; + ts =3D arg_temp(arg); reg =3D tcg_target_call_iarg_regs[i]; tcg_reg_free(s, reg, allocated_regs); =20 @@ -2669,7 +2668,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) /* mark dead temporaries and free the associated registers */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[op->args[i]]); + temp_dead(s, arg_temp(op->args[i])); } } =20 @@ -2695,7 +2694,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) /* assign output registers and emit moves if needed */ for(i =3D 0; i < nb_oargs; i++) { arg =3D op->args[i]; - ts =3D &s->temps[arg]; + ts =3D arg_temp(arg); reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); =20 @@ -2873,7 +2872,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } break; case INDEX_op_discard: - temp_dead(s, &s->temps[op->args[0]]); + temp_dead(s, arg_temp(op->args[0])); break; case INDEX_op_set_label: tcg_reg_alloc_bb_end(s, s->reserved_regs); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v6 06/50] tcg: Add temp_global bit to TCGTemp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This avoids needing to test the index of a temp against nb_globals. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 12 ++++++++---- tcg/optimize.c | 15 ++++++++------- tcg/tcg.c | 11 ++++++++--- 3 files changed, 24 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index f06187fd8e..fc4d1ed58b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -579,10 +579,14 @@ typedef struct TCGTemp { unsigned int indirect_base:1; unsigned int mem_coherent:1; unsigned int mem_allocated:1; - unsigned int temp_local:1; /* If true, the temp is saved across - basic blocks. Otherwise, it is not - preserved across basic blocks. */ - unsigned int temp_allocated:1; /* never used for code gen */ + /* If true, the temp is saved across both basic blocks and + translation blocks. */ + unsigned int temp_global:1; + /* If true, the temp is saved across basic blocks but dead + at the end of translation blocks. If false, the temp is + dead at the end of basic blocks. */ + unsigned int temp_local:1; + unsigned int temp_allocated:1; =20 tcg_target_long val; struct TCGTemp *mem_base; diff --git a/tcg/optimize.c b/tcg/optimize.c index d8c3a7ed56..55f9e83ce8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -116,25 +116,26 @@ static TCGOpcode op_to_movi(TCGOpcode op) } } =20 -static TCGArg find_better_copy(TCGContext *s, TCGArg temp) +static TCGArg find_better_copy(TCGContext *s, TCGArg arg) { + TCGTemp *ts =3D arg_temp(arg); TCGArg i; =20 /* If this is already a global, we can't do better. */ - if (temp < s->nb_globals) { - return temp; + if (ts->temp_global) { + return arg; } =20 /* Search for a global first. */ - for (i =3D temps[temp].next_copy ; i !=3D temp ; i =3D temps[i].next_c= opy) { + for (i =3D temps[arg].next_copy ; i !=3D arg; i =3D temps[i].next_copy= ) { if (i < s->nb_globals) { return i; } } =20 /* If it is a temp, search for a temp local. */ - if (!arg_temp(temp)->temp_local) { - for (i =3D temps[temp].next_copy ; i !=3D temp ; i =3D temps[i].ne= xt_copy) { + if (!ts->temp_local) { + for (i =3D temps[arg].next_copy ; i !=3D arg; i =3D temps[i].next_= copy) { if (s->temps[i].temp_local) { return i; } @@ -142,7 +143,7 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg te= mp) } =20 /* Failure to find a better representation, return the same temp. */ - return temp; + return arg; } =20 static bool temps_are_copies(TCGArg arg1, TCGArg arg2) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2704aa8a4d..915e041bea 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -489,9 +489,14 @@ static inline TCGTemp *tcg_temp_alloc(TCGContext *s) =20 static inline TCGTemp *tcg_global_alloc(TCGContext *s) { + TCGTemp *ts; + tcg_debug_assert(s->nb_globals =3D=3D s->nb_temps); s->nb_globals++; - return tcg_temp_alloc(s); + ts =3D tcg_temp_alloc(s); + ts->temp_global =3D 1; + + return ts; } =20 static int tcg_global_reg_new_internal(TCGContext *s, TCGType type, @@ -1190,7 +1195,7 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char = *buf, int buf_size, { int idx =3D temp_idx(s, ts); =20 - if (idx < s->nb_globals) { + if (ts->temp_global) { pstrcpy(buf, buf_size, ts->name); } else if (ts->temp_local) { snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); @@ -2128,7 +2133,7 @@ static void temp_free_or_dead(TCGContext *s, TCGTemp = *ts, int free_or_dead) } ts->val_type =3D (free_or_dead < 0 || ts->temp_local - || temp_idx(s, ts) < s->nb_globals + || ts->temp_global ? TEMP_VAL_MEM : TEMP_VAL_DEAD); } =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15081756262971004.1132414369055; Mon, 16 Oct 2017 10:40:26 -0700 (PDT) Received: from localhost ([::1]:34347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49NF-0005Ca-Hq for importer@patchew.org; Mon, 16 Oct 2017 13:40:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499n-0001yQ-EP for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499k-0003Kf-9t for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:27 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:51119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499k-0003K5-3u for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:24 -0400 Received: by mail-pg0-x230.google.com with SMTP id y7so7341944pgb.7 for ; Mon, 16 Oct 2017 10:26:24 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v6 07/50] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index fc4d1ed58b..5fcdec1fc5 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -731,7 +731,7 @@ extern bool parallel_cpus; =20 static inline TCGTemp *arg_temp(TCGArg a) { - return &tcg_ctx.temps[a]; + return a =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; } =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175222241209.22921584329845; Mon, 16 Oct 2017 10:33:42 -0700 (PDT) Received: from localhost ([::1]:34322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Gc-0008Ap-Dc for importer@patchew.org; Mon, 16 Oct 2017 13:33:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499n-0001yR-Eb for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499l-0003MN-Nn for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:27 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:55270) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499l-0003LY-I2 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:25 -0400 Received: by mail-pg0-x22c.google.com with SMTP id l24so7292738pgu.11 for ; Mon, 16 Oct 2017 10:26:25 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v6 08/50] tcg: Introduce temp_arg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 7 +++++++ tcg/tcg.c | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 5fcdec1fc5..1e456d8e5a 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -729,6 +729,13 @@ struct TCGContext { extern TCGContext tcg_ctx; extern bool parallel_cpus; =20 +static inline TCGArg temp_arg(TCGTemp *ts) +{ + ptrdiff_t n =3D ts - tcg_ctx.temps; + tcg_debug_assert(n >=3D 0 && n < tcg_ctx.nb_temps); + return n; +} + static inline TCGTemp *arg_temp(TCGArg a) { return a =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; diff --git a/tcg/tcg.c b/tcg/tcg.c index 915e041bea..31279ab3bb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1941,7 +1941,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) TCGOp *lop =3D tcg_op_insert_before(s, op, lopc, 3); =20 lop->args[0] =3D dir; - lop->args[1] =3D temp_idx(s, its->mem_base); + lop->args[1] =3D temp_arg(its->mem_base); lop->args[2] =3D its->mem_offset; =20 /* Loaded, but synced with memory. */ @@ -2012,7 +2012,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) TCGOp *sop =3D tcg_op_insert_after(s, op, sopc, 3); =20 sop->args[0] =3D dir; - sop->args[1] =3D temp_idx(s, its->mem_base); + sop->args[1] =3D temp_arg(its->mem_base); sop->args[2] =3D its->mem_offset; =20 temp_state[arg] =3D TS_MEM; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15081750686770.2890951992015971; Mon, 16 Oct 2017 10:31:08 -0700 (PDT) Received: from localhost ([::1]:34314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49EF-00065R-Nv for importer@patchew.org; Mon, 16 Oct 2017 13:31:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499q-00021f-5O for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499o-0003ON-0j for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:30 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:46994) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499n-0003Ne-NT for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:27 -0400 Received: by mail-pg0-x22a.google.com with SMTP id k7so7341995pga.3 for ; Mon, 16 Oct 2017 10:26:27 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v6 09/50] tcg: Use per-temp state data in liveness X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This avoids having to allocate external memory for each temporary. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 6 ++ tcg/tcg.c | 225 ++++++++++++++++++++++++++++++++--------------------------= ---- 2 files changed, 122 insertions(+), 109 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 1e456d8e5a..4352c0ee8c 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -592,6 +592,12 @@ typedef struct TCGTemp { struct TCGTemp *mem_base; intptr_t mem_offset; const char *name; + + /* Pass-specific information that can be stored for a temporary. + One word worth of integer data, and one pointer to data + allocated separately. */ + uintptr_t state; + void *state_ptr; } TCGTemp; =20 typedef struct TCGContext TCGContext; diff --git a/tcg/tcg.c b/tcg/tcg.c index 31279ab3bb..719db9f2b6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1622,42 +1622,54 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *ol= d_op, =20 /* liveness analysis: end of function: all temps are dead, and globals should be in memory. */ -static inline void tcg_la_func_end(TCGContext *s, uint8_t *temp_state) +static void tcg_la_func_end(TCGContext *s) { - memset(temp_state, TS_DEAD | TS_MEM, s->nb_globals); - memset(temp_state + s->nb_globals, TS_DEAD, s->nb_temps - s->nb_global= s); + int ng =3D s->nb_globals; + int nt =3D s->nb_temps; + int i; + + for (i =3D 0; i < ng; ++i) { + s->temps[i].state =3D TS_DEAD | TS_MEM; + } + for (i =3D ng; i < nt; ++i) { + s->temps[i].state =3D TS_DEAD; + } } =20 /* liveness analysis: end of basic block: all temps are dead, globals and local temps should be in memory. */ -static inline void tcg_la_bb_end(TCGContext *s, uint8_t *temp_state) +static void tcg_la_bb_end(TCGContext *s) { - int i, n; + int ng =3D s->nb_globals; + int nt =3D s->nb_temps; + int i; =20 - tcg_la_func_end(s, temp_state); - for (i =3D s->nb_globals, n =3D s->nb_temps; i < n; i++) { - if (s->temps[i].temp_local) { - temp_state[i] |=3D TS_MEM; - } + for (i =3D 0; i < ng; ++i) { + s->temps[i].state =3D TS_DEAD | TS_MEM; + } + for (i =3D ng; i < nt; ++i) { + s->temps[i].state =3D (s->temps[i].temp_local + ? TS_DEAD | TS_MEM + : TS_DEAD); } } =20 /* Liveness analysis : update the opc_arg_life array to tell if a given input arguments is dead. Instructions updating dead temporaries are removed. */ -static void liveness_pass_1(TCGContext *s, uint8_t *temp_state) +static void liveness_pass_1(TCGContext *s) { int nb_globals =3D s->nb_globals; int oi, oi_prev; =20 - tcg_la_func_end(s, temp_state); + tcg_la_func_end(s); =20 for (oi =3D s->gen_op_buf[0].prev; oi !=3D 0; oi =3D oi_prev) { int i, nb_iargs, nb_oargs; TCGOpcode opc_new, opc_new2; bool have_opc_new2; TCGLifeData arg_life =3D 0; - TCGArg arg; + TCGTemp *arg_ts; =20 TCGOp * const op =3D &s->gen_op_buf[oi]; TCGOpcode opc =3D op->opc; @@ -1677,8 +1689,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) /* pure functions can be removed if their result is unused= */ if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { for (i =3D 0; i < nb_oargs; i++) { - arg =3D op->args[i]; - if (temp_state[arg] !=3D TS_DEAD) { + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts->state !=3D TS_DEAD) { goto do_not_remove_call; } } @@ -1688,41 +1700,41 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) =20 /* output args are dead */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D op->args[i]; - if (temp_state[arg] & TS_DEAD) { + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts->state & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } - if (temp_state[arg] & TS_MEM) { + if (arg_ts->state & TS_MEM) { arg_life |=3D SYNC_ARG << i; } - temp_state[arg] =3D TS_DEAD; + arg_ts->state =3D TS_DEAD; } =20 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | TCG_CALL_NO_READ_GLOBALS))) { /* globals should go back to memory */ - memset(temp_state, TS_DEAD | TS_MEM, nb_globals); + for (i =3D 0; i < nb_globals; i++) { + s->temps[i].state =3D TS_DEAD | TS_MEM; + } } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { /* globals should be synced to memory */ for (i =3D 0; i < nb_globals; i++) { - temp_state[i] |=3D TS_MEM; + s->temps[i].state |=3D TS_MEM; } } =20 /* record arguments that die in this helper */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D op->args[i]; - if (arg !=3D TCG_CALL_DUMMY_ARG) { - if (temp_state[arg] & TS_DEAD) { - arg_life |=3D DEAD_ARG << i; - } + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts && arg_ts->state & TS_DEAD) { + arg_life |=3D DEAD_ARG << i; } } /* input arguments are live for preceding opcodes */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D op->args[i]; - if (arg !=3D TCG_CALL_DUMMY_ARG) { - temp_state[arg] &=3D ~TS_DEAD; + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts) { + arg_ts->state &=3D ~TS_DEAD; } } } @@ -1732,7 +1744,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) break; case INDEX_op_discard: /* mark the temporary as dead */ - temp_state[op->args[0]] =3D TS_DEAD; + arg_temp(op->args[0])->state =3D TS_DEAD; break; =20 case INDEX_op_add2_i32: @@ -1753,8 +1765,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) the low part. The result can be optimized to a simple add or sub. This happens often for x86_64 guest when the cpu mode is set to 32 bit. */ - if (temp_state[op->args[1]] =3D=3D TS_DEAD) { - if (temp_state[op->args[0]] =3D=3D TS_DEAD) { + if (arg_temp(op->args[1])->state =3D=3D TS_DEAD) { + if (arg_temp(op->args[0])->state =3D=3D TS_DEAD) { goto do_remove; } /* Replace the opcode and adjust the args in place, @@ -1791,8 +1803,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) do_mul2: nb_iargs =3D 2; nb_oargs =3D 2; - if (temp_state[op->args[1]] =3D=3D TS_DEAD) { - if (temp_state[op->args[0]] =3D=3D TS_DEAD) { + if (arg_temp(op->args[1])->state =3D=3D TS_DEAD) { + if (arg_temp(op->args[0])->state =3D=3D TS_DEAD) { /* Both parts of the operation are dead. */ goto do_remove; } @@ -1800,7 +1812,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) op->opc =3D opc =3D opc_new; op->args[1] =3D op->args[2]; op->args[2] =3D op->args[3]; - } else if (temp_state[op->args[0]] =3D=3D TS_DEAD && have_opc_= new2) { + } else if (arg_temp(op->args[0])->state =3D=3D TS_DEAD && have= _opc_new2) { /* The low part of the operation is dead; generate the hig= h. */ op->opc =3D opc =3D opc_new2; op->args[0] =3D op->args[1]; @@ -1823,7 +1835,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *t= emp_state) implies side effects */ if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs !=3D 0) { for (i =3D 0; i < nb_oargs; i++) { - if (temp_state[op->args[i]] !=3D TS_DEAD) { + if (arg_temp(op->args[i])->state !=3D TS_DEAD) { goto do_not_remove; } } @@ -1833,36 +1845,36 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) do_not_remove: /* output args are dead */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D op->args[i]; - if (temp_state[arg] & TS_DEAD) { + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts->state & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } - if (temp_state[arg] & TS_MEM) { + if (arg_ts->state & TS_MEM) { arg_life |=3D SYNC_ARG << i; } - temp_state[arg] =3D TS_DEAD; + arg_ts->state =3D TS_DEAD; } =20 /* if end of basic block, update */ if (def->flags & TCG_OPF_BB_END) { - tcg_la_bb_end(s, temp_state); + tcg_la_bb_end(s); } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { /* globals should be synced to memory */ for (i =3D 0; i < nb_globals; i++) { - temp_state[i] |=3D TS_MEM; + s->temps[i].state |=3D TS_MEM; } } =20 /* record arguments that die in this opcode */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - arg =3D op->args[i]; - if (temp_state[arg] & TS_DEAD) { + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts->state & TS_DEAD) { arg_life |=3D DEAD_ARG << i; } } /* input arguments are live for preceding opcodes */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - temp_state[op->args[i]] &=3D ~TS_DEAD; + arg_temp(op->args[i])->state &=3D ~TS_DEAD; } } break; @@ -1872,16 +1884,12 @@ static void liveness_pass_1(TCGContext *s, uint8_t = *temp_state) } =20 /* Liveness analysis: Convert indirect regs to direct temporaries. */ -static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state) +static bool liveness_pass_2(TCGContext *s) { int nb_globals =3D s->nb_globals; - int16_t *dir_temps; - int i, oi, oi_next; + int nb_temps, i, oi, oi_next; bool changes =3D false; =20 - dir_temps =3D tcg_malloc(nb_globals * sizeof(int16_t)); - memset(dir_temps, 0, nb_globals * sizeof(int16_t)); - /* Create a temporary for each indirect global. */ for (i =3D 0; i < nb_globals; ++i) { TCGTemp *its =3D &s->temps[i]; @@ -1889,11 +1897,18 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) TCGTemp *dts =3D tcg_temp_alloc(s); dts->type =3D its->type; dts->base_type =3D its->base_type; - dir_temps[i] =3D temp_idx(s, dts); + its->state_ptr =3D dts; + } else { + its->state_ptr =3D NULL; } + /* All globals begin dead. */ + its->state =3D TS_DEAD; + } + for (nb_temps =3D s->nb_temps; i < nb_temps; ++i) { + TCGTemp *its =3D &s->temps[i]; + its->state_ptr =3D NULL; + its->state =3D TS_DEAD; } - - memset(temp_state, TS_DEAD, nb_globals); =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp *op =3D &s->gen_op_buf[oi]; @@ -1901,7 +1916,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *t= emp_state) const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; int nb_iargs, nb_oargs, call_flags; - TCGArg arg, dir; + TCGTemp *arg_ts, *dir_ts; =20 oi_next =3D op->next; =20 @@ -1929,23 +1944,21 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) =20 /* Make sure that input arguments are available. */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D op->args[i]; - /* Note this unsigned test catches TCG_CALL_ARG_DUMMY too. */ - if (arg < nb_globals) { - dir =3D dir_temps[arg]; - if (dir !=3D 0 && temp_state[arg] =3D=3D TS_DEAD) { - TCGTemp *its =3D arg_temp(arg); - TCGOpcode lopc =3D (its->type =3D=3D TCG_TYPE_I32 + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts) { + dir_ts =3D arg_ts->state_ptr; + if (dir_ts && arg_ts->state =3D=3D TS_DEAD) { + TCGOpcode lopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 ? INDEX_op_ld_i32 : INDEX_op_ld_i64); TCGOp *lop =3D tcg_op_insert_before(s, op, lopc, 3); =20 - lop->args[0] =3D dir; - lop->args[1] =3D temp_arg(its->mem_base); - lop->args[2] =3D its->mem_offset; + lop->args[0] =3D temp_arg(dir_ts); + lop->args[1] =3D temp_arg(arg_ts->mem_base); + lop->args[2] =3D arg_ts->mem_offset; =20 /* Loaded, but synced with memory. */ - temp_state[arg] =3D TS_MEM; + arg_ts->state =3D TS_MEM; } } } @@ -1954,14 +1967,14 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) No action is required except keeping temp_state up to date so that we reload when needed. */ for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg =3D op->args[i]; - if (arg < nb_globals) { - dir =3D dir_temps[arg]; - if (dir !=3D 0) { - op->args[i] =3D dir; + arg_ts =3D arg_temp(op->args[i]); + if (arg_ts) { + dir_ts =3D arg_ts->state_ptr; + if (dir_ts) { + op->args[i] =3D temp_arg(dir_ts); changes =3D true; if (IS_DEAD_ARG(i)) { - temp_state[arg] =3D TS_DEAD; + arg_ts->state =3D TS_DEAD; } } } @@ -1975,51 +1988,49 @@ static bool liveness_pass_2(TCGContext *s, uint8_t = *temp_state) for (i =3D 0; i < nb_globals; ++i) { /* Liveness should see that globals are synced back, that is, either TS_DEAD or TS_MEM. */ - tcg_debug_assert(dir_temps[i] =3D=3D 0 - || temp_state[i] !=3D 0); + arg_ts =3D &s->temps[i]; + tcg_debug_assert(arg_ts->state_ptr =3D=3D 0 + || arg_ts->state !=3D 0); } } else { for (i =3D 0; i < nb_globals; ++i) { /* Liveness should see that globals are saved back, that is, TS_DEAD, waiting to be reloaded. */ - tcg_debug_assert(dir_temps[i] =3D=3D 0 - || temp_state[i] =3D=3D TS_DEAD); + arg_ts =3D &s->temps[i]; + tcg_debug_assert(arg_ts->state_ptr =3D=3D 0 + || arg_ts->state =3D=3D TS_DEAD); } } =20 /* Outputs become available. */ for (i =3D 0; i < nb_oargs; i++) { - arg =3D op->args[i]; - if (arg >=3D nb_globals) { + arg_ts =3D arg_temp(op->args[i]); + dir_ts =3D arg_ts->state_ptr; + if (!dir_ts) { continue; } - dir =3D dir_temps[arg]; - if (dir =3D=3D 0) { - continue; - } - op->args[i] =3D dir; + op->args[i] =3D temp_arg(dir_ts); changes =3D true; =20 /* The output is now live and modified. */ - temp_state[arg] =3D 0; + arg_ts->state =3D 0; =20 /* Sync outputs upon their last write. */ if (NEED_SYNC_ARG(i)) { - TCGTemp *its =3D arg_temp(arg); - TCGOpcode sopc =3D (its->type =3D=3D TCG_TYPE_I32 + TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 ? INDEX_op_st_i32 : INDEX_op_st_i64); TCGOp *sop =3D tcg_op_insert_after(s, op, sopc, 3); =20 - sop->args[0] =3D dir; - sop->args[1] =3D temp_arg(its->mem_base); - sop->args[2] =3D its->mem_offset; + sop->args[0] =3D temp_arg(dir_ts); + sop->args[1] =3D temp_arg(arg_ts->mem_base); + sop->args[2] =3D arg_ts->mem_offset; =20 - temp_state[arg] =3D TS_MEM; + arg_ts->state =3D TS_MEM; } /* Drop outputs that are dead. */ if (IS_DEAD_ARG(i)) { - temp_state[arg] =3D TS_DEAD; + arg_ts->state =3D TS_DEAD; } } } @@ -2791,27 +2802,23 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) s->la_time -=3D profile_getclock(); #endif =20 - { - uint8_t *temp_state =3D tcg_malloc(s->nb_temps + s->nb_indirects); - - liveness_pass_1(s, temp_state); + liveness_pass_1(s); =20 - if (s->nb_indirects > 0) { + if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { - qemu_log_lock(); - qemu_log("OP before indirect lowering:\n"); - tcg_dump_ops(s); - qemu_log("\n"); - qemu_log_unlock(); - } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) + && qemu_log_in_addr_range(tb->pc))) { + qemu_log_lock(); + qemu_log("OP before indirect lowering:\n"); + tcg_dump_ops(s); + qemu_log("\n"); + qemu_log_unlock(); + } #endif - /* Replace indirect temps with direct temps. */ - if (liveness_pass_2(s, temp_state)) { - /* If changes were made, re-run liveness. */ - liveness_pass_1(s, temp_state); - } + /* Replace indirect temps with direct temps. */ + if (liveness_pass_2(s)) { + /* If changes were made, re-run liveness. */ + liveness_pass_1(s); } } =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150817579416425.572211614528783; Mon, 16 Oct 2017 10:43:14 -0700 (PDT) Received: from localhost ([::1]:34360 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Pw-0007Vg-Bs for importer@patchew.org; Mon, 16 Oct 2017 13:43:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499p-00020a-GA for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499o-0003Op-Gp for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:29 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:51119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499o-0003OF-BR for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:28 -0400 Received: by mail-pg0-x234.google.com with SMTP id y7so7342099pgb.7 for ; Mon, 16 Oct 2017 10:26:28 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=14UnMYMoZqmrJ9oz6osYwF58UTet1QjRnDjyBDt55ag=; b=As0pz48359ajQ6Ug9EXlJEMwQrr+/sBS2QWjxNai+8p5WVwOfF/3fhxDhd/KPcwzyt cWCxYnHDyAMA1I1wR8su2o/xtzhG4R8Czl3zkg0nSRbBH8v/Jj1AgL0kBSjehiIdz6us y8Imv7uxHkCYAxQuD+ZTCX1xHefxk52O13iMk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=14UnMYMoZqmrJ9oz6osYwF58UTet1QjRnDjyBDt55ag=; b=C+ufwKSvNESbtYGEZuDZ1xO1r5P2w0Ih2hgT19R+GMgkvKJNyJzEzcf9bl34RzhNBN lIA36VjVSI18BA7n5woZCky5cRpwyUu3E1UMBbABND/hBcrSlDcQE2U5DFzp2JTLONmX 6pkklOCCa+6rL5qesImLY+rbpp80nuOW+DvqKDOuiokitlYo8FYktjzn97YrRbY62Leo TTBiORMN+ag5kivSexfWOwKo6v8QefmGGsyKYNnRDWXijmD7tNu+yiy+ylc4dL1Voh76 HvebcZ7EHC4BPbeGTuB4SJ2GS+YnrD2JhI4vtDwSeRlfKF/iUAhsIWQekIyop2tjh0U7 7qbw== X-Gm-Message-State: AMCzsaXMfjtUMc5FQCHT5CpcbaIG6mOhpqb4sXVYQz05IVhR7UoQarZa klk+O1zmZ8ixVAgi+Dmjjpf5cMISRpU= X-Google-Smtp-Source: AOwi7QCNegFNvChZ1UiFH9u0w7h60vCqBUCeCCRnDWwYOAsV4p3oDLl8Phm4hNZNwg+khhZZQk0W5g== X-Received: by 10.84.135.101 with SMTP id 92mr9657204pli.180.1508174787215; Mon, 16 Oct 2017 10:26:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:29 -0700 Message-Id: <20171016172609.23422-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v6 10/50] tcg: Avoid loops against variable bounds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Copy s->nb_globals or s->nb_temps to a local variable for the purposes of iteration. This should allow the compiler to use low-overhead looping constructs on some hosts. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 719db9f2b6..bb342e06dd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1166,23 +1166,16 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGAr= g ret, =20 static void tcg_reg_alloc_start(TCGContext *s) { - int i; + int i, n; TCGTemp *ts; - for(i =3D 0; i < s->nb_globals; i++) { + + for (i =3D 0, n =3D s->nb_globals; i < n; i++) { ts =3D &s->temps[i]; - if (ts->fixed_reg) { - ts->val_type =3D TEMP_VAL_REG; - } else { - ts->val_type =3D TEMP_VAL_MEM; - } + ts->val_type =3D (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); } - for(i =3D s->nb_globals; i < s->nb_temps; i++) { + for (n =3D s->nb_temps; i < n; i++) { ts =3D &s->temps[i]; - if (ts->temp_local) { - ts->val_type =3D TEMP_VAL_MEM; - } else { - ts->val_type =3D TEMP_VAL_DEAD; - } + ts->val_type =3D (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); ts->mem_allocated =3D 0; ts->fixed_reg =3D 0; } @@ -2284,9 +2277,9 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCG= RegSet allocated_regs) temporary registers needs to be allocated to store a constant. */ static void save_globals(TCGContext *s, TCGRegSet allocated_regs) { - int i; + int i, n; =20 - for (i =3D 0; i < s->nb_globals; i++) { + for (i =3D 0, n =3D s->nb_globals; i < n; i++) { temp_save(s, &s->temps[i], allocated_regs); } } @@ -2296,9 +2289,9 @@ static void save_globals(TCGContext *s, TCGRegSet all= ocated_regs) temporary registers needs to be allocated to store a constant. */ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) { - int i; + int i, n; =20 - for (i =3D 0; i < s->nb_globals; i++) { + for (i =3D 0, n =3D s->nb_globals; i < n; i++) { TCGTemp *ts =3D &s->temps[i]; tcg_debug_assert(ts->val_type !=3D TEMP_VAL_REG || ts->fixed_reg --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508174975827995.6800290917452; Mon, 16 Oct 2017 10:29:35 -0700 (PDT) Received: from localhost ([::1]:34303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Cf-0004Pz-1J for importer@patchew.org; Mon, 16 Oct 2017 13:29:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499q-000227-Ld for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499p-0003Pm-OP for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:30 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:56145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499p-0003PC-Iq for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:29 -0400 Received: by mail-pf0-x234.google.com with SMTP id 17so16278912pfn.12 for ; Mon, 16 Oct 2017 10:26:29 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PATCH v6 11/50] tcg: Change temp_allocate_frame arg to TCGTemp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bb342e06dd..163ec8b1c0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2103,10 +2103,8 @@ static void check_regs(TCGContext *s) } #endif =20 -static void temp_allocate_frame(TCGContext *s, int temp) +static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - TCGTemp *ts; - ts =3D &s->temps[temp]; #if !(defined(__sparc__) && TCG_TARGET_REG_BITS =3D=3D 64) /* Sparc64 stack is accessed with offset of 2047 */ s->current_frame_offset =3D (s->current_frame_offset + @@ -2159,7 +2157,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, } if (!ts->mem_coherent) { if (!ts->mem_allocated) { - temp_allocate_frame(s, temp_idx(s, ts)); + temp_allocate_frame(s, ts); } switch (ts->val_type) { case TEMP_VAL_CONST: @@ -2389,7 +2387,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); if (!ots->mem_allocated) { - temp_allocate_frame(s, op->args[0]); + temp_allocate_frame(s, ots); } tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); if (IS_DEAD_ARG(1)) { --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150817513110627.54644591230965; Mon, 16 Oct 2017 10:32:11 -0700 (PDT) Received: from localhost ([::1]:34316 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49FD-0006rV-9h for importer@patchew.org; Mon, 16 Oct 2017 13:32:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499r-00023B-Jj for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499q-0003Qs-Te for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:31 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:43802) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499q-0003QI-OL for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:30 -0400 Received: by mail-pf0-x22c.google.com with SMTP id a8so15843593pfc.0 for ; Mon, 16 Oct 2017 10:26:30 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uc08eLaVrb5X9wMHbwVKCwEfLsADWaQlNRMzz5RsmlE=; b=TUWNgFnH6wuiJdxdPcuX8mBHR5B0BMODVr4X6mftNDh/1+wu7Kj7gMFcAXhnnvlFTO T5LBDN0Jiw187vDd+wMsHZzD42OmGdbvKpFT2p4fsethxYr6X46RRUj5SRevQeDPtz1c UOdc1flEjD4MXvUf0WOxzrlgn1FJ2YTh/Pdi0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uc08eLaVrb5X9wMHbwVKCwEfLsADWaQlNRMzz5RsmlE=; b=aUYRKoh1+Gx/N/1+aq0fXsaxyO3Zu3+6SII9VfSDcEwUn/hSOoE6yO7yEHUOM1Fwo8 BWJ5Szbl91MXZvo8/wNU+4feDBakIGqwohWtjPxbJgGvyvdJJ0MwsHkyBG83DCAfin3e PbsF7VoL9bcZUc2drVmg0OVviweAd2IEa8ZfesV0qklgUVJU0gYfOyB7qcyMypuwdh8J 5PjqL1GMaQgQKGHuGlcz4hVaZrMH3PmsmeN7nW8XsjEzvVvhnOwhunA2kqQ0o5dRfkcz t33hEhVGWA6VPyRloLHZr0eJ5xVa1mlZW70KeMDTGcjYc0OTzsLIcLO34NgnwlWBi/Ck Tfsw== X-Gm-Message-State: AMCzsaUR6Toq3Sdm9+CZfFAOozrNTSNMB2gPuEAZrbRX3UyfZuQDwGTg VAnmO8MD59Oh4zNyydzQ59pByXfXZbY= X-Google-Smtp-Source: AOwi7QCheYJMZpXyD+P65vNc6ygSFM3vMRpD3p1zhPKttaTWtWOpbbu34kvS5uEccOaBvCbpgZf0Pg== X-Received: by 10.99.55.1 with SMTP id e1mr8507805pga.175.1508174789580; Mon, 16 Oct 2017 10:26:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:31 -0700 Message-Id: <20171016172609.23422-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH v6 12/50] tcg: Remove unused TCG_CALL_DUMMY_TCGV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 1 - 1 file changed, 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 4352c0ee8c..e0615de90f 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -496,7 +496,6 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCG= v_ptr t) #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) =20 /* used to align parameters */ -#define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1) #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) =20 /* Conditions. Note that these are laid out for easy manipulation by --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176021703536.679360621719; Mon, 16 Oct 2017 10:47:01 -0700 (PDT) Received: from localhost ([::1]:34379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49TX-0002Gp-TB for importer@patchew.org; Mon, 16 Oct 2017 13:46:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499t-00026Z-Kp for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499s-0003SC-Nk for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:33 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:51667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499s-0003RQ-DK for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:32 -0400 Received: by mail-pf0-x22b.google.com with SMTP id n14so16279924pfh.8 for ; Mon, 16 Oct 2017 10:26:32 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u0QX5W2ChFDKotIY5fy9QRJPxN94Nx0++sj/1I+ayIo=; b=RJgShSMCAjcfmEayH8aE+sbXcxt70xhYTr+zPclrv2ZwW2YM3npC3wc30cSbvrccFb DNfH4N3taAnirn29cUp71CqkyKXkTZB97CNaY62jVSE16iZs3FI5kuL7/j7oCJAQdhGu OC7a6zpwynsYtjPES+7IkfUvjhZ9RnDy8sskI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u0QX5W2ChFDKotIY5fy9QRJPxN94Nx0++sj/1I+ayIo=; b=S9eh0HhRNgY/AIYW9AA6NK+2pRJAcEcTXCVmPprE0DI5OJj8BkXES7gz5zGgOHctSw VCd1CRlB/qB31PhHoMmDZ1JM0EyHVAHduk0dDrT4xfI2WaJgJcFZpVqzC7bXyfrIkF1x v9LxFZZTe4W78RI7y1Yv4qtmXih0c+q0P/EAxjgIy31+IZteRjTISa1WBftpFxg08vyr tQVdnoian4LTePGv1uBSWVJ4L4+UnweW83QDwDmxGjbT6zyau84PIY3JOKyHdbOw46Fe mz4K0E0ho6ns0kEGcFtZo0KSaF1Bn3Pz9kb86A6UACk9LZYuwNn2/60+HL9BujPIWuAt Dnow== X-Gm-Message-State: AMCzsaUwc2CIDp2GkYOd1I3KUUi6QyRD5gN1Xl2AJdKeuzZBLjiKidIf iJbaSwpPBJlJvENxa2Xs+LpuPghbsJk= X-Google-Smtp-Source: ABhQp+Qq353R0XBDANIM2xJy5zpelCDKYB7Sru6IFOJDA0ej/o8mXTDuyx6R0B8wpifZJr+YJ9zr8Q== X-Received: by 10.84.138.131 with SMTP id 3mr68361plp.238.1508174790953; Mon, 16 Oct 2017 10:26:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:32 -0700 Message-Id: <20171016172609.23422-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH v6 13/50] tcg: Export temp_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson At the same time, drop the TCGContext argument and use tcg_ctx instead. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 7 ++++++- tcg/tcg.c | 15 ++++----------- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index e0615de90f..c50805217c 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -734,13 +734,18 @@ struct TCGContext { extern TCGContext tcg_ctx; extern bool parallel_cpus; =20 -static inline TCGArg temp_arg(TCGTemp *ts) +static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n =3D ts - tcg_ctx.temps; tcg_debug_assert(n >=3D 0 && n < tcg_ctx.nb_temps); return n; } =20 +static inline TCGArg temp_arg(TCGTemp *ts) +{ + return temp_idx(ts); +} + static inline TCGTemp *arg_temp(TCGArg a) { return a =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; diff --git a/tcg/tcg.c b/tcg/tcg.c index 163ec8b1c0..b39944d42a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -473,13 +473,6 @@ void tcg_func_start(TCGContext *s) s->gen_next_op_idx =3D 1; } =20 -static inline int temp_idx(TCGContext *s, TCGTemp *ts) -{ - ptrdiff_t n =3D ts - s->temps; - tcg_debug_assert(n >=3D 0 && n < s->nb_temps); - return n; -} - static inline TCGTemp *tcg_temp_alloc(TCGContext *s) { int n =3D s->nb_temps++; @@ -516,7 +509,7 @@ static int tcg_global_reg_new_internal(TCGContext *s, T= CGType type, ts->name =3D name; tcg_regset_set_reg(s->reserved_regs, reg); =20 - return temp_idx(s, ts); + return temp_idx(ts); } =20 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t siz= e) @@ -605,7 +598,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr = base, ts->mem_offset =3D offset; ts->name =3D name; } - return temp_idx(s, ts); + return temp_idx(ts); } =20 static int tcg_temp_new_internal(TCGType type, int temp_local) @@ -645,7 +638,7 @@ static int tcg_temp_new_internal(TCGType type, int temp= _local) ts->temp_allocated =3D 1; ts->temp_local =3D temp_local; } - idx =3D temp_idx(s, ts); + idx =3D temp_idx(ts); } =20 #if defined(CONFIG_DEBUG_TCG) @@ -1186,7 +1179,7 @@ static void tcg_reg_alloc_start(TCGContext *s) static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, TCGTemp *ts) { - int idx =3D temp_idx(s, ts); + int idx =3D temp_idx(ts); =20 if (ts->temp_global) { pstrcpy(buf, buf_size, ts->name); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150817531240735.868339193282054; Mon, 16 Oct 2017 10:35:12 -0700 (PDT) Received: from localhost ([::1]:34328 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49IA-0000xm-HP for importer@patchew.org; Mon, 16 Oct 2017 13:35:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e499x-0002AV-V3 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499u-0003TG-E0 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:37 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:54601) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499u-0003Sf-1l for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:34 -0400 Received: by mail-pf0-x22c.google.com with SMTP id n89so8658549pfk.11 for ; Mon, 16 Oct 2017 10:26:33 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xQu3a0vMkMDgADARfkzGV6Yh21BxIRbkHvrajy96WtQ=; b=YUiOg1CFzRMO03I+eClmcYXMb+0AcGAHUQj8pj7OBw+GDn4n5VPRvt9Jy7WJsE2YxI 7xCjpC6vIQ24r4xxGMJdIg30IfPBJIz4fJYbdskkQ6kJOq17VFPOhZUneqZ0ThloFHrM GTuEGApe6zRqnpRozm6Sa7g9GOX6lrP6opXiA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xQu3a0vMkMDgADARfkzGV6Yh21BxIRbkHvrajy96WtQ=; b=Vka3KI/xM6ano2m1upJ0A9hmKHMpJJZpcykYYmNS+3O415kZhS228bvbU7oUaWtpv9 tmo1UAv2ogEF7swvjepoqWMnFq6+1WzKfAmkoe8eRa5sMXWcsdcrLDegv7R25+O1WPOc o0i5fa1RxF96gceg120+SoArPyQUKNGz1cYFApvSprMrMP3Ryz43tsxS9SayyvO24HA8 CvRTsx7hUOtFwZnS0bzUXOYk8ne7PIIjHcRSp9c7LXXzE3QP/QGtPsQ4FF5OEAZwP+Z5 J3S695A3kOBoN3vdnTO94R0F87nCYdWyeM+eQDwQ4fXjiqzb1ohsUaPQvgVLmYrGvoS3 m86w== X-Gm-Message-State: AMCzsaVuQTr77sVuCGQWXEAFWHv8lbFWbxs73Z+VT37JvITJK+cFqvfm VO5fYZ2bfLDxNyaa7s9+IY0v3rPvud8= X-Google-Smtp-Source: AOwi7QCvn6NkEyuH+WEeGwp032dIbFNDRBkGzeNapUJNe9XIGfzJbn9v17glTc4xori5MPyOgyq6FQ== X-Received: by 10.98.198.138 with SMTP id x10mr7920006pfk.55.1508174792395; Mon, 16 Oct 2017 10:26:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:33 -0700 Message-Id: <20171016172609.23422-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH v6 14/50] tcg: Use per-temp state data in optimize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson While we're touching many of the lines anyway, adjust the naming of the functions to better distinguish when "TCGArg" vs "TCGTemp" should be used. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 5 + tcg/optimize.c | 430 +++++++++++++++++++++++++++++++++--------------------= ---- 2 files changed, 252 insertions(+), 183 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index c50805217c..563e7d36aa 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -751,6 +751,11 @@ static inline TCGTemp *arg_temp(TCGArg a) return a =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; } =20 +static inline size_t arg_index(TCGArg a) +{ + return a; +} + static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { tcg_ctx.gen_op_buf[op_idx].args[arg] =3D v; diff --git a/tcg/optimize.c b/tcg/optimize.c index 55f9e83ce8..ead7bb5e4f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -34,34 +34,63 @@ =20 struct tcg_temp_info { bool is_const; - uint16_t prev_copy; - uint16_t next_copy; + TCGTemp *prev_copy; + TCGTemp *next_copy; tcg_target_ulong val; tcg_target_ulong mask; }; =20 -static struct tcg_temp_info temps[TCG_MAX_TEMPS]; +static struct tcg_temp_info temps_[TCG_MAX_TEMPS]; static TCGTempSet temps_used; =20 -static inline bool temp_is_const(TCGArg arg) +static inline struct tcg_temp_info *ts_info(TCGTemp *ts) { - return temps[arg].is_const; + return ts->state_ptr; } =20 -static inline bool temp_is_copy(TCGArg arg) +static inline struct tcg_temp_info *arg_info(TCGArg arg) { - return temps[arg].next_copy !=3D arg; + return ts_info(arg_temp(arg)); +} + +static inline bool ts_is_const(TCGTemp *ts) +{ + return ts_info(ts)->is_const; +} + +static inline bool arg_is_const(TCGArg arg) +{ + return ts_is_const(arg_temp(arg)); +} + +static inline bool ts_is_copy(TCGTemp *ts) +{ + return ts_info(ts)->next_copy !=3D ts; +} + +static inline bool arg_is_copy(TCGArg arg) +{ + return ts_is_copy(arg_temp(arg)); } =20 /* Reset TEMP's state, possibly removing the temp for the list of copies. = */ -static void reset_temp(TCGArg temp) +static void reset_ts(TCGTemp *ts) { - temps[temps[temp].next_copy].prev_copy =3D temps[temp].prev_copy; - temps[temps[temp].prev_copy].next_copy =3D temps[temp].next_copy; - temps[temp].next_copy =3D temp; - temps[temp].prev_copy =3D temp; - temps[temp].is_const =3D false; - temps[temp].mask =3D -1; + struct tcg_temp_info *ti =3D ts_info(ts); + struct tcg_temp_info *pi =3D ts_info(ti->prev_copy); + struct tcg_temp_info *ni =3D ts_info(ti->next_copy); + + ni->prev_copy =3D ti->prev_copy; + pi->next_copy =3D ti->next_copy; + ti->next_copy =3D ts; + ti->prev_copy =3D ts; + ti->is_const =3D false; + ti->mask =3D -1; +} + +static void reset_temp(TCGArg arg) +{ + reset_ts(arg_temp(arg)); } =20 /* Reset all temporaries, given that there are NB_TEMPS of them. */ @@ -71,17 +100,26 @@ static void reset_all_temps(int nb_temps) } =20 /* Initialize and activate a temporary. */ -static void init_temp_info(TCGArg temp) +static void init_ts_info(TCGTemp *ts) { - if (!test_bit(temp, temps_used.l)) { - temps[temp].next_copy =3D temp; - temps[temp].prev_copy =3D temp; - temps[temp].is_const =3D false; - temps[temp].mask =3D -1; - set_bit(temp, temps_used.l); + size_t idx =3D temp_idx(ts); + if (!test_bit(idx, temps_used.l)) { + struct tcg_temp_info *ti =3D &temps_[idx]; + + ts->state_ptr =3D ti; + ti->next_copy =3D ts; + ti->prev_copy =3D ts; + ti->is_const =3D false; + ti->mask =3D -1; + set_bit(idx, temps_used.l); } } =20 +static void init_arg_info(TCGArg arg) +{ + init_ts_info(arg_temp(arg)); +} + static int op_bits(TCGOpcode op) { const TCGOpDef *def =3D &tcg_op_defs[op]; @@ -116,50 +154,49 @@ static TCGOpcode op_to_movi(TCGOpcode op) } } =20 -static TCGArg find_better_copy(TCGContext *s, TCGArg arg) +static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) { - TCGTemp *ts =3D arg_temp(arg); - TCGArg i; + TCGTemp *i; =20 /* If this is already a global, we can't do better. */ if (ts->temp_global) { - return arg; + return ts; } =20 /* Search for a global first. */ - for (i =3D temps[arg].next_copy ; i !=3D arg; i =3D temps[i].next_copy= ) { - if (i < s->nb_globals) { + for (i =3D ts_info(ts)->next_copy; i !=3D ts; i =3D ts_info(i)->next_c= opy) { + if (i->temp_global) { return i; } } =20 /* If it is a temp, search for a temp local. */ if (!ts->temp_local) { - for (i =3D temps[arg].next_copy ; i !=3D arg; i =3D temps[i].next_= copy) { - if (s->temps[i].temp_local) { + for (i =3D ts_info(ts)->next_copy; i !=3D ts; i =3D ts_info(i)->ne= xt_copy) { + if (ts->temp_local) { return i; } } } =20 /* Failure to find a better representation, return the same temp. */ - return arg; + return ts; } =20 -static bool temps_are_copies(TCGArg arg1, TCGArg arg2) +static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) { - TCGArg i; + TCGTemp *i; =20 - if (arg1 =3D=3D arg2) { + if (ts1 =3D=3D ts2) { return true; } =20 - if (!temp_is_copy(arg1) || !temp_is_copy(arg2)) { + if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) { return false; } =20 - for (i =3D temps[arg1].next_copy ; i !=3D arg1 ; i =3D temps[i].next_c= opy) { - if (i =3D=3D arg2) { + for (i =3D ts_info(ts1)->next_copy; i !=3D ts1; i =3D ts_info(i)->next= _copy) { + if (i =3D=3D ts2) { return true; } } @@ -167,22 +204,28 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return false; } =20 +static bool args_are_copies(TCGArg arg1, TCGArg arg2) +{ + return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); +} + static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg = val) { TCGOpcode new_op =3D op_to_movi(op->opc); tcg_target_ulong mask; + struct tcg_temp_info *di =3D arg_info(dst); =20 op->opc =3D new_op; =20 reset_temp(dst); - temps[dst].is_const =3D true; - temps[dst].val =3D val; + di->is_const =3D true; + di->val =3D val; mask =3D val; if (TCG_TARGET_REG_BITS > 32 && new_op =3D=3D INDEX_op_movi_i32) { /* High bits of the destination are now garbage. */ mask |=3D ~0xffffffffull; } - temps[dst].mask =3D mask; + di->mask =3D mask; =20 op->args[0] =3D dst; op->args[1] =3D val; @@ -190,35 +233,44 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op= , TCGArg dst, TCGArg val) =20 static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg s= rc) { - if (temps_are_copies(dst, src)) { + TCGTemp *dst_ts =3D arg_temp(dst); + TCGTemp *src_ts =3D arg_temp(src); + struct tcg_temp_info *di; + struct tcg_temp_info *si; + tcg_target_ulong mask; + TCGOpcode new_op; + + if (ts_are_copies(dst_ts, src_ts)) { tcg_op_remove(s, op); return; } =20 - TCGOpcode new_op =3D op_to_mov(op->opc); - tcg_target_ulong mask; + reset_ts(dst_ts); + di =3D ts_info(dst_ts); + si =3D ts_info(src_ts); + new_op =3D op_to_mov(op->opc); =20 op->opc =3D new_op; + op->args[0] =3D dst; + op->args[1] =3D src; =20 - reset_temp(dst); - mask =3D temps[src].mask; + mask =3D si->mask; if (TCG_TARGET_REG_BITS > 32 && new_op =3D=3D INDEX_op_mov_i32) { /* High bits of the destination are now garbage. */ mask |=3D ~0xffffffffull; } - temps[dst].mask =3D mask; - - if (arg_temp(src)->type =3D=3D arg_temp(dst)->type) { - temps[dst].next_copy =3D temps[src].next_copy; - temps[dst].prev_copy =3D src; - temps[temps[dst].next_copy].prev_copy =3D dst; - temps[src].next_copy =3D dst; - temps[dst].is_const =3D temps[src].is_const; - temps[dst].val =3D temps[src].val; - } + di->mask =3D mask; =20 - op->args[0] =3D dst; - op->args[1] =3D src; + if (src_ts->type =3D=3D dst_ts->type) { + struct tcg_temp_info *ni =3D ts_info(si->next_copy); + + di->next_copy =3D si->next_copy; + di->prev_copy =3D src_ts; + ni->prev_copy =3D dst_ts; + si->next_copy =3D dst_ts; + di->is_const =3D si->is_const; + di->val =3D si->val; + } } =20 static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) @@ -465,18 +517,20 @@ static bool do_constant_folding_cond_eq(TCGCond c) static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, TCGArg y, TCGCond c) { - if (temp_is_const(x) && temp_is_const(y)) { + tcg_target_ulong xv =3D arg_info(x)->val; + tcg_target_ulong yv =3D arg_info(y)->val; + if (arg_is_const(x) && arg_is_const(y)) { switch (op_bits(op)) { case 32: - return do_constant_folding_cond_32(temps[x].val, temps[y].val,= c); + return do_constant_folding_cond_32(xv, yv, c); case 64: - return do_constant_folding_cond_64(temps[x].val, temps[y].val,= c); + return do_constant_folding_cond_64(xv, yv, c); default: tcg_abort(); } - } else if (temps_are_copies(x, y)) { + } else if (args_are_copies(x, y)) { return do_constant_folding_cond_eq(c); - } else if (temp_is_const(y) && temps[y].val =3D=3D 0) { + } else if (arg_is_const(y) && yv =3D=3D 0) { switch (c) { case TCG_COND_LTU: return 0; @@ -496,12 +550,15 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, T= CGArg *p2, TCGCond c) TCGArg al =3D p1[0], ah =3D p1[1]; TCGArg bl =3D p2[0], bh =3D p2[1]; =20 - if (temp_is_const(bl) && temp_is_const(bh)) { - uint64_t b =3D ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[b= l].val; + if (arg_is_const(bl) && arg_is_const(bh)) { + tcg_target_ulong blv =3D arg_info(bl)->val; + tcg_target_ulong bhv =3D arg_info(bh)->val; + uint64_t b =3D deposit64(blv, 32, 32, bhv); =20 - if (temp_is_const(al) && temp_is_const(ah)) { - uint64_t a; - a =3D ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].va= l; + if (arg_is_const(al) && arg_is_const(ah)) { + tcg_target_ulong alv =3D arg_info(al)->val; + tcg_target_ulong ahv =3D arg_info(ah)->val; + uint64_t a =3D deposit64(alv, 32, 32, ahv); return do_constant_folding_cond_64(a, b, c); } if (b =3D=3D 0) { @@ -515,7 +572,7 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCG= Arg *p2, TCGCond c) } } } - if (temps_are_copies(al, bl) && temps_are_copies(ah, bh)) { + if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { return do_constant_folding_cond_eq(c); } return 2; @@ -525,8 +582,8 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, T= CGArg *p2) { TCGArg a1 =3D *p1, a2 =3D *p2; int sum =3D 0; - sum +=3D temp_is_const(a1); - sum -=3D temp_is_const(a2); + sum +=3D arg_is_const(a1); + sum -=3D arg_is_const(a2); =20 /* Prefer the constant in second argument, and then the form op a, a, b, which is better handled on non-RISC hosts. */ @@ -541,10 +598,10 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1,= TCGArg *p2) static bool swap_commutative2(TCGArg *p1, TCGArg *p2) { int sum =3D 0; - sum +=3D temp_is_const(p1[0]); - sum +=3D temp_is_const(p1[1]); - sum -=3D temp_is_const(p2[0]); - sum -=3D temp_is_const(p2[1]); + sum +=3D arg_is_const(p1[0]); + sum +=3D arg_is_const(p1[1]); + sum -=3D arg_is_const(p2[0]); + sum -=3D arg_is_const(p2[1]); if (sum > 0) { TCGArg t; t =3D p1[0], p1[0] =3D p2[0], p2[0] =3D t; @@ -586,23 +643,24 @@ void tcg_optimize(TCGContext *s) nb_oargs =3D op->callo; nb_iargs =3D op->calli; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - tmp =3D op->args[i]; - if (tmp !=3D TCG_CALL_DUMMY_ARG) { - init_temp_info(tmp); + TCGTemp *ts =3D arg_temp(op->args[i]); + if (ts) { + init_ts_info(ts); } } } else { nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - init_temp_info(op->args[i]); + init_arg_info(op->args[i]); } } =20 /* Do copy propagation */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - if (temp_is_copy(op->args[i])) { - op->args[i] =3D find_better_copy(s, op->args[i]); + TCGTemp *ts =3D arg_temp(op->args[i]); + if (ts && ts_is_copy(ts)) { + op->args[i] =3D temp_arg(find_better_copy(s, ts)); } } =20 @@ -671,7 +729,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(sar): CASE_OP_32_64(rotl): CASE_OP_32_64(rotr): - if (temp_is_const(op->args[1]) && temps[op->args[1]].val =3D= =3D 0) { + if (arg_is_const(op->args[1]) + && arg_info(op->args[1])->val =3D=3D 0) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } @@ -681,7 +740,7 @@ void tcg_optimize(TCGContext *s) TCGOpcode neg_op; bool have_neg; =20 - if (temp_is_const(op->args[2])) { + if (arg_is_const(op->args[2])) { /* Proceed with possible constant folding. */ break; } @@ -695,8 +754,8 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (temp_is_const(op->args[1]) - && temps[op->args[1]].val =3D=3D 0) { + if (arg_is_const(op->args[1]) + && arg_info(op->args[1])->val =3D=3D 0) { op->opc =3D neg_op; reset_temp(op->args[0]); op->args[1] =3D op->args[2]; @@ -706,34 +765,34 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(xor): CASE_OP_32_64(nand): - if (!temp_is_const(op->args[1]) - && temp_is_const(op->args[2]) - && temps[op->args[2]].val =3D=3D -1) { + if (!arg_is_const(op->args[1]) + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D -1) { i =3D 1; goto try_not; } break; CASE_OP_32_64(nor): - if (!temp_is_const(op->args[1]) - && temp_is_const(op->args[2]) - && temps[op->args[2]].val =3D=3D 0) { + if (!arg_is_const(op->args[1]) + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D 0) { i =3D 1; goto try_not; } break; CASE_OP_32_64(andc): - if (!temp_is_const(op->args[2]) - && temp_is_const(op->args[1]) - && temps[op->args[1]].val =3D=3D -1) { + if (!arg_is_const(op->args[2]) + && arg_is_const(op->args[1]) + && arg_info(op->args[1])->val =3D=3D -1) { i =3D 2; goto try_not; } break; CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(op->args[2]) - && temp_is_const(op->args[1]) - && temps[op->args[1]].val =3D=3D 0) { + if (!arg_is_const(op->args[2]) + && arg_is_const(op->args[1]) + && arg_info(op->args[1])->val =3D=3D 0) { i =3D 2; goto try_not; } @@ -774,9 +833,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(or): CASE_OP_32_64(xor): CASE_OP_32_64(andc): - if (!temp_is_const(op->args[1]) - && temp_is_const(op->args[2]) - && temps[op->args[2]].val =3D=3D 0) { + if (!arg_is_const(op->args[1]) + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D 0) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } @@ -784,9 +843,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(and): CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(op->args[1]) - && temp_is_const(op->args[2]) - && temps[op->args[2]].val =3D=3D -1) { + if (!arg_is_const(op->args[1]) + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D -1) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } @@ -801,21 +860,21 @@ void tcg_optimize(TCGContext *s) affected =3D -1; switch (opc) { CASE_OP_32_64(ext8s): - if ((temps[op->args[1]].mask & 0x80) !=3D 0) { + if ((arg_info(op->args[1])->mask & 0x80) !=3D 0) { break; } CASE_OP_32_64(ext8u): mask =3D 0xff; goto and_const; CASE_OP_32_64(ext16s): - if ((temps[op->args[1]].mask & 0x8000) !=3D 0) { + if ((arg_info(op->args[1])->mask & 0x8000) !=3D 0) { break; } CASE_OP_32_64(ext16u): mask =3D 0xffff; goto and_const; case INDEX_op_ext32s_i64: - if ((temps[op->args[1]].mask & 0x80000000) !=3D 0) { + if ((arg_info(op->args[1])->mask & 0x80000000) !=3D 0) { break; } case INDEX_op_ext32u_i64: @@ -823,111 +882,114 @@ void tcg_optimize(TCGContext *s) goto and_const; =20 CASE_OP_32_64(and): - mask =3D temps[op->args[2]].mask; - if (temp_is_const(op->args[2])) { + mask =3D arg_info(op->args[2])->mask; + if (arg_is_const(op->args[2])) { and_const: - affected =3D temps[op->args[1]].mask & ~mask; + affected =3D arg_info(op->args[1])->mask & ~mask; } - mask =3D temps[op->args[1]].mask & mask; + mask =3D arg_info(op->args[1])->mask & mask; break; =20 case INDEX_op_ext_i32_i64: - if ((temps[op->args[1]].mask & 0x80000000) !=3D 0) { + if ((arg_info(op->args[1])->mask & 0x80000000) !=3D 0) { break; } case INDEX_op_extu_i32_i64: /* We do not compute affected as it is a size changing op. */ - mask =3D (uint32_t)temps[op->args[1]].mask; + mask =3D (uint32_t)arg_info(op->args[1])->mask; break; =20 CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless op->args[2] is constant, we can't infer anything from it. = */ - if (temp_is_const(op->args[2])) { - mask =3D ~temps[op->args[2]].mask; + if (arg_is_const(op->args[2])) { + mask =3D ~arg_info(op->args[2])->mask; goto and_const; } - /* But we certainly know nothing outside op->args[1] may be se= t. */ - mask =3D temps[op->args[1]].mask; + /* But we certainly know nothing outside args[1] may be set. */ + mask =3D arg_info(op->args[1])->mask; break; =20 case INDEX_op_sar_i32: - if (temp_is_const(op->args[2])) { - tmp =3D temps[op->args[2]].val & 31; - mask =3D (int32_t)temps[op->args[1]].mask >> tmp; + if (arg_is_const(op->args[2])) { + tmp =3D arg_info(op->args[2])->val & 31; + mask =3D (int32_t)arg_info(op->args[1])->mask >> tmp; } break; case INDEX_op_sar_i64: - if (temp_is_const(op->args[2])) { - tmp =3D temps[op->args[2]].val & 63; - mask =3D (int64_t)temps[op->args[1]].mask >> tmp; + if (arg_is_const(op->args[2])) { + tmp =3D arg_info(op->args[2])->val & 63; + mask =3D (int64_t)arg_info(op->args[1])->mask >> tmp; } break; =20 case INDEX_op_shr_i32: - if (temp_is_const(op->args[2])) { - tmp =3D temps[op->args[2]].val & 31; - mask =3D (uint32_t)temps[op->args[1]].mask >> tmp; + if (arg_is_const(op->args[2])) { + tmp =3D arg_info(op->args[2])->val & 31; + mask =3D (uint32_t)arg_info(op->args[1])->mask >> tmp; } break; case INDEX_op_shr_i64: - if (temp_is_const(op->args[2])) { - tmp =3D temps[op->args[2]].val & 63; - mask =3D (uint64_t)temps[op->args[1]].mask >> tmp; + if (arg_is_const(op->args[2])) { + tmp =3D arg_info(op->args[2])->val & 63; + mask =3D (uint64_t)arg_info(op->args[1])->mask >> tmp; } break; =20 case INDEX_op_extrl_i64_i32: - mask =3D (uint32_t)temps[op->args[1]].mask; + mask =3D (uint32_t)arg_info(op->args[1])->mask; break; case INDEX_op_extrh_i64_i32: - mask =3D (uint64_t)temps[op->args[1]].mask >> 32; + mask =3D (uint64_t)arg_info(op->args[1])->mask >> 32; break; =20 CASE_OP_32_64(shl): - if (temp_is_const(op->args[2])) { - tmp =3D temps[op->args[2]].val & (TCG_TARGET_REG_BITS - 1); - mask =3D temps[op->args[1]].mask << tmp; + if (arg_is_const(op->args[2])) { + tmp =3D arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS = - 1); + mask =3D arg_info(op->args[1])->mask << tmp; } break; =20 CASE_OP_32_64(neg): /* Set to 1 all bits to the left of the rightmost. */ - mask =3D -(temps[op->args[1]].mask & -temps[op->args[1]].mask); + mask =3D -(arg_info(op->args[1])->mask + & -arg_info(op->args[1])->mask); break; =20 CASE_OP_32_64(deposit): - mask =3D deposit64(temps[op->args[1]].mask, op->args[3], - op->args[4], temps[op->args[2]].mask); + mask =3D deposit64(arg_info(op->args[1])->mask, + op->args[3], op->args[4], + arg_info(op->args[2])->mask); break; =20 CASE_OP_32_64(extract): - mask =3D extract64(temps[op->args[1]].mask, op->args[2], op->a= rgs[3]); + mask =3D extract64(arg_info(op->args[1])->mask, + op->args[2], op->args[3]); if (op->args[2] =3D=3D 0) { - affected =3D temps[op->args[1]].mask & ~mask; + affected =3D arg_info(op->args[1])->mask & ~mask; } break; CASE_OP_32_64(sextract): - mask =3D sextract64(temps[op->args[1]].mask, + mask =3D sextract64(arg_info(op->args[1])->mask, op->args[2], op->args[3]); if (op->args[2] =3D=3D 0 && (tcg_target_long)mask >=3D 0) { - affected =3D temps[op->args[1]].mask & ~mask; + affected =3D arg_info(op->args[1])->mask & ~mask; } break; =20 CASE_OP_32_64(or): CASE_OP_32_64(xor): - mask =3D temps[op->args[1]].mask | temps[op->args[2]].mask; + mask =3D arg_info(op->args[1])->mask | arg_info(op->args[2])->= mask; break; =20 case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - mask =3D temps[op->args[2]].mask | 31; + mask =3D arg_info(op->args[2])->mask | 31; break; =20 case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - mask =3D temps[op->args[2]].mask | 63; + mask =3D arg_info(op->args[2])->mask | 63; break; =20 case INDEX_op_ctpop_i32: @@ -943,7 +1005,7 @@ void tcg_optimize(TCGContext *s) break; =20 CASE_OP_32_64(movcond): - mask =3D temps[op->args[3]].mask | temps[op->args[4]].mask; + mask =3D arg_info(op->args[3])->mask | arg_info(op->args[4])->= mask; break; =20 CASE_OP_32_64(ld8u): @@ -997,7 +1059,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mul): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - if ((temp_is_const(op->args[2]) && temps[op->args[2]].val =3D= =3D 0)) { + if (arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D 0) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } @@ -1010,7 +1073,7 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64(or): CASE_OP_32_64(and): - if (temps_are_copies(op->args[1], op->args[2])) { + if (args_are_copies(op->args[1], op->args[2])) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } @@ -1024,7 +1087,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): CASE_OP_32_64(sub): CASE_OP_32_64(xor): - if (temps_are_copies(op->args[1], op->args[2])) { + if (args_are_copies(op->args[1], op->args[2])) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } @@ -1057,8 +1120,8 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - if (temp_is_const(op->args[1])) { - tmp =3D do_constant_folding(opc, temps[op->args[1]].val, 0= ); + if (arg_is_const(op->args[1])) { + tmp =3D do_constant_folding(opc, arg_info(op->args[1])->va= l, 0); tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } @@ -1086,9 +1149,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): CASE_OP_32_64(rem): CASE_OP_32_64(remu): - if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) { - tmp =3D do_constant_folding(opc, temps[op->args[1]].val, - temps[op->args[2]].val); + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp =3D do_constant_folding(opc, arg_info(op->args[1])->va= l, + arg_info(op->args[2])->val); tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } @@ -1096,8 +1159,8 @@ void tcg_optimize(TCGContext *s) =20 CASE_OP_32_64(clz): CASE_OP_32_64(ctz): - if (temp_is_const(op->args[1])) { - TCGArg v =3D temps[op->args[1]].val; + if (arg_is_const(op->args[1])) { + TCGArg v =3D arg_info(op->args[1])->val; if (v !=3D 0) { tmp =3D do_constant_folding(opc, v, 0); tcg_opt_gen_movi(s, op, op->args[0], tmp); @@ -1109,17 +1172,18 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 CASE_OP_32_64(deposit): - if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) { - tmp =3D deposit64(temps[op->args[1]].val, op->args[3], - op->args[4], temps[op->args[2]].val); + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp =3D deposit64(arg_info(op->args[1])->val, + op->args[3], op->args[4], + arg_info(op->args[2])->val); tcg_opt_gen_movi(s, op, op->args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(extract): - if (temp_is_const(op->args[1])) { - tmp =3D extract64(temps[op->args[1]].val, + if (arg_is_const(op->args[1])) { + tmp =3D extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); tcg_opt_gen_movi(s, op, op->args[0], tmp); break; @@ -1127,8 +1191,8 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 CASE_OP_32_64(sextract): - if (temp_is_const(op->args[1])) { - tmp =3D sextract64(temps[op->args[1]].val, + if (arg_is_const(op->args[1])) { + tmp =3D sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); tcg_opt_gen_movi(s, op, op->args[0], tmp); break; @@ -1166,9 +1230,9 @@ void tcg_optimize(TCGContext *s) tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); break; } - if (temp_is_const(op->args[3]) && temp_is_const(op->args[4])) { - tcg_target_ulong tv =3D temps[op->args[3]].val; - tcg_target_ulong fv =3D temps[op->args[4]].val; + if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { + tcg_target_ulong tv =3D arg_info(op->args[3])->val; + tcg_target_ulong fv =3D arg_info(op->args[4])->val; TCGCond cond =3D op->args[5]; if (fv =3D=3D 1 && tv =3D=3D 0) { cond =3D tcg_invert_cond(cond); @@ -1185,12 +1249,12 @@ void tcg_optimize(TCGContext *s) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - if (temp_is_const(op->args[2]) && temp_is_const(op->args[3]) - && temp_is_const(op->args[4]) && temp_is_const(op->args[5]= )) { - uint32_t al =3D temps[op->args[2]].val; - uint32_t ah =3D temps[op->args[3]].val; - uint32_t bl =3D temps[op->args[4]].val; - uint32_t bh =3D temps[op->args[5]].val; + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) + && arg_is_const(op->args[4]) && arg_is_const(op->args[5]))= { + uint32_t al =3D arg_info(op->args[2])->val; + uint32_t ah =3D arg_info(op->args[3])->val; + uint32_t bl =3D arg_info(op->args[4])->val; + uint32_t bh =3D arg_info(op->args[5])->val; uint64_t a =3D ((uint64_t)ah << 32) | al; uint64_t b =3D ((uint64_t)bh << 32) | bl; TCGArg rl, rh; @@ -1214,9 +1278,9 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_mulu2_i32: - if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])) { - uint32_t a =3D temps[op->args[2]].val; - uint32_t b =3D temps[op->args[3]].val; + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { + uint32_t a =3D arg_info(op->args[2])->val; + uint32_t b =3D arg_info(op->args[3])->val; uint64_t r =3D (uint64_t)a * b; TCGArg rl, rh; TCGOp *op2 =3D tcg_op_insert_before(s, op, INDEX_op_movi_i= 32, 2); @@ -1247,10 +1311,10 @@ void tcg_optimize(TCGContext *s) } } else if ((op->args[4] =3D=3D TCG_COND_LT || op->args[4] =3D=3D TCG_COND_GE) - && temp_is_const(op->args[2]) - && temps[op->args[2]].val =3D=3D 0 - && temp_is_const(op->args[3]) - && temps[op->args[3]].val =3D=3D 0) { + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val =3D=3D 0 + && arg_is_const(op->args[3]) + && arg_info(op->args[3])->val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: @@ -1318,15 +1382,15 @@ void tcg_optimize(TCGContext *s) tcg_opt_gen_movi(s, op, op->args[0], tmp); } else if ((op->args[5] =3D=3D TCG_COND_LT || op->args[5] =3D=3D TCG_COND_GE) - && temp_is_const(op->args[3]) - && temps[op->args[3]].val =3D=3D 0 - && temp_is_const(op->args[4]) - && temps[op->args[4]].val =3D=3D 0) { + && arg_is_const(op->args[3]) + && arg_info(op->args[3])->val =3D=3D 0 + && arg_is_const(op->args[4]) + && arg_info(op->args[4])->val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: reset_temp(op->args[0]); - temps[op->args[0]].mask =3D 1; + arg_info(op->args[0])->mask =3D 1; op->opc =3D INDEX_op_setcond_i32; op->args[1] =3D op->args[2]; op->args[2] =3D op->args[4]; @@ -1352,7 +1416,7 @@ void tcg_optimize(TCGContext *s) } do_setcond_low: reset_temp(op->args[0]); - temps[op->args[0]].mask =3D 1; + arg_info(op->args[0])->mask =3D 1; op->opc =3D INDEX_op_setcond_i32; op->args[2] =3D op->args[3]; op->args[3] =3D op->args[5]; @@ -1386,7 +1450,7 @@ void tcg_optimize(TCGContext *s) & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS)= )) { for (i =3D 0; i < nb_globals; i++) { if (test_bit(i, temps_used.l)) { - reset_temp(i); + reset_ts(&s->temps[i]); } } } @@ -1408,7 +1472,7 @@ void tcg_optimize(TCGContext *s) /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). = */ if (i =3D=3D 0) { - temps[op->args[i]].mask =3D mask; + arg_info(op->args[i])->mask =3D mask; } } } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175249881570.4466563991654; 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X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH v6 15/50] tcg: Push tcg_ctx into generator functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg-op.h | 100 +++++++++++++++++++++++++++----------------------------= ---- tcg/tcg-op.c | 47 ++++++++++++++-------------- 2 files changed, 69 insertions(+), 78 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 18d01b2f43..de9a61206a 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -28,173 +28,166 @@ =20 /* Basic output routines. Not for general consumption. */ =20 -void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg); -void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg); -void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg); -void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); -void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, - TCGArg, TCGArg); -void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, - TCGArg, TCGArg, TCGArg); - +void tcg_gen_op1(TCGOpcode, TCGArg); +void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); +void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); +void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg= ); =20 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1)); + tcg_gen_op1(opc, GET_TCGV_I32(a1)); } =20 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1)); + tcg_gen_op1(opc, GET_TCGV_I64(a1)); } =20 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) { - tcg_gen_op1(&tcg_ctx, opc, a1); + tcg_gen_op1(opc, a1); } =20 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); + tcg_gen_op2(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); } =20 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); + tcg_gen_op2(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); } =20 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2); + tcg_gen_op2(opc, GET_TCGV_I32(a1), a2); } =20 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2); + tcg_gen_op2(opc, GET_TCGV_I64(a1), a2); } =20 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, a1, a2); + tcg_gen_op2(opc, a1, a2); } =20 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), - GET_TCGV_I32(a2), GET_TCGV_I32(a3)); + tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3)); } =20 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), - GET_TCGV_I64(a2), GET_TCGV_I64(a3)); + tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3)); } =20 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); + tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); } =20 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); + tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); } =20 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset); } =20 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset); } =20 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4)); } =20 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4)); } =20 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), a4); + tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3),= a4); } =20 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), a4); + tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3),= a4); } =20 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); + tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); } =20 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); + tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); } =20 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); } =20 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); } =20 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); } =20 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); } =20 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4, a5); } =20 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGv_i64 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4, a5); } =20 @@ -202,7 +195,7 @@ static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_= i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGv_i32 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), GET_TCGV_I32(a6)); } @@ -211,7 +204,7 @@ static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_= i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGv_i64 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), GET_TCGV_I64(a6)); } @@ -220,7 +213,7 @@ static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv= _i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); } =20 @@ -228,7 +221,7 @@ static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv= _i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); } =20 @@ -236,7 +229,7 @@ static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCG= v_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); } =20 @@ -244,7 +237,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCG= v_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); } =20 @@ -253,12 +246,12 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, T= CGv_i64 a1, TCGv_i64 a2, =20 static inline void gen_set_label(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l)); + tcg_gen_op1(INDEX_op_set_label, label_arg(l)); } =20 static inline void tcg_gen_br(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); + tcg_gen_op1(INDEX_op_br, label_arg(l)); } =20 void tcg_gen_mb(TCGBar); @@ -732,25 +725,24 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret,= TCGv_i64 lo, TCGv_i64 hi) # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc); + tcg_gen_op1(INDEX_op_insn_start, pc); } # else static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, - (uint32_t)pc, (uint32_t)(pc >> 32)); + tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); } # endif #elif TARGET_INSN_START_WORDS =3D=3D 2 # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1); + tcg_gen_op2(INDEX_op_insn_start, pc, a1); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op4(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32)); } @@ -760,13 +752,13 @@ static inline void tcg_gen_insn_start(target_ulong pc= , target_ulong a1) static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2); + tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op6(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32), (uint32_t)a2, (uint32_t)(a2 >> 32)); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bd84a782e3..bff4b95097 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -46,8 +46,9 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); Up to and including filling in the forward link immediately. We'll do proper termination of the end of the list after we finish translation. = */ =20 -static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc) +static inline TCGOp *tcg_emit_op(TCGOpcode opc) { + TCGContext *ctx =3D &tcg_ctx; int oi =3D ctx->gen_next_op_idx; int ni =3D oi + 1; int pi =3D oi - 1; @@ -65,42 +66,40 @@ static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOp= code opc) return op; } =20 -void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1) +void tcg_gen_op1(TCGOpcode opc, TCGArg a1) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; } =20 -void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2) +void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; op->args[1] =3D a2; } =20 -void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1, - TCGArg a2, TCGArg a3) +void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; op->args[1] =3D a2; op->args[2] =3D a3; } =20 -void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1, - TCGArg a2, TCGArg a3, TCGArg a4) +void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; op->args[1] =3D a2; op->args[2] =3D a3; op->args[3] =3D a4; } =20 -void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1, - TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5) +void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, + TCGArg a4, TCGArg a5) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; op->args[1] =3D a2; op->args[2] =3D a3; @@ -108,10 +107,10 @@ void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGA= rg a1, op->args[4] =3D a5; } =20 -void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, - TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6) +void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, + TCGArg a4, TCGArg a5, TCGArg a6) { - TCGOp *op =3D tcg_emit_op(ctx, opc); + TCGOp *op =3D tcg_emit_op(opc); op->args[0] =3D a1; op->args[1] =3D a2; op->args[2] =3D a3; @@ -123,7 +122,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, void tcg_gen_mb(TCGBar mb_type) { if (parallel_cpus) { - tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); + tcg_gen_op1(INDEX_op_mb, mb_type); } } =20 @@ -2458,7 +2457,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_LOW(arg)); } else if (TCG_TARGET_HAS_extrl_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrl_i64_i32, + tcg_gen_op2(INDEX_op_extrl_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); @@ -2470,7 +2469,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); } else if (TCG_TARGET_HAS_extrh_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrh_i64_i32, + tcg_gen_op2(INDEX_op_extrh_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { TCGv_i64 t =3D tcg_temp_new_i64(); @@ -2486,7 +2485,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_extu_i32_i64, + tcg_gen_op2(INDEX_op_extu_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2497,7 +2496,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_ext_i32_i64, + tcg_gen_op2(INDEX_op_ext_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2609,7 +2608,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), = oi); + tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi); } #endif } @@ -2622,7 +2621,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), = oi); + tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi); } #else if (TCG_TARGET_REG_BITS =3D=3D 32) { --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175393145840.9258663405341; Mon, 16 Oct 2017 10:36:33 -0700 (PDT) Received: from localhost ([::1]:34336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49JT-000241-7j for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH v6 16/50] tcg: Push tcg_ctx into tcg_gen_callN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- include/exec/helper-gen.h | 12 ++++++------ tcg/tcg.h | 3 +-- tcg/tcg.c | 4 ++-- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 8239ffc77c..476acd9220 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -9,7 +9,7 @@ #define DEF_HELPER_FLAGS_0(name, flags, ret) \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -17,7 +17,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1)) \ { \ TCGArg args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -25,7 +25,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ TCGArg args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -33,7 +33,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ TCGArg args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -43,7 +43,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -53,7 +53,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ } =20 #include "helper.h" diff --git a/tcg/tcg.h b/tcg/tcg.h index 563e7d36aa..0d61932301 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -951,8 +951,7 @@ do {\ =20 bool tcg_op_supported(TCGOpcode op); =20 -void tcg_gen_callN(TCGContext *s, void *func, - TCGArg ret, int nargs, TCGArg *args); +void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args); =20 void tcg_op_remove(TCGContext *s, TCGOp *op); TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int n= arg); diff --git a/tcg/tcg.c b/tcg/tcg.c index b39944d42a..113700ccc1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -974,9 +974,9 @@ bool tcg_op_supported(TCGOpcode op) /* Note: we convert the 64 bit args to 32 bit and do some alignment and endian swap. Maybe it would be better to do the alignment and endian swap in tcg_reg_alloc_call(). */ -void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, - int nargs, TCGArg *args) +void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args) { + TCGContext *s =3D &tcg_ctx; int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175492841896.9839633415362; Mon, 16 Oct 2017 10:38:12 -0700 (PDT) Received: from localhost ([::1]:34341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49L8-0003Nj-2S for importer@patchew.org; Mon, 16 Oct 2017 13:38:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49A1-0002Dm-EC for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e499z-0003Wk-ES for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:41 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:49548) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e499z-0003WG-6O for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:39 -0400 Received: by mail-pf0-x229.google.com with SMTP id i5so3201637pfe.6 for ; Mon, 16 Oct 2017 10:26:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=92fYPmyDY0Oeji9Zv0dqXtG7mvhGw3J9iH8TfLx4JI8=; b=cZT81WGrKt94lRn2A1QUNPt05trfgieEA4lvS4QgSQ5xo+jMweY8FFm6Mibm/l3ub3 ICTaNX1MMIOpXxxQ2XIOY6E5FNrbIi4lxuNIP3or0FHIVxFf6/uxbcyFedfh4BvqKFZR 9syJ3eK0vrUobtKMsNTW98zEAOZ0EyUfUY7vI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=92fYPmyDY0Oeji9Zv0dqXtG7mvhGw3J9iH8TfLx4JI8=; b=gPhaUnDDEeebe9M8jxie+9BuuX+CJbVi9+UpTUple4uZQIZksrv6iOlJ436NyWs0QP 2i1HUm2iYCU9oKKkql/5tRbNwz4BwrMwP6proP/k1YpoAS6w1MZRqdqSlqRAgbEAlXac 9Jc8qHSfq701ZG5d08BmONOB6vVoQEG1D1ySdx+aabUerNxDzzVCIgQ7DcwrM8qf3I0Y m4JGWrN7C3T868cRlhOPbp7UmaMu00iD+5xpwOIf90de4Hylfwj6hAMnBjwknp7TVmaF uvkvTlt1HEcRMeGwMPutvq+P+UXqTGVEvnioG0YxUxoIgimTH6LhmpnlXJXVEXr+ayAi Jylg== X-Gm-Message-State: AMCzsaWHRxvy2kOFB8rLqNX4eENGxTTMwhw5VkiRFqm1HhAcZharqjHO VrEbDFJAUNq5x1QTOEf/VKvZ5tZTbN0= X-Google-Smtp-Source: AOwi7QCKs9jWw1/MuB46Xyhw+LxiDT+tms8uWDyD8nl7HLdPMy2jW49K/3BtYS9Tau6x9P19Yw/TgQ== X-Received: by 10.84.171.195 with SMTP id l61mr9416774plb.64.1508174797617; Mon, 16 Oct 2017 10:26:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:36 -0700 Message-Id: <20171016172609.23422-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PATCH v6 17/50] tcg: Introduce index_arg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For multi-threaded tcg we have one TCGContext per thread. With that, plus static cpu_* variables, we need the translators to handle indicies. We transform those to "arguments" at opcode generating time. For now, that transformation is a no-op. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg-op.h | 92 ++++++++++++++++++++++++++++++--------------------------= ---- tcg/tcg.h | 20 +++++++++++++ tcg/tcg-op.c | 14 ++++----- tcg/tcg.c | 26 ++++++++--------- 4 files changed, 86 insertions(+), 66 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index de9a61206a..ca1a3becb9 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -37,12 +37,12 @@ void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCG= Arg, TCGArg, TCGArg); =20 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) { - tcg_gen_op1(opc, GET_TCGV_I32(a1)); + tcg_gen_op1(opc, tcgv_i32_arg(a1)); } =20 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) { - tcg_gen_op1(opc, GET_TCGV_I64(a1)); + tcg_gen_op1(opc, tcgv_i64_arg(a1)); } =20 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) @@ -52,22 +52,22 @@ static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a= 1) =20 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { - tcg_gen_op2(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); + tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); } =20 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { - tcg_gen_op2(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); + tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); } =20 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { - tcg_gen_op2(opc, GET_TCGV_I32(a1), a2); + tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); } =20 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { - tcg_gen_op2(opc, GET_TCGV_I64(a1), a2); + tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); } =20 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) @@ -78,167 +78,167 @@ static inline void tcg_gen_op2ii(TCGOpcode opc, TCGAr= g a1, TCGArg a2) static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3) { - tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3)); + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); } =20 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { - tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3)); + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); } =20 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3) { - tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); } =20 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3) { - tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); } =20 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset); + tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); } =20 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset); + tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); } =20 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4) { - tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4)); + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4)); } =20 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4) { - tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4)); + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4)); } =20 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGArg a4) { - tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3),= a4); + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3),= a4); } =20 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGArg a4) { - tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3),= a4); + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3),= a4); } =20 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); } =20 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); } =20 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { - tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); } =20 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { - tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); } =20 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { - tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); } =20 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { - tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); } =20 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), a4, a5); + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), a4, a5); } =20 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGv_i64 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), a4, a5); + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), a4, a5); } =20 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGv_i32 a6) { - tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), - GET_TCGV_I32(a6)); + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), + tcgv_i32_arg(a6)); } =20 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGv_i64 a6) { - tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), - GET_TCGV_I64(a6)); + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), + tcgv_i64_arg(a6)); } =20 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGArg a6) { - tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); } =20 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGArg a6) { - tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); } =20 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), - GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); } =20 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), - GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); } =20 =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 0d61932301..b8ede7fe5c 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -756,6 +756,26 @@ static inline size_t arg_index(TCGArg a) return a; } =20 +static inline TCGArg index_arg(size_t n) +{ + return n; +} + +static inline TCGArg tcgv_i32_arg(TCGv_i32 t) +{ + return index_arg(GET_TCGV_I32(t)); +} + +static inline TCGArg tcgv_i64_arg(TCGv_i64 t) +{ + return index_arg(GET_TCGV_I64(t)); +} + +static inline TCGArg tcgv_ptr_arg(TCGv_ptr t) +{ + return index_arg(GET_TCGV_PTR(t)); +} + static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { tcg_ctx.gen_op_buf[op_idx].args[arg] =3D v; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bff4b95097..be4b623e82 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2458,7 +2458,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) tcg_gen_mov_i32(ret, TCGV_LOW(arg)); } else if (TCG_TARGET_HAS_extrl_i64_i32) { tcg_gen_op2(INDEX_op_extrl_i64_i32, - GET_TCGV_I32(ret), GET_TCGV_I64(arg)); + tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } else { tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); } @@ -2470,7 +2470,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); } else if (TCG_TARGET_HAS_extrh_i64_i32) { tcg_gen_op2(INDEX_op_extrh_i64_i32, - GET_TCGV_I32(ret), GET_TCGV_I64(arg)); + tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } else { TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, arg, 32); @@ -2486,7 +2486,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { tcg_gen_op2(INDEX_op_extu_i32_i64, - GET_TCGV_I64(ret), GET_TCGV_I32(arg)); + tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } } =20 @@ -2497,7 +2497,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } else { tcg_gen_op2(INDEX_op_ext_i32_i64, - GET_TCGV_I64(ret), GET_TCGV_I32(arg)); + tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } } =20 @@ -2563,7 +2563,7 @@ void tcg_gen_lookup_and_goto_ptr(void) if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); - tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); + tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } else { tcg_gen_exit_tb(0); @@ -2608,7 +2608,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi); + tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi); } #endif } @@ -2621,7 +2621,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi); + tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi); } #else if (TCG_TARGET_REG_BITS =3D=3D 32) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 113700ccc1..129aecca60 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1054,25 +1054,25 @@ void tcg_gen_callN(void *func, TCGArg ret, int narg= s, TCGArg *args) two return temporaries, and reassemble below. */ retl =3D tcg_temp_new_i64(); reth =3D tcg_temp_new_i64(); - op->args[pi++] =3D GET_TCGV_I64(reth); - op->args[pi++] =3D GET_TCGV_I64(retl); + op->args[pi++] =3D tcgv_i64_arg(reth); + op->args[pi++] =3D tcgv_i64_arg(retl); nb_rets =3D 2; } else { - op->args[pi++] =3D ret; + op->args[pi++] =3D index_arg(ret); nb_rets =3D 1; } #else if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { #ifdef HOST_WORDS_BIGENDIAN - op->args[pi++] =3D ret + 1; - op->args[pi++] =3D ret; + op->args[pi++] =3D index_arg(ret + 1); + op->args[pi++] =3D index_arg(ret); #else - op->args[pi++] =3D ret; - op->args[pi++] =3D ret + 1; + op->args[pi++] =3D index_arg(ret); + op->args[pi++] =3D index_arg(ret + 1); #endif nb_rets =3D 2; } else { - op->args[pi++] =3D ret; + op->args[pi++] =3D index_arg(ret); nb_rets =3D 1; } #endif @@ -1103,17 +1103,17 @@ void tcg_gen_callN(void *func, TCGArg ret, int narg= s, TCGArg *args) have to get more complicated to differentiate between stack arguments and register arguments. */ #if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) - op->args[pi++] =3D args[i] + 1; - op->args[pi++] =3D args[i]; + op->args[pi++] =3D index_arg(args[i] + 1); + op->args[pi++] =3D index_arg(args[i]); #else - op->args[pi++] =3D args[i]; - op->args[pi++] =3D args[i] + 1; + op->args[pi++] =3D index_arg(args[i]); + op->args[pi++] =3D index_arg(args[i] + 1); #endif real_args +=3D 2; continue; } =20 - op->args[pi++] =3D args[i]; + op->args[pi++] =3D index_arg(args[i]); real_args++; } op->args[pi++] =3D (uintptr_t)func; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175420057444.7286034476268; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W/uVhJTBBm1QQTcQZ5J5hpaa/mYKhmO+eNQ749BoQnc=; b=gFW2XShd8C6UDw3abz56YyC3V96r5EK01BVi4ld5vfTaAF1RJI+zQxPVyGl2yW0V72 YNCYe0iJxR8nKQ11MJtI2wHP+XKYFgZ8ggn7koheX7yQTrsF57YKkeRJHeJFancBHyCH +tOGq5iYxlFqVo8OhnKUFDLV88AcukPXaNjg8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W/uVhJTBBm1QQTcQZ5J5hpaa/mYKhmO+eNQ749BoQnc=; b=mB9zxhsmIzCfhnmvyXUxKyiomZQDpR4h5TXPhbuNBcis0DZnWHgocpAqerSs0vQU5e QLlUiRqHYLG18s3vhxhipQoKcVvVw1CwXDvfkcNo8PMSRX1NHvKUfDAgDcbmjO07Q0Gv v8Vxsj1FJT8My3YwHEA77BZ7yaG/2tYChIgWP+mb5mv+6fo+j30Fqj5DXJGpgyW4NAJU Kafj6HIO80iSJP8Bd0qtfEKbGmrpAsxjgd4bDD/tgJXIu1vIWMPKsHNxL3TcMqqF+z/b pphoRtYD9Q+XuKYdgZf6/nozjwWaMe3HOQwcxkwYNc93RguvZ8JnCkjaG/CG0+dgm4q9 g/cQ== X-Gm-Message-State: AMCzsaV+2WHY+Y9nYrramsVZ8y0BU5pjCbKC50kV9yyVN6ymU72yK6YU iTwWaB8wbxd5cshqghJxOsJ+VfvVbgQ= X-Google-Smtp-Source: AOwi7QAde+ThUnfKOzgm4ez6HN4ak7CwTBr/Jy2Vl6H7dZ4OIWZC51y8Skc/R3ICsFz97NN4ptxfDw== X-Received: by 10.159.208.2 with SMTP id a2mr9709858plp.370.1508174798617; Mon, 16 Oct 2017 10:26:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:37 -0700 Message-Id: <20171016172609.23422-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PATCH v6 18/50] tcg: Reserve temporary index 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since we cast indicies to pointers, reserving 0 allows us to use NULL for unused/dummy instead of (T *)-1. Signed-off-by: Richard Henderson --- tcg/tcg.h | 16 ++++++++-------- tcg/tcg.c | 5 ++++- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index b8ede7fe5c..ccf1bcdaf6 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -471,13 +471,13 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(T= CGv_ptr t) #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) =3D=3D GET_TCGV_PTR(b)) =20 /* Dummy definition to avoid compiler warnings. */ -#define TCGV_UNUSED_I32(x) x =3D MAKE_TCGV_I32(-1) -#define TCGV_UNUSED_I64(x) x =3D MAKE_TCGV_I64(-1) -#define TCGV_UNUSED_PTR(x) x =3D MAKE_TCGV_PTR(-1) +#define TCGV_UNUSED_I32(x) ((x) =3D NULL) +#define TCGV_UNUSED_I64(x) ((x) =3D NULL) +#define TCGV_UNUSED_PTR(x) ((x) =3D NULL) =20 -#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) =3D=3D -1) -#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) =3D=3D -1) -#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) =3D=3D -1) +#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) =3D=3D 0) +#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) =3D=3D 0) +#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) =3D=3D 0) =20 /* call flags */ /* Helper does not read globals (either directly or through an exception).= It @@ -496,7 +496,7 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCG= v_ptr t) #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) =20 /* used to align parameters */ -#define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) +#define TCG_CALL_DUMMY_ARG ((TCGArg)0) =20 /* Conditions. Note that these are laid out for easy manipulation by the functions below: @@ -737,7 +737,7 @@ extern bool parallel_cpus; static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n =3D ts - tcg_ctx.temps; - tcg_debug_assert(n >=3D 0 && n < tcg_ctx.nb_temps); + tcg_debug_assert(n > 0 && n < tcg_ctx.nb_temps); return n; } =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 129aecca60..7cf39f7067 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -333,7 +333,10 @@ void tcg_context_init(TCGContext *s) int *sorted_args; =20 memset(s, 0, sizeof(*s)); - s->nb_globals =3D 0; + /* Reserve temp index 0 so that, with the funny casting that we do, + the first one doesn't look like NULL. */ + s->nb_globals =3D 1; + s->nb_temps =3D 1; =20 /* Count total number of arguments and allocate the corresponding space */ --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176188096627.0190770234366; Mon, 16 Oct 2017 10:49:48 -0700 (PDT) Received: from localhost ([::1]:34387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49WK-0004e5-BN for importer@patchew.org; Mon, 16 Oct 2017 13:49:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49A2-0002EZ-9T for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49A1-0003YL-Ij for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:42 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:52539) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49A1-0003Xq-CZ for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:41 -0400 Received: by mail-pg0-x22f.google.com with SMTP id a192so5918766pge.9 for ; Mon, 16 Oct 2017 10:26:41 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v6 19/50] target/alpha: Avoid translate_init unless tcg_enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8a21f4e01..b52ebd7356 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -260,7 +260,9 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr =3D env; tlb_flush(cs); =20 - alpha_translate_init(); + if (tcg_enabled()) { + alpha_translate_init(); + } =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175736325440.88014948924604; Mon, 16 Oct 2017 10:42:16 -0700 (PDT) Received: from localhost ([::1]:34358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Oy-0006di-Ca for importer@patchew.org; Mon, 16 Oct 2017 13:42:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49A6-0002KX-Jf for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49A3-0003Zn-Mw for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:46 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:54129) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49A3-0003Z7-Bd for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:43 -0400 Received: by mail-pg0-x234.google.com with SMTP id s2so7346584pge.10 for ; Mon, 16 Oct 2017 10:26:43 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IONFb2XJk+VDbXqkgo7RAVhmeHix+0CIeS5n+r84MQs=; b=Z4X1fZpaD6tPaKi5w8ehJZ9vYmKlGYCHZTsmQOXnNLPFP0/cEhVZx/d1AxA3LrmVVu bsJdGeC3GfAwRoZH6OXcht7TUbq0E7sddsUva1JfT18IUj/lXD4PDWzyB3ia8Gz2YlCL HFxvoWf5BB++CSOxlTu9xcFjQBB7UHSWFCSKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IONFb2XJk+VDbXqkgo7RAVhmeHix+0CIeS5n+r84MQs=; b=TN1/sFSW/D3YbZvqpJyPxdwI6RZsOGeU+jvhozj+rFO+3J8M7nRLwEgM4LnsIxoikP OiRQc0nwzmL4FjeCOFWZQPNjLHP9lJW3vPlHtSgocBNbRaQkgQ4iGI/9bn9PW0HKXFc2 xPj8RCaptabsajUEDyEQuApicdJ6OASbvO8GJB5TNvxdzy3PQUDAF9Wy1DpwXyN+D0AJ sdRl1FUFlOaoKvbVQTyy3ylJ3c+5zsGyr2fn4gsevmWFHp3hrxc51hxZazlo0yjE+vw7 xyrXG6GoqXIabU0HRAhRw6HUBw4c0TrDVYid6g5QiHdiU9CV2ERZu/euMWTgGJGzCqxW UfqQ== X-Gm-Message-State: AMCzsaWStVZa2+mSDP5bKEd2NYtQIi+pMFHGnzJlP30LvK97gcsfcYW3 2YRaqpUS4OU4gII9N/YTSjHv46B7XxE= X-Google-Smtp-Source: AOwi7QBYunlwpbsdTaRVKhv7PygRKERxAudhrDMT++z/L27aqi6oYwJV3Z6qm+Mx29KgMdPAXAn7ig== X-Received: by 10.159.208.5 with SMTP id a5mr9745636plp.436.1508174801733; Mon, 16 Oct 2017 10:26:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:39 -0700 Message-Id: <20171016172609.23422-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v6 20/50] qom: Introduce CPUClass.tcg_initialize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Cc: Andreas F=C3=A4rber Signed-off-by: Richard Henderson Acked-by: Andreas F=C3=A4rber Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qom/cpu.h | 8 ++++++-- target/sparc/cpu.h | 2 +- exec.c | 7 ++++++- target/alpha/cpu.c | 5 +---- target/alpha/translate.c | 6 ------ target/arm/cpu.c | 6 +----- target/cris/cpu.c | 16 ++++++---------- target/hppa/cpu.c | 3 +-- target/hppa/translate.c | 6 ------ target/i386/cpu.c | 5 +---- target/i386/translate.c | 6 ------ target/lm32/cpu.c | 7 +------ target/m68k/cpu.c | 7 +------ target/microblaze/cpu.c | 7 +------ target/mips/cpu.c | 5 +---- target/mips/translate.c | 7 ------- target/moxie/cpu.c | 7 +------ target/moxie/translate.c | 6 ------ target/nios2/cpu.c | 7 +------ target/openrisc/cpu.c | 7 +------ target/ppc/translate.c | 6 ------ target/ppc/translate_init.c | 5 +---- target/s390x/cpu.c | 7 +------ target/sh4/cpu.c | 5 +---- target/sh4/translate.c | 7 ------- target/sparc/cpu.c | 5 +---- target/sparc/translate.c | 9 +-------- target/tilegx/cpu.c | 7 +------ target/tricore/cpu.c | 5 +---- target/tricore/translate.c | 5 +---- target/unicore32/cpu.c | 7 +------ target/xtensa/cpu.c | 7 +------ 32 files changed, 40 insertions(+), 165 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 0efebdbcf4..df0ba86202 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -195,10 +195,8 @@ typedef struct CPUClass { void *opaque); =20 const struct VMStateDescription *vmsd; - int gdb_num_core_regs; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); - bool gdb_stop_before_watchpoint; =20 void (*cpu_exec_enter)(CPUState *cpu); void (*cpu_exec_exit)(CPUState *cpu); @@ -206,6 +204,12 @@ typedef struct CPUClass { =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); + void (*tcg_initialize)(void); + + /* Keep non-pointer data at the end to minimize holes. */ + int gdb_num_core_regs; + bool gdb_stop_before_watchpoint; + bool tcg_initialized; } CPUClass; =20 #ifdef HOST_WORDS_BIGENDIAN diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 1598f65927..bf2b8931cc 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -594,7 +594,7 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, =20 =20 /* translate.c */ -void gen_intermediate_code_init(CPUSPARCState *env); +void sparc_tcg_init(void); =20 /* cpu-exec.c */ =20 diff --git a/exec.c b/exec.c index 6378714a2b..30a1a9fb79 100644 --- a/exec.c +++ b/exec.c @@ -763,10 +763,15 @@ void cpu_exec_initfn(CPUState *cpu) =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { - CPUClass *cc ATTRIBUTE_UNUSED =3D CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 cpu_list_add(cpu); =20 + if (tcg_enabled() && !cc->tcg_initialized) { + cc->tcg_initialized =3D true; + cc->tcg_initialize(); + } + #ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b52ebd7356..bc9520535b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -260,10 +260,6 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr =3D env; tlb_flush(cs); =20 - if (tcg_enabled()) { - alpha_translate_init(); - } - env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) env->flags =3D ENV_FLAG_PS_USER | ENV_FLAG_FEN; @@ -301,6 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) dc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; + cc->tcg_initialize =3D alpha_translate_init; =20 cc->gdb_num_core_regs =3D 67; } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f32c95b9a1..3c8d1dc333 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -124,14 +124,8 @@ void alpha_translate_init(void) }; #endif =20 - static bool done_init =3D 0; int i; =20 - if (done_init) { - return; - } - done_init =3D 1; - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 88578f360e..056284985d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -534,7 +534,6 @@ static void arm_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); ARMCPU *cpu =3D ARM_CPU(obj); - static bool inited; =20 cs->env_ptr =3D &cpu->env; cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, @@ -578,10 +577,6 @@ static void arm_cpu_initfn(Object *obj) =20 if (tcg_enabled()) { cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ - if (!inited) { - inited =3D true; - arm_translate_init(); - } } } =20 @@ -1765,6 +1760,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #endif =20 cc->disas_set_info =3D arm_disas_set_info; + cc->tcg_initialize =3D arm_translate_init; } =20 static void cpu_register(const ARMCPUInfo *info) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 88d93f2d11..527a3448bf 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -181,7 +181,6 @@ static void cris_cpu_initfn(Object *obj) CRISCPU *cpu =3D CRIS_CPU(obj); CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; - static bool tcg_initialized; =20 cs->env_ptr =3D env; =20 @@ -191,15 +190,6 @@ static void cris_cpu_initfn(Object *obj) /* IRQ and NMI lines. */ qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); #endif - - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized =3D true; - if (env->pregs[PR_VR] < 32) { - cris_initialize_crisv10_tcg(); - } else { - cris_initialize_tcg(); - } - } } =20 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) @@ -210,6 +200,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 8; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; + cc->tcg_initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -220,6 +211,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 9; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; + cc->tcg_initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -230,6 +222,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 10; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; + cc->tcg_initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -240,6 +233,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 11; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; + cc->tcg_initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) @@ -250,6 +244,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 17; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; + cc->tcg_initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) @@ -322,6 +317,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; =20 cc->disas_set_info =3D cris_disas_set_info; + cc->tcg_initialize =3D cris_initialize_tcg; } =20 static const TypeInfo cris_cpu_type_info =3D { diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a477b452f0..9e7b0d4ccb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -108,8 +108,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr =3D env; cpu_hppa_loaded_fr0(env); set_snan_bit_is_one(true, &env->fp_status); - - hppa_translate_init(); } =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) @@ -136,6 +134,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; cc->disas_set_info =3D hppa_cpu_disas_set_info; + cc->tcg_initialize =3D hppa_translate_init; =20 cc->gdb_num_core_regs =3D 128; } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 26242f4b3c..334ee74e4c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -124,14 +124,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; =20 - static bool done_init =3D 0; int i; =20 - if (done_init) { - return; - } - done_init =3D 1; - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 98732cd65f..53ec94ac9b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3719,10 +3719,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 - if (tcg_enabled()) { - tcg_x86_init(); - } - #ifndef CONFIG_USER_ONLY qemu_register_reset(x86_cpu_machine_reset_cb, cpu); =20 @@ -4216,6 +4212,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #endif cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; =20 dc->user_creatable =3D true; } diff --git a/target/i386/translate.c b/target/i386/translate.c index 5d61fa96ad..51860c8db2 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8329,12 +8329,6 @@ void tcg_x86_init(void) "bnd0_ub", "bnd1_ub", "bnd2_ub", "bnd3_ub" }; int i; - static bool initialized; - - if (initialized) { - return; - } - initialized =3D true; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bf081f56d2..7f3a292f2b 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -163,16 +163,10 @@ static void lm32_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); LM32CPU *cpu =3D LM32_CPU(obj); CPULM32State *env =3D &cpu->env; - static bool tcg_initialized; =20 cs->env_ptr =3D env; =20 env->flags =3D 0; - - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized =3D true; - lm32_translate_init(); - } } =20 static void lm32_basic_cpu_initfn(Object *obj) @@ -286,6 +280,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; + cc->tcg_initialize =3D lm32_translate_init; } =20 static void lm32_register_cpu_type(const LM32CPUInfo *info) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 8c70e0805c..5da19e570b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -247,14 +247,8 @@ static void m68k_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); M68kCPU *cpu =3D M68K_CPU(obj); CPUM68KState *env =3D &cpu->env; - static bool inited; =20 cs->env_ptr =3D env; - - if (tcg_enabled() && !inited) { - inited =3D true; - m68k_tcg_init(); - } } =20 static const VMStateDescription vmstate_m68k_cpu =3D { @@ -288,6 +282,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; + cc->tcg_initialize =3D m68k_tcg_init; =20 cc->gdb_num_core_regs =3D 18; cc->gdb_core_xml_file =3D "cf-core.xml"; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index ddffe86e9b..5700652e06 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -205,7 +205,6 @@ static void mb_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); CPUMBState *env =3D &cpu->env; - static bool tcg_initialized; =20 cs->env_ptr =3D env; =20 @@ -215,11 +214,6 @@ static void mb_cpu_initfn(Object *obj) /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); #endif - - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized =3D true; - mb_tcg_init(); - } } =20 static const VMStateDescription vmstate_mb_cpu =3D { @@ -289,6 +283,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_num_core_regs =3D 32 + 5; =20 cc->disas_set_info =3D mb_disas_set_info; + cc->tcg_initialize =3D mb_tcg_init; } =20 static const TypeInfo mb_cpu_type_info =3D { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c15b894362..0ae70288dd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -150,10 +150,6 @@ static void mips_cpu_initfn(Object *obj) =20 cs->env_ptr =3D env; env->cpu_model =3D mcc->cpu_def; - - if (tcg_enabled()) { - mips_tcg_init(); - } } =20 static char *mips_cpu_type_name(const char *cpu_model) @@ -202,6 +198,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; + cc->tcg_initialize =3D mips_tcg_init; =20 cc->gdb_num_core_regs =3D 73; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/mips/translate.c b/target/mips/translate.c index ac05f3aa09..ef07fa827e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20453,11 +20453,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fp= rintf_function cpu_fprintf, void mips_tcg_init(void) { int i; - static int inited; - - /* Initialize various static tables. */ - if (inited) - return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; @@ -20506,8 +20501,6 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); - - inited =3D 1; } =20 #include "translate_init.c" diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 30bd44fcad..24ab3f3708 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -77,14 +77,8 @@ static void moxie_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); MoxieCPU *cpu =3D MOXIE_CPU(obj); - static int inited; =20 cs->env_ptr =3D &cpu->env; - - if (tcg_enabled() && !inited) { - inited =3D 1; - moxie_translate_init(); - } } =20 static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) @@ -122,6 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; + cc->tcg_initialize =3D moxie_translate_init; } =20 static void moxielite_initfn(Object *obj) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 3cfd232558..eaf5103920 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -94,7 +94,6 @@ void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_= function cpu_fprintf, void moxie_translate_init(void) { int i; - static int done_init; static const char * const gregnames[16] =3D { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", @@ -102,9 +101,6 @@ void moxie_translate_init(void) "$r10", "$r11", "$r12", "$r13" }; =20 - if (done_init) { - return; - } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, @@ -118,8 +114,6 @@ void moxie_translate_init(void) offsetof(CPUMoxieState, cc_a), "cc_a"); cc_b =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, cc_b), "cc_b"); - - done_init =3D 1; } =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 5b02fb67ea..4742e52c78 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -69,18 +69,12 @@ static void nios2_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); Nios2CPU *cpu =3D NIOS2_CPU(obj); CPUNios2State *env =3D &cpu->env; - static bool tcg_initialized; =20 cs->env_ptr =3D env; =20 #if !defined(CONFIG_USER_ONLY) mmu_init(env); #endif - - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized =3D true; - nios2_tcg_init(); - } } =20 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) @@ -215,6 +209,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 49; + cc->tcg_initialize =3D nios2_tcg_init; } =20 static const TypeInfo nios2_cpu_type_info =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index af9cdcc102..2b5a59061c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -87,18 +87,12 @@ static void openrisc_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); - static int inited; =20 cs->env_ptr =3D &cpu->env; =20 #ifndef CONFIG_USER_ONLY cpu_openrisc_mmu_init(cpu); #endif - - if (tcg_enabled() && !inited) { - inited =3D 1; - openrisc_translate_init(); - } } =20 /* CPU models */ @@ -170,6 +164,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) dc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; + cc->tcg_initialize =3D openrisc_translate_init; } =20 static void cpu_register(const OpenRISCCPUInfo *info) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 606b605ba0..770b461704 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -84,10 +84,6 @@ void ppc_translate_init(void) int i; char* p; size_t cpu_reg_names_size; - static int done_init =3D 0; - - if (done_init) - return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; @@ -191,8 +187,6 @@ void ppc_translate_init(void) =20 cpu_access_type =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUPPCState, access_= type), "access_type"); - - done_init =3D 1; } =20 /* internal defines */ diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index c6399a3a0d..4397254dbf 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -10661,10 +10661,6 @@ static void ppc_cpu_initfn(Object *obj) env->sps =3D (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : def= sps_4k; } #endif /* defined(TARGET_PPC64) */ - - if (tcg_enabled()) { - ppc_translate_init(); - } } =20 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) @@ -10742,6 +10738,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif + cc->tcg_initialize =3D ppc_translate_init; =20 dc->fw_name =3D "PowerPC,UNKNOWN"; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3fdf9bae70..74b64032f4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -235,7 +235,6 @@ static void s390_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); S390CPU *cpu =3D S390_CPU(obj); CPUS390XState *env =3D &cpu->env; - static bool inited; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif @@ -253,11 +252,6 @@ static void s390_cpu_initfn(Object *obj) env->cpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, c= pu); s390_cpu_set_state(CPU_STATE_STOPPED, cpu); #endif - - if (tcg_enabled() && !inited) { - inited =3D true; - s390x_translate_init(); - } } =20 static void s390_cpu_finalize(Object *obj) @@ -498,6 +492,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #endif #endif cc->disas_set_info =3D s390_cpu_disas_set_info; + cc->tcg_initialize =3D s390x_translate_init; =20 cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; cc->gdb_core_xml_file =3D "s390x-core64.xml"; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 252440e019..89abce2472 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -258,10 +258,6 @@ static void superh_cpu_initfn(Object *obj) cs->env_ptr =3D env; =20 env->movcal_backup_tail =3D &(env->movcal_backup); - - if (tcg_enabled()) { - sh4_translate_init(); - } } =20 static const VMStateDescription vmstate_sh_cpu =3D { @@ -297,6 +293,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; + cc->tcg_initialize =3D sh4_translate_init; =20 cc->gdb_num_core_regs =3D 59; =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8db9fba26e..b4e4fd3782 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -81,7 +81,6 @@ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond; void sh4_translate_init(void) { int i; - static int done_init =3D 0; static const char * const gregnames[24] =3D { "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", @@ -100,10 +99,6 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; =20 - if (done_init) { - return; - } - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 @@ -163,8 +158,6 @@ void sh4_translate_init(void) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, fregs[= i]), fregnames[i]); - - done_init =3D 1; } =20 void superh_cpu_dump_state(CPUState *cs, FILE *f, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index beab90f3e6..47d0927707 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -784,10 +784,6 @@ static void sparc_cpu_initfn(Object *obj) =20 cs->env_ptr =3D env; =20 - if (tcg_enabled()) { - gen_intermediate_code_init(env); - } - if (scc->cpu_def) { env->def =3D *scc->cpu_def; } @@ -891,6 +887,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; + cc->tcg_initialize =3D sparc_tcg_init; =20 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs =3D 86; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6290705b11..f63d7fb6ab 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5862,9 +5862,8 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) #endif } =20 -void gen_intermediate_code_init(CPUSPARCState *env) +void sparc_tcg_init(void) { - static int inited; static const char gregnames[32][4] =3D { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", @@ -5917,12 +5916,6 @@ void gen_intermediate_code_init(CPUSPARCState *env) =20 unsigned int i; =20 - /* init various static tables */ - if (inited) { - return; - } - inited =3D 1; - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 7345f5a8b5..2ef8ea7daa 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -103,14 +103,8 @@ static void tilegx_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); TileGXCPU *cpu =3D TILEGX_CPU(obj); CPUTLGState *env =3D &cpu->env; - static bool tcg_initialized; =20 cs->env_ptr =3D env; - - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized =3D true; - tilegx_tcg_init(); - } } =20 static void tilegx_cpu_do_interrupt(CPUState *cs) @@ -161,6 +155,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->set_pc =3D tilegx_cpu_set_pc; cc->handle_mmu_fault =3D tilegx_cpu_handle_mmu_fault; cc->gdb_num_core_regs =3D 0; + cc->tcg_initialize =3D tilegx_tcg_init; } =20 static const TypeInfo tilegx_cpu_type_info =3D { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 871eb35453..cd93806d47 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -109,10 +109,6 @@ static void tricore_cpu_initfn(Object *obj) CPUTriCoreState *env =3D &cpu->env; =20 cs->env_ptr =3D env; - - if (tcg_enabled()) { - tricore_tcg_init(); - } } =20 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) @@ -182,6 +178,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->set_pc =3D tricore_cpu_set_pc; cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_attrs_debug =3D tricore_cpu_get_phys_page_attrs_debu= g; + cc->tcg_initialize =3D tricore_tcg_init; } =20 static void cpu_register(const TriCoreCPUInfo *info) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 4e4198e887..b6cfbdfa9f 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8880,10 +8880,7 @@ static void tricore_tcg_init_csfr(void) void tricore_tcg_init(void) { int i; - static int inited; - if (inited) { - return; - } + cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; /* reg init */ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 138acc9dd8..526604ff78 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -117,7 +117,6 @@ static void uc32_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); UniCore32CPU *cpu =3D UNICORE32_CPU(obj); CPUUniCore32State *env =3D &cpu->env; - static bool inited; =20 cs->env_ptr =3D env; =20 @@ -130,11 +129,6 @@ static void uc32_cpu_initfn(Object *obj) #endif =20 tlb_flush(cs); - - if (tcg_enabled() && !inited) { - inited =3D true; - uc32_translate_init(); - } } =20 static const VMStateDescription vmstate_uc32_cpu =3D { @@ -162,6 +156,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) #else cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; #endif + cc->tcg_initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index dcdc765a86..a5651e5dab 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -121,7 +121,6 @@ static void xtensa_cpu_initfn(Object *obj) XtensaCPU *cpu =3D XTENSA_CPU(obj); XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; - static bool tcg_inited; =20 cs->env_ptr =3D env; env->config =3D xcc->config; @@ -131,11 +130,6 @@ static void xtensa_cpu_initfn(Object *obj) memory_region_init_io(env->system_er, NULL, NULL, env, "er", UINT64_C(0x100000000)); address_space_init(env->address_space_er, env->system_er, "ER"); - - if (tcg_enabled() && !tcg_inited) { - tcg_inited =3D true; - xtensa_translate_init(); - } } =20 static const VMStateDescription vmstate_xtensa_cpu =3D { @@ -170,6 +164,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->do_unassigned_access =3D xtensa_cpu_do_unassigned_access; #endif cc->debug_excp_handler =3D xtensa_breakpoint_handler; + cc->tcg_initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; } =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CKzrL3nrIbxNWEEUClAtJxQyYcnjHcU6IGSZwQDG0YE=; b=ZbTWWpez/7DqTR8WXo+ltznZXYs9OmU3R+UH5rU84ya2DUIN7B7HogfD6xuwfq6kWm nPGsmgNYvf3aIZcJcD4cFj2EPB5+eSz94aw2b4RiVsWcmWUF9cYRGcGAez5FT7tO6pCk UVKjVU+hlnrkB2vnD1hLBH1ypBfkrP9/Gq7RY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CKzrL3nrIbxNWEEUClAtJxQyYcnjHcU6IGSZwQDG0YE=; b=k3AHD6tsF9fijXwmtBf/iHOcZY1zoR0okmK3hSHEQqtLtKghTWZA13KxUzhZs6fr0R pZooFlY2FBqlYdp9ipUHYwl2jSSBSOC7ekku2j52seOHkoj3zwCYxBEEXt9Sx3Qo9ym6 5Kt0LBugcTunuqwu6dJVUMvCICrkA7mQuCzvPZnTexla2rikzOuF1ck9yxytf8Yng+oE loUy504IDNe8NcWYyDz+AMNautDtgMS6afkOysESOiVHJ2qI5XeRZomkk6BqhaaDtbxJ tSBC/ExO8mYNIjU6NGL+Fqg/iOz1eQGMH6o95PmMpk5z3Yo1gTKzAlLmwz9NkQLtyDiQ DOag== X-Gm-Message-State: AMCzsaVgr7PKagMd6pg9hJ7CglZinp3yDPKaFyZXCbpinIk87zkKkXho 0uWn7SPovacdPPuFvC5XOKWkEZJmlXo= X-Google-Smtp-Source: AOwi7QC3Z/FY+BnS6jKqPTduZxfObGkI8KKn5gWhXR9qi16D1PYGqj/dHuWDWdJPsyXhBF032pwP3A== X-Received: by 10.159.207.131 with SMTP id z3mr9724184plo.191.1508174803241; Mon, 16 Oct 2017 10:26:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:40 -0700 Message-Id: <20171016172609.23422-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v6 21/50] tcg: Use pointers in TCGOp->args X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This limits the indexing into tcg_ctx.temps to initial opcode generation time. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index ccf1bcdaf6..d5bf61b1cf 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -741,24 +741,29 @@ static inline size_t temp_idx(TCGTemp *ts) return n; } =20 +static inline TCGTemp *idx_temp(size_t n) +{ + return n =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[n]; +} + static inline TCGArg temp_arg(TCGTemp *ts) { - return temp_idx(ts); + return (uintptr_t)ts; } =20 static inline TCGTemp *arg_temp(TCGArg a) { - return a =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; + return (TCGTemp *)a; } =20 static inline size_t arg_index(TCGArg a) { - return a; + return temp_idx(arg_temp(a)); } =20 static inline TCGArg index_arg(size_t n) { - return n; + return temp_arg(idx_temp(n)); } =20 static inline TCGArg tcgv_i32_arg(TCGv_i32 t) --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175752649728.7240444008661; Mon, 16 Oct 2017 10:42:32 -0700 (PDT) Received: from localhost ([::1]:34359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49PH-0006vM-Pf for importer@patchew.org; Mon, 16 Oct 2017 13:42:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49A8-0002Ma-JJ for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49A6-0003bw-M3 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:48 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:47608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49A6-0003bH-DH for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:46 -0400 Received: by mail-pf0-x22a.google.com with SMTP id z11so16297869pfk.4 for ; Mon, 16 Oct 2017 10:26:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4KOSZmF6KY2F5O3AWX8XxXx225xmKmTHj8EK9B+6V/c=; b=EbFE2CNYNmhGk6tGdDVfHdF4Cif50NcIrH2/o7szGaqmNkNuwwVLasVzLlNzRhkk6o ewXwjd75LRB89Xx/fkXVsxcVf8VTypbuZjw8TmFJXn+UWk2Ne1y4h6Mk/3m2H+IVKoHR Yw5/4e8/OkCDHAYI/jp+XtMtyfo9cmjncFR3A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4KOSZmF6KY2F5O3AWX8XxXx225xmKmTHj8EK9B+6V/c=; b=OV1eyCI7XDXH439YWbuzIXYNdiusPm3Wz3wtSifzUMa2oc3YMMrg1itbIqhQzuGvA/ Y41Qpa7Pz1yvDHE3CQ8LEewtaanpY8+m4IYi66l0OAzy3tY4LRgKtTNhMN5eGrS8btQQ 56EX25dLhM4sYz6MRiYv9HyTctlRBSz/0zCBYLZxYfM+shYfd+cN801h6QblGKR/DvHq KGvFP4u1YDOQh0XRX+vRg5b85lUnvITyUpRYCDGtyNN0JFKFjTmLbdWEh8unIWziTqjM L37OpRlTdCWXnjfbIMahoV2BnY/AjTPGO70US25+qvxXpiHxZtvq4BTaHZzeJmXeoF6V gZig== X-Gm-Message-State: AMCzsaUZoP2hDBq2tTtN2t/yI4YZU2cDqsBjOC1JPNvzhsQLSsS7Tz3p HIT1IFdeOWUWqERCGfTvvc2i5YKSfP8= X-Google-Smtp-Source: AOwi7QDbbdZ3M4G/LVc88lzMXKCuTYULOLEfJFWvHz8ZU9ZrQlaVsKt5YQslJKMpEVe+2I0DEJ13FA== X-Received: by 10.84.198.131 with SMTP id p3mr9625895pld.245.1508174805016; Mon, 16 Oct 2017 10:26:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:41 -0700 Message-Id: <20171016172609.23422-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v6 22/50] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This will enable us to decouple code translation from the value of parallel_cpus at any given time. It will also help us minimize TB flushes when generating code via EXCP_ATOMIC. Note that the declaration of parallel_cpus is brought to exec-all.h to be able to define there the "curr_cflags" inline. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 20 +++++++++++++++++++- include/exec/tb-hash-xx.h | 9 ++++++--- include/exec/tb-hash.h | 4 ++-- include/exec/tb-lookup.h | 6 +++--- tcg/tcg.h | 1 - accel/tcg/cpu-exec.c | 45 +++++++++++++++++++++++--------------------= -- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 13 +++++++++---- exec.c | 2 +- tests/qht-bench.c | 2 +- 10 files changed, 65 insertions(+), 39 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 53f1835c43..352abc7450 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -325,6 +325,9 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ +#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ +/* cflags' mask for hashing/comparison */ +#define CF_HASH_MASK (CF_PARALLEL) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; @@ -365,11 +368,26 @@ struct TranslationBlock { uintptr_t jmp_list_first; }; =20 +extern bool parallel_cpus; + +/* Hide the atomic_read to make code a little easier on the eyes */ +static inline uint32_t tb_cflags(const TranslationBlock *tb) +{ + return atomic_read(&tb->cflags); +} + +/* current cflags for hashing/comparison */ +static inline uint32_t curr_cflags(void) +{ + return parallel_cpus ? CF_PARALLEL : 0; +} + void tb_free(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags); + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); =20 /* GETPC is the true target of the return instruction that we'll execute. = */ diff --git a/include/exec/tb-hash-xx.h b/include/exec/tb-hash-xx.h index 6cd3022c07..747a9a612c 100644 --- a/include/exec/tb-hash-xx.h +++ b/include/exec/tb-hash-xx.h @@ -48,8 +48,8 @@ * xxhash32, customized for input variables that are not guaranteed to be * contiguous in memory. */ -static inline -uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f) +static inline uint32_t +tb_hash_func7(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f, uint32_t g) { uint32_t v1 =3D TB_HASH_XX_SEED + PRIME32_1 + PRIME32_2; uint32_t v2 =3D TB_HASH_XX_SEED + PRIME32_2; @@ -78,7 +78,7 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) v4 *=3D PRIME32_1; =20 h32 =3D rol32(v1, 1) + rol32(v2, 7) + rol32(v3, 12) + rol32(v4, 18); - h32 +=3D 24; + h32 +=3D 28; =20 h32 +=3D e * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; @@ -86,6 +86,9 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) h32 +=3D f * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; =20 + h32 +=3D g * PRIME32_3; + h32 =3D rol32(h32, 17) * PRIME32_4; + h32 ^=3D h32 >> 15; h32 *=3D PRIME32_2; h32 ^=3D h32 >> 13; diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h index 17b5ee0edf..0526c4f678 100644 --- a/include/exec/tb-hash.h +++ b/include/exec/tb-hash.h @@ -59,9 +59,9 @@ static inline unsigned int tb_jmp_cache_hash_func(target_= ulong pc) =20 static inline uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t fl= ags, - uint32_t trace_vcpu_dstate) + uint32_t cf_mask, uint32_t trace_vcpu_dstate) { - return tb_hash_func6(phys_pc, pc, flags, trace_vcpu_dstate); + return tb_hash_func7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate); } =20 #endif diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 436b6d5ecf..296138591a 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -21,7 +21,7 @@ /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock * tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, - uint32_t *flags) + uint32_t *flags, uint32_t cf_mask) { CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; @@ -35,10 +35,10 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, t= arget_ulong *cs_base, tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - !(atomic_read(&tb->cflags) & CF_INVALID))) { + (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) =3D=3D cf_mas= k)) { return tb; } - tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask); if (tb =3D=3D NULL) { return NULL; } diff --git a/tcg/tcg.h b/tcg/tcg.h index d5bf61b1cf..5e1170b299 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -732,7 +732,6 @@ struct TCGContext { }; =20 extern TCGContext tcg_ctx; -extern bool parallel_cpus; =20 static inline size_t temp_idx(TCGTemp *ts) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 363dfa208a..39ec9508d1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -207,7 +207,8 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, tb_lock(); tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles | CF_NOCACHE - | (ignore_icount ? CF_IGNORE_ICOUNT : 0)); + | (ignore_icount ? CF_IGNORE_ICOUNT : 0) + | curr_cflags()); tb->orig_tb =3D orig_tb; tb_unlock(); =20 @@ -225,31 +226,27 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, static void cpu_exec_step(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; + uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { - mmap_lock(); - tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, - 1 | CF_NOCACHE | CF_IGNORE_ICOUNT); - tb->orig_tb =3D NULL; - tb_unlock(); - mmap_unlock(); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, + cflags & CF_HASH_MASK); + if (tb =3D=3D NULL) { + mmap_lock(); + tb_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb_unlock(); + mmap_unlock(); + } =20 cc->cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb_nocache(tb, pc); + trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); - - tb_lock(); - tb_phys_invalidate(tb, -1); - tb_free(tb); - tb_unlock(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -281,6 +278,7 @@ struct tb_desc { CPUArchState *env; tb_page_addr_t phys_page1; uint32_t flags; + uint32_t cf_mask; uint32_t trace_vcpu_dstate; }; =20 @@ -294,7 +292,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !(atomic_read(&tb->cflags) & CF_INVALID)) { + (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) =3D=3D desc->cf_mask= ) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; @@ -313,7 +311,8 @@ static bool tb_cmp(const void *p, const void *d) } =20 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags) + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask) { tb_page_addr_t phys_pc; struct tb_desc desc; @@ -322,11 +321,12 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, tar= get_ulong pc, desc.env =3D (CPUArchState *)cpu->env_ptr; desc.cs_base =3D cs_base; desc.flags =3D flags; + desc.cf_mask =3D cf_mask; desc.trace_vcpu_dstate =3D *cpu->trace_dstate; desc.pc =3D pc; phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; - h =3D tb_hash_func(phys_pc, pc, flags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); } =20 @@ -373,8 +373,9 @@ static inline TranslationBlock *tb_find(CPUState *cpu, target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; + uint32_t cf_mask =3D curr_cflags(); =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { /* mmap_lock is needed by tb_gen_code, and mmap_lock must be * taken outside tb_lock. As system emulation is currently @@ -387,10 +388,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu, /* There's a chance that our desired tb has been translated while * taking the locks so we check again inside the lock. */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); if (likely(tb =3D=3D NULL)) { /* if no translated code available, then translate it now */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cf_mask); } =20 mmap_unlock(); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 54d89100d9..25f0cabfed 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -151,7 +151,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) target_ulong cs_base, pc; uint32_t flags; =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb =3D=3D NULL) { return tcg_ctx.code_gen_epilogue; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5ce99d549..1271944ae8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1101,7 +1101,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, + tb->trace_vcpu_dstate); qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); =20 /* remove the TB from the page list */ @@ -1245,7 +1246,8 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, + tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 #ifdef CONFIG_USER_ONLY @@ -1548,7 +1550,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t sta= rt, tb_page_addr_t end, /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, + 1 | curr_cflags()); cpu_loop_exit_noexc(cpu); } #endif @@ -1666,7 +1669,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t ad= dr, uintptr_t pc) /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, + 1 | curr_cflags()); /* tb_lock will be reset after cpu_loop_exit_noexc longjmps * back into the cpu_exec loop. */ return true; @@ -1810,6 +1814,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) } =20 cflags =3D n | CF_LAST_IO; + cflags |=3D curr_cflags(); pc =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; diff --git a/exec.c b/exec.c index 30a1a9fb79..5d43d9541f 100644 --- a/exec.c +++ b/exec.c @@ -2435,7 +2435,7 @@ static void check_watchpoint(int offset, int len, Mem= TxAttrs attrs, int flags) cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); + tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cfla= gs()); cpu_loop_exit_noexc(cpu); } } diff --git a/tests/qht-bench.c b/tests/qht-bench.c index 11c1cec766..4cabdfd62a 100644 --- a/tests/qht-bench.c +++ b/tests/qht-bench.c @@ -103,7 +103,7 @@ static bool is_equal(const void *obj, const void *userp) =20 static inline uint32_t h(unsigned long v) { - return tb_hash_func6(v, 0, 0, 0); + return tb_hash_func7(v, 0, 0, 0, 0); } =20 /* --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150817558534990.91240156564288; Mon, 16 Oct 2017 10:39:45 -0700 (PDT) Received: from localhost ([::1]:34346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ma-0004fx-HY for importer@patchew.org; Mon, 16 Oct 2017 13:39:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49A8-0002MU-Gd for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49A7-0003ci-Pb for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:48 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:54267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49A7-0003cF-JK for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:47 -0400 Received: by mail-pf0-x22b.google.com with SMTP id t188so13793979pfd.10 for ; Mon, 16 Oct 2017 10:26:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VRiKczW003TPQXKPZ0Vbsvn24QSHkBE9hREgv3VRI1c=; b=EkmrCE8zapzN55q4B+lewAXE/3DQK1rGGDZEMLtRUdTQ1tKtByjhQIoGu+G9niC7ja bOACwK4xsnRMW1SpuytSCdaFhOAxynPqpSNeCPxBzhZ1+3NaQNOM81xAgH+WNfjNyVLa +MM8S3cbdDTU6TRcrP1FBwL9cMDvNfcu5TBkA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VRiKczW003TPQXKPZ0Vbsvn24QSHkBE9hREgv3VRI1c=; b=kuZeqgOwcvfMm0Nn7h6UNacalNuzzHIwhOlAPjTfIflSjP03e8tmQ/KtM8zP/hxLt5 QzeQrfQlZGSFNLf0WZKcWN0FDvqA2IlUZG19iJjz2AlpyMyE9RYiBFwbRYtzke+CR93g prwKU40T5sA2OS2pTsOuL3J0hYvxFISqAhwrvBOMEbakygyte8fu8vjSi1l4CmQKu5Tk ggMWn1QJQqJd2ar6DgM1OVeklWy8kZAOqR5Fpcer7djf7l8eZi55ZIbPh2RSYuEUg+jH lhcHuQf+TS5nTTKbJ0Kfr/B1dRMNWt4J2Pob5sqMfcVzBj5dKvPmqy7MAhR/nDhymyDQ mxBg== X-Gm-Message-State: AMCzsaVXJ0HXpwO+MDGDiPjbcIY9FbLkcajCcJkv/8Pnsz2/tJRQhW2/ V/LZK+tswmVRa2IdVot7HAjFBFOvdj8= X-Google-Smtp-Source: AOwi7QDehbYdPEiqgrX9b8GnTYzQKLcEYxyLQKtDDumxlnrBmbMtedUuHH96kx0QISfQnNsPPwwBBg== X-Received: by 10.98.17.202 with SMTP id 71mr9380843pfr.142.1508174806401; Mon, 16 Oct 2017 10:26:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:42 -0700 Message-Id: <20171016172609.23422-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH v6 23/50] hack dump tb->flags and tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" --- accel/tcg/cpu-exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 39ec9508d1..99f1d519c5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -146,9 +146,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) uint8_t *tb_ptr =3D itb->tc.ptr; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, - "Trace %p [%d: " TARGET_FMT_lx "] %s\n", + "Trace %p [%d: " TARGET_FMT_lx ", %x, %x] %s\n", itb->tc.ptr, cpu->cpu_index, itb->pc, - lookup_symbol(itb->pc)); + itb->flags, itb->cflags, lookup_symbol(itb->pc)= ); =20 #if defined(DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_CPU) --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176361720167.1331179910867; Mon, 16 Oct 2017 10:52:41 -0700 (PDT) Received: from localhost ([::1]:34401 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Z4-00076g-V1 for importer@patchew.org; Mon, 16 Oct 2017 13:52:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52456) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AA-0002OE-C6 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49A9-0003da-3t for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:50 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:54267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49A8-0003d7-Sl for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:49 -0400 Received: by mail-pf0-x22c.google.com with SMTP id t188so13794023pfd.10 for ; Mon, 16 Oct 2017 10:26:48 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sJo+iGomDG5NL/43UhVM4Ppm/0mTQM65rKN2jIeYUSc=; b=UoU8LvrKNygT5NSnI4AJ4vYq4V4InDnH1r/CN7f8kGx9/ztMjT/77CNH2WLp6nIfqS yNC9Ne9zzFzGVAPGzdsTXGBg84ytr3TDmIrW+bGMpKXcr8h6fhDeaKF/0uVxcFuvTBYL xUpSsieutK5LD/QWHKrAspr3v5ujrI19lwuPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sJo+iGomDG5NL/43UhVM4Ppm/0mTQM65rKN2jIeYUSc=; b=DFOQj8zwMRJFHJpXcX3m9GEBSzP9o9LOmvQ77byTVWbz7BDsL7JmLUbudnkvAodUba +BMeyrmOUuV5oIQkpHD7N1FC0Ll3WH5YpqTmTd6z/ftWwlA+Z8T0x5vtBhV/hkBIlenP iY3NkCi6eQBy0jaz/ZM7uZIWioMEl/5DZL2+3LQ0kKlDVMw5uYHr/zkuuoqSL4rlunnz /DE8tiZJJSJ9le+s0E4spo4V9jSExAWwmvhzG6z4Np5AMBqyI+0tYnttRwZ7B5vS0ao5 mSnET8hXm7IAMZt1GQ+C/GTr9cFDp1LP61OghNMdAA0s4rKji4cpmBsrKXDzjffcElyb fCqw== X-Gm-Message-State: AMCzsaUPXaIYRjLF1ftTRnkCbjd2SFkd8ge/saTRd+zUHRn2uh2DnhFI rA+fdAui6k6TmfnAYzRuJGo9Ke+4uh4= X-Google-Smtp-Source: AOwi7QCiFttcS7MqufjM2glxx4frxF14q0OYQJktiQYBYKmJVHapaVlAvh96HfH5zxSm30+U4u8qdg== X-Received: by 10.159.211.7 with SMTP id bc7mr9700708plb.425.1508174807699; Mon, 16 Oct 2017 10:26:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:43 -0700 Message-Id: <20171016172609.23422-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH v6 24/50] tcg: Add CPUState step_next_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were generating code during tb_invalidate_phys_page_range and check_watchpoint, and (seemingly) discarding the TB, assuming that it would magically be picked up during the next iteration through the cpu_exec loop. Instead, set a flag in CPUState so that we set cflags to properly request a TB with a single guest insn so that there is no more magic. Signed-off-by: Richard Henderson --- include/qom/cpu.h | 1 + accel/tcg/cpu-exec.c | 19 +++++++++++++++---- accel/tcg/translate-all.c | 18 ++++-------------- exec.c | 6 +----- 4 files changed, 21 insertions(+), 23 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index df0ba86202..1fb165a43c 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -344,6 +344,7 @@ struct CPUState { bool unplug; bool crash_occurred; bool exit_request; + bool step_next_tb; /* updates protected by BQL */ uint32_t interrupt_request; int singlestep_enabled; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 99f1d519c5..df410a8d6e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -367,13 +367,12 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, =20 static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, - int tb_exit) + int tb_exit, uint32_t cf_mask) { TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; - uint32_t cf_mask =3D curr_cflags(); =20 tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { @@ -501,7 +500,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) } else if (replay_has_exception() && cpu->icount_decr.u16.low + cpu->icount_extra =3D=3D 0) { /* try to cause an exception pending in the log */ - cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0), true); + cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), tru= e); *ret =3D -1; return true; #endif @@ -697,7 +696,19 @@ int cpu_exec(CPUState *cpu) int tb_exit =3D 0; =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { - TranslationBlock *tb =3D tb_find(cpu, last_tb, tb_exit); + uint32_t cf_mask =3D curr_cflags(); + TranslationBlock *tb; + + /* For precise smc, we generate a block containing just the + instruction modifying the memory, ensuring that it cannot + modify itself. We also need to single-step past a + stop-after-access watchpoint. */ + if (cpu->step_next_tb) { + cf_mask |=3D 1; + cpu->step_next_tb =3D false; + } + + tb =3D tb_find(cpu, last_tb, tb_exit, cf_mask); cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1271944ae8..a7415c8661 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1463,14 +1463,12 @@ void tb_invalidate_phys_page_range(tb_page_addr_t s= tart, tb_page_addr_t end, int is_cpu_write_access) { TranslationBlock *tb, *tb_next; -#if defined(TARGET_HAS_PRECISE_SMC) - CPUState *cpu =3D current_cpu; - CPUArchState *env =3D NULL; -#endif tb_page_addr_t tb_start, tb_end; PageDesc *p; int n; #ifdef TARGET_HAS_PRECISE_SMC + CPUState *cpu =3D current_cpu; + CPUArchState *env =3D NULL; int current_tb_not_found =3D is_cpu_write_access; TranslationBlock *current_tb =3D NULL; int current_tb_modified =3D 0; @@ -1547,11 +1545,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t st= art, tb_page_addr_t end, #endif #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { - /* we generate a block containing just the instruction - modifying the memory. It will ensure that it cannot modify - itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, - 1 | curr_cflags()); + cpu->step_next_tb =3D true; cpu_loop_exit_noexc(cpu); } #endif @@ -1666,11 +1660,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t a= ddr, uintptr_t pc) p->first_tb =3D NULL; #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { - /* we generate a block containing just the instruction - modifying the memory. It will ensure that it cannot modify - itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, - 1 | curr_cflags()); + cpu->step_next_tb =3D true; /* tb_lock will be reset after cpu_loop_exit_noexc longjmps * back into the cpu_exec loop. */ return true; diff --git a/exec.c b/exec.c index 5d43d9541f..a9737ba5e9 100644 --- a/exec.c +++ b/exec.c @@ -2390,11 +2390,8 @@ static void check_watchpoint(int offset, int len, Me= mTxAttrs attrs, int flags) { CPUState *cpu =3D current_cpu; CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu->env_ptr; - target_ulong pc, cs_base; target_ulong vaddr; CPUWatchpoint *wp; - uint32_t cpu_flags; =20 assert(tcg_enabled()); if (cpu->watchpoint_hit) { @@ -2434,8 +2431,7 @@ static void check_watchpoint(int offset, int len, Mem= TxAttrs attrs, int flags) cpu->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cpu); } else { - cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cfla= gs()); + cpu->step_next_tb =3D true; cpu_loop_exit_noexc(cpu); } } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175895306240.35853346133626; Mon, 16 Oct 2017 10:44:55 -0700 (PDT) Received: from localhost ([::1]:34366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Rb-0000QD-Im for importer@patchew.org; Mon, 16 Oct 2017 13:44:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AB-0002P6-A5 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AA-0003eR-ED for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:51 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:45356) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AA-0003e4-8O for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:50 -0400 Received: by mail-pf0-x22f.google.com with SMTP id d28so16307464pfe.2 for ; Mon, 16 Oct 2017 10:26:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cM3365VCpQ9z81Wh/bl09YMwsCGOpw96BCbOfolWxcA=; b=H2cKlubnqmQUV0X+nLEojYRFkoRzHOMQty8ZuFzaxzFlS0R0QFzOhZfNbx2y5cAOgY I73xp/ekhmgfG7TGR0xhIwTA2Xf/nZk2ZR1EULbDG2ePTxWGr/jOjQ4T4+BG2tklVe2f Kf+MtM8wYgMau+LEvKjxSCgC1lqYS19/spedw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cM3365VCpQ9z81Wh/bl09YMwsCGOpw96BCbOfolWxcA=; b=rMn+Jmzuc2xf2q5yw2cgDt+AsXbxBZP1MO927f/HuyO9mpXho+Hf99mYgfuZuWFFvU qhhkgQRMmuRdUKGKKgiy1FMUtrCor1Ny+1+HOUbYT7/10IIe3KfpT1PSAPxdY2WSTsaq Wt0mBB1+SxzPLWUizFGhp/9okfnIGdkNJPRBgZh1NFsa6qH+22PlF1JFaN51Ei4Iqog/ mE+8CqIysiTQSrbqV3AXNMXmOFbW7jVBnnBYEc9/pLKP50Z0kCkstFzATx9/XqSeaK3v oNW6+3o+iPWvDFRsqCiVa7MwdMXK6h+wiVDbvgHOFHkn/KDVzJyGZucDSFf1tG71GTD4 I6Tw== X-Gm-Message-State: AMCzsaVvUgi/FXU3zZJcwj2Ej0daA8BKXDgB6pJatkTgbAPtPW+RKELf G9IIvPmsh3wernfnuC2UFnAoiiWcpzI= X-Google-Smtp-Source: AOwi7QAKqUGZqPs1bsAFScZlRuwTPIdhYWHbW5Ux1X9Wumh3zvF7RhI4SUmuMjIJemxTshyDenK21g== X-Received: by 10.84.135.101 with SMTP id 92mr9657914pli.180.1508174809172; Mon, 16 Oct 2017 10:26:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:44 -0700 Message-Id: <20171016172609.23422-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH v6 25/50] tcg: Include CF_COUNT_MASK in CF_HASH_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 352abc7450..0fdb72bb22 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -327,7 +327,7 @@ struct TranslationBlock { #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ #define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ /* cflags' mask for hashing/comparison */ -#define CF_HASH_MASK (CF_PARALLEL) +#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175907643699.1817971511468; Mon, 16 Oct 2017 10:45:07 -0700 (PDT) Received: from localhost ([::1]:34368 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Rd-0000Qf-JB for importer@patchew.org; Mon, 16 Oct 2017 13:44:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AH-0002Wo-Cu for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AC-0003g1-U9 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:57 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:46253) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AC-0003fT-Gq for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:52 -0400 Received: by mail-pf0-x235.google.com with SMTP id p87so16295701pfj.3 for ; Mon, 16 Oct 2017 10:26:52 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AGUyEKSJAcrEkwgnab2mR61mPgzHbHM+d2dXxvqAYno=; b=DARwxK9szzv5IVq1g4pBlKMSma6DnMjf0EV95ggoRk65eCQIChfF6IsyD0ajnlM/ls Z7qrCUcG6xeJ0XPu6sAmeR+jnrvX5ao3f7y/YqkeeIVMcwv/Cm2nzxr3NPzGO1V3mHyM M6QhSxh8RpuG5d2puA3dBAQIz/xrQAHKmBxWg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AGUyEKSJAcrEkwgnab2mR61mPgzHbHM+d2dXxvqAYno=; b=QFDfVHAgFqCVfW4pQBHRlPAKrVyy+7YyMhK9lL9CXbmIjJgrcw+zvlulR5/u9I7NWv G31C3xdzBnYZZtDSZ9P9f2OX5XvuON/8xE/KtiQvOV/dREKSW+VLY7jl8gnt3cAwYsj5 z6afsJFqA+U3o8z9cFg0TAZujmZUagVMvSpvP8laGh+aNQPaTqpX0tfX9pHo02qGx4rb bKJHA0Iw/ICpM5pFF33GlOQRO3wABKg29SLSn1xIMkBMVykFE4SB2ThB9vQN8O0/wTt+ +q93D1wSzKTHr4gqNqkgEYzfSDSPcOn3QIk6l7k9ddS1a2QH2KkakRGOHF0V+sMbUhpx 7WCg== X-Gm-Message-State: AMCzsaW+bgiw1CupSNQwRti+Fl37genviSpwKQgmNkXn7xZA4LJmIRDe 0nCBiHHCDTONZFOk73eA08M1C/brvvk= X-Google-Smtp-Source: AOwi7QAzqfd/tu9susrtB8fosCZcDE+wL9UTlhaMLz69Nzyovp0uH2AlrcqRCTVBpmKyg/l0YDanqQ== X-Received: by 10.98.64.207 with SMTP id f76mr9275314pfd.279.1508174810743; Mon, 16 Oct 2017 10:26:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:45 -0700 Message-Id: <20171016172609.23422-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PATCH v6 26/50] tcg: convert tb->cflags reads to tb_cflags(tb) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=3D$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 8 ++++---- accel/tcg/translator.c | 4 ++-- target/alpha/translate.c | 4 ++-- target/arm/translate-a64.c | 7 ++++--- target/arm/translate.c | 6 +++--- target/cris/translate.c | 6 +++--- target/hppa/translate.c | 2 +- target/i386/translate.c | 48 +++++++++++++++++++++------------------= ---- target/lm32/translate.c | 14 ++++++------- target/m68k/translate.c | 6 +++--- target/microblaze/translate.c | 6 +++--- target/mips/translate.c | 26 +++++++++++------------ target/moxie/translate.c | 2 +- target/nios2/translate.c | 6 +++--- target/openrisc/translate.c | 6 +++--- target/ppc/translate.c | 6 +++--- target/ppc/translate_init.c | 32 ++++++++++++++--------------- target/s390x/translate.c | 8 ++++---- target/sh4/translate.c | 6 +++--- target/sparc/translate.c | 6 +++--- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 6 +++--- target/xtensa/translate.c | 28 ++++++++++++------------- 24 files changed, 124 insertions(+), 123 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9b3cb14dfa..48b566c1c9 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -13,7 +13,7 @@ static inline void gen_tb_start(TranslationBlock *tb) TCGv_i32 count, imm; =20 exitreq_label =3D gen_new_label(); - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { count =3D tcg_temp_local_new_i32(); } else { count =3D tcg_temp_new_i32(); @@ -22,7 +22,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_ld_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { imm =3D tcg_temp_new_i32(); /* We emit a movi with a dummy immediate argument. Keep the insn i= ndex * of the movi so that we later (when we know the actual insn coun= t) @@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } @@ -46,7 +46,7 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know * the actual insn count. */ tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index afa3af478a..23c6602cd9 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -45,7 +45,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, db->singlestep_enabled =3D cpu->singlestep_enabled; =20 /* Instruction counting */ - max_insns =3D db->tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -95,7 +95,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D max_insns && (db->tb->cflags & CF_LAST_IO= )) { + if (db->num_insns =3D=3D max_insns && (tb_cflags(db->tb) & CF_LAST= _IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 3c8d1dc333..53b8c036e2 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -455,7 +455,7 @@ static bool in_superpage(DisasContext *ctx, int64_t add= r) =20 static bool use_exit_tb(DisasContext *ctx) { - return ((ctx->base.tb->cflags & CF_LAST_IO) + return ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_enabled || singlestep); } @@ -2399,7 +2399,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) case 0xC000: /* RPCC */ va =3D dest_gpr(ctx, ra); - if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a39b9d3633..e9bee8c196 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -348,7 +348,8 @@ static inline bool use_goto_tb(DisasContext *s, int n, = uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags = & CF_LAST_IO)) { + if (s->base.singlestep_enabled || s->ss_active || + (tb_cflags(s->base.tb) & CF_LAST_IO)) { return false; } =20 @@ -1561,7 +1562,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { gen_io_start(); } =20 @@ -1592,7 +1593,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } } =20 - if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->base.is_jmp =3D DISAS_UPDATE; diff --git a/target/arm/translate.c b/target/arm/translate.c index 4da1a4cbc6..dfa547b1db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7704,7 +7704,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) break; } =20 - if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { + if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { gen_io_start(); } =20 @@ -7795,7 +7795,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { + if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -12253,7 +12253,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + if (tb_cflags(dc->base.tb) & CF_LAST_IO && dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. = */ cpu_abort(cpu, "IO on conditional branch instruction"); } diff --git a/target/cris/translate.c b/target/cris/translate.c index 38a999e6f1..07ec2b1831 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3141,7 +3141,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -3171,7 +3171,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } dc->clear_x =3D 1; @@ -3244,7 +3244,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 npc =3D dc->pc; =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); /* Force an update if the per-tb cpu state has changed. */ if (dc->is_jmp =3D=3D DISAS_NEXT diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 334ee74e4c..460b4d3154 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -469,7 +469,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx) static bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Suppress goto_tb in the case of single-steping and IO. */ - if ((ctx->base.tb->cflags & CF_LAST_IO) || ctx->base.singlestep_enable= d) { + if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_ena= bled) { return false; } return true; diff --git a/target/i386/translate.c b/target/i386/translate.c index 51860c8db2..f60582082e 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -1117,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1132,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1152,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -6301,7 +6301,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6316,7 +6316,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6332,14 +6332,14 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6353,14 +6353,14 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6371,14 +6371,14 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6391,14 +6391,14 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7106,11 +7106,11 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7565,11 +7565,11 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7934,24 +7934,24 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8415,7 +8415,7 @@ static int i386_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cpu, record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT= ); + dc->repz_opt =3D !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICO= UNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8481,7 +8481,7 @@ static void i386_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cpu) the flag and abort the translation to give the irqs a chance to happen */ dc->base.is_jmp =3D DISAS_TOO_MANY; - } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + } else if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 65bc9c0bf6..d4a2e00165 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -880,24 +880,24 @@ static void dec_wcsr(DisasContext *dc) break; case CSR_IM: /* mark as an io operation because it could cause an interrupt */ - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp =3D DISAS_UPDATE; break; case CSR_IP: /* mark as an io operation because it could cause an interrupt */ - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp =3D DISAS_UPDATE; @@ -1078,7 +1078,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1106,7 +1106,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1119,7 +1119,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) && (dc->pc < next_page_start) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d738f32f9c..d199105559 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5547,7 +5547,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->done_mac =3D 0; dc->writeback_mask =3D 0; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5573,7 +5573,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5585,7 +5585,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) (pc_offset) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); if (unlikely(cs->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 067b0878d6..c70a2d6644 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1666,7 +1666,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1701,7 +1701,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1763,7 +1763,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) npc =3D dc->jmp_pc; } =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); /* Force an update if the per-tb cpu state has changed. */ if (dc->is_jmp =3D=3D DISAS_NEXT diff --git a/target/mips/translate.c b/target/mips/translate.c index ef07fa827e..aadffbec39 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5327,11 +5327,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5734,7 +5734,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS32); =20 - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -6401,7 +6401,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) trace_mips_translate_c0("mtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -6679,11 +6679,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -7072,7 +7072,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS64); =20 - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -7727,7 +7727,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) trace_mips_translate_c0("dmtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -10756,11 +10756,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, = int rd, int sel) gen_store_gpr(t0, rt); break; case 2: - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdhwr_cc(t0, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_store_gpr(t0, rt); @@ -20248,7 +20248,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -20274,7 +20274,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -20335,7 +20335,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) if (singlestep) break; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (cs->singlestep_enabled && ctx.bstate !=3D BS_BRANCH) { diff --git a/target/moxie/translate.c b/target/moxie/translate.c index eaf5103920..3f1e609028 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -832,7 +832,7 @@ void gen_intermediate_code(CPUState *cs, struct Transla= tionBlock *tb) ctx.singlestep_enabled =3D 0; ctx.bstate =3D BS_NONE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6b0961837d..507d04e573 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -827,7 +827,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlo= ck *tb) max_insns =3D 1; } else { int page_insns =3D (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)= ) / 4; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -854,7 +854,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlo= ck *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -871,7 +871,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlo= ck *tb) !tcg_op_buf_full() && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 112db1ad0f..666d050650 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1546,7 +1546,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -1589,7 +1589,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } disas_openrisc_insn(dc, cpu); @@ -1612,7 +1612,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) && (dc->pc < next_page_start) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 770b461704..5e637d2e97 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7261,7 +7261,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) msr_se =3D 1; #endif num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -7289,7 +7289,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) LOG_DISAS("----------------\n"); LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", ctx.nip, ctx.mem_idx, (int)msr_ir); - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) gen_io_start(); if (unlikely(need_byteswap(&ctx))) { ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.nip)); @@ -7370,7 +7370,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) exit(1); } } - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { gen_goto_tb(&ctx, 0, ctx.nip); diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 4397254dbf..e00c485a4e 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -176,11 +176,11 @@ static void spr_write_ureg(DisasContext *ctx, int spr= n, int gprn) #if !defined(CONFIG_USER_ONLY) static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -188,11 +188,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn= , int sprn) =20 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -203,11 +203,11 @@ static void spr_write_decr(DisasContext *ctx, int spr= n, int gprn) /* Time base */ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -215,11 +215,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn,= int sprn) =20 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -240,11 +240,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn= , int sprn) #if !defined(CONFIG_USER_ONLY) static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -252,11 +252,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn= , int gprn) =20 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -284,11 +284,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn= , int sprn) /* HDECR */ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -296,11 +296,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gpr= n, int sprn) =20 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 165d2cac3e..b950b16d9b 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -554,7 +554,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_exit_tb(DisasContext *s) { return (s->singlestep_enabled || - (s->tb->cflags & CF_LAST_IO) || + (tb_cflags(s->tb) & CF_LAST_IO) || (s->tb->flags & FLAG_MASK_PER)); } =20 @@ -5881,7 +5881,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5906,7 +5906,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5925,7 +5925,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) } } while (status =3D=3D NO_EXIT); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b4e4fd3782..33176c9926 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2248,7 +2248,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) (ctx.tbflags & (1 << SR_RB))) * 0x10; ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; =20 - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -2292,7 +2292,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -2300,7 +2300,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) decode_opc(&ctx); ctx.pc +=3D 2; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f63d7fb6ab..05414ce8a8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5772,7 +5772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) #endif =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5801,7 +5801,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) goto exit_gen_loop; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5828,7 +5828,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) num_insns < max_insns); =20 exit_gen_loop: - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (!dc->is_br) { diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ace2830a84..5cd84f6b25 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2378,7 +2378,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint64_t pc_start =3D tb->pc; uint64_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; int num_insns =3D 0; - int max_insns =3D tb->cflags & CF_COUNT_MASK; + int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 dc->pc =3D pc_start; dc->mmuidx =3D 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index b6cfbdfa9f..042c0e69bc 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8790,7 +8790,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) int num_insns, max_insns; =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 6c094d59d7..d717de0335 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1900,7 +1900,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) cpu_F1d =3D tcg_temp_new_i64(); next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1933,7 +1933,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1958,7 +1958,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->pc < next_page_start && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index d7bf07e8e6..f62319eddd 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -517,12 +517,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t s= r, unsigned access) =20 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(d, cpu_SR[sr]); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); return true; } @@ -702,11 +702,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 static void gen_check_interrupts(DisasContext *dc) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -760,11 +760,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr,= TCGv_i32 v) =20 static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wsr_ccount(cpu_env, v); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); return true; @@ -801,11 +801,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 tcg_gen_mov_i32(cpu_SR[sr], v); tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccompare(cpu_env, tmp); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); ret =3D true; @@ -900,11 +900,11 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4) TCGv_i32 pc =3D tcg_const_i32(dc->next_pc); TCGv_i32 intlevel =3D tcg_const_i32(imm4); =20 - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_waiti(cpu_env, pc, intlevel); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } tcg_temp_free(pc); @@ -3126,7 +3126,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) CPUXtensaState *env =3D cs->env_ptr; DisasContext dc; int insn_count =3D 0; - int max_insns =3D tb->cflags & CF_COUNT_MASK; + int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; uint32_t pc_start =3D tb->pc; uint32_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -3162,7 +3162,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) =20 gen_tb_start(tb); =20 - if ((tb->cflags & CF_USE_ICOUNT) && + if ((tb_cflags(tb) & CF_USE_ICOUNT) && (tb->flags & XTENSA_TBFLAG_YIELD)) { tcg_gen_insn_start(dc.pc); ++insn_count; @@ -3194,7 +3194,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) break; } =20 - if (insn_count =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (insn_count =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -3235,7 +3235,7 @@ done: tcg_temp_free(dc.next_icount); } =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jyya47iTzUAdCGaEw+6tfV7WebwryS73Is3iHDpzmrA=; b=OVn+DCR+ELufyR9O4DIPXa1tuGnLPG8DhBJY07+R9qG7rOpHVHeCSCD6xTiYE0Zcfx IgBhz05A7fIX66RtcfPHa8K1Hrz4HXdn+kDYxmp84SeCjjeLaxYfM/XJ3emvTi+3Adyo yKrS7pbr8iBIT421vxskL7ojVE3RRl3lYfh9s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jyya47iTzUAdCGaEw+6tfV7WebwryS73Is3iHDpzmrA=; b=DfaOJbtuuPRgPRh+WQV6io0MYxtNSnZGcoFzj5jqVIXTmeXe312s0WFHlNl34oJ7yY 2UWn+KdkI46s4Jnh1eiIQcAJ57a5KDapDW+Mj3NRTdqofIQrJAJLFCahbG+g366XjB/U CyzGBSCPQsZilWyJEWCGRYWvhenK1WjutX8EPkM/5/3HgMYcJaPklKSytnUajJwwqHTd dwUnQobd2azs+ykzl+ep7hqW/AOPe358W0MnBcQu5aoaZdHruU+ntoCztEd7o819JHij l1yAwlroqwpArUYY+pxSJ5qjQHVMk/RyQHwSjpTQvRnWinVxsqEygXE1BVUqvoBTfhUJ /hrA== X-Gm-Message-State: AMCzsaUM6SywKlciYbAjXm6sQDtIsc5PVKu79aqYu0+WYy6Hr/WAJy1o jtV+1sybr8hLZbF5o1WWJVBMPXs/HJY= X-Google-Smtp-Source: AOwi7QBJ2hx1/nzdMh0dn/rw8kiPduunqWYf0EWoF1syRWQRI7/oUCxadtN/mgxnt4SKV+TBXOOJtw== X-Received: by 10.98.69.86 with SMTP id s83mr9549614pfa.32.1508174811934; Mon, 16 Oct 2017 10:26:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:46 -0700 Message-Id: <20171016172609.23422-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v6 27/50] target/arm: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/arm/helper-a64.h | 4 ++++ target/arm/helper-a64.c | 38 ++++++++++++++++++++++++++++++++------ target/arm/op_helper.c | 7 ------- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ target/arm/translate.c | 9 +++++++-- 5 files changed, 68 insertions(+), 21 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba533..85d86741db 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32= , f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82cff5..d0e435ca4b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, = uint32_t bytes) } =20 /* Returns 0 on success; 1 otherwise. */ -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env,= uint64_t addr, return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true); +} + +static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env,= uint64_t addr, =20 return !success; } + +uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true); +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 3914145709..138d0df82f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -502,13 +502,6 @@ void HELPER(yield)(CPUARMState *env) ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); =20 - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - g_assert(!parallel_cpus); - /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the * top level loop so that a more deserving VCPU has a chance to run. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e9bee8c196..f6b364c04b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1336,13 +1336,18 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 3: /* WFI */ s->base.is_jmp =3D DISAS_WFI; return; + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* YIELD */ - if (!parallel_cpus) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ - if (!parallel_cpus) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp =3D DISAS_WFE; } return; @@ -1931,11 +1936,25 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, + cpu_exclusive_addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive= _addr, + cpu_reg(s, rt), cpu_reg(s, = rt2)); + } } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, + cpu_exclusive_addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive= _addr, + cpu_reg(s, rt), cpu_reg(s, = rt2)); + } } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, diff --git a/target/arm/translate.c b/target/arm/translate.c index dfa547b1db..397cc7afea 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4546,8 +4546,13 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* yield */ - if (!parallel_cpus) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->base.is_jmp =3D DISAS_YIELD; } @@ -4557,7 +4562,7 @@ static void gen_nop_hint(DisasContext *s, int val) s->base.is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ - if (!parallel_cpus) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->base.is_jmp =3D DISAS_WFE; } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176403452572.5591682821065; Mon, 16 Oct 2017 10:53:23 -0700 (PDT) Received: from localhost ([::1]:34402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Zg-0007fc-Ek for importer@patchew.org; Mon, 16 Oct 2017 13:53:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AI-0002YE-Ks for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AE-0003h9-Jx for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:58 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:49549) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AE-0003gm-E1 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:54 -0400 Received: by mail-pf0-x229.google.com with SMTP id i5so3202092pfe.6 for ; Mon, 16 Oct 2017 10:26:54 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RAagLYFqCSetGLwSSInErglxie5S43P08bbjsB82qWY=; b=EoeWklp95HqvNRQ0FZmSn5SXvU7JOQmFsNZtRmLS1pey1zhVmgJOPvSRA0QOo8Wd2t p1duEFtwt6rhIJmS3RSoO6MdDyeizE9s+CX8VcMDR8mwJwJBNw5U9ytkpGlqyv3whTgY OhBnEIjd5S20sBungacXt1EQTZzunXmAc2Gvw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RAagLYFqCSetGLwSSInErglxie5S43P08bbjsB82qWY=; b=JbLqueFayGcVU5Z0QnAkG3HM7Hyfu1CnHmhXnh/0sXq0zsyJAp/vj+PlHIF+KJ6SCD wtcYi4fYGwRS/I1bCFUgZyOoCKVRmefm8d37N52R+o7Pv05Pxxqmf9Ts6tfQlHLUImMV LrBzYmHtaRaptuDW5kuW76/8c0BM5yrxSRlW/PS7NCCHYb2chCmUklPZVlvsixJnTJL2 EzW6I0TRnmse8E6D1QyxP5JdwK4XMrg77gmtA5ndhYPI6Txrmcx48WCzXeEz9AWd8dTM 7aNvNn82XFE8iNckNsW89HOvtZ0pyY6SEyz+536g/ITG25nYxhv3KAMrR54c2xmAD3N0 simQ== X-Gm-Message-State: AMCzsaVRfuaMgDs1/ar+eIklc/y9mXKOd3oox6fNBRYsWXBgB4mGx3MJ xsQlY0WAeSvfMRKICwfMrvpjJfqKLC0= X-Google-Smtp-Source: AOwi7QCOojsB6nnaKgh5qsKhGSnogyF6mC2wB2Y3dphXaX25x4awgqc3Xqx3KMr2boGt5YiygMzPcQ== X-Received: by 10.98.198.138 with SMTP id x10mr7920705pfk.55.1508174813259; Mon, 16 Oct 2017 10:26:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:47 -0700 Message-Id: <20171016172609.23422-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PATCH v6 28/50] target/hppa: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++---- target/hppa/translate.c | 12 ++++++++++-- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 789f07fc0a..0a6b900555 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -3,7 +3,9 @@ DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) =20 DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index c05c0d5572..3104404e8d 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -76,7 +76,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #endif } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 @@ -89,7 +90,7 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr,= target_ulong val) break; case 1: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); @@ -102,14 +103,26 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong a= ddr, target_ulong val) } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_b(env, addr, val, false); +} + +void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_b(env, addr, val, true); +} + +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 switch (addr & 3) { case 3: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr - 3, val, 0xffffff00u, ra); } else { cpu_stw_data_ra(env, addr - 3, val >> 16, ra); @@ -132,6 +145,17 @@ void HELPER(stby_e)(CPUHPPAState *env, target_ulong ad= dr, target_ulong val) } } =20 +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_e(env, addr, val, false); +} + +void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_e(env, addr, val, true); +} + target_ulong HELPER(probe_r)(target_ulong addr) { return page_check_range(addr, 1, PAGE_READ); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 460b4d3154..08b2c73291 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2291,9 +2291,17 @@ static DisasJumpType trans_stby(DisasContext *ctx, u= int32_t insn, val =3D load_gpr(ctx, rt); =20 if (a) { - gen_helper_stby_e(cpu_env, addr, val); + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stby_e_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_e(cpu_env, addr, val); + } } else { - gen_helper_stby_b(cpu_env, addr, val); + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stby_b_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_b(cpu_env, addr, val); + } } =20 if (m) { --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176230055971.7993861000259; Mon, 16 Oct 2017 10:50:30 -0700 (PDT) Received: from localhost ([::1]:34389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49X1-0005Cz-92 for importer@patchew.org; Mon, 16 Oct 2017 13:50:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52496) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AG-0002WF-OZ for qemu-devel@nongnu.org; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fqWJKypEERna3DL8OZNR6W8KwfaZwhXECLG28bhJ+UM=; b=E/0o1Ngy+HLRwWAOtYNs3QJkHMsdixhOFQvlcMw+BKY52rAfeTg5NRyhe2S5t/MpbS yKBDTy2FjKnAKv6OKL3CbBbTKmVZwAdvCdXiJUhzhmXcpZCEg7ffT0JEectl+8VJAXop DEZ5oPUbNTA5raXvOjoEOnUmuFqZUAMz8SgvA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fqWJKypEERna3DL8OZNR6W8KwfaZwhXECLG28bhJ+UM=; b=QqNi+BQpXkwiAaPSy31aM0Vl7feTU9jYf00YdYmTSafwTLkybJtFZugZEq3QU79ndD FXCpJura8wq9GVSYlY6BQKcTQDTKIrd4ZyUXTYwOqxnKwkw5P0punbUee2X7bSuJ7qT2 bJXDreO9O++wB1RD/yixBOOF1iBfw7Ne4iAwUiuAf9CZxiDGRuKGkelM0sH9iNleE/N+ DObaBsA7l+aDWVvb+W7DcwZhYULpU7RqmvTcQ5hVGW/SNDRIrN/HBPWeZ+wHiVTOv+Gc h053uWQReBrBJD4GMzM4qKdjSkfqOPiXz08DGYotkfXPTBoZQnbX35rW96oDgwNMB7zt Q/5Q== X-Gm-Message-State: AMCzsaWYBRUZ8xU9XKLWHPGy8Naol7x2bEeGt49QdC1VwVHNr+IXCQlE v8Em89klqqRgUiLjFp3S6GwQHIr/EsA= X-Google-Smtp-Source: AOwi7QBYkSqCqytaGyVIeD2Lugrqs7cTpIcLU372eMHXVKb+jMuC+eyUT3sS5zlxrdZB7NLsXtEfHw== X-Received: by 10.98.35.18 with SMTP id j18mr9436391pfj.37.1508174814448; Mon, 16 Oct 2017 10:26:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:48 -0700 Message-Id: <20171016172609.23422-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH v6 29/50] target/i386: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/i386/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index f60582082e..6663cd1db8 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -5265,7 +5265,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_P= ARALLEL)) { gen_helper_cmpxchg16b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg16b_unlocked(cpu_env, cpu_A0); @@ -5276,7 +5276,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) if (!(s->cpuid_features & CPUID_CX8)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_P= ARALLEL)) { gen_helper_cmpxchg8b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg8b_unlocked(cpu_env, cpu_A0); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508175732906233.0879435451002; Mon, 16 Oct 2017 10:42:12 -0700 (PDT) Received: from localhost ([::1]:34357 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ow-0006d0-Aa for importer@patchew.org; Mon, 16 Oct 2017 13:42:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52517) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AI-0002Y1-Di for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AH-0003j8-8N for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:58 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:55519) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AH-0003iT-05 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:57 -0400 Received: by mail-pg0-x22f.google.com with SMTP id b11so7346201pgn.12 for ; Mon, 16 Oct 2017 10:26:56 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xFDqbXK1UuvZhOApzTuLKyN0ZQDx68yPe+6wHJld0dI=; b=keYDoO/P+btU0HrZwDOAiTL3PY3Y5Fz9eDUHp4QJjEoluRIDDvNGJscDnIH6rUdF12 AKXKbKfLZ0IkPCbs38qoWmCh0CxLHgghd16Oooy3oom0JyEApBpIawpcRnE2szwsBSL1 sFFRU8Kt2vEgxqtwjIrAuzKcccM7z3bkeZeGM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xFDqbXK1UuvZhOApzTuLKyN0ZQDx68yPe+6wHJld0dI=; b=g6dwvtIDCerh16Ax+vnV3FCyZI9UMLXoSyTMwpomoLco531ZVIglNXHa2mQkGKo0nS ma6Cj24y288BsDWFTy/x9/1Gp7lHwSW9HBsxZy3pRmX66HFycFjjDn1WFjomQ3EfQar8 5txuDAkEpClW+RzkYmKMB+HCLvoKRGZkfv4VRIboFxkxIm9zmqMabM11Mqu8N9qHa+6i 6mlFVZ5RKAMxkud7I4uQn322sPEe+1MGddsMCIph5A+lgWaNh2UvtFw7u2ZBqEko6tx2 v8xh3TTKRRSYZEB/FBR5jV276tYJGHioEf2FXxfnuHrgMsLhlspqsFnRlgcRA2Sd7P6B syew== X-Gm-Message-State: AMCzsaWKhZM5glw5NZnYSc2ELRKuclpXb2eUry5cLeL/u8sCTQir4NQ/ F+Fp0yDyZylXmkKMJoTtHeGQBXSlebk= X-Google-Smtp-Source: AOwi7QBl+eyl46dOoiFPMIzYtYRfXutA5nvHmFiKIeW3qKVoGWVUsz/EIeoT5mFeTRpm8JamcNzeog== X-Received: by 10.84.231.2 with SMTP id f2mr9353698plk.256.1508174815836; Mon, 16 Oct 2017 10:26:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:49 -0700 Message-Id: <20171016172609.23422-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v6 30/50] target/m68k: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/m68k/helper.h | 1 + target/m68k/op_helper.c | 33 ++++++++++++++++++++------------- target/m68k/translate.c | 12 ++++++++++-- 3 files changed, 31 insertions(+), 15 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 475a1f2186..eebe52dae5 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -11,6 +11,7 @@ DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) DEF_HELPER_4(cas2w, void, env, i32, i32, i32) DEF_HELPER_4(cas2l, void, env, i32, i32, i32) +DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) =20 #define dh_alias_fp ptr #define dh_ctype_fp FPReg * diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 7b5126c88d..63089511cb 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -361,6 +361,7 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int re= gr, int32_t den) env->dregs[numr] =3D quot; } =20 +/* We're executing in a serial context -- no need to be atomic. */ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) { uint32_t Dc1 =3D extract32(regs, 9, 3); @@ -374,17 +375,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2) int16_t l1, l2; uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { - /* Tell the main loop we need to serialize this insn. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } else { - /* We're executing in a serial context -- no need to be atomic. */ - l1 =3D cpu_lduw_data_ra(env, a1, ra); - l2 =3D cpu_lduw_data_ra(env, a2, ra); - if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stw_data_ra(env, a1, u1, ra); - cpu_stw_data_ra(env, a2, u2, ra); - } + l1 =3D cpu_lduw_data_ra(env, a1, ra); + l2 =3D cpu_lduw_data_ra(env, a2, ra); + if (l1 =3D=3D c1 && l2 =3D=3D c2) { + cpu_stw_data_ra(env, a1, u1, ra); + cpu_stw_data_ra(env, a2, u2, ra); } =20 if (c1 !=3D l1) { @@ -399,7 +394,8 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) env->dregs[Dc2] =3D deposit32(env->dregs[Dc2], 0, 16, l2); } =20 -void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32= _t a2, + bool parallel) { uint32_t Dc1 =3D extract32(regs, 9, 3); uint32_t Dc2 =3D extract32(regs, 6, 3); @@ -416,7 +412,7 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) TCGMemOpIdx oi; #endif =20 - if (parallel_cpus) { + if (parallel) { /* We're executing in a parallel context -- must be atomic. */ #ifdef CONFIG_ATOMIC64 uint64_t c, u, l; @@ -470,6 +466,17 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, u= int32_t a1, uint32_t a2) env->dregs[Dc2] =3D l2; } =20 +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +{ + do_cas2l(env, regs, a1, a2, false); +} + +void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1, + uint32_t a2) +{ + do_cas2l(env, regs, a1, a2, true); +} + struct bf_data { uint32_t addr; uint32_t bofs; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d199105559..3506864030 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2312,7 +2312,11 @@ DISAS_INSN(cas2w) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2w(cpu_env, regs, addr1, addr2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_exit_atomic(cpu_env); + } else { + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2w also assigned to env->cc_op. */ @@ -2358,7 +2362,11 @@ DISAS_INSN(cas2l) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2l(cpu_env, regs, addr1, addr2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); + } else { + gen_helper_cas2l(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2l also assigned to env->cc_op. */ --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p5KcfTV/19rdduEHLMjjQjn3skOs1jiMQVA1+BKU01Q=; b=YAxqSKnZKtJcg8IycZu0whBXF8fja6AnYcVvvIScJDe51EkGX1HOIb2RElj/ituGKD w4pOMb1pjrgJrqDjrag3Sr9nXRPNtVcu19QFET9Os3R20G7dhQ5HvnbYpizU0KhcUvBb PDs7B7+exaKkBnkN9zOB0OS84sTC2+dKQLKAA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p5KcfTV/19rdduEHLMjjQjn3skOs1jiMQVA1+BKU01Q=; b=CufbnRYLDRVPEWQAS6HiIZF1HOPMcC4LC2Jgys0a7+NiM4l2cVoIRazuopuVeE48gb BVxag589AEFotclcc6hHDZ8g2oSkz7S6tEr0CwlPo5hWnGQmEh3gfYMUVvVTowCP+Xvf sBCx41nYkKh9p5DgJMniFcr3Meww/Zizst1bYpX0NKFr+/CP0K2hfxE53xjgBzb8J8i8 rk4/XKPMPP9hz3QhKBJZbWstsBDYzpVNEQyi2THucW5m++XiK9Clk+NrTy7g6dgI/R3Z amAaMQ/K0fIZGVC3Zy30XZhEslzsqDnCMgWdRxbvVLw4E+vOMCYMtIUiqm44UI5n2yWR yECg== X-Gm-Message-State: AMCzsaUlEtRJcrUw69bh07tEF6xE7xG6Du2J4TwAAiTRNOpLsX2N7B8n JT3cQiMmpqpgJwi0WgrAsE2UKKtImLk= X-Google-Smtp-Source: ABhQp+Q+iMu43/4egXfmwEFtFX86pre7s1fYcH4koOTcr+DpfFtgGe7EwOse7mDVinu6xLjraVKQGA== X-Received: by 10.84.202.194 with SMTP id q2mr1680737plh.19.1508174817221; Mon, 16 Oct 2017 10:26:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:50 -0700 Message-Id: <20171016172609.23422-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PATCH v6 31/50] target/s390x: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/s390x/helper.h | 4 +++ target/s390x/mem_helper.c | 80 +++++++++++++++++++++++++++++++++++++------= ---- target/s390x/translate.c | 26 ++++++++++++--- 3 files changed, 88 insertions(+), 22 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 52c2963baa..d0da36c988 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -34,7 +34,9 @@ DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) +DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) +DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) @@ -106,7 +108,9 @@ DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(stfle, i32, env, i64) DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64) DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(cu12, i32, env, i32, i32, i32) DEF_HELPER_4(cu14, i32, env, i32, i32, i32) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bbbe1c62b3..6055f3915c 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1361,8 +1361,8 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) +static void do_cdsg(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3, bool parallel) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); @@ -1370,7 +1370,7 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, Int128 oldv; bool fail; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -1402,7 +1402,20 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 -uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64= _t a2) +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, false); +} + +void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, true); +} + +static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, + uint64_t a2, bool parallel) { #if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx =3D cpu_mmu_index(env, false); @@ -1438,7 +1451,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) the complete operation is not. Therefore we do not need to assert = serial context in order to implement this. That said, restart early if we= can't support either operation that is supposed to be atomic. */ - if (parallel_cpus) { + if (parallel) { int mask =3D 0; #if !defined(CONFIG_ATOMIC64) mask =3D -8; @@ -1462,7 +1475,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) uint32_t cv =3D env->regs[r3]; uint32_t ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_USER_ONLY uint32_t *haddr =3D g2h(a1); ov =3D atomic_cmpxchg__nocheck(haddr, cv, nv); @@ -1485,7 +1498,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) uint64_t cv =3D env->regs[r3]; uint64_t ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC64 # ifdef CONFIG_USER_ONLY uint64_t *haddr =3D g2h(a1); @@ -1495,7 +1508,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) ov =3D helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, = ra); # endif #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1515,13 +1528,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint64_t a2) Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC128 TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); cc =3D !int128_eq(ov, cv); #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1565,13 +1578,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint64_t a2) cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC128 TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); Int128 sv =3D int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1592,6 +1605,17 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r= 3, uint64_t a1, uint64_t a2) g_assert_not_reached(); } =20 +uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64= _t a2) +{ + return do_csst(env, r3, a1, a2, false); +} + +uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a= 1, + uint64_t a2) +{ + return do_csst(env, r3, a1, a2, true); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { @@ -2019,12 +2043,12 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -2045,13 +2069,23 @@ uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t a= ddr) return hi; } =20 +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, false); +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, true); +} + /* store pair to quadword */ -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) +static void do_stpq(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high, bool parallel) { uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -2069,6 +2103,18 @@ void HELPER(stpq)(CPUS390XState *env, uint64_t addr, } } =20 +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, false); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, true); +} + /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. diff --git a/target/s390x/translate.c b/target/s390x/translate.c index b950b16d9b..399aeb2800 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1966,7 +1966,11 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps = *o) addr =3D get_address(s, 0, b2, d2); t_r1 =3D tcg_const_i32(r1); t_r3 =3D tcg_const_i32(r3); - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); + } else { + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + } tcg_temp_free_i64(addr); tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r3); @@ -1980,7 +1984,11 @@ static ExitStatus op_csst(DisasContext *s, DisasOps = *o) int r3 =3D get_field(s->fields, r3); TCGv_i32 t_r3 =3D tcg_const_i32(r3); =20 - gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2); + } else { + gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2); + } tcg_temp_free_i32(t_r3); =20 set_cc_static(s); @@ -2937,7 +2945,7 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o) TCGMemOp mop =3D s->insn->data; =20 /* In a parallel context, stop the world and single step. */ - if (parallel_cpus) { + if (tb_cflags(s->tb) & CF_PARALLEL) { potential_page_fault(s); gen_exception(EXCP_ATOMIC); return EXIT_NORETURN; @@ -2958,7 +2966,11 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *= o) =20 static ExitStatus op_lpq(DisasContext *s, DisasOps *o) { - gen_helper_lpq(o->out, cpu_env, o->in2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_lpq_parallel(o->out, cpu_env, o->in2); + } else { + gen_helper_lpq(o->out, cpu_env, o->in2); + } return_low128(o->out2); return NO_EXIT; } @@ -4279,7 +4291,11 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps = *o) =20 static ExitStatus op_stpq(DisasContext *s, DisasOps *o) { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); + } else { + gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + } return NO_EXIT; } =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176065229834.5424976074748; Mon, 16 Oct 2017 10:47:45 -0700 (PDT) Received: from localhost ([::1]:34382 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49UM-0002w4-Gz for importer@patchew.org; Mon, 16 Oct 2017 13:47:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AN-0002cy-4u for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AJ-0003lP-Q0 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:03 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:57332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AJ-0003ku-K5 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:26:59 -0400 Received: by mail-pg0-x22b.google.com with SMTP id m18so7344105pgd.13 for ; Mon, 16 Oct 2017 10:26:59 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Ma9RsLmJse9wKSQr2fdk1qKcq67iH7WS9DOCSRJnyU=; b=JwA4pkuRDCQufvDyrg00h+j2sc5Jyqo9f3fUTkbjaIYfGqmk6SbDLeHpkXGqHj01Yu B7jQWMMwLlQROlfqF27K8fwZWh0zf73D8Xdt1wgAngQNWSkNfIWpBzV1/0taG5onqwWy MibVuOtTjUaURyzHa2NkT4XT3GjW2N13KAb6g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Ma9RsLmJse9wKSQr2fdk1qKcq67iH7WS9DOCSRJnyU=; b=ZC/vbNyuIyWa3x44OjeHy2l5PM/Y104sDAnI1oUYRd1rBdyhVsss4ghRLlFyES87JW PMAS8RR7TMSaN0LR/dgBgDY1JKdXW0vdPtDk0ADWWncLfG/SaPXCRTeJmHtm4gC8/TX9 IfFiYiW2+WJnhAu5X32LmxsidNtkn8oHoeP5e0yNb3Sq7JYlPSBADZ8b1sm2T6ilb+jF /exxL+B4TwAj8ZRaAhrgUUpxR6OCFDZN5D0O7lbhjDg4yfVw5Fi/rYOBldLsTxR+ua4b kjmng3uAFaAMIgeMp3rJXEnmeu88osRM8nRhQzAa37sOsxZMvAxkxnWZ6cX4yed9SJas 51Mg== X-Gm-Message-State: AMCzsaUVEdAl9zfs/tKLbb3CSIzhGdjU2NbVFNFyxFau70Kg4j0jaovv jOPDBpDbPHowOuKsPTNCmb0fmbdULx0= X-Google-Smtp-Source: AOwi7QBd+6BwNuNTyP38ZCQG9ymZLVEgme60ePOxYTod+RWQrdHtN/j1g81OPobc4TrvZHl0/WdrhQ== X-Received: by 10.98.9.27 with SMTP id e27mr9163232pfd.284.1508174818482; Mon, 16 Oct 2017 10:26:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:51 -0700 Message-Id: <20171016172609.23422-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH v6 32/50] target/sh4: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/sh4/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 33176c9926..f918bae978 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -521,7 +521,7 @@ static void _decode_opc(DisasContext * ctx) /* Detect the start of a gUSA region. If so, update envflags and end the TB. This will allow us to see the end of the region (stored in R0) in the next TB. */ - if (B11_8 =3D=3D 15 && B7_0s < 0 && parallel_cpus) { + if (B11_8 =3D=3D 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARAL= LEL)) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); ctx->bstate =3D BS_STOP; } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176520516597.4457071654232; Mon, 16 Oct 2017 10:55:20 -0700 (PDT) Received: from localhost ([::1]:34412 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49bj-000137-Nc for importer@patchew.org; Mon, 16 Oct 2017 13:55:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52593) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AN-0002cv-3y for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AL-0003mc-1g for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:03 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:43803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AK-0003lt-Rx for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:00 -0400 Received: by mail-pf0-x233.google.com with SMTP id a8so15844580pfc.0 for ; Mon, 16 Oct 2017 10:27:00 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XrDOWbNcFJTmBQzRovNO+7qJou3wvKXhrlz+xDEDj2I=; b=c39tBE9kuxeZSWVu+nUoyX+vfQ59dyyCT7g5A7MXYQETvX4VE0zcZH5pH25OvIm+SV mujqHIBt4QUGTduF+kKj4qaxwSDPxPV6Xl/GlExBn+RT3fBqUiY1zHOmX7c3WaQJSvTX 6QD+37Ocdprm67F4DtpmGV0CBRZkK4xuH7ukI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XrDOWbNcFJTmBQzRovNO+7qJou3wvKXhrlz+xDEDj2I=; b=d8cI3ofovvBNl+ZX8XZz34ISsOAbGXsfr3Eh5+l7jUuuTZiTLyv4MS5DvfaaueowtO M1TKkpTUaXCoF1UJgB6+yjn7WulI7cy/x5z3UbAedQfezaUxI6AmaGmUOfVHzuX5oPdf /5kgRek33YYOUOL5Jk0jnlp/4/GuHBt/yJ5bhtXGqMtEf7CK8dwBw5Qg4GfL7y9sPuj6 qqEj4dCnfGYDVGxIO0r7PNd4rk+ejiBGntQdfRtSXp1yrTcESQyMUuImill2QB2fQ+4L YhY0kaxMg8ikdKF5tZNmcB/C9p2+Y1/ofAb9uvbvzPYUQimAQFSwvRVNBwH/67EeKyWT QvoA== X-Gm-Message-State: AMCzsaVKen4gsUd1iibQ474Nv+uK9eL5QFeZHKhnLjTCaJYy734VY/9P ehSn+etfVIb5D70UBxzmYJ49lCZGILw= X-Google-Smtp-Source: AOwi7QDGbSDXrX4J7aNx7W4RSudsTdZUszvSrauZLgnqVlQYxH9P7RYUqUsC86VB3xslKqUwgGfJmQ== X-Received: by 10.98.57.215 with SMTP id u84mr9294600pfj.300.1508174819642; Mon, 16 Oct 2017 10:26:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:52 -0700 Message-Id: <20171016172609.23422-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v6 33/50] target/sparc: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 05414ce8a8..0669d4e8e5 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2442,7 +2442,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst= , TCGv addr, int insn) default: /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ - if (parallel_cpus) { + if (tb_cflags(dc->tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176149960210.81848870549175; Mon, 16 Oct 2017 10:49:09 -0700 (PDT) Received: from localhost ([::1]:34385 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Vg-00043g-8a for importer@patchew.org; Mon, 16 Oct 2017 13:49:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AS-0002ik-IQ for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AM-0003og-KV for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:08 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:47624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AM-0003nm-Ep for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:02 -0400 Received: by mail-pg0-x232.google.com with SMTP id r25so7349314pgn.4 for ; Mon, 16 Oct 2017 10:27:02 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rNneEMePZmh2n3MgU+clGSMraZtaGE+TiRXzcHouM8E=; b=KpT6/9swbCbXrI2IV0xjjoIuCYiFe6cP57GAz/iOBniN65YI3c2Y4lukI8tsDynkpV HRuOjk0MPl+0zC9MuIbZC99Ii/JcGLqalIYsoY9cQdhN0GRHYF4z31ZyyAOXO1TAQheI p0YjlVqsF3jBGWNb233E1ELmRZVmt1IJJEWto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rNneEMePZmh2n3MgU+clGSMraZtaGE+TiRXzcHouM8E=; b=O3W3UjXNePTbooNa2Dbz1SJFsfYMTPpDXhbGU7sM840dJPojkkOECcv24TVRExi8sK 75jj10mKzn6ichy0iK9GwH+hMQozd1eMoqCMkFXIvGv7mWOaMepJ3IulvQFhVlR/RTK5 7ZVSC1bg9zOPB+D9xBCnKfgaAEvBxMBAhqqWzet7MXVl6ze4HrTuCMUR+43ExlceZ4l+ 6EfWdFSMbJ8B+avnMfX1DxTbv8+ir1IXF+LqtHmaETNZ+uWxQXZnLBJ4dqaYBidGZBtj 1pBjFEd+XCOVTsNL1t6u12IGPO0kqoRQAWXHISWE2krwT7L9qA+TA/cs+RMkOs82uWhm Nq/g== X-Gm-Message-State: AMCzsaVs+/kfH7Xl4J/KVgyliQPZPOkwMXzVoXXAVUvyhXMHfamwEeUD hdrMkouTwaib1KcTcbuceL5+TimP0MM= X-Google-Smtp-Source: AOwi7QDAmAiDZFzGxQQlqihhAVz8CKgiRNQ95VzhrNx1EJON2Pp8ZbdLj0HVG5qm2FO1QMuuok/bkg== X-Received: by 10.84.210.166 with SMTP id a35mr9719602pli.426.1508174821230; Mon, 16 Oct 2017 10:27:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:53 -0700 Message-Id: <20171016172609.23422-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PATCH v6 34/50] tcg: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a field to TCGContext, storing there a copy of tb->cflags. Most architectures have <=3D 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the new field. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/tcg-op.c | 10 +++++----- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 5e1170b299..6736a9fe2e 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,6 +656,7 @@ struct TCGContext { uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ =20 TCGRegSet reserved_regs; + uint32_t tb_cflags; /* cflags of the current TB */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a7415c8661..d3dee985b4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1296,6 +1296,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; + tcg_ctx.tb_cflags =3D cflags; =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index be4b623e82..3253451115 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, T= CGArg a3, =20 void tcg_gen_mb(TCGBar mb_type) { - if (parallel_cpus) { + if (tcg_ctx.tb_cflags & CF_PARALLEL) { tcg_gen_op1(INDEX_op_mb, mb_type); } } @@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!parallel_cpus) { + if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!parallel_cpus) { + if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176715258486.5931338939714; Mon, 16 Oct 2017 10:58:35 -0700 (PDT) Received: from localhost ([::1]:34431 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49el-0004TY-4K for importer@patchew.org; Mon, 16 Oct 2017 13:58:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52618) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AO-0002en-TI for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AN-0003ph-Rf for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:04 -0400 Received: from mail-pf0-x232.google.com ([2607:f8b0:400e:c00::232]:54267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AN-0003p1-M7 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:03 -0400 Received: by mail-pf0-x232.google.com with SMTP id t188so13794494pfd.10 for ; Mon, 16 Oct 2017 10:27:03 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l2NW2eibSR6aGsXmh0Di9NTdRoHSvwrB4y9R4avxQdo=; b=A4E/Wz2oIIVhlLqFDnBPy8OL20f0FkOC0ntYtTThSvay8mf9Aks7flFggTfoCv+V2e i4/ePeAVcFAZ+wPqkbN7hsonR53lgDKYIzrkAzBRss5QFShyiYLFzSyujbhXPKGcJcgP iCdaH679JSZ8yMyKSMxejUF1FJmNt1TB+KtsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l2NW2eibSR6aGsXmh0Di9NTdRoHSvwrB4y9R4avxQdo=; b=Tns/dOSGgKZYi4LKnFO2gMSqU6GFY3RighGAmA8Ef2QJyEqAZo0DnY08lOcmk6hnJS Tt0Q8NGGsBLvhkDkBQOBaM+kjym/pd42WMgVqg8IuVP41FR5UkSurWsmogNOuRsxFBNI LpQWSSirKgFH9c3H1KShfaVW3OARIKjcaEKc2RLhOydCh4vmWVahzp4ergG7gaYoxUbj pKZK0XaCxQlzVIsvnF+CgG2zOUfIRi+iGVHYwvTn5K4yIkZ1/HQgAjTQMgj/Hr6/kZir YFQYu/SGwmkOknVizitkYeG2UjWll91rJ5tk4TYdrnKBL1yK7jwO1eFdWT/B0TLVL2S0 BoGQ== X-Gm-Message-State: AMCzsaWIFjUKL/4wMUjEUXVazQ9Q4QXjK85wpN3BbeBs6ryxvHXQOYwL LuIGVyGnM3TKsK7QKbGpWLcbN3hgx5s= X-Google-Smtp-Source: AOwi7QC8H7yzJz2anJ+Nicfo7PgmbdLViYpKwGLe3z11DCh6PcAOgE26BcK8hqK2k7Lyw4jiCCCnjQ== X-Received: by 10.99.95.203 with SMTP id t194mr6880123pgb.318.1508174822423; Mon, 16 Oct 2017 10:27:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:54 -0700 Message-Id: <20171016172609.23422-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PATCH v6 35/50] cpu-exec: lookup/generate TB outside exclusive region during step_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Now that all code generation has been converted to check CF_PARALLEL, we can generate !CF_PARALLEL code without having yet set !parallel_cpus -- and therefore without having to be in the exclusive region during cpu_exec_step_atomic. While at it, merge cpu_exec_step into cpu_exec_step_atomic. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index df410a8d6e..0eecbccebc 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -223,30 +223,40 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, } #endif =20 -static void cpu_exec_step(CPUState *cpu) +void cpu_exec_step_atomic(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; + uint32_t cf_mask =3D cflags & CF_HASH_MASK; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, - cflags & CF_HASH_MASK); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { mmap_lock(); tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); + if (likely(tb =3D=3D NULL)) { + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + } tb_unlock(); mmap_unlock(); } =20 + start_exclusive(); + + /* Since we got here, we know that parallel_cpus must be true. */ + parallel_cpus =3D false; cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); + parallel_cpus =3D true; + + end_exclusive(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -260,18 +270,6 @@ static void cpu_exec_step(CPUState *cpu) } } =20 -void cpu_exec_step_atomic(CPUState *cpu) -{ - start_exclusive(); - - /* Since we got here, we know that parallel_cpus must be true. */ - parallel_cpus =3D false; - cpu_exec_step(cpu); - parallel_cpus =3D true; - - end_exclusive(); -} - struct tb_desc { target_ulong pc; target_ulong cs_base; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150817597297977.30331970773625; Mon, 16 Oct 2017 10:46:12 -0700 (PDT) Received: from localhost ([::1]:34377 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Sr-0001fv-89 for importer@patchew.org; Mon, 16 Oct 2017 13:46:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AQ-0002fy-2o for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AP-0003qj-B3 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:06 -0400 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:54602) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AP-0003qE-4t for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:05 -0400 Received: by mail-pf0-x22d.google.com with SMTP id n89so8659477pfk.11 for ; Mon, 16 Oct 2017 10:27:05 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fTnG+pYtyBDmdpZrb4pJY39N9JOIdfqX72NWpGL3Keo=; b=cKEfGkonb1Rlufh36vyzisx2hvd+oC/MIa1t8pKqBb5CJZLqqflrmjEqrs9lR4HNb0 Hw4HplGybjUNAnkaej/b/a9EGzDLgNzi+fPWfCukPJ9+4781+rFPvNSoOiEUkU02B7iS GbsftVIh29keoMvgMDgpzColaP1poZBOyq9ls= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fTnG+pYtyBDmdpZrb4pJY39N9JOIdfqX72NWpGL3Keo=; b=GQNcyB5PkQI7mMR/xOEnKKMLlffmiQm7x7504oMKzDOdgOuSW2ARk4qE/XKkU9ja0n WYoQMgKb3WrZ3iPTHAiLvd5jSwkmLYjZIrWwZ2hOTlvuFw6AuN/u6oeHOe4SkIDn7Kvm Fsipmqjh1YpMgMv2dY4OjaEXwR9CYTjlC5/RbWAJ3cwoQ3QOpOyxzhhw1vGRCTFUpwH2 MGZWo/14luFo55bxlS3Mg3Ov1YE82sDDAT+xr2bmfIm1ZtKAmr06F2fnkmJimnZXVPFU FAeLzzGdHVN/4AMxJ342JBbx4bk6MUH1uF9dB9Spb/GYo5NYm3Oz94/NBnACjqZ+RGAo pMIQ== X-Gm-Message-State: AMCzsaVyKb3Fn+AWOnvFONFjzX8Oi/d1JHpbsxLOz08yb2ZA42VaX/MK m67WHkGZP22nKUoS0eeXAoTUvEfmifE= X-Google-Smtp-Source: AOwi7QA7PcUee+74F9OomEGOt/IQlwQfmS9SYYycINZSJkleuEVheUaXlChpycMZ5lXMlwXbH2Aumg== X-Received: by 10.98.70.137 with SMTP id o9mr9307535pfi.19.1508174823969; Mon, 16 Oct 2017 10:27:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:55 -0700 Message-Id: <20171016172609.23422-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PATCH v6 36/50] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These flags are used by target/*/translate.c, and affect code generation. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 0fdb72bb22..a3bd3e7abd 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -327,7 +327,8 @@ struct TranslationBlock { #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ #define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ /* cflags' mask for hashing/comparison */ -#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL) +#define CF_HASH_MASK \ + (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176677110545.2388359526731; Mon, 16 Oct 2017 10:57:57 -0700 (PDT) Received: from localhost ([::1]:34429 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49eE-00040i-DG for importer@patchew.org; Mon, 16 Oct 2017 13:57:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AR-0002hw-Mz for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AQ-0003rt-Gd for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:07 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:44288) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AQ-0003rI-A2 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:06 -0400 Received: by mail-pf0-x236.google.com with SMTP id x7so16318020pfa.1 for ; Mon, 16 Oct 2017 10:27:06 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vw/hp+C1d3vT3b7ZsD+YkxtyOWMep2FJT3usVPD/ybU=; b=Z6JFuhqMt+qpc9rxSanHrM2nQa0s1p+Vaj0ZM0ZA5uE+wlhzVh1NT1PxCVzsCs1iay aVJK77uOqHoj7rMh8A1/FQqXDkSdkv3XG0Mrp7Q6lSrSGiXPwjHCVJy3637cZqAOuwYw bEd6qSo0K87sqA4PajUyNAitTAGVxCn5yVrOY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vw/hp+C1d3vT3b7ZsD+YkxtyOWMep2FJT3usVPD/ybU=; b=NeW5I7JZiZFbE/OdCo7NiO5nDbnzxGaUdG3ooz3LKsWelhPlK7iFXwlgBlPmj5KEpL Syepv0EZgQuFFkg0fuBJDAoBvGcRd70TWzTszjW4MkEZLyQevSqeEHoBD1/HQrNyIqrS Its1bseGinu55aDCkVgss2mvsFjBOmdeYi1lB78qUx/XxL2NiNma+6OZxRSD5kdNUE6n WH9hM4mDSiKXMmoaVaYj0v9thPs0i1fqgL9FNyTExTvQQe4am15JE0K2VThi3yLBLclw Gf9nB317CuM6fNC+xLQNQu3dcOx7+ZAoL2chv07icu3UWE6MTZuDWI9Y36FhUk/9FS11 gcSg== X-Gm-Message-State: AMCzsaXRo2uW6beVdefRbGZlxSljJnC92FgdQ5Nrk2JRxL9GqvSC2fAU RLXSC29oP4BRK6UBSgdvKVA+kunJ1z0= X-Google-Smtp-Source: AOwi7QAPcU2fSe69dQDidCb1GYO2K2T1k9cVIxoUhAzKwaCRItzRY33flgGh1uRIe3I4k+t2FNoHYw== X-Received: by 10.98.75.221 with SMTP id d90mr9496235pfj.90.1508174825070; Mon, 16 Oct 2017 10:27:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:56 -0700 Message-Id: <20171016172609.23422-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PATCH v6 37/50] tcg: Remove CF_IGNORE_ICOUNT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have curr_cflags, we can include CF_USE_ICOUNT early and then remove it as necessary. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 17 +++++++++-------- accel/tcg/cpu-exec.c | 16 +++++++++------- accel/tcg/translate-all.c | 3 --- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3bd3e7abd..f14c6a56eb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -22,6 +22,7 @@ =20 #include "qemu-common.h" #include "exec/tb-context.h" +#include "sysemu/cpus.h" =20 /* allow to see translation results - the slowdown should be negligible, s= o we leave it */ #define DEBUG_DISAS @@ -319,13 +320,12 @@ struct TranslationBlock { size <=3D TARGET_PAGE_SIZE) */ uint16_t icount; uint32_t cflags; /* compile flags */ -#define CF_COUNT_MASK 0x7fff -#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ -#define CF_NOCACHE 0x10000 /* To be freed after execution */ -#define CF_USE_ICOUNT 0x20000 -#define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ -#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ -#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ +#define CF_COUNT_MASK 0x00007fff +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_NOCACHE 0x00010000 /* To be freed after execution */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Setters need tb_lock */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ /* cflags' mask for hashing/comparison */ #define CF_HASH_MASK \ (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) @@ -380,7 +380,8 @@ static inline uint32_t tb_cflags(const TranslationBlock= *tb) /* current cflags for hashing/comparison */ static inline uint32_t curr_cflags(void) { - return parallel_cpus ? CF_PARALLEL : 0; + return (parallel_cpus ? CF_PARALLEL : 0) + | (use_icount ? CF_USE_ICOUNT : 0); } =20 void tb_free(TranslationBlock *tb); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 0eecbccebc..59fd784436 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -198,17 +198,19 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, TranslationBlock *orig_tb, bool ignore_icount) { TranslationBlock *tb; + uint32_t cflags =3D curr_cflags() | CF_NOCACHE; + + if (ignore_icount) { + cflags &=3D ~CF_USE_ICOUNT; + } =20 /* Should never happen. We only end up here when an existing TB is too long. */ - if (max_cycles > CF_COUNT_MASK) - max_cycles =3D CF_COUNT_MASK; + cflags |=3D MIN(max_cycles, CF_COUNT_MASK); =20 tb_lock(); - tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, - max_cycles | CF_NOCACHE - | (ignore_icount ? CF_IGNORE_ICOUNT : 0) - | curr_cflags()); + tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, + orig_tb->flags, cflags); tb->orig_tb =3D orig_tb; tb_unlock(); =20 @@ -229,7 +231,7 @@ void cpu_exec_step_atomic(CPUState *cpu) TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; + uint32_t cflags =3D 1; uint32_t cf_mask =3D cflags & CF_HASH_MASK; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d3dee985b4..d6b3bc0a38 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1274,9 +1274,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, assert_memory_lock(); =20 phys_pc =3D get_page_addr_code(env, pc); - if (use_icount && !(cflags & CF_IGNORE_ICOUNT)) { - cflags |=3D CF_USE_ICOUNT; - } =20 tb =3D tb_alloc(pc); if (unlikely(!tb)) { --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176866759261.01606341541844; Mon, 16 Oct 2017 11:01:06 -0700 (PDT) Received: from localhost ([::1]:34447 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49hJ-0006ik-Vi for importer@patchew.org; Mon, 16 Oct 2017 14:01:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AU-0002kr-8H for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AS-0003tB-5r for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:10 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:47624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AR-0003sV-T3 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:08 -0400 Received: by mail-pg0-x235.google.com with SMTP id r25so7349502pgn.4 for ; Mon, 16 Oct 2017 10:27:07 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4eLQGwLbfn+m/deJ/0OTHG97Y6YcJ69T4LHmy2PbIMc=; b=BJgeJS8ExdzEY2WaD3xf6TbpuIB9SdWsGyfjcOPGKaJFrPwgDZHu1kBWMm2FyxiLOM RBH5SY5vyzvyD44YYrxkCBEp0LWldz0WX2oDYdUUPXDnvEsCvsTBr6/bJxiTmDMqHqBI W6T4HZ4QkSLLnN5rt82vmL97r9zeQF/HaEwyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4eLQGwLbfn+m/deJ/0OTHG97Y6YcJ69T4LHmy2PbIMc=; b=pF6+9jF6XfN0s9iT1JPYd5yRU2X01J5swXUMMJmktSbV0QauiYWUfszVn83FbD2g1M qn6rE1WMQRFdvGqQZiAzIHAnF/DW8dXc3esMiHtNDhAudWSZHm0rGyLBfoC1oxN85IJX fizGG61+GbkjFCCpYJOLRlhdlbjwKCzcPtnqbvACoSJtTTobUdif2ypoqQc/XmLafdhO Y9WVIOCyi9CdaBYyW86ztBY0gYwgQrVgu76zEnm53yHwBtlZ8XemvOHjPGvrYWwI9JDg y7p5s7saTuQHvZ+Y1bSvGhtlCTts01IDiBzwBBU/PlPDDTWVdUP7wm82tQXER0bkPkHH mSkg== X-Gm-Message-State: AMCzsaWyMZnLwjADr4NJtVr0mL4DA5F1DmeGclf+2xNUvMEQNbB2Y+GQ 5KxDHmiY0Y7q9SiKXIjlfJD74Nhr2qI= X-Google-Smtp-Source: ABhQp+RHnoBo/QE+Df322R2k5h/miy1zE6g5ciI0LCBgTO+fap16Z6xKhvV+wDwrWv2qflOt1z20oQ== X-Received: by 10.101.69.8 with SMTP id n8mr826427pgq.79.1508174826470; Mon, 16 Oct 2017 10:27:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:57 -0700 Message-Id: <20171016172609.23422-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH v6 38/50] translate-all: use a binary search tree to track TBs in TBContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This is a prerequisite for supporting multiple TCG contexts, since we will have threads generating code in separate regions of code_gen_buffer. For this we need a new field (.size) in struct tb_tc to keep track of the size of the translated code. This field uses a size_t to avoid adding a hole to the struct, although really an unsigned int would have been enough. The comparison function we use is optimized for the common case: insertions. Profiling shows that upon booting debian-arm, 98% of comparisons are between existing tb's (i.e. a->size and b->size are both !0), which happens during insertions (and removals, but those are rare). The remaining cases are lookups. From reading the glib sources we see that the first key is always the lookup key. However, the code does not assume this to always be the case because this behaviour is not guaranteed in the glib docs. However, we embed this knowledge in the code as a branch hint for the compiler. Note that tb_free does not free space in the code_gen_buffer anymore, since we cannot easily know whether the tb is the last one inserted in code_gen_buffer. The next patch in this series renames tb_free to tb_remove to reflect this. Performance-wise, lookups in tb_find_pc are the same as before: O(log n). However, insertions are O(log n) instead of O(1), which results in a small slowdown when booting debian-arm: Performance counter stats for 'build/arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Dimg/arm/jessie-arm32.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel img/arm/aarch32-current-linux-kernel-only.img \ -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): - Before: 8048.598422 task-clock (msec) # 0.931 CPUs utilized = ( +- 0.28% ) 16,974 context-switches # 0.002 M/sec = ( +- 0.12% ) 0 cpu-migrations # 0.000 K/sec 10,125 page-faults # 0.001 M/sec = ( +- 1.23% ) 35,144,901,879 cycles # 4.367 GHz = ( +- 0.14% ) stalled-cycles-frontend stalled-cycles-backend 65,758,252,643 instructions # 1.87 insns per cycl= e ( +- 0.33% ) 10,871,298,668 branches # 1350.707 M/sec = ( +- 0.41% ) 192,322,212 branch-misses # 1.77% of all branche= s ( +- 0.32% ) 8.640869419 seconds time elapsed = ( +- 0.57% ) - After: 8146.242027 task-clock (msec) # 0.923 CPUs utilized = ( +- 1.23% ) 17,016 context-switches # 0.002 M/sec = ( +- 0.40% ) 0 cpu-migrations # 0.000 K/sec 18,769 page-faults # 0.002 M/sec = ( +- 0.45% ) 35,660,956,120 cycles # 4.378 GHz = ( +- 1.22% ) stalled-cycles-frontend stalled-cycles-backend 65,095,366,607 instructions # 1.83 insns per cycl= e ( +- 1.73% ) 10,803,480,261 branches # 1326.192 M/sec = ( +- 1.95% ) 195,601,289 branch-misses # 1.81% of all branche= s ( +- 0.39% ) 8.828660235 seconds time elapsed = ( +- 0.38% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 5 ++ include/exec/tb-context.h | 4 +- accel/tcg/translate-all.c | 217 ++++++++++++++++++++++++------------------= ---- 3 files changed, 118 insertions(+), 108 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f14c6a56eb..4c4242a1d8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -306,10 +306,15 @@ static inline void tb_invalidate_phys_addr(AddressSpa= ce *as, hwaddr addr) =20 /* * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a bin= ary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. @search is brought here for consistency, since it is al= so + * a TC-related field. */ struct tb_tc { void *ptr; /* pointer to the translated code */ uint8_t *search; /* pointer to search data */ + size_t size; }; =20 struct TranslationBlock { diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 25c2afe753..1fa8dcc737 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -31,10 +31,8 @@ typedef struct TBContext TBContext; =20 struct TBContext { =20 - TranslationBlock **tbs; + GTree *tb_tree; struct qht htable; - size_t tbs_size; - int nb_tbs; /* any access to the tbs or the page table must use this lock */ QemuMutex tb_lock; =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d6b3bc0a38..083e1c7336 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -776,6 +776,48 @@ static inline void *alloc_code_gen_buffer(void) } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ =20 +/* compare a pointer @ptr and a tb_tc @s */ +static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) +{ + if (ptr >=3D s->ptr + s->size) { + return 1; + } else if (ptr < s->ptr) { + return -1; + } + return 0; +} + +static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) +{ + const struct tb_tc *a =3D ap; + const struct tb_tc *b =3D bp; + + /* + * When both sizes are set, we know this isn't a lookup. + * This is the most likely case: every TB must be inserted; lookups + * are a lot less frequent. + */ + if (likely(a->size && b->size)) { + if (a->ptr > b->ptr) { + return 1; + } else if (a->ptr < b->ptr) { + return -1; + } + /* a->ptr =3D=3D b->ptr should happen only on deletions */ + g_assert(a->size =3D=3D b->size); + return 0; + } + /* + * All lookups have either .size field set to 0. + * From the glib sources we see that @ap is always the lookup key. How= ever + * the docs provide no guarantee, so we just mark this case as likely. + */ + if (likely(a->size =3D=3D 0)) { + return ptr_cmp_tb_tc(a->ptr, b); + } + return ptr_cmp_tb_tc(b->ptr, a); +} + static inline void code_gen_alloc(size_t tb_size) { tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); @@ -784,15 +826,7 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - - /* size this conservatively -- realloc later if needed */ - tcg_ctx.tb_ctx.tbs_size =3D - tcg_ctx.code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE / 8; - if (unlikely(!tcg_ctx.tb_ctx.tbs_size)) { - tcg_ctx.tb_ctx.tbs_size =3D 64 * 1024; - } - tcg_ctx.tb_ctx.tbs =3D g_new(TranslationBlock *, tcg_ctx.tb_ctx.tbs_si= ze); - + tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); } =20 @@ -829,7 +863,6 @@ void tcg_exec_init(unsigned long tb_size) static TranslationBlock *tb_alloc(target_ulong pc) { TranslationBlock *tb; - TBContext *ctx; =20 assert_tb_locked(); =20 @@ -837,12 +870,6 @@ static TranslationBlock *tb_alloc(target_ulong pc) if (unlikely(tb =3D=3D NULL)) { return NULL; } - ctx =3D &tcg_ctx.tb_ctx; - if (unlikely(ctx->nb_tbs =3D=3D ctx->tbs_size)) { - ctx->tbs_size *=3D 2; - ctx->tbs =3D g_renew(TranslationBlock *, ctx->tbs, ctx->tbs_size); - } - ctx->tbs[ctx->nb_tbs++] =3D tb; return tb; } =20 @@ -851,16 +878,7 @@ void tb_free(TranslationBlock *tb) { assert_tb_locked(); =20 - /* In practice this is mostly used for single use temporary TB - Ignore the hard cases and just back up if this TB happens to - be the last one generated. */ - if (tcg_ctx.tb_ctx.nb_tbs > 0 && - tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { - size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); - - tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; - tcg_ctx.tb_ctx.nb_tbs--; - } + g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -918,11 +936,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 if (DEBUG_TB_FLUSH_GATE) { - printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0); + size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -933,7 +952,10 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) cpu_tb_jmp_cache_clear(cpu); } =20 - tcg_ctx.tb_ctx.nb_tbs =3D 0; + /* Increment the refcount first so that destroy acts as a reset */ + g_tree_ref(tcg_ctx.tb_ctx.tb_tree); + g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 @@ -1340,6 +1362,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (unlikely(search_size < 0)) { goto buffer_overflow; } + tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER tcg_ctx.code_time +=3D profile_getclock() - ti; @@ -1410,6 +1433,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); + g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1670,37 +1694,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t = addr, uintptr_t pc) } #endif =20 -/* find the TB 'tb' such that tb[0].tc_ptr <=3D tc_ptr < - tb[1].tc_ptr. Return NULL if not found */ +/* + * Find the TB 'tb' such that + * tb->tc.ptr <=3D tc_ptr < tb->tc.ptr + tb->tc.size + * Return NULL if not found. + */ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { - int m_min, m_max, m; - uintptr_t v; - TranslationBlock *tb; + struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - if (tcg_ctx.tb_ctx.nb_tbs <=3D 0) { - return NULL; - } - if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || - tc_ptr >=3D (uintptr_t)tcg_ctx.code_gen_ptr) { - return NULL; - } - /* binary search (cf Knuth) */ - m_min =3D 0; - m_max =3D tcg_ctx.tb_ctx.nb_tbs - 1; - while (m_min <=3D m_max) { - m =3D (m_min + m_max) >> 1; - tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc.ptr; - if (v =3D=3D tc_ptr) { - return tb; - } else if (tc_ptr < v) { - m_max =3D m - 1; - } else { - m_min =3D m + 1; - } - } - return tcg_ctx.tb_ctx.tbs[m_max]; + return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1886,63 +1889,67 @@ static void print_qht_statistics(FILE *f, fprintf_f= unction cpu_fprintf, g_free(hgram); } =20 +struct tb_tree_stats { + size_t target_size; + size_t max_target_size; + size_t direct_jmp_count; + size_t direct_jmp2_count; + size_t cross_page; +}; + +static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer = data) +{ + const TranslationBlock *tb =3D value; + struct tb_tree_stats *tst =3D data; + + tst->target_size +=3D tb->size; + if (tb->size > tst->max_target_size) { + tst->max_target_size =3D tb->size; + } + if (tb->page_addr[1] !=3D -1) { + tst->cross_page++; + } + if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp_count++; + if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp2_count++; + } + } + return false; +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) { - int i, target_code_size, max_target_code_size; - int direct_jmp_count, direct_jmp2_count, cross_page; - TranslationBlock *tb; + struct tb_tree_stats tst =3D {}; struct qht_stats hst; + size_t nb_tbs; =20 tb_lock(); =20 - target_code_size =3D 0; - max_target_code_size =3D 0; - cross_page =3D 0; - direct_jmp_count =3D 0; - direct_jmp2_count =3D 0; - for (i =3D 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { - tb =3D tcg_ctx.tb_ctx.tbs[i]; - target_code_size +=3D tb->size; - if (tb->size > max_target_code_size) { - max_target_code_size =3D tb->size; - } - if (tb->page_addr[1] !=3D -1) { - cross_page++; - } - if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp_count++; - if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp2_count++; - } - } - } + nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); - cpu_fprintf(f, "TB count %d\n", tcg_ctx.tb_ctx.nb_tbs); - cpu_fprintf(f, "TB avg target size %d max=3D%d bytes\n", - tcg_ctx.tb_ctx.nb_tbs ? target_code_size / - tcg_ctx.tb_ctx.nb_tbs : 0, - max_target_code_size); + cpu_fprintf(f, "TB count %zu\n", nb_tbs); + cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", + nb_tbs ? tst.target_size / nb_tbs : 0, + tst.max_target_size); cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0, - target_code_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - target_code_size : 0); - cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, - tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); - cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=3D%d %d%%)\n", - direct_jmp_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0, - direct_jmp2_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); + nb_tbs ? (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / nb_tbs : 0, + tst.target_size ? (double) (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / + tst.target_size : 0); + cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, + nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); + cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", + tst.direct_jmp_count, + nb_tbs ? (tst.direct_jmp_count * 100) / nb_tbs : 0, + tst.direct_jmp2_count, + nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176241843252.02044262119034; Mon, 16 Oct 2017 10:50:41 -0700 (PDT) Received: from localhost ([::1]:34391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49X8-0005II-5C for importer@patchew.org; Mon, 16 Oct 2017 13:50:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AY-0002mN-Bg for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AT-0003uI-CY for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:12 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:51122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AT-0003tg-88 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:09 -0400 Received: by mail-pg0-x22f.google.com with SMTP id y7so7343538pgb.7 for ; Mon, 16 Oct 2017 10:27:09 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rKW+KdkvOF9EOXRo7dmyn5uHsd88uC8X4HeG4p5K65U=; b=bQVxkSQ5W+lkHlM6fURtZ9FSAwBbVMjwxofuXMmGOe810itLIC9/ZR7ayMpbJSgYp5 KKhFVapWqSGNKTp85iimCUJoZn0F0FcMZCl/Us/bBQSywabXeqeKWhH5XswW+4/6FtOp wvLx2eOKrRnG/kewNttbCZ0T1EZ0V0E811Q10= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rKW+KdkvOF9EOXRo7dmyn5uHsd88uC8X4HeG4p5K65U=; b=JJw93jyo+a8563MXs+2ZpOvnxRkhau+zHPp9uC5inaMvUWb1UZ2vTGJs37RTme4s13 VXXWbNDRYRGJ7r9QIlcv/fjQjUeXFgxuUppkymDJ+N4mcdV2/bVUoBRAIVPtTCKB+TQL qKEVQAmfJGq2gmPuCj7IisM2uDhZlnpydAKZPFwSsU1qSLBPIbPk3Guemd5tdQYccicd gr5tAbEe7+Qtr2J6WIlnIfiI66eiz7yZ3e57Rn5RfDFizhcuQWFdykecCkGMxp0s21ww AlywFWqZmrsZFB64dA/HCsvEhSzBDTpyn59KAAX3BW/7Ygb5zkjuwZ+23a1GktnEREsE n/gw== X-Gm-Message-State: AMCzsaXIPbknFwxBvi6su22NG7Urgfhmw6DSu6aSRqCyYFzAbZIKN/ur Djlz/12tsyno5N/B3BPrtDdWcrHpzYk= X-Google-Smtp-Source: AOwi7QBQT8sMxMIUTxJoDBqmdL36DvXBx3DxTmX8P4O7BQNDBzclBPeU4N8xTB0Yk20V8nb9Y5pkxw== X-Received: by 10.84.171.195 with SMTP id l61mr9417701plb.64.1508174828101; Mon, 16 Oct 2017 10:27:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:58 -0700 Message-Id: <20171016172609.23422-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v6 39/50] exec-all: rename tb_free to tb_remove X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4c4242a1d8..746f4be71e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -389,7 +389,7 @@ static inline uint32_t curr_cflags(void) | (use_icount ? CF_USE_ICOUNT : 0); } =20 -void tb_free(TranslationBlock *tb); +void tb_remove(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 59fd784436..6a4a33235b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -220,7 +220,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, =20 tb_lock(); tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); tb_unlock(); } #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 083e1c7336..76db9c775a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -375,7 +375,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) if (tb->cflags & CF_NOCACHE) { /* one-shot translation, invalidate it immediately */ tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); } r =3D true; } @@ -874,7 +874,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) } =20 /* Called with tb_lock held. */ -void tb_free(TranslationBlock *tb) +void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 @@ -1816,7 +1816,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) * cpu_exec_nocache() */ tb_phys_invalidate(tb->orig_tb, -1); } - tb_free(tb); + tb_remove(tb); } /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177041400593.4983918742381; Mon, 16 Oct 2017 11:04:01 -0700 (PDT) Received: from localhost ([::1]:34467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49k8-0000Z6-66 for importer@patchew.org; Mon, 16 Oct 2017 14:04:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AY-0002mO-Bf for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AV-0003vd-14 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:12 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:49899) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AU-0003v1-PB for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:10 -0400 Received: by mail-pg0-x22a.google.com with SMTP id g6so5925014pgn.6 for ; Mon, 16 Oct 2017 10:27:10 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bUAYvoRE++vtOhfTfGcC3GQ+auq5Nx2oS4tsDzfqZ3k=; b=CLQ5O5h/WNFJND+/AzeiA3mqCHqdzFzDEdjPILv3NYHeK+zq/ylJcLwRECqinYrjeS 8vmETiiVXUy8WX80irDgHwS5l0ImKJej1sxmg8FL16QyqhOe7NR0MdWqG2CAISNEq7Zt NWKIc0bTlm+dkt7vsGTvEVncSUEcmk4n95138= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bUAYvoRE++vtOhfTfGcC3GQ+auq5Nx2oS4tsDzfqZ3k=; b=R1k+cdfUKxE6JPOtDB6mNff1cHKNEprJHm9HzcMgBDMTpmM5RORiIrTrp+CFylhw+k 0HSRkdHrW0/eYDurBTibP3TbBBNqFQnAjbxLzwYlKw1gk15ibQ5H7uz4n5cY0I75+4l6 Zy4h1zTQGa5k01kFgs2aY2kcOWwMlEuskdqQdhcona1CwmEvhgWS2IVamCyCJScHaZG+ IF4vLrDLhf1/lGaa9Ua6BetpW1SFb+CXZK6U3xuERFZjtU3WVGxsH4ObYgqtVaoNaIMD SxyMw1y6gwgkCrJ47zHLqw8sLXGkYpsYOch5LaO/91/2F+KUHlbX1FxCkv0mu4s6XrOT Vnhw== X-Gm-Message-State: AMCzsaVbZw45yb9/9ueR0EYAlvMxKx1nPx6E5tu38DMJXndK/4iHYX9B BNT4tNIWYb87M40eJAKHhs4eZfRS8mk= X-Google-Smtp-Source: AOwi7QBQzvLdT/y2A1JXw0buMJ02cRf8Ery+RaBxoTWwQW9709nYmx0RWngYa/7glk3x32GJEC6qsQ== X-Received: by 10.99.95.201 with SMTP id t192mr7101759pgb.398.1508174829527; Mon, 16 Oct 2017 10:27:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:59 -0700 Message-Id: <20171016172609.23422-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v6 40/50] translate-all: report correct avg host TB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the corresponding translated code") we are not fully utilizing code_gen_buffer for translated code, and therefore are incorrectly reporting the amount of translated code as well as the average host TB size. Address this by: - Making the conscious choice of misreporting the total translated code; doing otherwise would mislead users into thinking "-tb-size" is not honoured. - Expanding tb_tree_stats to accurately count the bytes of translated code = on the host, and using this for reporting the average tb host size, as well as the expansion ratio. In the future we might want to consider reporting the accurate numbers for the total translated code, together with a "bookkeeping/overhead" field to account for the TB structs. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 76db9c775a..b21671d6f4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -923,6 +923,15 @@ static void page_flush_tb(void) } } =20 +static gboolean tb_host_size_iter(gpointer key, gpointer value, gpointer d= ata) +{ + const TranslationBlock *tb =3D value; + size_t *size =3D data; + + *size +=3D tb->tc.size; + return false; +} + /* flush all the translation blocks */ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) { @@ -937,11 +946,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 if (DEBUG_TB_FLUSH_GATE) { size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t host_size =3D 0; =20 - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, - nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); + nb_tbs > 0 ? host_size / nb_tbs : 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -1890,6 +1900,7 @@ static void print_qht_statistics(FILE *f, fprintf_fun= ction cpu_fprintf, } =20 struct tb_tree_stats { + size_t host_size; size_t target_size; size_t max_target_size; size_t direct_jmp_count; @@ -1902,6 +1913,7 @@ static gboolean tb_tree_stats_iter(gpointer key, gpoi= nter value, gpointer data) const TranslationBlock *tb =3D value; struct tb_tree_stats *tst =3D data; =20 + tst->host_size +=3D tb->tc.size; tst->target_size +=3D tb->size; if (tb->size > tst->max_target_size) { tst->max_target_size =3D tb->size; @@ -1930,6 +1942,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); + /* + * Report total code size including the padding and TB structs; + * otherwise users might think "-tb-size" is not honoured. + * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. + */ cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); @@ -1937,12 +1954,9 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, tst.max_target_size); - cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / nb_tbs : 0, - tst.target_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tst.target_size : 0); + cpu_fprintf(f, "TB avg host size %zu bytes (expansion ratio: %0.1f)= \n", + nb_tbs ? tst.host_size / nb_tbs : 0, + tst.target_size ? (double)tst.host_size / tst.target_size = : 0); cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176838783938.3189731021045; Mon, 16 Oct 2017 11:00:38 -0700 (PDT) Received: from localhost ([::1]:34441 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49gn-0006DT-33 for importer@patchew.org; Mon, 16 Oct 2017 14:00:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49AY-0002mP-Bl for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AW-0003wl-IP for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:14 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:50194) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AW-0003wG-9g for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:12 -0400 Received: by mail-pf0-x22b.google.com with SMTP id b6so7885746pfh.7 for ; Mon, 16 Oct 2017 10:27:12 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5gLpsSURJCvdKy3g1+IW5c1QZdKxsnrW9+1xstSV9Ls=; b=DNthPiMD4QqrlXilpuv4RsJryKtl6VLkJw69bU1MeF2+as6uYK9GIRrCXfTARwb03y cNfiCIIUc0sY05Sbbvd3cQQe3rDxIUaoSMFcD9KrW1ROUz+8eiZBc+3j0Q04scg5KQBI RrSIxh1a0kUqY1lJuDGaASR/kMZLfV+YDutoQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5gLpsSURJCvdKy3g1+IW5c1QZdKxsnrW9+1xstSV9Ls=; b=YU0tN59QtQVVnYcr6apX/vg76amWgJBsOgSFqJG4Ask9SuE6S1/4vXPQcazzZvHOyg QQfigM7ALUvE5vi/z3i5Wk9TwGJbMI9pD8PKktmJjXRYfUfUK/O8sNdqZmziRIefzuSa K7l0/MfwkJi4g7q1eI/tr5+RfQsSYnAAEajnCi6UeVcbhuqtnX5NblkJhZUmrl1IATjB fuWpn6eQOW3Lr4wEDa5Q1fqxn5cGItdVsGDLtvJaE87ncrOIUby9S79W12adRmY0oQ8f OIZQK8xMa3oQfgP+MLfjP8c8TvT7Nk7tEtPbS+4EJLHGv2S2ut3fK3IsfxXI0G0XO1x2 s71w== X-Gm-Message-State: AMCzsaUFykyJ+Mqm7Y1n+HesyJDNhOvAn7SW+zWtNkkr2oFPhVaIKY0F sqUag4mqgQgUmiBD9IE5l3iqhftQ6xU= X-Google-Smtp-Source: AOwi7QDxgT6+xIneYa2o3RszmDgeYafujc9eSUPSwPEqo3Gg595HCczaVfFN+y72gfKVTwRUtYz6vA== X-Received: by 10.159.208.2 with SMTP id a2mr9710880plp.370.1508174831016; Mon, 16 Oct 2017 10:27:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:00 -0700 Message-Id: <20171016172609.23422-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH v6 41/50] tcg: take tb_ctx out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/tb-context.h | 2 ++ tcg/tcg.h | 2 -- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 57 +++++++++++++++++++++++--------------------= ---- linux-user/main.c | 6 ++--- 5 files changed, 34 insertions(+), 35 deletions(-) diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 1fa8dcc737..1d41202485 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -41,4 +41,6 @@ struct TBContext { int tb_phys_invalidate_count; }; =20 +extern TBContext tb_ctx; + #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index 6736a9fe2e..58267fd3fd 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -705,8 +705,6 @@ struct TCGContext { /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; =20 - TBContext tb_ctx; - /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ TCGv_env tcg_env; /* *_exec */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 6a4a33235b..bb1b00eaf6 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -327,7 +327,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targe= t_ulong pc, phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); - return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); + return qht_lookup(&tb_ctx.htable, tb_cmp, &desc, h); } =20 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b21671d6f4..86247f87ad 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -154,6 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_ctx; +TBContext tb_ctx; bool parallel_cpus; =20 /* translation block context */ @@ -185,7 +186,7 @@ static void page_table_config_init(void) void tb_lock(void) { assert_tb_unlocked(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); have_tb_lock++; } =20 @@ -193,13 +194,13 @@ void tb_unlock(void) { assert_tb_locked(); have_tb_lock--; - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); } =20 void tb_lock_reset(void) { if (have_tb_lock) { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); have_tb_lock =3D 0; } } @@ -826,15 +827,15 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); + qemu_mutex_init(&tb_ctx.tb_lock); } =20 static void tb_htable_init(void) { unsigned int mode =3D QHT_MODE_AUTO_RESIZE; =20 - qht_init(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); + qht_init(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); } =20 /* Must be called before using the QEMU cpus. 'tb_size' is the size @@ -878,7 +879,7 @@ void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 - g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); + g_tree_remove(tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -940,15 +941,15 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) /* If it is already been done on request of another CPU, * just retry. */ - if (tcg_ctx.tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { + if (tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { goto done; } =20 if (DEBUG_TB_FLUSH_GATE) { - size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); size_t host_size =3D 0; =20 - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); @@ -963,17 +964,16 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 /* Increment the refcount first so that destroy acts as a reset */ - g_tree_ref(tcg_ctx.tb_ctx.tb_tree); - g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + g_tree_ref(tb_ctx.tb_tree); + g_tree_destroy(tb_ctx.tb_tree); =20 - qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); + qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ - atomic_mb_set(&tcg_ctx.tb_ctx.tb_flush_count, - tcg_ctx.tb_ctx.tb_flush_count + 1); + atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); =20 done: tb_unlock(); @@ -982,7 +982,7 @@ done: void tb_flush(CPUState *cpu) { if (tcg_enabled()) { - unsigned tb_flush_count =3D atomic_mb_read(&tcg_ctx.tb_ctx.tb_flus= h_count); + unsigned tb_flush_count =3D atomic_mb_read(&tb_ctx.tb_flush_count); async_safe_run_on_cpu(cpu, do_tb_flush, RUN_ON_CPU_HOST_INT(tb_flush_count)); } @@ -1015,7 +1015,7 @@ do_tb_invalidate_check(struct qht *ht, void *p, uint3= 2_t hash, void *userp) static void tb_invalidate_check(target_ulong address) { address &=3D TARGET_PAGE_MASK; - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_invalidate_check, &address); + qht_iter(&tb_ctx.htable, do_tb_invalidate_check, &address); } =20 static void @@ -1035,7 +1035,7 @@ do_tb_page_check(struct qht *ht, void *p, uint32_t ha= sh, void *userp) /* verify that all the pages have correct rights for code */ static void tb_page_check(void) { - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); + qht_iter(&tb_ctx.htable, do_tb_page_check, NULL); } =20 #endif /* CONFIG_USER_ONLY */ @@ -1135,7 +1135,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, tb->trace_vcpu_dstate); - qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); + qht_remove(&tb_ctx.htable, tb, h); =20 /* remove the TB from the page list */ if (tb->page_addr[0] !=3D page_addr) { @@ -1164,7 +1164,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) /* suppress any remaining jumps to this TB */ tb_jmp_unlink(tb); =20 - tcg_ctx.tb_ctx.tb_phys_invalidate_count++; + tb_ctx.tb_phys_invalidate_count++; } =20 #ifdef CONFIG_SOFTMMU @@ -1280,7 +1280,7 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, /* add in the hash table */ h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, tb->trace_vcpu_dstate); - qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); + qht_insert(&tb_ctx.htable, tb, h); =20 #ifdef CONFIG_USER_ONLY if (DEBUG_TB_CHECK_GATE) { @@ -1443,7 +1443,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); - g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); + g_tree_insert(tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1713,7 +1713,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); + return g_tree_lookup(tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1938,8 +1938,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) =20 tb_lock(); =20 - nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); + nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); + g_tree_foreach(tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); /* @@ -1965,15 +1965,14 @@ void dump_exec_info(FILE *f, fprintf_function cpu_f= printf) tst.direct_jmp2_count, nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 - qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); + qht_statistics_init(&tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); qht_statistics_destroy(&hst); =20 cpu_fprintf(f, "\nStatistics:\n"); cpu_fprintf(f, "TB flush count %u\n", - atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); - cpu_fprintf(f, "TB invalidate count %d\n", - tcg_ctx.tb_ctx.tb_phys_invalidate_count); + atomic_read(&tb_ctx.tb_flush_count)); + cpu_fprintf(f, "TB invalidate count %d\n", tb_ctx.tb_phys_invalidate_c= ount); cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 diff --git a/linux-user/main.c b/linux-user/main.c index 829f974662..b288670121 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -114,7 +114,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) void fork_start(void) { cpu_list_lock(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); mmap_fork_start(); } =20 @@ -130,11 +130,11 @@ void fork_end(int child) QTAILQ_REMOVE(&cpus, cpu, node); } } - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_init(&tb_ctx.tb_lock); qemu_init_cpu_list(); gdbserver_fork(thread_cpu); } else { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); cpu_list_unlock(); } } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177206599206.62605462633098; Mon, 16 Oct 2017 11:06:46 -0700 (PDT) Received: from localhost ([::1]:34485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49mf-0002hD-MU for importer@patchew.org; Mon, 16 Oct 2017 14:06:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ac-0002rA-Lp for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49AY-0003zm-L0 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:18 -0400 Received: from mail-pg0-x236.google.com ([2607:f8b0:400e:c05::236]:48221) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49AY-0003xw-7F for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:14 -0400 Received: by mail-pg0-x236.google.com with SMTP id v78so7337086pgb.5 for ; Mon, 16 Oct 2017 10:27:14 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v6 42/50] tcg: define tcg_init_ctx and make tcg_ctx a pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 10 ++-- tcg/tcg.h | 19 ++++---- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 109 +++++++++++++++++++++-----------------= ---- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 +- target/cris/translate_v10.c | 2 +- target/hppa/translate.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/s390x/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/tcg-op.c | 46 +++++++++--------- tcg/tcg.c | 22 +++++---- 28 files changed, 128 insertions(+), 124 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 48b566c1c9..c58b0b2585 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count =3D tcg_temp_new_i32(); } =20 - tcg_gen_ld_i32(count, tcg_ctx.tcg_env, + tcg_gen_ld_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx.tcg_env, + tcg_gen_st16_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } =20 @@ -56,13 +56,13 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ - tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next =3D 0; + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next =3D 0; } =20 static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } @@ -70,7 +70,7 @@ static inline void gen_io_start(void) static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/tcg/tcg.h b/tcg/tcg.h index 58267fd3fd..859020a0fd 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -730,18 +730,19 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; =20 -extern TCGContext tcg_ctx; +extern TCGContext tcg_init_ctx; +extern TCGContext *tcg_ctx; =20 static inline size_t temp_idx(TCGTemp *ts) { - ptrdiff_t n =3D ts - tcg_ctx.temps; - tcg_debug_assert(n > 0 && n < tcg_ctx.nb_temps); + ptrdiff_t n =3D ts - tcg_ctx->temps; + tcg_debug_assert(n > 0 && n < tcg_ctx->nb_temps); return n; } =20 static inline TCGTemp *idx_temp(size_t n) { - return n =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[n]; + return n =3D=3D TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx->temps[n]; } =20 static inline TCGArg temp_arg(TCGTemp *ts) @@ -781,13 +782,13 @@ static inline TCGArg tcgv_ptr_arg(TCGv_ptr t) =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { - tcg_ctx.gen_op_buf[op_idx].args[arg] =3D v; + tcg_ctx->gen_op_buf[op_idx].args[arg] =3D v; } =20 /* The number of opcodes emitted so far. */ static inline int tcg_op_buf_count(void) { - return tcg_ctx.gen_next_op_idx; + return tcg_ctx->gen_next_op_idx; } =20 /* Test for whether to terminate the TB for using too many opcodes. */ @@ -806,7 +807,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s); /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; uint8_t *ptr, *ptr_end; =20 /* ??? This is a weak placeholder for minimum malloc alignment. */ @@ -815,7 +816,7 @@ static inline void *tcg_malloc(int size) ptr =3D s->pool_cur; ptr_end =3D ptr + size; if (unlikely(ptr_end > s->pool_end)) { - return tcg_malloc_internal(&tcg_ctx, size); + return tcg_malloc_internal(tcg_ctx, size); } else { s->pool_cur =3D ptr_end; return ptr; @@ -1154,7 +1155,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #else # define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) + ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_pt= r) #endif =20 void tcg_register_jit(void *buf, size_t buf_size); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 25f0cabfed..4172ffda82 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -153,7 +153,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb =3D=3D NULL) { - return tcg_ctx.code_gen_epilogue; + return tcg_ctx->code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 86247f87ad..826d9869dd 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -153,7 +153,8 @@ static int v_l2_levels; static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ -TCGContext tcg_ctx; +TCGContext tcg_init_ctx; +TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 @@ -209,7 +210,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); =20 void cpu_gen_init(void) { - tcg_context_init(&tcg_ctx);=20 + tcg_context_init(&tcg_init_ctx); } =20 /* Encode VAL as a signed leb128 sequence at P. @@ -267,7 +268,7 @@ static target_long decode_sleb128(uint8_t **pp) =20 static int encode_search(TranslationBlock *tb, uint8_t *block) { - uint8_t *highwater =3D tcg_ctx.code_gen_highwater; + uint8_t *highwater =3D tcg_ctx->code_gen_highwater; uint8_t *p =3D block; int i, j, n; =20 @@ -280,12 +281,12 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) if (i =3D=3D 0) { prev =3D (j =3D=3D 0 ? tb->pc : 0); } else { - prev =3D tcg_ctx.gen_insn_data[i - 1][j]; + prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } - p =3D encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); } - prev =3D (i =3D=3D 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]); - p =3D encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev); + prev =3D (i =3D=3D 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); =20 /* Test for (pending) buffer overflow. The assumption is that any one row beginning below the high water mark cannot overrun @@ -345,8 +346,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx.restore_time +=3D profile_getclock() - ti; - tcg_ctx.restore_count++; + tcg_ctx->restore_time +=3D profile_getclock() - ti; + tcg_ctx->restore_count++; #endif return 0; } @@ -592,7 +593,7 @@ static inline void *split_cross_256mb(void *buf1, size_= t size1) buf1 =3D buf2; } =20 - tcg_ctx.code_gen_buffer_size =3D size1; + tcg_ctx->code_gen_buffer_size =3D size1; return buf1; } #endif @@ -655,16 +656,16 @@ static inline void *alloc_code_gen_buffer(void) size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx.code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) + if (size > tcg_ctx->code_gen_buffer_size) { + size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) & qemu_real_host_page_mask) - (uintptr_t)buf; } - tcg_ctx.code_gen_buffer_size =3D size; + tcg_ctx->code_gen_buffer_size =3D size; =20 #ifdef __mips__ if (cross_256mb(buf, size)) { buf =3D split_cross_256mb(buf, size); - size =3D tcg_ctx.code_gen_buffer_size; + size =3D tcg_ctx->code_gen_buffer_size; } #endif =20 @@ -677,7 +678,7 @@ static inline void *alloc_code_gen_buffer(void) #elif defined(_WIN32) static inline void *alloc_code_gen_buffer(void) { - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf1, *buf2; =20 /* Perform the allocation in two steps, so that the guard page @@ -696,7 +697,7 @@ static inline void *alloc_code_gen_buffer(void) { int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf; =20 /* Constrain the position of the buffer based on the host cpu. @@ -713,7 +714,7 @@ static inline void *alloc_code_gen_buffer(void) flags |=3D MAP_32BIT; /* Cannot expect to map more than 800MB in low memory. */ if (size > 800u * 1024 * 1024) { - tcg_ctx.code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; + tcg_ctx->code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; } # elif defined(__sparc__) start =3D 0x40000000ul; @@ -753,7 +754,7 @@ static inline void *alloc_code_gen_buffer(void) default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); - size2 =3D tcg_ctx.code_gen_buffer_size; + size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); } else { @@ -821,9 +822,9 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer b= p) =20 static inline void code_gen_alloc(size_t tb_size) { - tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); - tcg_ctx.code_gen_buffer =3D alloc_code_gen_buffer(); - if (tcg_ctx.code_gen_buffer =3D=3D NULL) { + tcg_ctx->code_gen_buffer_size =3D size_code_gen_buffer(tb_size); + tcg_ctx->code_gen_buffer =3D alloc_code_gen_buffer(); + if (tcg_ctx->code_gen_buffer =3D=3D NULL) { fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } @@ -851,7 +852,7 @@ void tcg_exec_init(unsigned long tb_size) #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); #endif } =20 @@ -867,7 +868,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) =20 assert_tb_locked(); =20 - tb =3D tcg_tb_alloc(&tcg_ctx); + tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(tb =3D=3D NULL)) { return NULL; } @@ -951,11 +952,11 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); } - if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) - > tcg_ctx.code_gen_buffer_size) { + if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) + > tcg_ctx->code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); } =20 @@ -970,7 +971,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; + tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1318,44 +1319,44 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cpu_loop_exit(cpu); } =20 - gen_code_buf =3D tcg_ctx.code_gen_ptr; + gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tcg_ctx.tb_cflags =3D cflags; + tcg_ctx->tb_cflags =3D cflags; =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count1++; /* includes aborted translations because of + tcg_ctx->tb_count1++; /* includes aborted translations because of exceptions */ ti =3D profile_getclock(); #endif =20 - tcg_func_start(&tcg_ctx); + tcg_func_start(tcg_ctx); =20 - tcg_ctx.cpu =3D ENV_GET_CPU(env); + tcg_ctx->cpu =3D ENV_GET_CPU(env); gen_intermediate_code(cpu, tb); - tcg_ctx.cpu =3D NULL; + tcg_ctx->cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_RESET_OFFSET_INVALID; - tcg_ctx.tb_jmp_reset_offset =3D tb->jmp_reset_offset; + tcg_ctx->tb_jmp_reset_offset =3D tb->jmp_reset_offset; if (TCG_TARGET_HAS_direct_jump) { - tcg_ctx.tb_jmp_insn_offset =3D tb->jmp_target_arg; - tcg_ctx.tb_jmp_target_addr =3D NULL; + tcg_ctx->tb_jmp_insn_offset =3D tb->jmp_target_arg; + tcg_ctx->tb_jmp_target_addr =3D NULL; } else { - tcg_ctx.tb_jmp_insn_offset =3D NULL; - tcg_ctx.tb_jmp_target_addr =3D tb->jmp_target_arg; + tcg_ctx->tb_jmp_insn_offset =3D NULL; + tcg_ctx->tb_jmp_target_addr =3D tb->jmp_target_arg; } =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count++; - tcg_ctx.interm_time +=3D profile_getclock() - ti; + tcg_ctx->tb_count++; + tcg_ctx->interm_time +=3D profile_getclock() - ti; ti =3D profile_getclock(); #endif =20 @@ -1364,7 +1365,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, the tcg optimization currently hidden inside tcg_gen_code. All that should be required is to flush the TBs, allocate a new TB, re-initialize it per above, and re-do the actual code generation. = */ - gen_code_size =3D tcg_gen_code(&tcg_ctx, tb); + gen_code_size =3D tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { goto buffer_overflow; } @@ -1375,10 +1376,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock() - ti; - tcg_ctx.code_in_len +=3D tb->size; - tcg_ctx.code_out_len +=3D gen_code_size; - tcg_ctx.search_out_len +=3D search_size; + tcg_ctx->code_time +=3D profile_getclock() - ti; + tcg_ctx->code_in_len +=3D tb->size; + tcg_ctx->code_out_len +=3D gen_code_size; + tcg_ctx->search_out_len +=3D search_size; #endif =20 #ifdef DEBUG_DISAS @@ -1386,8 +1387,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); - if (tcg_ctx.data_gen_ptr) { - size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc.ptr; + if (tcg_ctx->data_gen_ptr) { + size_t code_size =3D tcg_ctx->data_gen_ptr - tb->tc.ptr; size_t data_size =3D gen_code_size - code_size; size_t i; =20 @@ -1396,12 +1397,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu, for (i =3D 0; i < data_size; i +=3D sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) =3D=3D 8) { qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n= ", - (uintptr_t)tcg_ctx.data_gen_ptr + i, - *(uint64_t *)(tcg_ctx.data_gen_ptr + i)); + (uintptr_t)tcg_ctx->data_gen_ptr + i, + *(uint64_t *)(tcg_ctx->data_gen_ptr + i)); } else { qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", - (uintptr_t)tcg_ctx.data_gen_ptr + i, - *(uint32_t *)(tcg_ctx.data_gen_ptr + i)); + (uintptr_t)tcg_ctx->data_gen_ptr + i, + *(uint32_t *)(tcg_ctx->data_gen_ptr + i)); } } } else { @@ -1413,7 +1414,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx.code_gen_ptr =3D (void *) + tcg_ctx->code_gen_ptr =3D (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, CODE_GEN_ALIGN); =20 @@ -1948,8 +1949,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index 836daac15c..392c0ed5fb 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -977,7 +977,7 @@ int main(int argc, char **argv) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/linux-user/main.c b/linux-user/main.c index b288670121..5f40c1a702 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4457,7 +4457,7 @@ int main(int argc, char **argv, char **envp) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 53b8c036e2..f6247bf38d 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -127,7 +127,7 @@ void alpha_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 31; i++) { cpu_std_ir[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/arm/translate.c b/target/arm/translate.c index 397cc7afea..7873c03ae8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -82,7 +82,7 @@ void arm_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 16; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/cris/translate.c b/target/cris/translate.c index 07ec2b1831..cd420e018f 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3369,7 +3369,7 @@ void cris_initialize_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 4a0b485d8e..5d489203f4 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1273,7 +1273,7 @@ void cris_initialize_crisv10_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 08b2c73291..9059812d4e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -127,7 +127,7 @@ void hppa_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gr[0]); for (i =3D 1; i < 32; i++) { diff --git a/target/i386/translate.c b/target/i386/translate.c index 6663cd1db8..dde7b144bd 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8331,7 +8331,7 @@ void tcg_x86_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_cc_op =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_o= p"); cpu_cc_dst =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_ds= t), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index d4a2e00165..6707967a2c 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1209,7 +1209,7 @@ void lm32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3506864030..26c8b4e0ba 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -70,7 +70,7 @@ void m68k_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 #define DEFO32(name, offset) \ QREG_##name =3D tcg_global_mem_new_i32(cpu_env, \ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c70a2d6644..22f8d6230b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1856,7 +1856,7 @@ void mb_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 env_debug =3D tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), diff --git a/target/mips/translate.c b/target/mips/translate.c index aadffbec39..7dfa94ab26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20455,7 +20455,7 @@ void mips_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gpr[0]); for (i =3D 1; i < 32; i++) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 3f1e609028..59c70b5cef 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -102,7 +102,7 @@ void moxie_translate_init(void) }; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i =3D 0; i < 16; i++) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 666d050650..b031f2db97 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -81,7 +81,7 @@ void openrisc_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_sr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5e637d2e97..2db0fe77ff 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -86,7 +86,7 @@ void ppc_translate_init(void) size_t cpu_reg_names_size; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 p =3D cpu_reg_names; cpu_reg_names_size =3D sizeof(cpu_reg_names); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 399aeb2800..1c58643293 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -113,7 +113,7 @@ void s390x_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; psw_addr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index f918bae978..c13be851ba 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -100,7 +100,7 @@ void sh4_translate_init(void) }; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 24; i++) { cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0669d4e8e5..adb286de8f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5917,7 +5917,7 @@ void sparc_tcg_init(void) unsigned int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 cpu_regwptr =3D tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index 5cd84f6b25..a744c38bb7 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2446,7 +2446,7 @@ void tilegx_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), = "pc"); for (i =3D 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 042c0e69bc..590cbbee8b 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8882,7 +8882,7 @@ void tricore_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; /* reg init */ for (i =3D 0 ; i < 16 ; i++) { cpu_gpr_a[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index d717de0335..070653e2d1 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -75,7 +75,7 @@ void uc32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f62319eddd..ab96b77d88 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -222,7 +222,7 @@ void xtensa_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3253451115..7764e2a497 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -48,7 +48,7 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); =20 static inline TCGOp *tcg_emit_op(TCGOpcode opc) { - TCGContext *ctx =3D &tcg_ctx; + TCGContext *ctx =3D tcg_ctx; int oi =3D ctx->gen_next_op_idx; int ni =3D oi + 1; int pi =3D oi - 1; @@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, T= CGArg a3, =20 void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx.tb_cflags & CF_PARALLEL) { + if (tcg_ctx->tb_cflags & CF_PARALLEL) { tcg_gen_op1(INDEX_op_mb, mb_type); } } @@ -2552,8 +2552,8 @@ void tcg_gen_goto_tb(unsigned idx) tcg_debug_assert(idx <=3D 1); #ifdef CONFIG_DEBUG_TCG /* Verify that we havn't seen this numbered exit before. */ - tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) =3D=3D 0); - tcg_ctx.goto_tb_issue_mask |=3D 1 << idx; + tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) =3D=3D 0); + tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif tcg_gen_op1i(INDEX_op_goto_tb, idx); } @@ -2562,7 +2562,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2648,7 +2648,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2657,7 +2657,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2676,7 +2676,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2690,7 +2690,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2806,11 +2806,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv= addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif =20 if (memop & MO_SIGN) { @@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -2851,14 +2851,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv= addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(retv, 0); @@ -2914,11 +2914,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv add= r, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx= )); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif =20 if (memop & MO_SIGN) { @@ -2959,14 +2959,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv add= r, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); @@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ diff --git a/tcg/tcg.c b/tcg/tcg.c index 7cf39f7067..e509fdc255 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -243,7 +243,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, t= cg_insn_unit *ptr) =20 TCGLabel *gen_new_label(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGLabel *l =3D tcg_malloc(sizeof(TCGLabel)); =20 *l =3D (TCGLabel){ @@ -385,6 +385,8 @@ void tcg_context_init(TCGContext *s) for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { indirect_reg_alloc_order[i] =3D tcg_target_reg_alloc_order[i]; } + + tcg_ctx =3D s; } =20 /* @@ -526,7 +528,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t = start, intptr_t size) =20 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -538,7 +540,7 @@ TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char = *name) =20 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -551,7 +553,7 @@ TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char = *name) int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *base_ts =3D &s->temps[GET_TCGV_PTR(base)]; TCGTemp *ts =3D tcg_global_alloc(s); int indirect_reg =3D 0, bigendian =3D 0; @@ -606,7 +608,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr = base, =20 static int tcg_temp_new_internal(TCGType type, int temp_local) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int idx, k; =20 @@ -668,7 +670,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) =20 static void tcg_temp_free_internal(int idx) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int k; =20 @@ -733,13 +735,13 @@ TCGv_i64 tcg_const_local_i64(int64_t val) #if defined(CONFIG_DEBUG_TCG) void tcg_clear_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; s->temps_in_use =3D 0; } =20 int tcg_check_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; if (s->temps_in_use) { /* Clear the count so that we don't give another * warning immediately next time around. @@ -979,7 +981,7 @@ bool tcg_op_supported(TCGOpcode op) and endian swap in tcg_reg_alloc_call(). */ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; @@ -2924,7 +2926,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int64_t tb_count =3D s->tb_count; int64_t tb_div_count =3D tb_count ? tb_count : 1; int64_t tot =3D s->interm_time + s->code_time; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177009057914.0120303273419; Mon, 16 Oct 2017 11:03:29 -0700 (PDT) Received: from localhost ([::1]:34461 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49jY-00006k-B4 for importer@patchew.org; Mon, 16 Oct 2017 14:03:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Aa-0002oL-61 for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v6 43/50] gen-icount: fold exitreq_label into TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 7 +++---- tcg/tcg.h | 2 ++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index c58b0b2585..fe80176462 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -6,13 +6,12 @@ /* Helpers for instruction counting code generation. */ =20 static int icount_start_insn_idx; -static TCGLabel *exitreq_label; =20 static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count, imm; =20 - exitreq_label =3D gen_new_label(); + tcg_ctx->exitreq_label =3D gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { count =3D tcg_temp_local_new_i32(); } else { @@ -34,7 +33,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(imm); } =20 - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx->tcg_env, @@ -52,7 +51,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int n= um_insns) tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); } =20 - gen_set_label(exitreq_label); + gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index 859020a0fd..dd11d9f835 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -717,6 +717,8 @@ struct TCGContext { struct TCGLabelPoolData *pool_labels; #endif =20 + TCGLabel *exitreq_label; + TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177174861897.5414242987029; Mon, 16 Oct 2017 11:06:14 -0700 (PDT) Received: from localhost ([::1]:34479 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49m4-0002Ba-J0 for importer@patchew.org; Mon, 16 Oct 2017 14:06:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52800) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ab-0002pM-5b for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49Aa-00041e-By for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:17 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:46254) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49Aa-00040w-5j for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:16 -0400 Received: by mail-pf0-x234.google.com with SMTP id p87so16296522pfj.3 for ; Mon, 16 Oct 2017 10:27:16 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vCy259Hd0iPkc7/74Haae/g7ny02+7f0iEMwV2uAIVI=; b=VlBO/fdEoBeNW3MLqaJPlq8nTgP+umFv5Wxbv3869MeYD/pDSqWrk6blyXbUXkPtig IyBOt6Su8WWydsWMwqPO0Nwh+gUVgq94HCFQ2bQhSxINqQviVazSGs1wxsP2gbwySNLT +GrFhmudMN/vNuCbtJfvIN9XbWGbuphzuTTeQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vCy259Hd0iPkc7/74Haae/g7ny02+7f0iEMwV2uAIVI=; b=Ewm/k4rUmwUuI39VO76vhAVjrAOGpjrzx33qZr7r2vmhiEjoAFseKplB0HP8VLlmUh MJMUAQ2DNV1ix/eKym2H0QSAlcQ/hy/w2yOmKkDzp8AawN2sYjqwGI7wCMsPaGadhVjn RWbLbQQfKceTXBDLpneC1HKQ2Lp/zmwGBpPJGXQP63KvGGXNbAm5m5zp/fbqFymSLYWr vYNQI9UgIsZOEWvnHYzX/h0tz2wqhrsJouS2WuwkX5lPUxjC5aeQnh08FgGtImzIOQPn MRWT6zNdig+xuOXB3rXgNubBZlWqgcwKsmyLh3pNh2Z4QRxh4vPbV2X/bAOcJjtFM1ow KJKQ== X-Gm-Message-State: AMCzsaW24vW0dx2s/Tq6GLN3ZNKtzE25T1ce310XTbn9vAl/pdmEFrJJ eixvg3cf+jvIU2mnp6x7SFQ7LDPtXqo= X-Google-Smtp-Source: AOwi7QAX+ZaUtKa5sek9Yydp2EsPj9/feRCwvtw/9Jqq0pxbEYI74nZCFRuTAbL1+uxlcloj8DSyZQ== X-Received: by 10.98.58.69 with SMTP id h66mr9275093pfa.121.1508174835064; Mon, 16 Oct 2017 10:27:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:03 -0700 Message-Id: <20171016172609.23422-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PATCH v6 44/50] tcg: introduce **tcg_ctxs to keep track of all TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Note that having n_tcg_ctxs is unnecessary. However, it is convenient to have it, since it will simplify iterating over the array: we'll have just a for loop instead of having to iterate over a NULL-terminated array (which would require n+1 elems) or having to check with ifdef's for usermode/softmmu. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index e509fdc255..225e7cccea 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -118,6 +118,9 @@ static bool tcg_out_ldst_finalize(TCGContext *s); =20 #define TCG_HIGHWATER 1024 =20 +static TCGContext **tcg_ctxs; +static unsigned int n_tcg_ctxs; + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -387,6 +390,8 @@ void tcg_context_init(TCGContext *s) } =20 tcg_ctx =3D s; + tcg_ctxs =3D &tcg_ctx; + n_tcg_ctxs =3D 1; } =20 /* --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176332971189.38546081803383; Mon, 16 Oct 2017 10:52:12 -0700 (PDT) Received: from localhost ([::1]:34399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49YQ-0006SO-3i for importer@patchew.org; Mon, 16 Oct 2017 13:51:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Af-0002tz-AY for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49Ac-00043U-1t for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:21 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:47608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49Ab-00042W-Q2 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:17 -0400 Received: by mail-pf0-x236.google.com with SMTP id z11so16298919pfk.4 for ; Mon, 16 Oct 2017 10:27:17 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UFyA04crwXq2Ky2kUeX488IkU0fCRnaCfCacYkCL7m0=; b=fdvy7Kv6gRZfjFcBb7EmOHThVZrjHCY2Xxy2ABbiLsSsvn1EfImV2TQd/OuSVcmUAZ d/bO0SY8GJAK8tdm/q9EoFtrbLXtBh744D2LhKQv/Vi0FVWOIc/HkvYV+sI/WZzGEbOU +4+fWMP3XflzxBIJIxOIF7U7dS8E4aXyi6V2U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UFyA04crwXq2Ky2kUeX488IkU0fCRnaCfCacYkCL7m0=; b=ox2+7DTBXAPr5I3pC+B0UqnG2nXMCuyBrWxshOS5hjjZliExnQzpqmKFGRcVsUMiV7 xl0BDjgAa6uzlp9G1o1DBUxXPvzuHckz2X21xAn754DcYJ+NHKaS1WZQZOd9O/bMFhhh QgvrNBR0+CBHrj8JWE5b43+W0wF59iEYUdtcLCAZ40mGM6cUL+KFYam/52w77EZ5gEbO vL2ZHa8s8tHbLlCBVniUQ/KUoLh7DGLER1Nyllh5BO8RtWY03BS9y2fdcKswhr08XX8/ PDWmKktBKJHhxr9vsndO3TlVZ1SwBxBP1yF2wFpSBC4Uy+G+0uQEvF4B0+r12dg42py2 F8rA== X-Gm-Message-State: AMCzsaUISbSMgVHg4jybj0ZgKTI7YIOsvUzb8Mh08WDb+5SbF2NneuP2 zVAMC5ilFXtappMPC7VdNzOyUYUQxAE= X-Google-Smtp-Source: AOwi7QB0/O0vJEFd7ylXdfBraafx5zhtDTAXBDGB0VJghuvTjGj9wfoCKfFjpr3KIgTw9vVgeyFpFQ== X-Received: by 10.159.211.7 with SMTP id bc7mr9701646plb.425.1508174836489; Mon, 16 Oct 2017 10:27:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:04 -0700 Message-Id: <20171016172609.23422-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PATCH v6 45/50] tcg: distribute profiling counters across TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This is groundwork for supporting multiple TCG contexts. To avoid scalability issues when profiling info is enabled, this patch makes the profiling info counters distributed via the following changes: 1) Consolidate profile info into its own struct, TCGProfile, which TCGContext also includes. Note that tcg_table_op_count is brought into TCGProfile after dropping the tcg_ prefix. 2) Iterate over the TCG contexts in the system to obtain the total counts. This change also requires updating the accessors to TCGProfile fields to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 38 +++++++++------- accel/tcg/translate-all.c | 23 +++++----- tcg/tcg.c | 110 ++++++++++++++++++++++++++++++++++++++----= ---- 3 files changed, 126 insertions(+), 45 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index dd11d9f835..50ebe76aca 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -641,6 +641,26 @@ QEMU_BUILD_BUG_ON(sizeof(TCGOp) !=3D 8 + sizeof(TCGArg= ) * MAX_OPC_PARAM); QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16)); =20 +typedef struct TCGProfile { + int64_t tb_count1; + int64_t tb_count; + int64_t op_count; /* total insn count */ + int op_count_max; /* max insn per TB */ + int64_t temp_count; + int temp_count_max; + int64_t del_op_count; + int64_t code_in_len; + int64_t code_out_len; + int64_t search_out_len; + int64_t interm_time; + int64_t code_time; + int64_t la_time; + int64_t opt_time; + int64_t restore_count; + int64_t restore_time; + int64_t table_op_count[NB_OPS]; +} TCGProfile; + struct TCGContext { uint8_t *pool_cur, *pool_end; TCGPool *pool_first, *pool_current, *pool_first_large; @@ -665,23 +685,7 @@ struct TCGContext { tcg_insn_unit *code_ptr; =20 #ifdef CONFIG_PROFILER - /* profiling info */ - int64_t tb_count1; - int64_t tb_count; - int64_t op_count; /* total insn count */ - int op_count_max; /* max insn per TB */ - int64_t temp_count; - int temp_count_max; - int64_t del_op_count; - int64_t code_in_len; - int64_t code_out_len; - int64_t search_out_len; - int64_t interm_time; - int64_t code_time; - int64_t la_time; - int64_t opt_time; - int64_t restore_count; - int64_t restore_time; + TCGProfile prof; #endif =20 #ifdef CONFIG_DEBUG_TCG diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 826d9869dd..614bb3adcc 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -312,6 +312,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti =3D profile_getclock(); #endif =20 @@ -346,8 +347,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx->restore_time +=3D profile_getclock() - ti; - tcg_ctx->restore_count++; + atomic_set(&prof->restore_time, + prof->restore_time + profile_getclock() - ti); + atomic_set(&prof->restore_count, prof->restore_count + 1); #endif return 0; } @@ -1302,6 +1304,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_insn_unit *gen_code_buf; int gen_code_size, search_size; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; #endif assert_memory_lock(); @@ -1329,8 +1332,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tb_cflags =3D cflags; =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count1++; /* includes aborted translations because of - exceptions */ + /* includes aborted translations because of exceptions */ + atomic_set(&prof->tb_count1, prof->tb_count1 + 1); ti =3D profile_getclock(); #endif =20 @@ -1355,8 +1358,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count++; - tcg_ctx->interm_time +=3D profile_getclock() - ti; + atomic_set(&prof->tb_count, prof->tb_count + 1); + atomic_set(&prof->interm_time, prof->interm_time + profile_getclock() = - ti); ti =3D profile_getclock(); #endif =20 @@ -1376,10 +1379,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx->code_time +=3D profile_getclock() - ti; - tcg_ctx->code_in_len +=3D tb->size; - tcg_ctx->code_out_len +=3D gen_code_size; - tcg_ctx->search_out_len +=3D search_size; + atomic_set(&prof->code_time, prof->code_time + profile_getclock() - ti= ); + atomic_set(&prof->code_in_len, prof->code_in_len + tb->size); + atomic_set(&prof->code_out_len, prof->code_out_len + gen_code_size); + atomic_set(&prof->search_out_len, prof->search_out_len + search_size); #endif =20 #ifdef DEBUG_DISAS diff --git a/tcg/tcg.c b/tcg/tcg.c index 225e7cccea..4b7dc800ec 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1560,7 +1560,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) memset(op, 0, sizeof(*op)); =20 #ifdef CONFIG_PROFILER - s->del_op_count++; + atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); #endif } =20 @@ -2731,15 +2731,79 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) =20 #ifdef CONFIG_PROFILER =20 -static int64_t tcg_table_op_count[NB_OPS]; +/* avoid copy/paste errors */ +#define PROF_ADD(to, from, field) \ + do { \ + (to)->field +=3D atomic_read(&((from)->field)); \ + } while (0) + +#define PROF_MAX(to, from, field) \ + do { \ + typeof((from)->field) val__ =3D atomic_read(&((from)->field)); \ + if (val__ > (to)->field) { \ + (to)->field =3D val__; \ + } \ + } while (0) + +/* Pass in a zero'ed @prof */ +static inline +void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) +{ + unsigned int i; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGProfile *orig =3D &tcg_ctxs[i]->prof; + + if (counters) { + PROF_ADD(prof, orig, tb_count1); + PROF_ADD(prof, orig, tb_count); + PROF_ADD(prof, orig, op_count); + PROF_MAX(prof, orig, op_count_max); + PROF_ADD(prof, orig, temp_count); + PROF_MAX(prof, orig, temp_count_max); + PROF_ADD(prof, orig, del_op_count); + PROF_ADD(prof, orig, code_in_len); + PROF_ADD(prof, orig, code_out_len); + PROF_ADD(prof, orig, search_out_len); + PROF_ADD(prof, orig, interm_time); + PROF_ADD(prof, orig, code_time); + PROF_ADD(prof, orig, la_time); + PROF_ADD(prof, orig, opt_time); + PROF_ADD(prof, orig, restore_count); + PROF_ADD(prof, orig, restore_time); + } + if (table) { + int i; + + for (i =3D 0; i < NB_OPS; i++) { + PROF_ADD(prof, orig, table_op_count[i]); + } + } + } +} + +#undef PROF_ADD +#undef PROF_MAX + +static void tcg_profile_snapshot_counters(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, true, false); +} + +static void tcg_profile_snapshot_table(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, false, true); +} =20 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { + TCGProfile prof =3D {}; int i; =20 + tcg_profile_snapshot_table(&prof); for (i =3D 0; i < NB_OPS; i++) { cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, - tcg_table_op_count[i]); + prof.table_op_count[i]); } } #else @@ -2752,6 +2816,9 @@ void tcg_dump_op_count(FILE *f, fprintf_function cpu_= fprintf) =20 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) { +#ifdef CONFIG_PROFILER + TCGProfile *prof =3D &s->prof; +#endif int i, oi, oi_next, num_insns; =20 #ifdef CONFIG_PROFILER @@ -2759,15 +2826,15 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) int n; =20 n =3D s->gen_op_buf[0].prev + 1; - s->op_count +=3D n; - if (n > s->op_count_max) { - s->op_count_max =3D n; + atomic_set(&prof->op_count, prof->op_count + n); + if (n > prof->op_count_max) { + atomic_set(&prof->op_count_max, n); } =20 n =3D s->nb_temps; - s->temp_count +=3D n; - if (n > s->temp_count_max) { - s->temp_count_max =3D n; + atomic_set(&prof->temp_count, prof->temp_count + n); + if (n > prof->temp_count_max) { + atomic_set(&prof->temp_count_max, n); } } #endif @@ -2784,7 +2851,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif =20 #ifdef USE_TCG_OPTIMIZATIONS @@ -2792,8 +2859,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time +=3D profile_getclock(); - s->la_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); + atomic_set(&prof->la_time, prof->la_time - profile_getclock()); #endif =20 liveness_pass_1(s); @@ -2817,7 +2884,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } =20 #ifdef CONFIG_PROFILER - s->la_time +=3D profile_getclock(); + atomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif =20 #ifdef DEBUG_DISAS @@ -2850,7 +2917,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 oi_next =3D op->next; #ifdef CONFIG_PROFILER - tcg_table_op_count[opc]++; + atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] += 1); #endif =20 switch (opc) { @@ -2931,10 +2998,17 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D tcg_ctx; - int64_t tb_count =3D s->tb_count; - int64_t tb_div_count =3D tb_count ? tb_count : 1; - int64_t tot =3D s->interm_time + s->code_time; + TCGProfile prof =3D {}; + const TCGProfile *s; + int64_t tb_count; + int64_t tb_div_count; + int64_t tot; + + tcg_profile_snapshot_counters(&prof); + s =3D &prof; + tb_count =3D s->tb_count; + tb_div_count =3D tb_count ? tb_count : 1; + tot =3D s->interm_time + s->code_time; =20 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n= ", tot, tot / 2.4e9); --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177350865517.9090233168142; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uJ+6idNGx8Q+mUo4Bnbv/J0eV4RGBdO4S7TS3gW8eL4=; b=YsGef0PXwF5kbJzuJnFXeJ8rDAvpeF+bINtn4rt60nLkh05rins48uZXTkNyw2CPjw ymb00DYbpnfRII5mSu3TM1rg8f/T7Lj9sY2NeTbnC05uWNJax56JeCh8iqhLB5qUAp5b xsUfQndVDQ6fbj3b40KiGsEDv1qm/jFT0pZE0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uJ+6idNGx8Q+mUo4Bnbv/J0eV4RGBdO4S7TS3gW8eL4=; b=GDX9Uk/OWOFJMSmv97jcuIzEZa3ihCgnGBSE5tJ7+AD8uQUcFM4VhgPyvEKYV+IHxZ 8Uq75+sn2H6dLCgy5a67WK5BlUm1yxJ61vBdxbKcIEYD4/UmRNHIMkCcsReRXcl8wGcl T0tnNaq4N5vO+sw+1WpXdNMDWhtMojvqv0y0wb5glLvF46y91CUTiyzrRFWQknHiaL+S JihEyHR+uvdGRW1sqIISMX728TACGsTUMmYKVNMJ1ZdvzRg+CUwXA+NDjx7Etix0kmA6 a3vcGzCl0VPsPKEyJL4m4cKaUKptH5jfTtKjEU6xtyBbw2TAvUf0YhTjqtYuYdvCu+93 CWbw== X-Gm-Message-State: AMCzsaXxoHxrktQqWtRfXQ4D52Eq0S4mI3A/q3QYAlJpHAHMd55zEheG tCT+S1hGdXQ1MAIbd6VTImFDikoRgFY= X-Google-Smtp-Source: AOwi7QCKHXe9hKzC10N6OR6P/REqUgb0k3aTJwXSx47orQzwaaCpxK750zPw/2+ZRRjlLNIIdurZZA== X-Received: by 10.84.173.4 with SMTP id o4mr9483914plb.152.1508174837914; Mon, 16 Oct 2017 10:27:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:05 -0700 Message-Id: <20171016172609.23422-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PATCH v6 46/50] tcg: allocate optimizer temps with tcg_malloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. While at it, also allocate temps_used directly as a bitmap of the required size, instead of using a bitmap of TCG_MAX_TEMPS via TCGTempSet. Performance-wise we lose about 1.12% in a translation-heavy workload such as booting+shutting down debian-arm: Performance counter stats for 'taskset -c 0 arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Ddie-on-boot.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): exec time (s) Relative slowdown wrt original (%) Suggested-by: Richard Henderson --------------------------------------------------------------- original 20.213321616 0. tcg_malloc 20.441130078 1.1270214 TCGContext 20.477846517 1.3086662 g_malloc 20.780527895 2.8061013 The other two alternatives shown in the table are: - TCGContext: embed temps[TCG_MAX_TEMPS] and TCGTempSet used_temps in TCGContext. This is simple enough but it isn't faster than using tcg_malloc; moreover, it wastes memory. - g_malloc: allocate/deallocate both temps and used_temps every time tcg_optimize is executed. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/optimize.c | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index ead7bb5e4f..847dfa44c9 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -40,9 +40,6 @@ struct tcg_temp_info { tcg_target_ulong mask; }; =20 -static struct tcg_temp_info temps_[TCG_MAX_TEMPS]; -static TCGTempSet temps_used; - static inline struct tcg_temp_info *ts_info(TCGTemp *ts) { return ts->state_ptr; @@ -93,31 +90,27 @@ static void reset_temp(TCGArg arg) reset_ts(arg_temp(arg)); } =20 -/* Reset all temporaries, given that there are NB_TEMPS of them. */ -static void reset_all_temps(int nb_temps) -{ - bitmap_zero(temps_used.l, nb_temps); -} - /* Initialize and activate a temporary. */ -static void init_ts_info(TCGTemp *ts) +static void init_ts_info(struct tcg_temp_info *infos, + TCGTempSet *temps_used, TCGTemp *ts) { size_t idx =3D temp_idx(ts); - if (!test_bit(idx, temps_used.l)) { - struct tcg_temp_info *ti =3D &temps_[idx]; + if (!test_bit(idx, temps_used->l)) { + struct tcg_temp_info *ti =3D &infos[idx]; =20 ts->state_ptr =3D ti; ti->next_copy =3D ts; ti->prev_copy =3D ts; ti->is_const =3D false; ti->mask =3D -1; - set_bit(idx, temps_used.l); + set_bit(idx, temps_used->l); } } =20 -static void init_arg_info(TCGArg arg) +static void init_arg_info(struct tcg_temp_info *infos, + TCGTempSet *temps_used, TCGArg arg) { - init_ts_info(arg_temp(arg)); + init_ts_info(infos, temps_used, arg_temp(arg)); } =20 static int op_bits(TCGOpcode op) @@ -616,6 +609,8 @@ void tcg_optimize(TCGContext *s) { int oi, oi_next, nb_temps, nb_globals; TCGOp *prev_mb =3D NULL; + struct tcg_temp_info *infos; + TCGTempSet temps_used; =20 /* Array VALS has an element for each temp. If this temp holds a constant then its value is kept in VALS' eleme= nt. @@ -624,7 +619,8 @@ void tcg_optimize(TCGContext *s) =20 nb_temps =3D s->nb_temps; nb_globals =3D s->nb_globals; - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); + infos =3D tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { tcg_target_ulong mask, partmask, affected; @@ -645,14 +641,14 @@ void tcg_optimize(TCGContext *s) for (i =3D 0; i < nb_oargs + nb_iargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); if (ts) { - init_ts_info(ts); + init_ts_info(infos, &temps_used, ts); } } } else { nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - init_arg_info(op->args[i]); + init_arg_info(infos, &temps_used, op->args[i]); } } =20 @@ -1213,7 +1209,7 @@ void tcg_optimize(TCGContext *s) op->args[1], op->args[2]); if (tmp !=3D 2) { if (tmp) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); op->opc =3D INDEX_op_br; op->args[0] =3D op->args[3]; } else { @@ -1302,7 +1298,7 @@ void tcg_optimize(TCGContext *s) if (tmp !=3D 2) { if (tmp) { do_brcond_true: - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); op->opc =3D INDEX_op_br; op->args[0] =3D op->args[5]; } else { @@ -1318,7 +1314,7 @@ void tcg_optimize(TCGContext *s) /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); op->opc =3D INDEX_op_brcond_i32; op->args[0] =3D op->args[1]; op->args[1] =3D op->args[3]; @@ -1344,7 +1340,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); op->opc =3D INDEX_op_brcond_i32; op->args[1] =3D op->args[2]; op->args[2] =3D op->args[4]; @@ -1464,7 +1460,7 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used.l, nb_temps); } else { do_reset_output: for (i =3D 0; i < nb_oargs; i++) { --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508177315717645.3624244390874; Mon, 16 Oct 2017 11:08:35 -0700 (PDT) Received: from localhost ([::1]:34495 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49oT-0004Il-VQ for importer@patchew.org; Mon, 16 Oct 2017 14:08:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Af-0002uF-Gy for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49Ae-00047I-JR for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:21 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:44289) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49Ae-00046N-Ef for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:20 -0400 Received: by mail-pf0-x22e.google.com with SMTP id x7so16318496pfa.1 for ; Mon, 16 Oct 2017 10:27:20 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i1HvMWTORlTi4mrRA3t7lTf3wipFQA4Aj9Z7zWl118Y=; b=Jdj99N04fRMSvtuW4Vyehc94g3n4LBmX+psq1ZUfjoxZTQOfax1ajadM1fIBN0Y/SG aAUATCIuknda/a0dnxESAemTtyQBa6PQhq+vWlJN4SsQC1s0vXJmUxx4JH519fV3zN63 e3BGASh+FF7X249EbHmVZjA9dvg6D1E4peJ/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i1HvMWTORlTi4mrRA3t7lTf3wipFQA4Aj9Z7zWl118Y=; b=YVqEk5buDOhKLylay36Xw5oCF+bqlbcclkeYbATWCXFR09VsjC21tPDX4TeO1/7kVI YgjZ99KYgUVIHTgY4gd3Uq1Wwt4XGQyuPZgEZ1kkOyiifFoK5tluC6FVdTZ+PnDdv436 nLCbPN3bVB8nklq5LrMTZcO5z4kJu+J/HiTzNdrY2JJfFGZuqsOziu75ZsCHJCcSGwp1 jMpYxRGGGQDxV+Ixy+vkL6tBddXwGUQiIm9Z8TamFLC1g7asxzQtUOpYrYPe25XskTvl Ae6+KCjJI08WBhC8ACiYE1MVDx9z8HlF/uC3dP/4Tbn08Xkjx4mgpMssaNIcADsg3ox6 NJwA== X-Gm-Message-State: AMCzsaWytVGXHS//NvimPjXk5sb/je/suVImW2C3saD2v9Zc8we17SxF rpHWCDVMvsiKkMNk6duzYtsuMlrWgoM= X-Google-Smtp-Source: AOwi7QDUqToJw+HNxSswfH/yYIA0Z7InXLaiyCZK6WPb2pSY5taSBbboiiBk7Gvi15TKSfdf7bcMjQ== X-Received: by 10.84.244.198 with SMTP id f6mr9808305plt.32.1508174839233; Mon, 16 Oct 2017 10:27:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:06 -0700 Message-Id: <20171016172609.23422-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PATCH v6 47/50] osdep: introduce qemu_mprotect_rwx/none X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 2 ++ util/osdep.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 826650c58a..281782d526 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -371,6 +371,8 @@ void sigaction_invoke(struct sigaction *action, #endif =20 int qemu_madvise(void *addr, size_t len, int advice); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); =20 int qemu_open(const char *name, int flags, ...); int qemu_close(int fd); diff --git a/util/osdep.c b/util/osdep.c index a479fedc4a..1231f9f876 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -73,6 +73,47 @@ int qemu_madvise(void *addr, size_t len, int advice) #endif } =20 +static int qemu_mprotect__osdep(void *addr, size_t size, int prot) +{ + g_assert(!((uintptr_t)addr & ~qemu_real_host_page_mask)); + g_assert(!(size & ~qemu_real_host_page_mask)); + +#ifdef _WIN32 + DWORD old_protect; + + if (!VirtualProtect(addr, size, prot, &old_protect)) { + error_report("%s: VirtualProtect failed with error code %ld", + __func__, GetLastError()); + return -1; + } + return 0; +#else + if (mprotect(addr, size, prot)) { + error_report("%s: mprotect failed: %s", __func__, strerror(errno)); + return -1; + } + return 0; +#endif +} + +int qemu_mprotect_rwx(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE); +#else + return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_= EXEC); +#endif +} + +int qemu_mprotect_none(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS); +#else + return qemu_mprotect__osdep(addr, size, PROT_NONE); +#endif +} + #ifndef _WIN32 =20 static int fcntl_op_setlk =3D -1; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176486258130.22038391686237; Mon, 16 Oct 2017 10:54:46 -0700 (PDT) Received: from localhost ([::1]:34409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49b2-0000PC-Fs for importer@patchew.org; Mon, 16 Oct 2017 13:54:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ah-0002vy-Aw for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49Ag-0004Aj-57 for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:23 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:55273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49Af-0004AD-Vo for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:22 -0400 Received: by mail-pg0-x22a.google.com with SMTP id l24so7294698pgu.11 for ; Mon, 16 Oct 2017 10:27:21 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6e72cvxx7Qfm+Rx17cGpbHvv52iihArS/ChNd5KPwAk=; b=klz3PaqFwrVNefFXr6rr41s0veG5Oa68bskf/3lWZXSQ6LG00OIJ3LkkLMyDlRGP/d vG3GtHhBCfDCZfr23Y/xXZ4eW5cDVjIGVCqVK35lKvBI+Apsf0y0P0qTPodY4gkuwY2+ sFFoB3RvofLm81OKRV3mRdFt/pWwbDiyte2kA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6e72cvxx7Qfm+Rx17cGpbHvv52iihArS/ChNd5KPwAk=; b=uNbkaUTWyD7PO2YBgKjd/EdAArlD40b/sHHC5uSzWqr0lotPpiJoOzDXZ3SE10YhHX bVbcTvbXoFRsh3ccgagOzH9dv67hvY1BWoaH9Oi9sBjbZ8sbizj+dgQp3CrK0D033r9b KtahFn6YOt/k5M1lVsyxo+P+X2/5zW9c0kltVLg4wlPZ0uDLiljlqoc6tNx0k5Xfp31A vudzW6JXTuNVffjd0SAAVkB9ni+YXccx4v7E2uyD6ozEOpaNQNnE6YPzzHiGpqB4zTVb fw9Uvrp/l+KzX4ySqFoQgnrtBu2UE9rNzGsurusXr3k3d+Zbsm86I8HWpx+ETq5Wr6YR 3rlw== X-Gm-Message-State: AMCzsaW5O1aNaVpF1dz/MhfznN/Wq56O5zISajz51YyIqOsjMf/8nY2J +U7ydeGdutES8r2VTfMRTQRf4X7kVLQ= X-Google-Smtp-Source: AOwi7QCqfBd80YJvWpmOAP37J8Dkcb83lW11fqfsDkK4J1MvTmNJrFyfm61cvqp5ep3HOnKP5CRG7g== X-Received: by 10.84.234.199 with SMTP id i7mr9485990plt.66.1508174840825; Mon, 16 Oct 2017 10:27:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:07 -0700 Message-Id: <20171016172609.23422-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v6 48/50] translate-all: use qemu_protect_rwx/none helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" The helpers require the address and size to be page-aligned, so do that before calling them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 61 ++++++++++---------------------------------= ---- 1 file changed, 13 insertions(+), 48 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 614bb3adcc..cc25b7555b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -604,63 +604,24 @@ static inline void *split_cross_256mb(void *buf1, siz= e_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); =20 -# ifdef _WIN32 -static inline void do_protect(void *addr, long size, int prot) -{ - DWORD old_protect; - VirtualProtect(addr, size, prot, &old_protect); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PAGE_EXECUTE_READWRITE); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PAGE_NOACCESS); -} -# else -static inline void do_protect(void *addr, long size, int prot) -{ - uintptr_t start, end; - - start =3D (uintptr_t)addr; - start &=3D qemu_real_host_page_mask; - - end =3D (uintptr_t)addr + size; - end =3D ROUND_UP(end, qemu_real_host_page_size); - - mprotect((void *)start, end - start, prot); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PROT_NONE); -} -# endif /* WIN32 */ - static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; + void *end =3D static_code_gen_buffer + sizeof(static_code_gen_buffer); size_t full_size, size; =20 - /* The size of the buffer, rounded down to end on a page boundary. */ - full_size =3D (((uintptr_t)buf + sizeof(static_code_gen_buffer)) - & qemu_real_host_page_mask) - (uintptr_t)buf; + /* page-align the beginning and end of the buffer */ + buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + end =3D QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); =20 /* Reserve a guard page. */ + full_size =3D end - buf; size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx->code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) - & qemu_real_host_page_mask) - (uintptr_t)buf; + size =3D QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size, + qemu_real_host_page_size); } tcg_ctx->code_gen_buffer_size =3D size; =20 @@ -671,8 +632,12 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - map_exec(buf, size); - map_none(buf + size, qemu_real_host_page_size); + if (qemu_mprotect_rwx(buf, size)) { + abort(); + } + if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { + abort(); + } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176415741130.0822615520658; Mon, 16 Oct 2017 10:53:35 -0700 (PDT) Received: from localhost ([::1]:34404 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Zq-0007mc-9v for importer@patchew.org; Mon, 16 Oct 2017 13:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Ak-00035X-Jj for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e49Ai-0004CJ-1m for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:26 -0400 Received: from mail-pg0-x231.google.com ([2607:f8b0:400e:c05::231]:51123) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e49Ah-0004BZ-OB for qemu-devel@nongnu.org; Mon, 16 Oct 2017 13:27:23 -0400 Received: by mail-pg0-x231.google.com with SMTP id y7so7344023pgb.7 for ; Mon, 16 Oct 2017 10:27:23 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.27.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:27:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FM4PMS/eOK5C7DcNIT9ct7Q+1MWfmBwl2qH0Cel/siI=; b=GAwIqH7UI39Iij7sm7yWX1NKd1b5VIjWyevsCebINZzMAbmjZrSku2IYbRf+oywUf1 5PIqJKJwY8L33cvJ+NLBsAq+iaGsRVaaf7La13hEvR5KvVYxHiQZTHXfvX181IhRKQRD VJc3kdHOfxtrentyJz0kONrWUpYcpt1JLeMLw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FM4PMS/eOK5C7DcNIT9ct7Q+1MWfmBwl2qH0Cel/siI=; b=L0OAP45a2zO1IJA2kp8onsV2ZHi0rCdwmwWvriNUWACx+RfYkeWTc1J1w2xggsJ2+C tVRK5WdavlAkMb+qkbjzmZ/QLnoSMiBF0K2ZEuHPSlKIZRgMkzGdKGlDSkZnouxTRRKD b7p6kZMCNooVB5hOcaTuUP9HxQmyYzhxumiesOPQr7hGYzoGQ1yIEm+Gsuk5/qW8SAu+ pXmjEy97Ha7nc9rtIJCLGDDdPgt2MIVG2TqmIOHw+txNZ8mwKg+0GtPLs2OTRlhmrRXj rT5GMGSJMhyOrxZei5kxK5xuefsOAW8+XH75wW4mxFwRei4NtZpDf21yPAeiQjGdQHo4 jDjQ== X-Gm-Message-State: AMCzsaW4DCOYNdSmU/GEEXfnJvdyl8IxQN7z6s/AAxQ6GT8qefYiHPYy 2onJX+IiNs3gLi1UXRc3fwLj2CgsMaY= X-Google-Smtp-Source: AOwi7QBY5cIeIPlEl4zCS0TDeCipvSxP6N3RVmCpP3sXoO2X/uOxpWQxeEqPF/tG0wKzgL8dSOi7Eg== X-Received: by 10.159.198.131 with SMTP id g3mr9715363plo.337.1508174842110; Mon, 16 Oct 2017 10:27:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:26:08 -0700 Message-Id: <20171016172609.23422-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PATCH v6 49/50] tcg: introduce regions to split code_gen_buffer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=3D83885014 nb_tbs=3D154739 avg_tb_size=3D357 qemu: flush code_size=3D83884902 nb_tbs=3D153136 avg_tb_size=3D363 qemu: flush code_size=3D83885014 nb_tbs=3D152777 avg_tb_size=3D364 qemu: flush code_size=3D83884950 nb_tbs=3D150057 avg_tb_size=3D373 qemu: flush code_size=3D83884998 nb_tbs=3D150234 avg_tb_size=3D373 qemu: flush code_size=3D83885014 nb_tbs=3D154009 avg_tb_size=3D360 qemu: flush code_size=3D83885014 nb_tbs=3D151007 avg_tb_size=3D370 qemu: flush code_size=3D83885014 nb_tbs=3D151816 avg_tb_size=3D367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=3D76328008 nb_tbs=3D141040 avg_tb_size=3D356 qemu: flush code_size=3D75366534 nb_tbs=3D138000 avg_tb_size=3D361 qemu: flush code_size=3D76864546 nb_tbs=3D140653 avg_tb_size=3D361 qemu: flush code_size=3D76309084 nb_tbs=3D135945 avg_tb_size=3D375 qemu: flush code_size=3D74581856 nb_tbs=3D132909 avg_tb_size=3D375 qemu: flush code_size=3D73927256 nb_tbs=3D135616 avg_tb_size=3D360 qemu: flush code_size=3D78629426 nb_tbs=3D142896 avg_tb_size=3D365 qemu: flush code_size=3D76667052 nb_tbs=3D138508 avg_tb_size=3D368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=3D21936504 nb_tbs=3D40570 avg_tb_size=3D354 qemu: flush code_size=3D11472174 nb_tbs=3D20633 avg_tb_size=3D370 qemu: flush code_size=3D11603976 nb_tbs=3D21059 avg_tb_size=3D365 qemu: flush code_size=3D23254872 nb_tbs=3D41243 avg_tb_size=3D377 qemu: flush code_size=3D28289496 nb_tbs=3D52057 avg_tb_size=3D358 qemu: flush code_size=3D43605160 nb_tbs=3D78896 avg_tb_size=3D367 qemu: flush code_size=3D45166552 nb_tbs=3D82158 avg_tb_size=3D364 qemu: flush code_size=3D63289640 nb_tbs=3D116494 avg_tb_size=3D358 qemu: flush code_size=3D51389960 nb_tbs=3D93937 avg_tb_size=3D362 qemu: flush code_size=3D59665928 nb_tbs=3D107063 avg_tb_size=3D372 qemu: flush code_size=3D38380824 nb_tbs=3D68597 avg_tb_size=3D374 qemu: flush code_size=3D44884568 nb_tbs=3D79901 avg_tb_size=3D376 qemu: flush code_size=3D50782632 nb_tbs=3D90681 avg_tb_size=3D374 qemu: flush code_size=3D39848888 nb_tbs=3D71433 avg_tb_size=3D372 qemu: flush code_size=3D64708840 nb_tbs=3D119052 avg_tb_size=3D359 qemu: flush code_size=3D49830008 nb_tbs=3D90992 avg_tb_size=3D362 qemu: flush code_size=3D68372408 nb_tbs=3D123442 avg_tb_size=3D368 qemu: flush code_size=3D33555560 nb_tbs=3D59514 avg_tb_size=3D378 qemu: flush code_size=3D44748344 nb_tbs=3D80974 avg_tb_size=3D367 qemu: flush code_size=3D37104248 nb_tbs=3D67609 avg_tb_size=3D364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 6 ++ accel/tcg/translate-all.c | 63 +++++-------- bsd-user/main.c | 1 + cpus.c | 12 +++ linux-user/main.c | 1 + tcg/tcg.c | 222 ++++++++++++++++++++++++++++++++++++++++++= +++- 6 files changed, 260 insertions(+), 45 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 50ebe76aca..d3d16a2cce 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -810,6 +810,12 @@ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); =20 +void tcg_region_init(void); +void tcg_region_reset_all(void); + +size_t tcg_code_size(void); +size_t tcg_code_capacity(void); + /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index cc25b7555b..66b1733911 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -608,15 +608,13 @@ static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; void *end =3D static_code_gen_buffer + sizeof(static_code_gen_buffer); - size_t full_size, size; + size_t size; =20 /* page-align the beginning and end of the buffer */ buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); end =3D QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); =20 - /* Reserve a guard page. */ - full_size =3D end - buf; - size =3D full_size - qemu_real_host_page_size; + size =3D end - buf; =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx->code_gen_buffer_size) { @@ -635,9 +633,6 @@ static inline void *alloc_code_gen_buffer(void) if (qemu_mprotect_rwx(buf, size)) { abort(); } - if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { - abort(); - } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; @@ -646,22 +641,16 @@ static inline void *alloc_code_gen_buffer(void) static inline void *alloc_code_gen_buffer(void) { size_t size =3D tcg_ctx->code_gen_buffer_size; - void *buf1, *buf2; - - /* Perform the allocation in two steps, so that the guard page - is reserved but uncommitted. */ - buf1 =3D VirtualAlloc(NULL, size + qemu_real_host_page_size, - MEM_RESERVE, PAGE_NOACCESS); - if (buf1 !=3D NULL) { - buf2 =3D VirtualAlloc(buf1, size, MEM_COMMIT, PAGE_EXECUTE_READWRI= TE); - assert(buf1 =3D=3D buf2); - } + void *buf; =20 - return buf1; + buf =3D VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + PAGE_EXECUTE_READWRITE); + return buf; } #else static inline void *alloc_code_gen_buffer(void) { + int prot =3D PROT_WRITE | PROT_READ | PROT_EXEC; int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; size_t size =3D tcg_ctx->code_gen_buffer_size; @@ -695,8 +684,7 @@ static inline void *alloc_code_gen_buffer(void) # endif # endif =20 - buf =3D mmap((void *)start, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + buf =3D mmap((void *)start, size, prot, flags, -1, 0); if (buf =3D=3D MAP_FAILED) { return NULL; } @@ -706,24 +694,23 @@ static inline void *alloc_code_gen_buffer(void) /* Try again, with the original still mapped, to avoid re-acquiring that 256mb crossing. This time don't specify an address. */ size_t size2; - void *buf2 =3D mmap(NULL, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + void *buf2 =3D mmap(NULL, size, prot, flags, -1, 0); switch ((int)(buf2 !=3D MAP_FAILED)) { case 1: if (!cross_256mb(buf2, size)) { /* Success! Use the new buffer. */ - munmap(buf, size + qemu_real_host_page_size); + munmap(buf, size); break; } /* Failure. Work with what we had. */ - munmap(buf2, size + qemu_real_host_page_size); + munmap(buf2, size); /* fallthru */ default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { - munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); + munmap(buf + size2, size - size2); } else { munmap(buf, size - size2); } @@ -734,10 +721,6 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - /* Make the final buffer accessible. The guard page at the end - will remain inaccessible with PROT_NONE. */ - mprotect(buf, size, PROT_WRITE | PROT_READ | PROT_EXEC); - /* Request large pages for the buffer. */ qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 @@ -918,13 +901,8 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) size_t host_size =3D 0; =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, - nb_tbs > 0 ? host_size / nb_tbs : 0); - } - if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) - > tcg_ctx->code_gen_buffer_size) { - cpu_abort(cpu, "Internal error: code buffer overflow\n"); + printf("qemu: flush code_size=3D%zu nb_tbs=3D%zu avg_tb_size=3D%zu= \n", + tcg_code_size(), nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : = 0); } =20 CPU_FOREACH(cpu) { @@ -938,7 +916,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; + tcg_region_reset_all(); /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1276,9 +1254,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 phys_pc =3D get_page_addr_code(env, pc); =20 + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { - buffer_overflow: /* flush must be done */ tb_flush(cpu); mmap_unlock(); @@ -1382,9 +1360,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx->code_gen_ptr =3D (void *) + atomic_set(&tcg_ctx->code_gen_ptr, (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, - CODE_GEN_ALIGN); + CODE_GEN_ALIGN)); =20 /* init jump list */ assert(((uintptr_t)tb & 3) =3D=3D 0); @@ -1916,9 +1894,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * otherwise users might think "-tb-size" is not honoured. * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ - cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, - tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); + cpu_fprintf(f, "gen code size %zu/%zu\n", + tcg_code_size(), tcg_code_capacity()); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index 392c0ed5fb..f1b244b59b 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -978,6 +978,7 @@ int main(int argc, char **argv) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/cpus.c b/cpus.c index c9a624003a..8e06257a74 100644 --- a/cpus.c +++ b/cpus.c @@ -1664,6 +1664,18 @@ static void qemu_tcg_init_vcpu(CPUState *cpu) char thread_name[VCPU_THREAD_NAME_SIZE]; static QemuCond *single_tcg_halt_cond; static QemuThread *single_tcg_cpu_thread; + static int tcg_region_inited; + + /* + * Initialize TCG regions--once. Now is a good time, because: + * (1) TCG's init context, prologue and target globals have been set u= p. + * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before t= he + * -accel flag is processed, so the check doesn't work then). + */ + if (!tcg_region_inited) { + tcg_region_inited =3D 1; + tcg_region_init(); + } =20 if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) { cpu->thread =3D g_malloc0(sizeof(QemuThread)); diff --git a/linux-user/main.c b/linux-user/main.c index 5f40c1a702..199d71ecbb 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4458,6 +4458,7 @@ int main(int argc, char **argv, char **envp) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/tcg/tcg.c b/tcg/tcg.c index 4b7dc800ec..1ce1b08525 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -121,6 +121,30 @@ static bool tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; =20 +/* + * We divide code_gen_buffer into equally-sized "regions" that TCG threads + * dynamically allocate from as demand dictates. Given appropriate region + * sizing, this minimizes flushes even when some TCG threads generate a lot + * more code than others. + */ +struct tcg_region_state { + QemuMutex lock; + + /* fields set at init time */ + void *start; + void *start_aligned; + void *end; + size_t n; + size_t size; /* size of one region */ + size_t stride; /* .size + guard size */ + + /* fields protected by the lock */ + size_t current; /* current region index */ + size_t agg_size_full; /* aggregate size of full regions */ +}; + +static struct tcg_region_state region; + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -258,6 +282,196 @@ TCGLabel *gen_new_label(void) =20 #include "tcg-target.inc.c" =20 +static void tcg_region_bounds(size_t curr_region, void **pstart, void **pe= nd) +{ + void *start, *end; + + start =3D region.start_aligned + curr_region * region.stride; + end =3D start + region.size; + + if (curr_region =3D=3D 0) { + start =3D region.start; + } + if (curr_region =3D=3D region.n - 1) { + end =3D region.end; + } + + *pstart =3D start; + *pend =3D end; +} + +static void tcg_region_assign(TCGContext *s, size_t curr_region) +{ + void *start, *end; + + tcg_region_bounds(curr_region, &start, &end); + + s->code_gen_buffer =3D start; + s->code_gen_ptr =3D start; + s->code_gen_buffer_size =3D end - start; + s->code_gen_highwater =3D end - TCG_HIGHWATER; +} + +static bool tcg_region_alloc__locked(TCGContext *s) +{ + if (region.current =3D=3D region.n) { + return true; + } + tcg_region_assign(s, region.current); + region.current++; + return false; +} + +/* + * Request a new region once the one in use has filled up. + * Returns true on error. + */ +static bool tcg_region_alloc(TCGContext *s) +{ + bool err; + /* read the region size now; alloc__locked will overwrite it on succes= s */ + size_t size_full =3D s->code_gen_buffer_size; + + qemu_mutex_lock(®ion.lock); + err =3D tcg_region_alloc__locked(s); + if (!err) { + region.agg_size_full +=3D size_full - TCG_HIGHWATER; + } + qemu_mutex_unlock(®ion.lock); + return err; +} + +/* + * Perform a context's first region allocation. + * This function does _not_ increment region.agg_size_full. + */ +static inline bool tcg_region_initial_alloc__locked(TCGContext *s) +{ + return tcg_region_alloc__locked(s); +} + +/* Call from a safe-work context */ +void tcg_region_reset_all(void) +{ + unsigned int i; + + qemu_mutex_lock(®ion.lock); + region.current =3D 0; + region.agg_size_full =3D 0; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + bool err =3D tcg_region_initial_alloc__locked(tcg_ctxs[i]); + + g_assert(!err); + } + qemu_mutex_unlock(®ion.lock); +} + +/* + * Initializes region partitioning. + * + * Called at init time from the parent thread (i.e. the one calling + * tcg_context_init), after the target's TCG globals have been set. + */ +void tcg_region_init(void) +{ + void *buf =3D tcg_init_ctx.code_gen_buffer; + void *aligned; + size_t size =3D tcg_init_ctx.code_gen_buffer_size; + size_t page_size =3D qemu_real_host_page_size; + size_t region_size; + size_t n_regions; + size_t i; + + /* We do not yet support multiple TCG contexts, so use one region for = now */ + n_regions =3D 1; + + /* The first region will be 'aligned - buf' bytes larger than the othe= rs */ + aligned =3D QEMU_ALIGN_PTR_UP(buf, page_size); + g_assert(aligned < tcg_init_ctx.code_gen_buffer + size); + /* + * Make region_size a multiple of page_size, using aligned as the star= t. + * As a result of this we might end up with a few extra pages at the e= nd of + * the buffer; we will assign those to the last region. + */ + region_size =3D (size - (aligned - buf)) / n_regions; + region_size =3D QEMU_ALIGN_DOWN(region_size, page_size); + + /* A region must have at least 2 pages; one code, one guard */ + g_assert(region_size >=3D 2 * page_size); + + /* init the region struct */ + qemu_mutex_init(®ion.lock); + region.n =3D n_regions; + region.size =3D region_size - page_size; + region.stride =3D region_size; + region.start =3D buf; + region.start_aligned =3D aligned; + /* page-align the end, since its last page will be a guard page */ + region.end =3D QEMU_ALIGN_PTR_DOWN(buf + size, page_size); + /* account for that last guard page */ + region.end -=3D page_size; + + /* set guard pages */ + for (i =3D 0; i < region.n; i++) { + void *start, *end; + int rc; + + tcg_region_bounds(i, &start, &end); + rc =3D qemu_mprotect_none(end, page_size); + g_assert(!rc); + } + + /* We do not yet support multiple TCG contexts so allocate the region = now */ + { + bool err =3D tcg_region_initial_alloc__locked(tcg_ctx); + + g_assert(!err); + } +} + +/* + * Returns the size (in bytes) of all translated code (i.e. from all regio= ns) + * currently in the cache. + * See also: tcg_code_capacity() + * Do not confuse with tcg_current_code_size(); that one applies to a sing= le + * TCG context. + */ +size_t tcg_code_size(void) +{ + unsigned int i; + size_t total; + + qemu_mutex_lock(®ion.lock); + total =3D region.agg_size_full; + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGContext *s =3D tcg_ctxs[i]; + size_t size; + + size =3D atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; + g_assert(size <=3D s->code_gen_buffer_size); + total +=3D size; + } + qemu_mutex_unlock(®ion.lock); + return total; +} + +/* + * Returns the code capacity (in bytes) of the entire cache, i.e. includin= g all + * regions. + * See also: tcg_code_size() + */ +size_t tcg_code_capacity(void) +{ + size_t guard_size, capacity; + + /* no need for synchronization; these variables are set at init time */ + guard_size =3D region.stride - region.size; + capacity =3D region.end + guard_size - region.start; + capacity -=3D region.n * (guard_size + TCG_HIGHWATER); + return capacity; +} + /* pool based memory allocation */ void *tcg_malloc_internal(TCGContext *s, int size) { @@ -404,13 +618,17 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) TranslationBlock *tb; void *next; =20 + retry: tb =3D (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); next =3D (void *)ROUND_UP((uintptr_t)(tb + 1), align); =20 if (unlikely(next > s->code_gen_highwater)) { - return NULL; + if (tcg_region_alloc(s)) { + return NULL; + } + goto retry; } - s->code_gen_ptr =3D next; + atomic_set(&s->code_gen_ptr, next); s->data_gen_ptr =3D NULL; return tb; } --=20 2.13.6 From nobody Fri May 3 10:55:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508176641799676.3458065335889; Mon, 16 Oct 2017 10:57:21 -0700 (PDT) Received: from localhost ([::1]:34427 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49dc-0002xO-S5 for importer@patchew.org; Mon, 16 Oct 2017 13:57:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52956) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e49Al-00036J-E8 for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PATCH v6 50/50] tcg: enable multiple TCG contexts in softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that targets do not need any conversion: targets initialize a TCGContext (e.g. defining TCG globals), and after this initialization has finished, the context is cloned by the vCPU threads, each of them keeping a separate copy. TCG threads claim one entry in tcg_ctxs[] by atomically increasing n_tcg_ctxs. Do not be too annoyed by the subsequent atomic_read's of that variable and tcg_ctxs; they are there just to play nice with analysis tools such as thread sanitizer. Note that we do not allocate an array of contexts (we allocate an array of pointers instead) because when tcg_context_init is called, we do not know yet how many contexts we'll use since the bool behind qemu_tcg_mttcg_enabled() isn't set yet. Previous patches folded some TCG globals into TCGContext. The non-const globals remaining are only set at init time, i.e. before the TCG threads are spawned. Here is a list of these set-at-init-time globals under tcg/: Only written by tcg_context_init: - indirect_reg_alloc_order - tcg_op_defs Only written by tcg_target_init (called from tcg_context_init): - tcg_target_available_regs - tcg_target_call_clobber_regs - arm: arm_arch, use_idiv_instructions - i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt, have_movbe, have_popcnt - mips: use_movnz_instructions, use_mips32_instructions, use_mips32r2_instructions, got_sigill (tcg_target_detect_isa) - ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr - s390: tb_ret_addr, s390_facilities - sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines), use_vis3_instructions Only written by tcg_prologue_init: - 'struct jit_code_entry one_entry' - aarch64: tb_ret_addr - arm: tb_ret_addr - i386: tb_ret_addr, guest_base_flags - ia64: tb_ret_addr - mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 7 ++- accel/tcg/translate-all.c | 2 +- cpus.c | 2 + linux-user/syscall.c | 1 + tcg/tcg.c | 146 ++++++++++++++++++++++++++++++++++++++++++= +--- 5 files changed, 145 insertions(+), 13 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index d3d16a2cce..60bab14958 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -737,7 +737,7 @@ struct TCGContext { }; =20 extern TCGContext tcg_init_ctx; -extern TCGContext *tcg_ctx; +extern __thread TCGContext *tcg_ctx; =20 static inline size_t temp_idx(TCGTemp *ts) { @@ -805,7 +805,7 @@ static inline bool tcg_op_buf_full(void) =20 /* pool based memory allocation */ =20 -/* tb_lock must be held for tcg_malloc_internal. */ +/* user-mode: tb_lock must be held for tcg_malloc_internal. */ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); @@ -816,7 +816,7 @@ void tcg_region_reset_all(void); size_t tcg_code_size(void); size_t tcg_code_capacity(void); =20 -/* Called with tb_lock held. */ +/* user-mode: Called with tb_lock held. */ static inline void *tcg_malloc(int size) { TCGContext *s =3D tcg_ctx; @@ -836,6 +836,7 @@ static inline void *tcg_malloc(int size) } =20 void tcg_context_init(TCGContext *s); +void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 66b1733911..ac8dfe645c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -154,7 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_init_ctx; -TCGContext *tcg_ctx; +__thread TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 diff --git a/cpus.c b/cpus.c index 8e06257a74..114c29b6a0 100644 --- a/cpus.c +++ b/cpus.c @@ -1307,6 +1307,7 @@ static void *qemu_tcg_rr_cpu_thread_fn(void *arg) CPUState *cpu =3D arg; =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); @@ -1454,6 +1455,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) g_assert(!use_icount); =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9b6364a266..364d67b664 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6215,6 +6215,7 @@ static void *clone_func(void *arg) TaskState *ts; =20 rcu_register_thread(); + tcg_register_thread(); env =3D info->env; cpu =3D ENV_GET_CPU(env); thread_cpu =3D cpu; diff --git a/tcg/tcg.c b/tcg/tcg.c index 1ce1b08525..f93f499061 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -58,6 +58,7 @@ =20 #include "elf.h" #include "exec/log.h" +#include "sysemu/sysemu.h" =20 /* Forward declarations for functions declared in tcg-target.inc.c and used here. */ @@ -353,25 +354,87 @@ static inline bool tcg_region_initial_alloc__locked(T= CGContext *s) /* Call from a safe-work context */ void tcg_region_reset_all(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 qemu_mutex_lock(®ion.lock); region.current =3D 0; region.agg_size_full =3D 0; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { - bool err =3D tcg_region_initial_alloc__locked(tcg_ctxs[i]); + for (i =3D 0; i < n_ctxs; i++) { + TCGContext *s =3D atomic_read(&tcg_ctxs[i]); + bool err =3D tcg_region_initial_alloc__locked(s); =20 g_assert(!err); } qemu_mutex_unlock(®ion.lock); } =20 +#ifdef CONFIG_USER_ONLY +static size_t tcg_n_regions(void) +{ + return 1; +} +#else +/* + * It is likely that some vCPUs will translate more code than others, so we + * first try to set more regions than max_cpus, with those regions being of + * reasonable size. If that's not possible we make do by evenly dividing + * the code_gen_buffer among the vCPUs. + */ +static size_t tcg_n_regions(void) +{ + size_t i; + + /* Use a single region if all we have is one vCPU thread */ + if (max_cpus =3D=3D 1 || !qemu_tcg_mttcg_enabled()) { + return 1; + } + + /* Try to have more regions than max_cpus, with each region being >=3D= 2 MB */ + for (i =3D 8; i > 0; i--) { + size_t regions_per_thread =3D i; + size_t region_size; + + region_size =3D tcg_init_ctx.code_gen_buffer_size; + region_size /=3D max_cpus * regions_per_thread; + + if (region_size >=3D 2 * 1024u * 1024) { + return max_cpus * regions_per_thread; + } + } + /* If we can't, then just allocate one region per vCPU thread */ + return max_cpus; +} +#endif + /* * Initializes region partitioning. * * Called at init time from the parent thread (i.e. the one calling * tcg_context_init), after the target's TCG globals have been set. + * + * Region partitioning works by splitting code_gen_buffer into separate re= gions, + * and then assigning regions to TCG threads so that the threads can trans= late + * code in parallel without synchronization. + * + * In softmmu the number of TCG threads is bounded by max_cpus, so we use = at + * least max_cpus regions in MTTCG. In !MTTCG we use a single region. + * Note that the TCG options from the command-line (i.e. -accel accel=3Dtc= g,[...]) + * must have been parsed before calling this function, since it calls + * qemu_tcg_mttcg_enabled(). + * + * In user-mode we use a single region. Having multiple regions in user-m= ode + * is not supported, because the number of vCPU threads (recall that each = thread + * spawned by the guest corresponds to a vCPU thread) is only bounded by t= he + * OS, and usually this number is huge (tens of thousands is not uncommon). + * Thus, given this large bound on the number of vCPU threads and the fact + * that code_gen_buffer is allocated at compile-time, we cannot guarantee + * that the availability of at least one region per vCPU thread. + * + * However, this user-mode limitation is unlikely to be a significant prob= lem + * in practice. Multi-threaded guests share most if not all of their trans= lated + * code, which makes parallel code generation less appealing than in softm= mu. */ void tcg_region_init(void) { @@ -383,8 +446,7 @@ void tcg_region_init(void) size_t n_regions; size_t i; =20 - /* We do not yet support multiple TCG contexts, so use one region for = now */ - n_regions =3D 1; + n_regions =3D tcg_n_regions(); =20 /* The first region will be 'aligned - buf' bytes larger than the othe= rs */ aligned =3D QEMU_ALIGN_PTR_UP(buf, page_size); @@ -422,13 +484,66 @@ void tcg_region_init(void) g_assert(!rc); } =20 - /* We do not yet support multiple TCG contexts so allocate the region = now */ + /* In user-mode we support only one ctx, so do the initial allocation = now */ +#ifdef CONFIG_USER_ONLY { bool err =3D tcg_region_initial_alloc__locked(tcg_ctx); =20 g_assert(!err); } +#endif +} + +/* + * All TCG threads except the parent (i.e. the one that called tcg_context= _init + * and registered the target's TCG globals) must register with this functi= on + * before initiating translation. + * + * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentati= on + * of tcg_region_init() for the reasoning behind this. + * + * In softmmu each caller registers its context in tcg_ctxs[]. Note that in + * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial conte= xt + * is not used anymore for translation once this function is called. + * + * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iter= ates + * over the array (e.g. tcg_code_size() the same for both softmmu and user= -mode. + */ +#ifdef CONFIG_USER_ONLY +void tcg_register_thread(void) +{ + tcg_ctx =3D &tcg_init_ctx; +} +#else +void tcg_register_thread(void) +{ + TCGContext *s =3D g_malloc(sizeof(*s)); + unsigned int i, n; + bool err; + + *s =3D tcg_init_ctx; + + /* Relink mem_base. */ + for (i =3D 0, n =3D tcg_init_ctx.nb_globals; i < n; ++i) { + if (tcg_init_ctx.temps[i].mem_base) { + ptrdiff_t b =3D tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.= temps; + tcg_debug_assert(b >=3D 0 && b < n); + s->temps[i].mem_base =3D &s->temps[b]; + } + } + + /* Claim an entry in tcg_ctxs */ + n =3D atomic_fetch_inc(&n_tcg_ctxs); + g_assert(n < max_cpus); + atomic_set(&tcg_ctxs[n], s); + + tcg_ctx =3D s; + qemu_mutex_lock(®ion.lock); + err =3D tcg_region_initial_alloc__locked(tcg_ctx); + g_assert(!err); + qemu_mutex_unlock(®ion.lock); } +#endif /* !CONFIG_USER_ONLY */ =20 /* * Returns the size (in bytes) of all translated code (i.e. from all regio= ns) @@ -439,13 +554,14 @@ void tcg_region_init(void) */ size_t tcg_code_size(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; size_t total; =20 qemu_mutex_lock(®ion.lock); total =3D region.agg_size_full; - for (i =3D 0; i < n_tcg_ctxs; i++) { - const TCGContext *s =3D tcg_ctxs[i]; + for (i =3D 0; i < n_ctxs; i++) { + const TCGContext *s =3D atomic_read(&tcg_ctxs[i]); size_t size; =20 size =3D atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; @@ -604,8 +720,18 @@ void tcg_context_init(TCGContext *s) } =20 tcg_ctx =3D s; + /* + * In user-mode we simply share the init context among threads, since = we + * use a single region. See the documentation tcg_region_init() for the + * reasoning behind this. + * In softmmu we will have at most max_cpus TCG threads. + */ +#ifdef CONFIG_USER_ONLY tcg_ctxs =3D &tcg_ctx; n_tcg_ctxs =3D 1; +#else + tcg_ctxs =3D g_new(TCGContext *, max_cpus); +#endif } =20 /* @@ -2967,10 +3093,12 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) static inline void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { - const TCGProfile *orig =3D &tcg_ctxs[i]->prof; + for (i =3D 0; i < n_ctxs; i++) { + TCGContext *s =3D atomic_read(&tcg_ctxs[i]); + const TCGProfile *orig =3D &s->prof; =20 if (counters) { PROF_ADD(prof, orig, tb_count1); --=20 2.13.6