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[61.45.56.248]) by smtp.gmail.com with ESMTPSA id m16sm2683903pgn.76.2017.10.13.06.49.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tZxa5m+hHTLQrNdGoE1qNPapFEDQOZhLpBXUdtSd2Fk=; b=VHWkWZu6u5mFAyTX74WDc25yOmnqKNmdxEEI7hZhXc0ccWgsnxUpu5F/cXk6x3PKc4 OSkvaV+0KtzG1cLCftNOAU8ZKeWqnvATwjcBjRTBCJraxSno61XSIaSr96dpOVai084z /JISK7VuOdYI/kKmsEH1+sdQtrrMhoqv1DcmvgXMwSFgp/YrSUL7ENhi50TiQI2Nkpsf gZ60+f5k6f1ywRtRS9cFWsc5Nt+A69ONFySAziypp+f6eo9Nov+yg2LrydrsqdaqBON1 Kl0VZAg2NI8LqsnYEnByPaadmgeZGRdORHBK7TBB4nHhQ6OhPWbuZDGOqHMI2l6E5mPC kATg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tZxa5m+hHTLQrNdGoE1qNPapFEDQOZhLpBXUdtSd2Fk=; b=PIrWE9bvqBK1NzEX1ZD2msRIRXA0zifgTsFsipHKDOka8Kh4jGs4HL+F1wTiHaJTX8 ctjrWRh2p48EYcHqjSl3Ruyng0vxXmKC5sjX/K8+A094dKEFEBfwPvT4INowpLBZZ5L9 yheOEdepDFHI56o7tdApl5C7fZ6HOsMDIgv1AYeM9C3XMz+WWf58yVyxvqv35ar4HaJD w7YAJjdi16vQ4sUJj4cr0lwcYlxLZb0aznIHGkGtEHjPiecgRcJfVJnRXevmqs9tntit FC+iKJcS6awqT8gws6+sPvkZWEuudlQOKy3odivi8v8buxlFjkzoJJ1DbJbawgTfsQK/ v+bQ== X-Gm-Message-State: AMCzsaU0A9GuvjGLF17hhljtjgqPk5/ZkEpAxYuODOX8s1tDVKQVWHTi bBZwX7FlheZeILSI2GfV1dAq59Kn X-Google-Smtp-Source: AOwi7QDii4Giu+T+QtuyKMpMpY0GYABtMv6QKXzF0lR0CStYfEfzEOH76brK8iEUgU17mWAYLjcQbA== X-Received: by 10.159.208.69 with SMTP id w5mr1447830plz.381.1507902592066; Fri, 13 Oct 2017 06:49:52 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:26 +0900 Message-Id: <20171013134930.32547-2-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- default-configs/or1k-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/ompic.c | 179 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 181 insertions(+) create mode 100644 hw/intc/ompic.c diff --git a/default-configs/or1k-softmmu.mak b/default-configs/or1k-softmm= u.mak index 10bfa7abb8..6f5824fd48 100644 --- a/default-configs/or1k-softmmu.mak +++ b/default-configs/or1k-softmmu.mak @@ -2,3 +2,4 @@ =20 CONFIG_SERIAL=3Dy CONFIG_OPENCORES_ETH=3Dy +CONFIG_OMPIC=3Dy diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 78426a7daf..ae358569a1 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -43,3 +43,4 @@ obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_vic.o obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_cpuif.o obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o obj-$(CONFIG_NIOS2) +=3D nios2_iic.o +obj-$(CONFIG_OMPIC) +=3D ompic.o diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c new file mode 100644 index 0000000000..c0e34d1268 --- /dev/null +++ b/hw/intc/ompic.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Pub= lic + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Authors: Stafford Horne + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "exec/memory.h" + +#define TYPE_OR1K_OMPIC "or1k-ompic" +#define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPI= C) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff) + +#define OMPIC_REG(addr) (((addr) >> 2) & 0x1) +#define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f) +#define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f) + +#define OMPIC_STATUS_IRQ_PENDING (1 << 30) +#define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16) +#define OMPIC_STATUS_DATA(data) ((data) & 0xffff) + +#define OMPIC_CONTROL 0 +#define OMPIC_STATUS 1 + +#define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory= */ +#define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per c= pu */ + +typedef struct OR1KOMPICState OR1KOMPICState; +typedef struct OR1KOMPICCPUState OR1KOMPICCPUState; + +struct OR1KOMPICCPUState { + qemu_irq irq; + uint32_t status; + uint32_t control; +}; + +struct OR1KOMPICState { + SysBusDevice parent_obj; + MemoryRegion mr; + + OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; + + uint32_t num_cpus; +}; + +static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size) +{ + OR1KOMPICState *s =3D opaque; + int src_cpu =3D OMPIC_SRC_CPU(addr); + + /* We can only write to control control, write control + update status= */ + if (OMPIC_REG(addr) =3D=3D OMPIC_CONTROL) { + return s->cpus[src_cpu].control; + } else { + return s->cpus[src_cpu].status; + } + +} + +static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned= size) +{ + OR1KOMPICState *s =3D opaque; + /* We can only write to control control, write control + update status= */ + if (OMPIC_REG(addr) =3D=3D OMPIC_CONTROL) { + int src_cpu =3D OMPIC_SRC_CPU(addr); + + s->cpus[src_cpu].control =3D data; + + if (data & OMPIC_CTRL_IRQ_GEN) { + int dst_cpu =3D OMPIC_CTRL_DST(data); + + s->cpus[dst_cpu].status =3D OMPIC_STATUS_IRQ_PENDING | + OMPIC_STATUS_SRC(src_cpu) | + OMPIC_STATUS_DATA(data); + + qemu_irq_raise(s->cpus[dst_cpu].irq); + } + if (data & OMPIC_CTRL_IRQ_ACK) { + s->cpus[src_cpu].status &=3D ~OMPIC_STATUS_IRQ_PENDING; + qemu_irq_lower(s->cpus[src_cpu].irq); + } + } +} + +static const MemoryRegionOps ompic_ops =3D { + .read =3D ompic_read, + .write =3D ompic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .max_access_size =3D 8, + }, +}; + +static void or1k_ompic_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + OR1KOMPICState *s =3D OR1K_OMPIC(obj); + + memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s, + "or1k-ompic", OMPIC_ADDRSPACE_SZ); + sysbus_init_mmio(sbd, &s->mr); +} + +static void or1k_ompic_realize(DeviceState *dev, Error **errp) +{ + OR1KOMPICState *s =3D OR1K_OMPIC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpus > OMPIC_MAX_CPUS) { + error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); + return; + } + /* Init IRQ sources for all CPUs */ + for (i =3D 0; i < s->num_cpus; i++) { + sysbus_init_irq(sbd, &s->cpus[i].irq); + } +} + +static Property or1k_ompic_properties[] =3D { + DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_or1k_ompic_cpu =3D { + .name =3D "or1k_ompic_cpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(status, OR1KOMPICCPUState), + VMSTATE_UINT32(control, OR1KOMPICCPUState), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_or1k_ompic =3D { + .name =3D TYPE_OR1K_OMPIC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1, + vmstate_or1k_ompic_cpu, OR1KOMPICCPUState), + VMSTATE_UINT32(num_cpus, OR1KOMPICState), + VMSTATE_END_OF_LIST() + } +}; + +static void or1k_ompic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D or1k_ompic_properties; + dc->realize =3D or1k_ompic_realize; + dc->vmsd =3D &vmstate_or1k_ompic; +} + +static const TypeInfo or1k_ompic_info =3D { + .name =3D TYPE_OR1K_OMPIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(OR1KOMPICState), + .instance_init =3D or1k_ompic_init, + .class_init =3D or1k_ompic_class_init, +}; + +static void or1k_ompic_register_types(void) +{ + type_register_static(&or1k_ompic_info); +} + +type_init(or1k_ompic_register_types) --=20 2.13.6 From nobody Fri May 3 13:58:57 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507902734312369.0212460190951; Fri, 13 Oct 2017 06:52:14 -0700 (PDT) Received: from localhost ([::1]:50428 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30Na-0000mN-Cr for importer@patchew.org; Fri, 13 Oct 2017 09:51:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30Lc-0007wY-7b for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:49:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e30Lb-0006c9-Kr for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:49:56 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:43639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e30Lb-0006bR-Eb for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:49:55 -0400 Received: by mail-pf0-x243.google.com with SMTP id a8so9858498pfc.0 for ; Fri, 13 Oct 2017 06:49:55 -0700 (PDT) Received: from localhost (g248.61-45-56.ppp.wakwak.ne.jp. [61.45.56.248]) by smtp.gmail.com with ESMTPSA id p90sm2731105pfj.157.2017.10.13.06.49.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HgFEK5+JxpY7RqBsayZHnG+hiUdQe0Uku0JP7Q084wY=; b=lVpTx7fMur1OP4/CRqyz7fQna9I99A9xnxv2bLxvVa6MstaLQKIyNA2O9GHObcvcLi y6nmz8JFAMGKuQysS/d9nWPZoiu4uhFT/3QQhcQfD3xP3kiAKpvqMFJrxmsCb108f/Hc YK/7Bqqg97sR8gC6wh5kqRrb083yR1THmXWJa+yYULjoQbT4MuEP8bObRhviR30vRARU nE4/P+2VGMp4jDniD29yCQYJrM3TEawxTHlsSgrtNKm9J1fJYc23EfJgSdTN7iqnf+r9 jacAnQukYEvZTNCJNeONIxaym3BR9I8P2/YHDHYtw/YpltdXUYz9nT6Z74/EfnpmDBy2 3uIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HgFEK5+JxpY7RqBsayZHnG+hiUdQe0Uku0JP7Q084wY=; b=krzYracqR9UM3Vmx0lzDwKLS8/JmppdZsBnBG16xTEwyf9DuhNEJrM5P5ENEibz74Y HXUDArrz9lYE651xQFAfS5b3oNs5k2zmti0pt923rZmtYcUFm7l2Stx3yLK0Jei8QRKW Ay7YUPo6kPete0R6swyF9X8qR2C7mDPwczo/HpvYRdVnA8sN9BQeA7EBw77sBsnIA868 QY5OtUZ/hVzvEKWGyo4fjNCfMS4a/R/L1bTH9jpnijo2GFVjIp/ap14gnr+PG7yH/WWE kyeKI/kFqLG5fcjYIIJNaFM4FAC2+CppxAF95F34Oce6yfLao+TwJwpKxJOdSwfyQJkn LZjg== X-Gm-Message-State: AMCzsaWlGr6TKnFDGKrO4kZmrvxHK+iqnkm/DDJ2Rfb6sVapx9Q14sY+ AdpOMqyx9tKxFIoU+x/lI5qzazjQ X-Google-Smtp-Source: AOwi7QDiy4kFL07Zl1cM6xeOXXkMss/o/9NsSTvt2Z8xseIKvSJqhY6pY/Q9GRThv7mewPT+P6yZgg== X-Received: by 10.159.218.69 with SMTP id x5mr1444971plv.4.1507902594316; Fri, 13 Oct 2017 06:49:54 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:27 +0900 Message-Id: <20171013134930.32547-3-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/sys_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index abdef5d6a5..dc6e5cc7f2 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" +#include "sysemu/sysemu.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->esr; =20 case TO_SPR(0, 128): /* COREID */ - return 0; + return cpu->parent_obj.cpu_index; =20 case TO_SPR(0, 129): /* NUMCORES */ - return 1; + return max_cpus; =20 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx =3D (spr - 1024); --=20 2.13.6 From nobody Fri May 3 13:58:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15079029628487.209352641329815; Fri, 13 Oct 2017 06:56:02 -0700 (PDT) Received: from localhost ([::1]:50445 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30RU-000417-4C for importer@patchew.org; Fri, 13 Oct 2017 09:56:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57809) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30Lf-0007zM-BA for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:50:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e30Le-0006eG-45 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:49:59 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:45361) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e30Ld-0006dY-SC for qemu-devel@nongnu.org; Fri, 13 Oct 2017 09:49:58 -0400 Received: by mail-pf0-x243.google.com with SMTP id d28so10321600pfe.2 for ; Fri, 13 Oct 2017 06:49:57 -0700 (PDT) Received: from localhost (g248.61-45-56.ppp.wakwak.ne.jp. [61.45.56.248]) by smtp.gmail.com with ESMTPSA id b23sm4818320pfm.148.2017.10.13.06.49.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BJOdWCY/Yh6knPz1kisg20o/ROj7u9D1prc6ivvtUB4=; b=jYphYcCwg6qlLmNrirmH3G8H4Bo+wRiFSjL2ZsZ0aeNASeuSVKBvP6plHVUHG5DJM5 L9bC3lQmqgdjzBO2b7BNUbrz4eOwMMU096YBqKXZH3oBscRLANVDAoyCVlyCV7Nf3CmD mca+neTAaSK1tlx2UZGTRL6K0OprRl/r77ZdqWxFqG6j1wwlKIiwwkp4hzlhYTnbZ6Y4 LQMa3I3fga/DMwh53rRTLrmWJkByiZNTJf4PACSUXg1Ih0hlQu7/62zKCDpx2Xe01lsZ 2FD3Y5jw/bZT24NqTvrZlDleJDcTER7G7fIqdgKVLl7lXCiL5f6/uU3kX3VVbhT3OWKH FU+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BJOdWCY/Yh6knPz1kisg20o/ROj7u9D1prc6ivvtUB4=; b=Q/8XDbHpCFtSMZoYAFK3OkJb2hD292b5ap0hCYcdNPjwskngaQhlEMV0tWtAs9m2jQ a+wsyhSMCL+nN/vgwfYgMMjreQ+nciedKaJAcox+4hKuFqiSqFZ2GcCiV3jVc+FlGLBF ipLkV6jT9S+0+6BUl8VzKKXdUi1pbQ8dEfL995T4+z8TlBNaNcS6mmSluRApKEdRh/Bg GBIRkGa4+ZmECE2pV3j5CGCXG4Xs8Qm2BmQRibpAluzFp052/hXm0ECMEPAEY8Q4P81X 2Cf8tMx0EWJpRxBVsrqtU3DFTCSa1AjjA/rqVprr+eBWRr6rnL9dWxwSIUNuXfr2y6E+ SOaw== X-Gm-Message-State: AMCzsaXokU3U0mDdx01nhA30u+DUyByeqCStagVjQZE14d/9OcJBzgbo Lw3USxipLvC+VSAgjVYQXZkTcIyQ X-Google-Smtp-Source: AOwi7QAcPIx+1U1+HJpXjn2yVHmzYyBvyLIYMMqZW/CU5OJ3xGuv0g4PtRHi+Ob4t5u9K+/Ogu7ZeQ== X-Received: by 10.99.64.1 with SMTP id n1mr1380892pga.185.1507902596687; Fri, 13 Oct 2017 06:49:56 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:28 +0900 Message-Id: <20171013134930.32547-4-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 62 +++++++++++++++++++++++++++++++++-------= ---- target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 4 ++- target/openrisc/machine.c | 1 - target/openrisc/sys_helper.c | 4 +-- 5 files changed, 52 insertions(+), 20 deletions(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index febc469170..4c5415ff75 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -25,39 +25,56 @@ =20 #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ =20 -/* The time when TTCR changes */ -static uint64_t last_clk; -static int is_counting; +/* Tick Timer global state to allow all cores to be in sync */ +typedef struct OR1KTimerState { + uint32_t ttcr; + uint64_t last_clk; +} OR1KTimerState; =20 +static OR1KTimerState *or1k_timer; + +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) +{ + or1k_timer->ttcr =3D val; +} + +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) +{ + return or1k_timer->ttcr; +} + +/* Add elapsed ticks to ttcr */ void cpu_openrisc_count_update(OpenRISCCPU *cpu) { uint64_t now; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - cpu->env.ttcr +=3D (uint32_t)((now - last_clk) / TIMER_PERIOD); - last_clk =3D now; + or1k_timer->ttcr +=3D (uint32_t)((now - or1k_timer->last_clk) + / TIMER_PERIOD); + or1k_timer->last_clk =3D now; } =20 +/* Update the next timeout time as difference between ttmr and ttcr */ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) { uint32_t wait; uint64_t now, next; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } =20 cpu_openrisc_count_update(cpu); - now =3D last_clk; + now =3D or1k_timer->last_clk; =20 - if ((cpu->env.ttmr & TTMR_TP) <=3D (cpu->env.ttcr & TTMR_TP)) { - wait =3D TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1; + if ((cpu->env.ttmr & TTMR_TP) <=3D (or1k_timer->ttcr & TTMR_TP)) { + wait =3D TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; wait +=3D cpu->env.ttmr & TTMR_TP; } else { - wait =3D (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP); + wait =3D (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); @@ -66,7 +83,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) { - is_counting =3D 1; + cpu->env.is_counting =3D 1; cpu_openrisc_count_update(cpu); } =20 @@ -74,7 +91,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu) { timer_del(cpu->env.timer); cpu_openrisc_count_update(cpu); - is_counting =3D 0; + cpu->env.is_counting =3D 0; } =20 static void openrisc_timer_cb(void *opaque) @@ -93,7 +110,7 @@ static void openrisc_timer_cb(void *opaque) case TIMER_NONE: break; case TIMER_INTR: - cpu->env.ttcr =3D 0; + or1k_timer->ttcr =3D 0; break; case TIMER_SHOT: cpu_openrisc_count_stop(cpu); @@ -105,9 +122,24 @@ static void openrisc_timer_cb(void *opaque) cpu_openrisc_timer_update(cpu); } =20 +static const VMStateDescription vmstate_or1k_timer =3D { + .name =3D "or1k_timer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(ttcr, OR1KTimerState), + VMSTATE_UINT64(last_clk, OR1KTimerState), + VMSTATE_END_OF_LIST() + } +}; + void cpu_openrisc_clock_init(OpenRISCCPU *cpu) { cpu->env.timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb= , cpu); cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; + + if (or1k_timer =3D=3D NULL) { + or1k_timer =3D g_new0(OR1KTimerState, 1); + vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); + } } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1d6330cbcc..0a46684987 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -61,7 +61,6 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.picsr =3D 0x00000000; =20 cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; #endif } =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 2721432c4f..3608cbad69 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,7 @@ typedef struct CPUOpenRISCState { =20 QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ - uint32_t ttcr; /* Timer tick count register */ + int is_counting; =20 uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ @@ -373,6 +373,8 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 /* hw/openrisc_timer.c */ void cpu_openrisc_clock_init(OpenRISCCPU *cpu); +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a20cce705d..0a793eb14d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -147,7 +147,6 @@ static const VMStateDescription vmstate_env =3D { =20 VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), - VMSTATE_UINT32(ttcr, CPUOpenRISCState), =20 VMSTATE_UINT32(picmr, CPUOpenRISCState), VMSTATE_UINT32(picsr, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index dc6e5cc7f2..9fb7d86b4b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -189,7 +189,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, break; =20 case TO_SPR(10, 1): /* TTCR */ - env->ttcr =3D rb; + cpu_openrisc_count_set(cpu, rb); if (env->ttmr & TIMER_NONE) { return; } @@ -312,7 +312,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, =20 case TO_SPR(10, 1): /* TTCR */ cpu_openrisc_count_update(cpu); - return env->ttcr; + return cpu_openrisc_count_get(cpu); =20 default: break; --=20 2.13.6 From nobody Fri May 3 13:58:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150790322224315.275283271627131; Fri, 13 Oct 2017 07:00:22 -0700 (PDT) Received: from localhost ([::1]:50462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30Vd-0007BZ-GW for importer@patchew.org; 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[61.45.56.248]) by smtp.gmail.com with ESMTPSA id w10sm2593183pfg.40.2017.10.13.06.49.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kQUr+jn02nx+3PZWPpNj/Rt3hCdwvT79bQYlRXSXpjk=; b=WKJxisSBAkQMHVePD8ilPvf0jqD8ieZppKLkvBPxGAgRJBxjW34GnOz37Fng1uBhAg dK5j3N7iz7BnWBwl0NVAcxCGAg96Yzg8gxPXDneLgJagMOh7ubuJnSXOFyGdPw+FwsvB 27KJJvLAEnFB/kcVA+MjC1QgzN/rfU/KiZJ/tCjewElRIysqUcCwjpjdBZG/6zUXqsLC tt5oGmsHClfCYLSRdfNF1ir4WCokN669YzDLcJWjst/OL15IrxhwdlyAbVSHyjUbXrDq lsQTa+wtnWcYqtlAesHsmMopJcthn61Xqz98TmwX3shK+FLoyFzQbgO8xzjjKZsB/WO5 fJAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kQUr+jn02nx+3PZWPpNj/Rt3hCdwvT79bQYlRXSXpjk=; b=tg754NuApf1WZ2ZI+mkatpWDNVOCRLPa1yDeOoMf6Ney96yeplXAMOfUkVs/UT+oir HFA2/65xRulknvi/RMjAWqL5eZ64UTCSmSJY7HxIDXFuOf5bXcxXHehJAqaCn0qep9Zo uHkoM+yJfVcnro1/ySNaQWD4eQrqNql7hImnZEi6jDRtnJMm6vXusRrfAxP/aj8jEG0N ViiJJ57c7RJ8tx49lKDV85wkePY64XbqND1EwjNFP4c1VtrSOM8i2miNpSm+PyUSbFfh YsLKX9DLXXIiotUuC1UgIIufO96ELZjjUgJGHds4A36GkbLFyaWf99kjKFXQCzqd8+43 cpfQ== X-Gm-Message-State: AMCzsaUEOvUzEp7DXRWX4kow0llwa3HE4evwFOz0K93YZz0jq8gh9wgW OqPiAYk1F47dXkjOv2nMMRaZXJ4v X-Google-Smtp-Source: AOwi7QBaCgtaG0q8nnVPzoFOilIYSiR34lsAgDMjtLjt+nhfQouUZFaO6/GgTO1bzOV6HIHhZdu4uQ== X-Received: by 10.99.182.66 with SMTP id v2mr1397345pgt.325.1507902599571; Fri, 13 Oct 2017 06:49:59 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:29 +0900 Message-Id: <20171013134930.32547-5-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 4/5] openrisc: Initial SMP support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire in ompic and add basic support for SMP. The OpenRISC is special in that interrupts for devices are routed to each core's PIC. This is achieved using the qemu_irq_split utility, but this currently limits OpenRISC to 2 cores. This models the reference architecture described in the OpenRISC spec 1.2 proposal. https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-= rev0.pdf The changes to the intialization of the sim include: CPU Reset o Reset each cpu to the bootstrap PC rather than only a single cpu as done before. o During Kernel loading the bootstrap PC is saved in a static global. Network Initialization o Connect the interrupt to each CPU o Use more simple sysbus_mmio_map() rather than memory_region_add_subregio= n() Sim Initialization o Initialize the pic and tick timer per cpu o Wire in the OMPIC if SMP is enabled o Wire the serial irq to each CPU using qemu_irq_split() Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 84 +++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 61 insertions(+), 23 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index e1eeffc490..1794c39005 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -35,36 +35,60 @@ =20 #define KERNEL_LOAD_ADDR 0x100 =20 +static struct openrisc_boot_info { + uint32_t bootstrap_pc; +} boot_info; + static void main_cpu_reset(void *opaque) { OpenRISCCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); =20 cpu_reset(CPU(cpu)); + + cpu_set_pc(cs, boot_info.bootstrap_pc); } =20 -static void openrisc_sim_net_init(MemoryRegion *address_space, - hwaddr base, - hwaddr descriptors, - qemu_irq irq, NICInfo *nd) +static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, + int num_cpus, qemu_irq **cpu_irqs, + int irq_pin, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; + int i; =20 dev =3D qdev_create(NULL, "open_eth"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); =20 s =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, irq); - memory_region_add_subregion(address_space, base, - sysbus_mmio_get_region(s, 0)); - memory_region_add_subregion(address_space, descriptors, - sysbus_mmio_get_region(s, 1)); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); + sysbus_mmio_map(s, 1, descriptors); } =20 -static void cpu_openrisc_load_kernel(ram_addr_t ram_size, - const char *kernel_filename, - OpenRISCCPU *cpu) +static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, + qemu_irq **cpu_irqs, int irq_pin) +{ + DeviceState *dev; + SysBusDevice *s; + int i; + + dev =3D qdev_create(NULL, "or1k-ompic"); + qdev_prop_set_uint32(dev, "num-cpus", num_cpus); + qdev_init_nofail(dev); + + s =3D SYS_BUS_DEVICE(dev); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); +} + +static void openrisc_load_kernel(ram_addr_t ram_size, + const char *kernel_filename) { long kernel_size; uint64_t elf_entry; @@ -83,6 +107,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_size =3D load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR, ram_size - KERNEL_LOAD_ADDR); + } + + if (entry <=3D 0) { entry =3D KERNEL_LOAD_ADDR; } =20 @@ -91,7 +118,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_filename); exit(1); } - cpu->env.pc =3D entry; + boot_info.bootstrap_pc =3D entry; } } =20 @@ -102,6 +129,8 @@ static void openrisc_sim_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; OpenRISCCPU *cpu =3D NULL; MemoryRegion *ram; + qemu_irq *cpu_irqs[2]; + qemu_irq serial_irq; int n; =20 if (!cpu_model) { @@ -114,33 +143,42 @@ static void openrisc_sim_init(MachineState *machine) fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } + cpu_openrisc_pic_init(cpu); + cpu_irqs[n] =3D (qemu_irq *) cpu->env.irq; + + cpu_openrisc_clock_init(cpu); + qemu_register_reset(main_cpu_reset, cpu); - main_cpu_reset(cpu); } =20 ram =3D g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fat= al); memory_region_add_subregion(get_system_memory(), 0, ram); =20 - cpu_openrisc_pic_init(cpu); - cpu_openrisc_clock_init(cpu); + if (nd_table[0].used) { + openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, + cpu_irqs, 4, nd_table); + } =20 - serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2], - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + if (smp_cpus > 1) { + openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); =20 - if (nd_table[0].used) { - openrisc_sim_net_init(get_system_memory(), 0x92000000, - 0x92000400, cpu->env.irq[4], nd_table); + serial_irq =3D qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); + } else { + serial_irq =3D cpu_irqs[0][2]; } =20 - cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); + serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + + openrisc_load_kernel(ram_size, kernel_filename); } =20 static void openrisc_sim_machine_init(MachineClass *mc) { mc->desc =3D "or1k simulation"; mc->init =3D openrisc_sim_init; - mc->max_cpus =3D 1; + mc->max_cpus =3D 2; mc->is_default =3D 1; } =20 --=20 2.13.6 From nobody Fri May 3 13:58:57 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507903103903451.0253908812116; Fri, 13 Oct 2017 06:58:23 -0700 (PDT) Received: from localhost ([::1]:50452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e30TS-0005VG-JO for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 5/5] openrisc: Only kick cpu on timeout, not on update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously we were kicking the cpu on every update. This caused problems noticeable in SMP configurations where one CPU got pinned continuously servicing timer exceptions. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index 4c5415ff75..850f88761c 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -78,7 +78,6 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); - qemu_cpu_kick(CPU(cpu)); } =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) @@ -120,6 +119,7 @@ static void openrisc_timer_cb(void *opaque) } =20 cpu_openrisc_timer_update(cpu); + qemu_cpu_kick(CPU(cpu)); } =20 static const VMStateDescription vmstate_or1k_timer =3D { --=20 2.13.6