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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id q9sm16942656pgs.1.2017.10.10.14.45.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 14:45:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Jly5Rz3bvuoFzSgbsnBs9cQIoqMrugJcKgw00N1v7Ns=; b=gpv0MtcJ8oFp47uxe9HryI+q+THGhBlQPgSGGG8ZaczfkrTGpin1MPaYP3Fl/MxOUh rO7EGUCJK50PQncBdsiKWXdgVr4k4esgBqvFJi+yDO9hGWF26m2Us21QPQT2UfL09qtk xSQNT3ny9Vrx10ITE0Irth6vOSWwnpFZ7Ui+s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Jly5Rz3bvuoFzSgbsnBs9cQIoqMrugJcKgw00N1v7Ns=; b=pHb4jWjvIkNUTEZ4R2d0OWq/MLLP1T+GdNRSe2vcp6NSluaqYWbyxm4X0XbzcUnoJI XMsWz7UkB9cYkhVFIIYpCM4zrsKa9XJv8GtGSkhy8VXWWfoBdlXNRppFj5xs31av09vk eoUICNpOKay9Oem6NAxkp7APATmna1y7WQUb3phj29LQCamRq2iIrw9lRT124s2vtv5n H/EyOFVPzMGaU5Hpd+8W7Mc0rOjphc1x4uE+OIQ17D859IwZ7p1dLs/R1kmPN75j9Cmm +hY7hsSlC7+GgGiu4HR4lVRjZ4LQbxsx78ACAocaFF3V3KdficCKS8p+6EfL+Ulmt4Sy zijg== X-Gm-Message-State: AMCzsaVnmG+8R/3S85sGtvSC701v/9qxPZpQFEYu4uxAe5AHH7EfdZhp g8hlJIEKz6k58kDYonYl+joRc149SRw= X-Google-Smtp-Source: AOwi7QAjxu1Or2sQ5KafK7KAmeaVqdoiGB5RCwGrK607wlBKrTHOdu4aBEVHLST6oLeldwzL0WF20g== X-Received: by 10.99.120.202 with SMTP id t193mr13801600pgc.419.1507671942564; Tue, 10 Oct 2017 14:45:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 14:45:40 -0700 Message-Id: <20171010214540.30970-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH] tcg: Initialize cpu_env generically X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/gen-icount.h | 8 ++++---- target/arm/translate.h | 1 - tcg/tcg.h | 9 +-------- target/alpha/translate.c | 4 ---- target/arm/translate.c | 4 ---- target/cris/translate.c | 3 --- target/cris/translate_v10.c | 2 -- target/hppa/translate.c | 4 ---- target/i386/translate.c | 3 --- target/lm32/translate.c | 4 ---- target/m68k/translate.c | 5 ----- target/microblaze/translate.c | 4 ---- target/mips/translate.c | 4 ---- target/moxie/translate.c | 7 ++----- target/nios2/translate.c | 3 --- target/openrisc/translate.c | 3 --- target/ppc/translate.c | 10 +++------- target/s390x/translate.c | 6 ------ target/sh4/translate.c | 7 +------ target/sparc/translate.c | 4 ---- target/tilegx/translate.c | 3 --- target/tricore/translate.c | 6 ++---- target/unicore32/translate.c | 4 ---- target/xtensa/translate.c | 3 --- tcg/tcg-op.c | 30 +++++++++++++++--------------- tcg/tcg.c | 31 +++++++------------------------ 26 files changed, 35 insertions(+), 137 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9b3cb14dfa..de52a67ee8 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count =3D tcg_temp_new_i32(); } =20 - tcg_gen_ld_i32(count, tcg_ctx.tcg_env, + tcg_gen_ld_i32(count, cpu_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 if (tb->cflags & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 if (tb->cflags & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx.tcg_env, + tcg_gen_st16_i32(count, cpu_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } =20 @@ -62,7 +62,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int n= um_insns) static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } @@ -70,7 +70,7 @@ static inline void gen_io_start(void) static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/target/arm/translate.h b/target/arm/translate.h index 3c96aec956..410ba79c0d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -80,7 +80,6 @@ typedef struct DisasCompare { } DisasCompare; =20 /* Share the TCG temporaries common between 32 and 64 bit modes. */ -extern TCGv_env cpu_env; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; diff --git a/tcg/tcg.h b/tcg/tcg.h index b2d42e3136..da1fefd6f1 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -702,7 +702,6 @@ struct TCGContext { =20 /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ - TCGv_env tcg_env; /* *_exec */ =20 /* These structures are private to tcg-target.inc.c. */ #ifdef TCG_TARGET_NEED_LDST_LABELS @@ -727,6 +726,7 @@ struct TCGContext { }; =20 extern TCGContext tcg_ctx; +extern TCGv_env cpu_env; extern bool parallel_cpus; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) @@ -783,9 +783,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t = start, intptr_t size); =20 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); =20 -TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); -TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); - TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); =20 @@ -904,8 +901,6 @@ do {\ #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n)) =20 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) -#define tcg_global_reg_new_ptr(R, N) \ - TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) #define tcg_global_mem_new_ptr(R, O, N) \ TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) @@ -915,8 +910,6 @@ do {\ #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n)) =20 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) -#define tcg_global_reg_new_ptr(R, N) \ - TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) #define tcg_global_mem_new_ptr(R, O, N) \ TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f32c95b9a1..bbfffc7173 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -78,7 +78,6 @@ struct DisasContext { #define DISAS_PC_STALE DISAS_TARGET_2 =20 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_std_ir[31]; static TCGv cpu_fir[31]; static TCGv cpu_pc; @@ -132,9 +131,6 @@ void alpha_translate_init(void) } done_init =3D 1; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - for (i =3D 0; i < 31; i++) { cpu_std_ir[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUAlphaState, ir[= i]), diff --git a/target/arm/translate.c b/target/arm/translate.c index fdc46cc525..722b66238a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -58,7 +58,6 @@ #define IS_USER(s) (s->user) #endif =20 -TCGv_env cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; @@ -81,9 +80,6 @@ void arm_translate_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - for (i =3D 0; i < 16; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, regs[i]), diff --git a/target/cris/translate.c b/target/cris/translate.c index 38a999e6f1..2fb0b62cad 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -66,7 +66,6 @@ #define CC_MASK_NZVC 0xf #define CC_MASK_RNZV 0x10e =20 -static TCGv_env cpu_env; static TCGv cpu_R[16]; static TCGv cpu_PR[16]; static TCGv cc_x; @@ -3368,8 +3367,6 @@ void cris_initialize_tcg(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 4a0b485d8e..fce78825cc 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1272,8 +1272,6 @@ void cris_initialize_crisv10_tcg(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 26242f4b3c..acc3cef92b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -83,7 +83,6 @@ typedef struct DisasInsn { } DisasInsn; =20 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_gr[32]; static TCGv cpu_iaoq_f; static TCGv cpu_iaoq_b; @@ -132,9 +131,6 @@ void hppa_translate_init(void) } done_init =3D 1; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - TCGV_UNUSED(cpu_gr[0]); for (i =3D 1; i < 32; i++) { cpu_gr[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/i386/translate.c b/target/i386/translate.c index 5d61fa96ad..792a0b7662 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -72,7 +72,6 @@ //#define MACRO_TEST 1 =20 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_A0; static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; static TCGv_i32 cpu_cc_op; @@ -8336,8 +8335,6 @@ void tcg_x86_init(void) } initialized =3D true; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cpu_cc_op =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_o= p"); cpu_cc_dst =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_ds= t), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 65bc9c0bf6..5d64db2da0 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 -static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; static TCGv cpu_ie; @@ -1208,9 +1207,6 @@ void lm32_translate_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPULM32State, regs[i]), diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d738f32f9c..4e95f38fda 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -44,8 +44,6 @@ static TCGv_i32 cpu_halted; static TCGv_i32 cpu_exception_index; =20 -static TCGv_env cpu_env; - static char cpu_reg_names[2 * 8 * 3 + 5 * 4]; static TCGv cpu_dregs[8]; static TCGv cpu_aregs[8]; @@ -69,9 +67,6 @@ void m68k_tcg_init(void) char *p; int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - #define DEFO32(name, offset) \ QREG_##name =3D tcg_global_mem_new_i32(cpu_env, \ offsetof(CPUM68KState, offset), #name); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 067b0878d6..821c628f00 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 static TCGv env_debug; -static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_SR[18]; static TCGv env_imm; @@ -1855,9 +1854,6 @@ void mb_tcg_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - env_debug =3D tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), "debug0"); diff --git a/target/mips/translate.c b/target/mips/translate.c index ac05f3aa09..a97a1425a3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1376,7 +1376,6 @@ enum { }; =20 /* global register indices */ -static TCGv_env cpu_env; static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget, bcond; @@ -20459,9 +20458,6 @@ void mips_tcg_init(void) if (inited) return; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - TCGV_UNUSED(cpu_gpr[0]); for (i =3D 1; i < 32; i++) cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 3cfd232558..7e0e5928d0 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -56,7 +56,6 @@ enum { =20 static TCGv cpu_pc; static TCGv cpu_gregs[16]; -static TCGv_env cpu_env; static TCGv cc_a, cc_b; =20 #include "exec/gen-icount.h" @@ -105,8 +104,8 @@ void moxie_translate_init(void) if (done_init) { return; } - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + done_init =3D 1; + cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i =3D 0; i < 16; i++) @@ -118,8 +117,6 @@ void moxie_translate_init(void) offsetof(CPUMoxieState, cc_a), "cc_a"); cc_b =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, cc_b), "cc_b"); - - done_init =3D 1; } =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6b0961837d..c8d1f3e724 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -789,7 +789,6 @@ static const char * const regnames[] =3D { "rpc" }; =20 -static TCGv_ptr cpu_env; static TCGv cpu_R[NUM_CORE_REGS]; =20 #include "exec/gen-icount.h" @@ -947,8 +946,6 @@ void nios2_tcg_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - for (i =3D 0; i < NUM_CORE_REGS; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 112db1ad0f..59dd80d7f4 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -53,7 +53,6 @@ typedef struct DisasContext { bool singlestep_enabled; } DisasContext; =20 -static TCGv_env cpu_env; static TCGv cpu_sr; static TCGv cpu_R[32]; static TCGv cpu_R0; @@ -80,8 +79,6 @@ void openrisc_translate_init(void) }; int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cpu_sr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 606b605ba0..f33667357a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -51,7 +51,6 @@ /* Code translation helpers = */ =20 /* global register indexes */ -static TCGv_env cpu_env; static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ + 10*4 + 22*5 /* FPR */ @@ -86,11 +85,10 @@ void ppc_translate_init(void) size_t cpu_reg_names_size; static int done_init =3D 0; =20 - if (done_init) + if (done_init) { return; - - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + } + done_init =3D 1; =20 p =3D cpu_reg_names; cpu_reg_names_size =3D sizeof(cpu_reg_names); @@ -191,8 +189,6 @@ void ppc_translate_init(void) =20 cpu_access_type =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUPPCState, access_= type), "access_type"); - - done_init =3D 1; } =20 /* internal defines */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 165d2cac3e..16d39073be 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -37,10 +37,6 @@ #include "qemu/log.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" - -/* global register indexes */ -static TCGv_env cpu_env; - #include "exec/gen-icount.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -112,8 +108,6 @@ void s390x_translate_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; psw_addr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8db9fba26e..d41be4f122 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -65,7 +65,6 @@ enum { }; =20 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_gregs[32]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; @@ -103,9 +102,7 @@ void sh4_translate_init(void) if (done_init) { return; } - - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + done_init =3D 1; =20 for (i =3D 0; i < 24; i++) { cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -163,8 +160,6 @@ void sh4_translate_init(void) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, fregs[= i]), fregnames[i]); - - done_init =3D 1; } =20 void superh_cpu_dump_state(CPUState *cs, FILE *f, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6290705b11..e6469634c0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -41,7 +41,6 @@ according to jump_pc[T2] */ =20 /* global register indexes */ -static TCGv_env cpu_env; static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv_i32 cpu_cc_op; @@ -5923,9 +5922,6 @@ void gen_intermediate_code_init(CPUSPARCState *env) } inited =3D 1; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - cpu_regwptr =3D tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), "regwptr"); diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ace2830a84..93fc2e8d2f 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -33,7 +33,6 @@ =20 #define FMT64X "%016" PRIx64 =20 -static TCGv_env cpu_env; static TCGv cpu_pc; static TCGv cpu_regs[TILEGX_R_COUNT]; =20 @@ -2445,8 +2444,6 @@ void tilegx_tcg_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), = "pc"); for (i =3D 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 4e4198e887..fac646eccc 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -47,8 +47,6 @@ static TCGv cpu_PSW_V; static TCGv cpu_PSW_SV; static TCGv cpu_PSW_AV; static TCGv cpu_PSW_SAV; -/* CPU env */ -static TCGv_env cpu_env; =20 #include "exec/gen-icount.h" =20 @@ -8884,8 +8882,8 @@ void tricore_tcg_init(void) if (inited) { return; } - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + inited =3D 1; + /* reg init */ for (i =3D 0 ; i < 16 ; i++) { cpu_gpr_a[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 6c094d59d7..a1c3d25285 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -54,7 +54,6 @@ typedef struct DisasContext { conditional executions state has been updated. */ #define DISAS_SYSCALL DISAS_TARGET_3 =20 -static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; =20 /* FIXME: These should be removed. */ @@ -74,9 +73,6 @@ void uc32_translate_init(void) { int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; - for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUUniCore32State, regs[i]), regn= ames[i]); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index d7bf07e8e6..37796642a8 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -77,7 +77,6 @@ typedef struct DisasContext { unsigned cpenable; } DisasContext; =20 -static TCGv_env cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; @@ -221,8 +220,6 @@ void xtensa_translate_init(void) }; int i; =20 - cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index d3c0e4799e..33eff03b07 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2592,7 +2592,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); + gen_helper_lookup_tb_ptr(ptr, cpu_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2678,7 +2678,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx.cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2687,7 +2687,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx.cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2706,7 +2706,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx.cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2720,7 +2720,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx.cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2836,11 +2836,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv= addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, cpu_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, cpu_env, addr, cmpv, newv); #endif =20 if (memop & MO_SIGN) { @@ -2881,14 +2881,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv= addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, cpu_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, cpu_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(retv, 0); @@ -2944,11 +2944,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv add= r, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx= )); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, cpu_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, cpu_env, addr, val); #endif =20 if (memop & MO_SIGN) { @@ -2989,14 +2989,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv add= r, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, cpu_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, cpu_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); diff --git a/tcg/tcg.c b/tcg/tcg.c index b075749b68..4b89684c3a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -119,6 +119,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s); #define TCG_HIGHWATER 1024 =20 TCGContext tcg_ctx =3D { }; +TCGv_env cpu_env =3D 0; static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -325,6 +326,8 @@ static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); +static int tcg_global_reg_new_internal(TCGContext *s, TCGType type, + TCGReg reg, const char *name); =20 void tcg_context_init(TCGContext *s) { @@ -383,6 +386,10 @@ void tcg_context_init(TCGContext *s) for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { indirect_reg_alloc_order[i] =3D tcg_target_reg_alloc_order[i]; } + + tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); + i =3D tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); + cpu_env =3D MAKE_TCGV_PTR(i); } =20 /* @@ -525,30 +532,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t= start, intptr_t size) s->frame_temp =3D &s->temps[idx]; } =20 -TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) -{ - TCGContext *s =3D &tcg_ctx; - int idx; - - if (tcg_regset_test_reg(s->reserved_regs, reg)) { - tcg_abort(); - } - idx =3D tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name); - return MAKE_TCGV_I32(idx); -} - -TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) -{ - TCGContext *s =3D &tcg_ctx; - int idx; - - if (tcg_regset_test_reg(s->reserved_regs, reg)) { - tcg_abort(); - } - idx =3D tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name); - return MAKE_TCGV_I64(idx); -} - int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { --=20 2.13.6