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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qsfB70w9CzKDOcAWwewK8f/2coAK2gFW2Q5mox1wx5o=; b=XOuH9YQvwHKWKirerHu2GryaBKPrJrf9W6qjDHbw3YZ2ogiTFcD4J1qPnYiRExCkZI Vr/FcpcNIpnCjHQelblbIFNgYl1cOrGa8/L7rs1DTTzn0PbqdjnEBIh9oS6D1Dlwtgby s79tLic3fJrXIXQy/OstLmb5QNhu9IR6WxnnQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qsfB70w9CzKDOcAWwewK8f/2coAK2gFW2Q5mox1wx5o=; b=Htk1TelQA33aooue+m7Qtoqd58NdVftANgdIIAes0ACes+jBqRa06sBf26rHwm3DFZ hll/ngpNCTcuJAra9iVYoDo+jQaWzzLbmFEU2acLOl7xtTZPmW4Ryfpod5dsOuHoYK0U aiGSplZiwh03fn6IRf4DRl75zfISOqhyHQBv6FeHbiodRPbAskxKWLpX8L77KpM6fZW7 wXppGlSms9x4cld/2HjqWnVFA4Y2K5y8a6874GEYqFYnv/wLpa3jMlW8h+VAm5/NtoFd t2gYd7UtvDs+uZo0qlTsCbzBi/qoeQz5GWiBevH8nJH2kqc43V2isEu4RMs5z+pw/Xof 2TYw== X-Gm-Message-State: AMCzsaWbEUXYN4EG/uODQqITmulkmt4++qh2b9G9E1SOuO52M9UTuIRV t072FN4WrdLh8zAwlXttEONbvb8PfWg= X-Google-Smtp-Source: AOwi7QA1RjyBky7hWDWGBCNpHXuWe7zQqLxiOWe68WHp2IGz/LOHhnyyTKnZw4zWR7+azqrnabvQ0g== X-Received: by 10.98.50.66 with SMTP id y63mr11740327pfy.155.1507596964564; Mon, 09 Oct 2017 17:56:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:38 -0700 Message-Id: <20171010005600.28735-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL 01/23] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f848d..e43ff8346b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f941783c5..c91db211bc 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bcbcc4db6c..5b1ef1442c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2d1ed06065..6b5d4bece2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1936,7 +1936,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597257862519.5458164632961; Mon, 9 Oct 2017 18:00:57 -0700 (PDT) Received: from localhost ([::1]:60502 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iuh-0005dH-3i for importer@patchew.org; Mon, 09 Oct 2017 21:00:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iq8-00029y-Ey for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iq7-0004H9-7u for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:08 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:43661) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iq7-0004GZ-2U for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:07 -0400 Received: by mail-pf0-x236.google.com with SMTP id d2so12282526pfh.0 for ; Mon, 09 Oct 2017 17:56:06 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uWX8ltUJ41jzpP0mhxc6dOVFBO5YtrjkEa7vnTfdaYc=; b=kp1BUMNE9i/d/XDGrsyr2iovJEuv2Y0dIw45muA98IwZt54z4nWywcE9j+Wcw3cogj HRF7duWiEVvEqHvZJoQxlEKCNqjiyfEkEimYYf198r6U5A9L05Zh57AM1WEToHq6J0Bs huLXBMQK/vz4qDphcJF7ScV+T6l5xnKtRh/R8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uWX8ltUJ41jzpP0mhxc6dOVFBO5YtrjkEa7vnTfdaYc=; b=aofAXop6s9LEr/bJmLzY2K4P+wOhSlMGEtMhtPnge9B0qIz9MsHZVwUMYdoPeKXDE0 JZV8cKaDy2645TnEQYAFwDwgLNM3pqDqh4Fr5cBBBNBfuflBv8TPe1sNTJezwRoXccDi YtEnLj6qIjgHI4xfMf0ya0QEwBJT1u1tahvn5sfPaY59SKDqEUoGABdJxbGYlkn186HP CcQJ+qUcwH2ItXP0+Nr7GnKw0W4AsYtP73KrK5SsNc0McyAr1BVhN5V8fcIYnA4EsCre uZLnEMkKkaEDj1EsQRl6Vk+hnw4d/4sHAeA87yRlIM8PA7FtrBMAYp1FbOE41ZQfqcHY GpwA== X-Gm-Message-State: AMCzsaV1Do0+Ej2buHOe1L+bzGcl6vuEqceH/VY2sFriRqqk3VTUjOKg Mt5VktLZsFL6riAMzbhu+mMv4pCMxjo= X-Google-Smtp-Source: AOwi7QAyPH4HiIH4oaUVFMKa7kiq6nzVOD6cn0zGWm7W4c1HJt4CI35/WL4LeJAtroDv8LPLVk4SjA== X-Received: by 10.98.26.203 with SMTP id a194mr8692474pfa.113.1507596965728; Mon, 09 Oct 2017 17:56:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:39 -0700 Message-Id: <20171010005600.28735-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 02/23] tcg: fix corruption of code_time profiling counter upon tb_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -=3D profile_getclock(), without later on getting +=3D profile_getclock() due to the goto). Fix it by using the ti variable, so that we only update code_time when there is no overflow. Note that in case there is an overflow we fail to account for the elapsed coding time, but this is quite rare so we can probably live with it. "info jit" before/after, roughly at the same time during debian-arm bootup: - before: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 998 JIT cycles -615191529184601 (-256329.804 s at 2.4 GHz) translated TBs 302310 (aborted=3D0 0.0%) avg ops/TB 48.4 max=3D438 deleted ops/TB 8.54 avg temps/TB 32.31 max=3D38 avg host code/TB 361.5 avg search data/TB 24.5 cycles/op -42014693.0 cycles/in byte -121444900.2 cycles/out byte -5629031.1 cycles/search byte -83114481.0 gen_interm time -0.0% gen_code time 100.0% optim./code time -0.0% liveness/code time -0.0% cpu_restore count 6236 avg cycles 110.4 - after: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 1010 JIT cycles 1996899624 (0.832 s at 2.4 GHz) translated TBs 297961 (aborted=3D0 0.0%) avg ops/TB 48.5 max=3D438 deleted ops/TB 8.56 avg temps/TB 32.31 max=3D38 avg host code/TB 361.8 avg search data/TB 24.5 cycles/op 138.2 cycles/in byte 398.4 cycles/out byte 18.5 cycles/search byte 273.1 gen_interm time 14.0% gen_code time 86.0% optim./code time 19.4% liveness/code time 10.3% cpu_restore count 6372 avg cycles 111.0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b5d4bece2..b3bfe65059 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1300,7 +1300,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; tcg_ctx.interm_time +=3D profile_getclock() - ti; - tcg_ctx.code_time -=3D profile_getclock(); + ti =3D profile_getclock(); #endif =20 /* ??? Overflow could be handled better here. In particular, we @@ -1318,7 +1318,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock(); + tcg_ctx.code_time +=3D profile_getclock() - ti; tcg_ctx.code_in_len +=3D tb->size; tcg_ctx.code_out_len +=3D gen_code_size; tcg_ctx.search_out_len +=3D search_size; --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150759709971763.84527196637532; Mon, 9 Oct 2017 17:58:19 -0700 (PDT) Received: from localhost ([::1]:60490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1is2-0003Qt-Ld for importer@patchew.org; Mon, 09 Oct 2017 20:58:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iq9-0002AB-Nr for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iq8-0004JT-US for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:09 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:52377) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iq8-0004IB-PK for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:08 -0400 Received: by mail-pf0-x236.google.com with SMTP id a1so12238474pfj.9 for ; Mon, 09 Oct 2017 17:56:08 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7R+gio33UwF3vi2Cvaa4aXxIYtef4+3eg4MJuM1tI6k=; b=WQrawERePKQXV2hUp52VuK6X2NHLaBHGvEsFqS8gS3MjtZ8BG/EnAhbwLdHgMdls3O IMF4c7xtwJKl0Z4fRzPJJBe2ePp4iS6qeLT2H5Ytc+hX1C5Zv+FqcMCi1vF/JpURi4gN 6bH5IEEiJ6s0dHQF3cm+CqA71U1tLRggPm/cQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7R+gio33UwF3vi2Cvaa4aXxIYtef4+3eg4MJuM1tI6k=; b=TV+tk8NVP5fVwtcxqZnDHorvWypLsonbNkks1ph0ET9IYXynndaFxRYPJugr/ZeELl O4OTNIeKrruq3ZmQXKtpKXA9j7t5f7zQnQqGXTOhGFDbjDM9U2TtHmpn9ueeVCilBBOT Awt24ucuNBZ9uvgIczp6hhgf3ThCqBrv5Iywqv/hgZS1yrMi9GQL6lOu62Tj7yNk3Sx7 Aw9n/bCttAhaAol9h/BQn+2yJFPCFO+cveD5cvnjwAHvfVASomWy5avjL3FuKBrieLH1 rPbfEdWLDcxvvuJCDe3pkoq5LQTIAI8/a76Iekew0JXpEGP/lXHXZtcqnUpFd4Dz4SUW 4yiQ== X-Gm-Message-State: AMCzsaWuoGk1lMS+PT9UkCEJwMvqZzb+VJMrPCEU+5OyDOr7AM1Ebh0m rm9dXUfbpVdKN1r6Tv3mimkKmLAD4X8= X-Google-Smtp-Source: AOwi7QDxx83GJ++3mehUVGYKPRW+LJohDgTiCY62XXMKEVVRX9ohGqvZw1gVBPF6ED6y42pZDQJv2w== X-Received: by 10.98.16.211 with SMTP id 80mr3684427pfq.72.1507596967481; Mon, 09 Oct 2017 17:56:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:40 -0700 Message-Id: <20171010005600.28735-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 03/23] exec-all: fix typos in TranslationBlock's documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 673fc066d0..a9a8bb6f83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -332,7 +332,7 @@ struct TranslationBlock { /* The following data are used to directly call another TB from * the code of this one. This can be done either by emitting direct or * indirect native jump instructions. These jumps are reset so that th= e TB - * just continue its execution. The TB can be linked to another one by + * just continues its execution. The TB can be linked to another one by * setting one of the jump targets (or patching the jump instruction).= Only * two of such jumps are supported. */ @@ -340,7 +340,7 @@ struct TranslationBlock { #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated = */ uintptr_t jmp_target_arg[2]; /* target address or offset */ =20 - /* Each TB has an assosiated circular list of TBs jumping to this one. + /* Each TB has an associated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. * Since each TB can have two jumps, it can participate in two lists. --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597257216909.727014100424; Mon, 9 Oct 2017 18:00:57 -0700 (PDT) Received: from localhost ([::1]:60503 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iuk-0005fI-FS for importer@patchew.org; Mon, 09 Oct 2017 21:00:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqB-0002B7-8a for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqA-0004L7-Eo for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:11 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:54344) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqA-0004KN-9B for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:10 -0400 Received: by mail-pf0-x229.google.com with SMTP id m28so10541354pfi.11 for ; Mon, 09 Oct 2017 17:56:10 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uG5OhsPX14oZq3VVK+Rfgxl4+EVwuLdEt9otmw2teC8=; b=c4pz7kmeN5ugK//xyaOIO3JymvrySnfYGHKD7nj9uFsVkrAB5QlGnZCu/wLHJNNa8N yOhGikXqNCm44E0thJvNVU6IvXFmAGEsJU1KBrEay4S/K3aRsOvp5hT5cEETF45ovg7S hoMWcgpIDFyJxBtaaZGpCEiMkjAfclzDfGch4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uG5OhsPX14oZq3VVK+Rfgxl4+EVwuLdEt9otmw2teC8=; b=CzI4qu90sC/5IZwFhaVN9yzne6ZpxBapCggvIii+Ui9U/mI8O8cWrUCt/n6JHMDH99 9JtLW1rItqgJKdWyOWFJ2UIQoqQDVPzAfqZBPf85pQ6/bGKUUhErOhpRfv6bXpNp5KTj d55kvYBd/eSULhPiiq8SWRZetbVEUsw5H/xJMoUyy2+VDK7HpssMd+o9d6cF2PWRqRjF ebSE5FMpU+iy54HcGZwrH6EnVDLc8OYD3vD33TK42jU39v3+0szUCetb2TmDuoPtPQhU RSrj/ksl457IcIOvjzqZf/2SGh+ABxZvCzevFFG3Mx2NaaYIXmCgOydSxMvaFVxSkSaV kSfg== X-Gm-Message-State: AMCzsaWQckeENemiVrp/FHEHSlo/Gx9hlafC2XTcXK/ge4QZRizpZ04R Yt4iOTY1OHCVgoiFYquOX/Tl1NRp01s= X-Google-Smtp-Source: AOwi7QDYTKxwTD4to2+V3gvHE/6OOCK+s+2VrOCHV2Tf5a7i/gYoBZeo3vHgcGDCIZnP/arZVNFRTA== X-Received: by 10.98.35.18 with SMTP id j18mr5852793pfj.37.1507596968754; Mon, 09 Oct 2017 17:56:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:41 -0700 Message-Id: <20171010005600.28735-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 04/23] translate-all: make have_tb_lock static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b3bfe65059..a7c1d4e3f2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -139,7 +139,7 @@ TCGContext tcg_ctx; bool parallel_cpus; =20 /* translation block context */ -__thread int have_tb_lock; +static __thread int have_tb_lock; =20 static void page_table_config_init(void) { --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597254302475.00001640091193; Mon, 9 Oct 2017 18:00:54 -0700 (PDT) Received: from localhost ([::1]:60501 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iug-0005bl-Dy for importer@patchew.org; Mon, 09 Oct 2017 21:00:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqC-0002CO-79 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqB-0004M5-Cx for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:12 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:45292) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqB-0004LI-7d for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:11 -0400 Received: by mail-pf0-x22b.google.com with SMTP id d28so768015pfe.2 for ; Mon, 09 Oct 2017 17:56:11 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jmmg93vGlfXYGCWPpMGtBaYKMC23pLLXYbM9fkFhyDY=; b=WJErV/y3XiLb3ZIVTu2bA7pRox6g2ZLd3wu69rf6xYhU3SP0zA03f3u/OF6qlk8vGh s6i5LBEF8E/httiixTM2ZICFYAsIDcZgDGUxzaCSa5mbsEJxgpGK0y5lLTNk2fhRwfaa fpC/NieRAH7cvTF9maSB9Qcw6bbSPW8ZocQbk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jmmg93vGlfXYGCWPpMGtBaYKMC23pLLXYbM9fkFhyDY=; b=KWOuwTk3vFoDE8MtmpREeRMk6tir50cY8dn2Cbh/CjTgln2QFhnGf2hH88PT0Tjt15 ezkxwrI9L6x0CqtnA/O40Opf7ZGnJuZQjJ31OZS0cKd7BoECGgdie73XpMdRUzO6o5wZ 9OKty1MUNYzZyPcjY5WCuburb3YJgb8dZVvWr+wQAXecE2/dOE8mksENnH0JbIr2igCC 3iYFvFlBnjAq8ujclvYeAaOPOh2fmIZRBoIdYm6VrGMZbKhwoEJnFt+OrF/jukdf8ijk kmoluYAEnbde3Y7iA+NRDuy/6bGX7GhRpThGkj32a00f7KceIgiXPrt8TTxZXY60gnJR Glng== X-Gm-Message-State: AMCzsaUYdBhx+gZ1dyOpVi9yEbmO0dQRDi7bFdpREB/ZYcwlURQok3Sx z+4HwDsTLC8Ut5KZajTAR3qZT3atmbg= X-Google-Smtp-Source: AOwi7QCKrudq+RbkbgaYSI7vjKSDt/Un6efkempRxBBfeUONbHljbOHjz2zHcvvOFJDZiqWTHNl+gQ== X-Received: by 10.84.224.1 with SMTP id r1mr10203207plj.65.1507596969899; Mon, 09 Oct 2017 17:56:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:42 -0700 Message-Id: <20171010005600.28735-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 05/23] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff6866624a..32104b8d8c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -372,7 +372,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - bool have_tb_lock =3D false; + bool acquired_tb_lock =3D false; =20 /* we record a subset of the CPU state. It will always be the same before a given translated block @@ -391,7 +391,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, */ mmap_lock(); tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; =20 /* There's a chance that our desired tb has been translated wh= ile * taking the locks so we check again inside the lock. @@ -419,15 +419,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, #endif /* See if we can patch the calling TB. */ if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - if (!have_tb_lock) { + if (!acquired_tb_lock) { tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; } if (!tb->invalid) { tb_add_jump(last_tb, tb_exit, tb); } } - if (have_tb_lock) { + if (acquired_tb_lock) { tb_unlock(); } return tb; --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597432152127.9489735397517; Mon, 9 Oct 2017 18:03:52 -0700 (PDT) Received: from localhost ([::1]:60512 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1ixS-0007vD-M3 for importer@patchew.org; Mon, 09 Oct 2017 21:03:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqD-0002DZ-BB for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqC-0004Nj-Ky for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:13 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:50841) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqC-0004Mf-Fm for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:12 -0400 Received: by mail-pf0-x236.google.com with SMTP id m63so15477716pfk.7 for ; Mon, 09 Oct 2017 17:56:12 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ldxUa5xmFXm5OESHWBxV8Hz1PBcjUVlLDSHgmwg+rLo=; b=LScE9Y5VJVAYcz8cP4OYKkjYdO5AQvnhUeMp9tHAta2u+lCcIAFOzq2SEM5h42B9q9 /VyuQkeebVhoX2BkFV4YJRCJ2M45J3wZDyijASL7Z5hTn2iHAVdv7Gg7FLv6qSQkW1wJ QXSU+5Q9WLBMrHEO8YbqeBb1vtYfexhBy2ULg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ldxUa5xmFXm5OESHWBxV8Hz1PBcjUVlLDSHgmwg+rLo=; b=gpoZqGLwGZe9e4PKGb/mOq6UD2ExG6FCnwvSBxl1twpx6vr+ngegTqY2DpMlXWjT2v 6eGhJ0B3IS/I0gdx9r2qzhy97a3H7YlbeM9NbuWUuNm3DtGyN6See3IZV3Smn3T6VHWr Ed/SCKwKTVtIykssEtpSFqxdLDcIU1SQjf0K9flrmi0tZ0iRymrTIO0vT1sSMDUMvlmE 2iuGmdvbzaEpShCRVz+Qt/+y1qNn3nYtrDav52CaF8jlBLZHgqis8x8bpN1dUCuVqLPu jJLpZaQF9rKA9ih+caZtAVYmEPB+clxUNpXpCg4BEI35frTSkVXIn6tFQZtKHOX303Bt BS3w== X-Gm-Message-State: AMCzsaWaMT1Vpqbuwz27khoryeHZb3WqWaf8MVF+E+tIKzThVzWyDl2w f1t59HWSP+71aeQxqmoS5afSb0lyZSw= X-Google-Smtp-Source: AOwi7QBLA/zbFsMXQIu+ZyzyPC/zcNYoziR4Gue+kLXWVUVjeQ+CSPVZaGcqHa8/A63u02Kx0Nal5Q== X-Received: by 10.98.57.220 with SMTP id u89mr11773668pfj.104.1507596971226; Mon, 09 Oct 2017 17:56:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:43 -0700 Message-Id: <20171010005600.28735-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 06/23] tcg/i386: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 69e49c9f58..63d27f10e7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2499,7 +2499,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597437830399.33240269077737; Mon, 9 Oct 2017 18:03:57 -0700 (PDT) Received: from localhost ([::1]:60514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1ixY-0007ye-V9 for importer@patchew.org; Mon, 09 Oct 2017 21:03:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqG-0002Gj-H0 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqD-0004Oq-TC for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:16 -0400 Received: from mail-pf0-x232.google.com ([2607:f8b0:400e:c00::232]:46678) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqD-0004OG-O1 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:13 -0400 Received: by mail-pf0-x232.google.com with SMTP id p87so6426375pfj.3 for ; Mon, 09 Oct 2017 17:56:13 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PULL 07/23] tcg/mips: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ce4030602f..e993138930 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2341,7 +2341,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) } } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S0, /* used for the global env (TCG_AREG0) */ TCG_REG_S1, TCG_REG_S2, --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597597126608.9469812581333; Mon, 9 Oct 2017 18:06:37 -0700 (PDT) Received: from localhost ([::1]:60528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j0D-0001iJ-61 for importer@patchew.org; Mon, 09 Oct 2017 21:06:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqG-0002H5-RN for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqF-0004QW-A0 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:16 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:56010) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqF-0004QA-1K for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:15 -0400 Received: by mail-pf0-x22e.google.com with SMTP id 17so7135521pfn.12 for ; Mon, 09 Oct 2017 17:56:14 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wd457BU/eqZFjwvIL+UFhAthcD+IPHmAi9wwvo87F4M=; b=Dc1Yy+4BHFmlPJcPP/bjZyNHXhpuprHPlB1Y9tHd7UFQX0u2TYuExNPwkZDvRmNyAr BTbt2Dl9Alr/t9325WvdlxOInWQooup7WQKTkEv2/pPbvk04F9P7vWSTGbKYdRGMZ6k5 vvphSPuZd9Xe7f3b0O9qmDJPkTM0o5pkXcIUo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wd457BU/eqZFjwvIL+UFhAthcD+IPHmAi9wwvo87F4M=; b=MXluFLQ2mMiG9RfruxZaVBG2pUqXRWm5P3ZNfeVRJdFSrNzq+qyMCsYKD+FrtnMJ4w 4pTU3cPJlhiEIUtMfvjtzhnrPNihtrCaOuK9ya7abmIkgXqMHEbfK5qzEjY7eOJliz0u iLIb884J4mrTr5nZFO6+zCbgqtFQ9LUJa9ZEQqHJPEei1a5HNcdsF2pYE5qR9aTE6rhB MY8cmkRc/fTV9oUHPkrHUbWuq0o8hU7styzVY6vrTFFtiYOjGD/uS4ZiCL8tmxJRiAF7 4kRjsCGQslhU4mHtnW1dIC7vdlBe5XbGzyWca0FNTalIZcfNG7n1QoSFDQCKOI3BJ85g MbSQ== X-Gm-Message-State: AMCzsaVF/UU/WsHFKZH8+gNJ0yQQNMZxHswaGnuIij0B+tmin8dr0rKJ 56jtP2kSWYZqRXr7Ix3JcK1XB+FHpR8= X-Google-Smtp-Source: AOwi7QCKE+6Hnb6ZbC/JdmwNe8aWatJo4o5kPkfeTvK3YRmUwstnF2wwc04clBzzXiOS7IGIApR58g== X-Received: by 10.98.79.146 with SMTP id f18mr11261744pfj.153.1507596973594; Mon, 09 Oct 2017 17:56:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:45 -0700 Message-Id: <20171010005600.28735-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PULL 08/23] tcg: remove addr argument from lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- tcg/tcg-op.h | 4 ++-- accel/tcg/tcg-runtime.c | 20 ++++++++++---------- target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 5 +---- target/hppa/translate.c | 6 +++--- target/i386/translate.c | 17 +++++------------ target/mips/translate.c | 4 ++-- target/s390x/translate.c | 2 +- target/sh4/translate.c | 4 ++-- tcg/tcg-op.c | 4 ++-- 12 files changed, 32 insertions(+), 42 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index c41d38a557..1df17d0ba9 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i6= 4) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) =20 -DEF_HELPER_FLAGS_2(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env, tl) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) =20 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) =20 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..18d01b2f43 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -797,7 +797,7 @@ static inline void tcg_gen_exit_tb(uintptr_t val) void tcg_gen_goto_tb(unsigned idx); =20 /** - * tcg_gen_lookup_and_goto_ptr() - look up a TB and jump to it if valid + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid * @addr: Guest address of the target TB * * If the TB is not valid, jump to the epilogue. @@ -805,7 +805,7 @@ void tcg_gen_goto_tb(unsigned idx); * This operation is optional. If the TCG backend does not implement goto_= ptr, * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. */ -void tcg_gen_lookup_and_goto_ptr(TCGv addr); +void tcg_gen_lookup_and_goto_ptr(void); =20 #if TARGET_LONG_BITS =3D=3D 32 #define tcg_temp_new() tcg_temp_new_i32() diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index aafb171294..b75394aba8 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -144,33 +144,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } =20 -void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) +void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, addr_hash; + uint32_t flags, hash; =20 - addr_hash =3D tb_jmp_cache_hash_func(addr); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + hash =3D tb_jmp_cache_hash_func(pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); =20 if (unlikely(!(tb - && tb->pc =3D=3D addr + && tb->pc =3D=3D pc && tb->cs_base =3D=3D cs_base && tb->flags =3D=3D flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, addr, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); if (!tb) { return tcg_ctx.code_gen_epilogue; } - atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + atomic_set(&cpu->tb_jmp_cache[hash], tb); } =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, + qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); + tb->tc_ptr, cpu->cpu_index, pc, + lookup_symbol(pc)); return tb->tc_ptr; } =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5a92c4accb..f32c95b9a1 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3029,7 +3029,7 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) /* FALLTHRU */ case DISAS_PC_UPDATED: if (!use_exit_tb(ctx)) { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; } /* FALLTHRU */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 899ffb96fc..a39b9d3633 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -379,7 +379,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; } } @@ -11363,7 +11363,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) gen_a64_set_pc_im(dc->pc); /* fall through */ case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; case DISAS_EXIT: tcg_gen_exit_tb(0); diff --git a/target/arm/translate.c b/target/arm/translate.c index ab1a12a1b8..fdc46cc525 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4173,10 +4173,7 @@ static inline bool use_goto_tb(DisasContext *s, targ= et_ulong dest) =20 static void gen_goto_ptr(void) { - TCGv addr =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, cpu_R[15]); - tcg_gen_lookup_and_goto_ptr(addr); - tcg_temp_free(addr); + tcg_gen_lookup_and_goto_ptr(); } =20 /* This will end the TB but doesn't guarantee we'll return to diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b6e2652341..26242f4b3c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -505,7 +505,7 @@ static void gen_goto_tb(DisasContext *ctx, int which, if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -1515,7 +1515,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv dest, if (link !=3D 0) { tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); } else { cond_prep(&ctx->null_cond); @@ -3873,7 +3873,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/i386/translate.c b/target/i386/translate.c index a8986f4c1a..a74e7bb177 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2511,7 +2511,7 @@ static void gen_bnd_jmp(DisasContext *s) If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of S->TF. This is used by the syscall/sysret insns. */ static void -do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) +do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { gen_update_cc_op(s); =20 @@ -2532,12 +2532,8 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env); - } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr =3D tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + } else if (jr) { + tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(0); } @@ -2547,10 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) static inline void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { - TCGv unused; - - TCGV_UNUSED(unused); - do_gen_eob_worker(s, inhibit, recheck_tf, unused); + do_gen_eob_worker(s, inhibit, recheck_tf, false); } =20 /* End of block. @@ -2569,7 +2562,7 @@ static void gen_eob(DisasContext *s) /* Jump to register */ static void gen_jr(DisasContext *s, TCGv dest) { - do_gen_eob_worker(s, false, false, dest); + do_gen_eob_worker(s, false, false, true); } =20 /* generate a jump to eip. No segment change must happen before as a diff --git a/target/mips/translate.c b/target/mips/translate.c index d16d879df7..ac05f3aa09 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4303,7 +4303,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int= n, target_ulong dest) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); } } =20 @@ -10883,7 +10883,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); break; default: fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 9ef95141f9..165d2cac3e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5949,7 +5949,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) } else if (use_exit_tb(&dc) || status =3D=3D EXIT_PC_STALE_NOCHAIN= ) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(psw_addr); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 10191073b2..8db9fba26e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -261,7 +261,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -278,7 +278,7 @@ static void gen_jump(DisasContext * ctx) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 688d91755b..d3c0e4799e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2588,11 +2588,11 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 -void tcg_gen_lookup_and_goto_ptr(TCGv addr) +void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env, addr); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597442318563.8682373035799; Mon, 9 Oct 2017 18:04:02 -0700 (PDT) Received: from localhost ([::1]:60513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1ixW-0007wM-OJ for importer@patchew.org; Mon, 09 Oct 2017 21:03:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqI-0002IT-8i for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqG-0004RE-MV for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:18 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:48099) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqG-0004Qs-DQ for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:16 -0400 Received: by mail-pf0-x235.google.com with SMTP id z11so5533039pfk.4 for ; Mon, 09 Oct 2017 17:56:16 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 09/23] tcg: consolidate TB lookups in tb_lookup__cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Note that in this commit we also fix a race, described by Richard Henderson during review. Think of this scenario with threads A and B: (A) Lookup succeeds for TB in hash without tb_lock (B) Sets the TB's tb->invalid flag (B) Removes the TB from tb_htable (B) Clears all CPU's tb_jmp_cache (A) Store TB into local tb_jmp_cache Given that order of events, (A) will keep executing that invalid TB until another flush of its tb_jmp_cache happens, which in theory might never happ= en. We can fix this by checking the tb->invalid flag every time we look up a TB from tb_jmp_cache, so that in the above scenario, next time we try to find that TB in tb_jmp_cache, we won't, and will therefore be forced to look it up in tb_htable. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Djessie.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): Before: 18714.917392 task-clock # 0.952 CPUs utilized = ( +- 0.95% ) 23,142 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 10,558 page-faults # 0.001 M/sec = ( +- 0.95% ) 53,957,727,252 cycles # 2.883 GHz = ( +- 0.91% ) [83.33%] 24,440,599,852 stalled-cycles-frontend # 45.30% frontend cycles idl= e ( +- 1.20% ) [83.33%] 16,495,714,424 stalled-cycles-backend # 30.57% backend cycles idl= e ( +- 0.95% ) [66.66%] 76,267,572,582 instructions # 1.41 insns per cycle # 0.32 stalled cycles per = insn ( +- 0.87% ) [83.34%] 12,692,186,323 branches # 678.186 M/sec = ( +- 0.92% ) [83.35%] 263,486,879 branch-misses # 2.08% of all branches = ( +- 0.73% ) [83.34%] 19.648474449 seconds time elapsed = ( +- 0.82% ) After, w/ inline (this patch): 18471.376627 task-clock # 0.955 CPUs utilized = ( +- 0.96% ) 23,048 context-switches # 0.001 M/sec = ( +- 0.48% ) 1 CPU-migrations # 0.000 M/sec 10,708 page-faults # 0.001 M/sec = ( +- 0.81% ) 53,208,990,796 cycles # 2.881 GHz = ( +- 0.98% ) [83.34%] 23,941,071,673 stalled-cycles-frontend # 44.99% frontend cycles idl= e ( +- 0.95% ) [83.34%] 16,161,773,848 stalled-cycles-backend # 30.37% backend cycles idl= e ( +- 0.76% ) [66.67%] 75,786,269,766 instructions # 1.42 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.24% ) [83.34%] 12,573,617,143 branches # 680.708 M/sec = ( +- 1.34% ) [83.33%] 260,235,550 branch-misses # 2.07% of all branches = ( +- 0.66% ) [83.33%] 19.340502161 seconds time elapsed = ( +- 0.56% ) After, w/o inline: 18791.253967 task-clock # 0.954 CPUs utilized = ( +- 0.78% ) 23,230 context-switches # 0.001 M/sec = ( +- 0.42% ) 1 CPU-migrations # 0.000 M/sec 10,563 page-faults # 0.001 M/sec = ( +- 1.27% ) 54,168,674,622 cycles # 2.883 GHz = ( +- 0.80% ) [83.34%] 24,244,712,629 stalled-cycles-frontend # 44.76% frontend cycles idl= e ( +- 1.37% ) [83.33%] 16,288,648,572 stalled-cycles-backend # 30.07% backend cycles idl= e ( +- 0.95% ) [66.66%] 77,659,755,503 instructions # 1.43 insns per cycle # 0.31 stalled cycles per = insn ( +- 0.97% ) [83.34%] 12,922,780,045 branches # 687.702 M/sec = ( +- 1.06% ) [83.34%] 261,962,386 branch-misses # 2.03% of all branches = ( +- 0.71% ) [83.35%] 19.700174670 seconds time elapsed = ( +- 0.56% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/tb-lookup.h | 49 ++++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/cpu-exec.c | 47 ++++++++++++++++++--------------------------= -- accel/tcg/tcg-runtime.c | 24 ++++++------------------ 3 files changed, 73 insertions(+), 47 deletions(-) create mode 100644 include/exec/tb-lookup.h diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h new file mode 100644 index 0000000000..9d32cb0c6e --- /dev/null +++ b/include/exec/tb-lookup.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef EXEC_TB_LOOKUP_H +#define EXEC_TB_LOOKUP_H + +#include "qemu/osdep.h" + +#ifdef NEED_CPU_H +#include "cpu.h" +#else +#include "exec/poison.h" +#endif + +#include "exec/exec-all.h" +#include "exec/tb-hash.h" + +/* Might cause an exception, so have a longjmp destination ready */ +static inline TranslationBlock * +tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, + uint32_t *flags) +{ + CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; + TranslationBlock *tb; + uint32_t hash; + + cpu_get_tb_cpu_state(env, pc, cs_base, flags); + hash =3D tb_jmp_cache_hash_func(*pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); + if (likely(tb && + tb->pc =3D=3D *pc && + tb->cs_base =3D=3D *cs_base && + tb->flags =3D=3D *flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + !atomic_read(&tb->invalid))) { + return tb; + } + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + if (tb =3D=3D NULL) { + return NULL; + } + atomic_set(&cpu->tb_jmp_cache[hash], tb); + return tb; +} + +#endif /* EXEC_TB_LOOKUP_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 32104b8d8c..f8a1d68db7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "qemu/rcu.h" #include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "exec/log.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) @@ -368,43 +369,31 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) { - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; =20 - /* we record a subset of the CPU state. It will - always be the same before a given translated block - is executed. */ - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]); - if (unlikely(!tb || tb->pc !=3D pc || tb->cs_base !=3D cs_base || - tb->flags !=3D flags || - tb->trace_vcpu_dstate !=3D *cpu->trace_dstate)) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - - /* mmap_lock is needed by tb_gen_code, and mmap_lock must be - * taken outside tb_lock. As system emulation is currently - * single threaded the locks are NOPs. - */ - mmap_lock(); - tb_lock(); - acquired_tb_lock =3D true; - - /* There's a chance that our desired tb has been translated wh= ile - * taking the locks so we check again inside the lock. - */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - /* if no translated code available, then translate it now = */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); - } + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + /* mmap_lock is needed by tb_gen_code, and mmap_lock must be + * taken outside tb_lock. As system emulation is currently + * single threaded the locks are NOPs. + */ + mmap_lock(); + tb_lock(); + acquired_tb_lock =3D true; =20 - mmap_unlock(); + /* There's a chance that our desired tb has been translated while + * taking the locks so we check again inside the lock. + */ + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + if (likely(tb =3D=3D NULL)) { + /* if no translated code available, then translate it now */ + tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); } =20 + mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup = */ atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index b75394aba8..d0edd944b0 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" =20 @@ -149,24 +149,12 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, hash; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - hash =3D tb_jmp_cache_hash_func(pc); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); - - if (unlikely(!(tb - && tb->pc =3D=3D pc - && tb->cs_base =3D=3D cs_base - && tb->flags =3D=3D flags - && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - return tcg_ctx.code_gen_epilogue; - } - atomic_set(&cpu->tb_jmp_cache[hash], tb); - } + uint32_t flags; =20 + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + return tcg_ctx.code_gen_epilogue; + } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", tb->tc_ptr, cpu->cpu_index, pc, --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597590716696.9422142834613; Mon, 9 Oct 2017 18:06:30 -0700 (PDT) Received: from localhost ([::1]:60526 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j05-0001cd-VY for importer@patchew.org; Mon, 09 Oct 2017 21:06:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqI-0002It-O5 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqH-0004S3-Pm for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:18 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:54344) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqH-0004Re-Jd for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:17 -0400 Received: by mail-pf0-x236.google.com with SMTP id m28so10541643pfi.11 for ; Mon, 09 Oct 2017 17:56:17 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 10/23] exec-all: bring tb->invalid into tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This gets rid of a hole in struct TranslationBlock. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 +-- include/exec/tb-lookup.h | 2 +- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 3 +-- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a9a8bb6f83..3135aaf4c9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -314,12 +314,11 @@ struct TranslationBlock { #define CF_NOCACHE 0x10000 /* To be freed after execution */ #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ +#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - uint16_t invalid; - void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9d32cb0c6e..436b6d5ecf 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -35,7 +35,7 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, tar= get_ulong *cs_base, tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - !atomic_read(&tb->invalid))) { + !(atomic_read(&tb->cflags) & CF_INVALID))) { return tb; } tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f8a1d68db7..9cd809d607 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -294,7 +294,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !atomic_read(&tb->invalid)) { + !(atomic_read(&tb->cflags) & CF_INVALID)) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; @@ -412,7 +412,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, tb_lock(); acquired_tb_lock =3D true; } - if (!tb->invalid) { + if (!(tb->cflags & CF_INVALID)) { tb_add_jump(last_tb, tb_exit, tb); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a7c1d4e3f2..ed65d68709 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1073,7 +1073,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 assert_tb_locked(); =20 - atomic_set(&tb->invalid, true); + atomic_set(&tb->cflags, tb->cflags | CF_INVALID); =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); @@ -1269,7 +1269,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tb->invalid =3D false; =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15075971094437.902918568355517; Mon, 9 Oct 2017 17:58:29 -0700 (PDT) Received: from localhost ([::1]:60491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1isL-0003fS-Ki for importer@patchew.org; Mon, 09 Oct 2017 20:58:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqJ-0002K0-Vj for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqJ-0004Sq-10 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:20 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:53904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqI-0004SJ-S8 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:18 -0400 Received: by mail-pf0-x234.google.com with SMTP id n73so8794153pfg.10 for ; Mon, 09 Oct 2017 17:56:18 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LAawtX8GSa0/i2pqKXJe98VeX6zP0igCbj0ZmpFAsd0=; b=c1NXz+LXThyxwUZ8CIutb3UHppOu4bJeRbkF7zOPJSh4qVbmdJqtRf+nwemJEhv81q mWcs4qV5LdPIpSrGYe4prOo2KHKdrJ+68ZrsjLPTti/KPp1EMQEEgmDiR1nSo8FAMh5Q c1DalxgtKm2WcTkDmPzI7z1rGvoue0qB81aLY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAawtX8GSa0/i2pqKXJe98VeX6zP0igCbj0ZmpFAsd0=; b=hVbTJC38bm29GKinC9e6EFFpr/47r/2sxP4bSRkwJm0VvQOaK2kHRYnjN26sUBc/2a npJEJJQbXHlHJtxGYgHcUVRsA8yufrGGHFecEvv40NeOns31ebG3eyn/ByY3onncyF1j 6mo2mxft/kM3QspRDsEGgJd4q27Yr261THKZYDpiJ7RMry89uV/x44Rrn+aElNQqBMHr vzDWYgz0FfiasBx91vNdPHeUntFeErDN5Vifa3NO4oBoes01QGIaqk1Py5j9vcv9vu4U 5HbCayHOA/gVELS4Dt+9Mt/AolUm8e7c8+fj0inM4FjTaQmLVV5Ry/3UOacA1mnSd1I6 Yxog== X-Gm-Message-State: AMCzsaX8qCRVBKrdn7MSudPsfxppvpZ1n8YU6qe0pxQ34E9cfdy0G+F2 KA9Kn8na78B1dYkqc7RQzBmGHGmEQOM= X-Google-Smtp-Source: AOwi7QBFH1zN+t+8EQgBZ6GLSTHGIvzu0ip73JBzkIZ1AF4KfSVa99c+Ydt5pLJjDONV84bpny8vjg== X-Received: by 10.99.176.79 with SMTP id z15mr10461435pgo.230.1507596977551; Mon, 09 Oct 2017 17:56:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:48 -0700 Message-Id: <20171010005600.28735-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 11/23] translate-all: define and use DEBUG_TB_FLUSH_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed65d68709..799b027e79 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_FLUSH +#define DEBUG_TB_FLUSH_GATE 1 +#else +#define DEBUG_TB_FLUSH_GATE 0 +#endif + #if !defined(CONFIG_USER_ONLY) /* TB consistency checks only implemented for usermode emulation. */ #undef DEBUG_TB_CHECK @@ -899,13 +905,13 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) goto done; } =20 -#if defined(DEBUG_TB_FLUSH) - printf("qemu: flush code_size=3D%ld nb_tbs=3D%d avg_tb_size=3D%ld\n", - (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer= )) / - tcg_ctx.tb_ctx.nb_tbs : 0); -#endif + if (DEBUG_TB_FLUSH_GATE) { + printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, + tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / + tcg_ctx.tb_ctx.nb_tbs : 0); + } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150759771902448.84046095029316; Mon, 9 Oct 2017 18:08:39 -0700 (PDT) Received: from localhost ([::1]:60535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j29-0003EP-AS for importer@patchew.org; Mon, 09 Oct 2017 21:08:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqL-0002LH-5P for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqK-0004Tb-7o for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:21 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:43662) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqK-0004TE-2D for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:20 -0400 Received: by mail-pf0-x235.google.com with SMTP id d2so12283029pfh.0 for ; Mon, 09 Oct 2017 17:56:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nCHgQRfd/6L6A+ZFLqYH/ozIQbUkersXx+TPVXfIV2w=; b=JtDbDyIJyGwXyhSqW9TjdNsbm8lXL0CEmSBnw9L1KCgb3BKLHkRru4I+RazstUkcHn 0rMGdpKrpdhkQPDzCmcy34RgOIZMOToyy4ypwCiYvRNDte1uxuEUDb8qiuqLJb4RqKQu lu6l5t6s6pXjH7MD6ltUN7Ur2fRaZw/oNAy24= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nCHgQRfd/6L6A+ZFLqYH/ozIQbUkersXx+TPVXfIV2w=; b=B+PbpMnn8o+ipr/sC/aYmnHuLZQYdxgWCrxNmKCxvWTDWKjuB8uxGtfbolkGMnZYyQ jbl9BlesQsYcQupmvheTNQ59mpWtYfMcKeu7leqk+KxW6EeNNFO+QAyIml7iWVq9lsCb +wW0cshsjde4aFpcgnQNToY+zipO7MQc4aaHQ4TGrCvSV/9mTH+m2jl4j6uzgiBruM5p EgLFntaZyUW8YQeUllt9a6SfHaFSvc6Kru+lbkxQUXLOkDGBEi7qtm46fGZfZYH+7Ked DFRd+GVf01w/VaPO9dRvQT5GhTQiL/iBbmBo3be4xXbltQa1rafE6X7rcqebtaKkjqGC lDjQ== X-Gm-Message-State: AMCzsaXTiRbOhbu42Ujkfr8OeTVokGfDXP9MJcLkJxXdLkR56QkpwFcg QQZgq3P8JdA2yrSBQ66cT+4sdxcCuI4= X-Google-Smtp-Source: AOwi7QAiubOPwdHiyaZWUxf/sDg3/oLFZ2IZe1vTFghq0wOO8DXa/Ja79tqcA2FExCZA2nODIZBcjQ== X-Received: by 10.98.182.15 with SMTP id j15mr881941pff.47.1507596978793; Mon, 09 Oct 2017 17:56:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:49 -0700 Message-Id: <20171010005600.28735-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 12/23] exec-all: introduce TB_PAGE_ADDR_FMT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function =E2=80=98tb_alloc_pag= e=E2=80=99: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format =E2=80=98%l= x=E2=80=99 expects argument of type =E2=80=98long unsigned int=E2=80=99, bu= t argument 2 has type =E2=80=98tb_page_addr_t {aka unsigned int}=E2=80=99 [= -Werror=3Dformat=3D] printf("protecting code page: 0x" TARGET_FMT_lx "\n", ^ cc1: all warnings being treated as errors /data/src/qemu/rules.mak:66: recipe for target 'accel/tcg/translate-all.o' = failed make[1]: *** [accel/tcg/translate-all.o] Error 1 Makefile:328: recipe for target 'subdir-mipsn32-linux-user' failed make: *** [subdir-mipsn32-linux-user] Error 2 cota@flamenco:/data/src/qemu/build ((18f3fe1...) *$)$ Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 ++ accel/tcg/translate-all.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3135aaf4c9..79f8041811 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,10 @@ type. */ #if defined(CONFIG_USER_ONLY) typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx #else typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif =20 #include "qemu/log.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 799b027e79..90b3eed9c6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1193,8 +1193,7 @@ static inline void tb_alloc_page(TranslationBlock *tb, mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); #ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TARGET_FMT_lx "\n", - page_addr); + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); #endif } #else --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597723691596.5375140430185; Mon, 9 Oct 2017 18:08:43 -0700 (PDT) Received: from localhost ([::1]:60536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j2F-0003HW-1D for importer@patchew.org; Mon, 09 Oct 2017 21:08:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqM-0002MH-0b for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqL-0004VZ-E9 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:22 -0400 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:53905) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqL-0004Uc-8e for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:21 -0400 Received: by mail-pf0-x22d.google.com with SMTP id n73so8794260pfg.10 for ; Mon, 09 Oct 2017 17:56:21 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 13/23] translate-all: define and use DEBUG_TB_INVALIDATE_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 90b3eed9c6..6b853b329c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_INVALIDATE +#define DEBUG_TB_INVALIDATE_GATE 1 +#else +#define DEBUG_TB_INVALIDATE_GATE 0 +#endif + #ifdef DEBUG_TB_FLUSH #define DEBUG_TB_FLUSH_GATE 1 #else @@ -1192,9 +1198,9 @@ static inline void tb_alloc_page(TranslationBlock *tb, } mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); -#ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); -#endif + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); + } } #else /* if some code is already present, then the pages are already --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597839638962.562890352796; Mon, 9 Oct 2017 18:10:39 -0700 (PDT) Received: from localhost ([::1]:60542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j3r-0004TA-M9 for importer@patchew.org; Mon, 09 Oct 2017 21:10:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqQ-0002Oi-C9 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqM-0004WM-NR for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:25 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:53905) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqM-0004Vt-Hf for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:22 -0400 Received: by mail-pf0-x22f.google.com with SMTP id n73so8794306pfg.10 for ; Mon, 09 Oct 2017 17:56:22 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 14/23] translate-all: define and use DEBUG_TB_CHECK_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b853b329c..26efad302d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -82,6 +82,12 @@ #undef DEBUG_TB_CHECK #endif =20 +#ifdef DEBUG_TB_CHECK +#define DEBUG_TB_CHECK_GATE 1 +#else +#define DEBUG_TB_CHECK_GATE 0 +#endif + /* Access to the various translations structures need to be serialised via= locks * for consistency. This is automatic for SoftMMU based system * emulation due to its single threaded nature. In user-mode emulation @@ -950,7 +956,13 @@ void tb_flush(CPUState *cpu) } } =20 -#ifdef DEBUG_TB_CHECK +/* + * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, + * so in order to prevent bit rot we compile them unconditionally in user-= mode, + * and let the optimizer get rid of them by wrapping their user-only calle= rs + * with if (DEBUG_TB_CHECK_GATE). + */ +#ifdef CONFIG_USER_ONLY =20 static void do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) @@ -994,7 +1006,7 @@ static void tb_page_check(void) qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); } =20 -#endif +#endif /* CONFIG_USER_ONLY */ =20 static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock= *tb) { @@ -1236,8 +1248,10 @@ static void tb_link_page(TranslationBlock *tb, tb_pa= ge_addr_t phys_pc, h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 -#ifdef DEBUG_TB_CHECK - tb_page_check(); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_page_check(); + } #endif } =20 @@ -2223,8 +2237,10 @@ int page_unprotect(target_ulong address, uintptr_t p= c) /* and since the content will be modified, we must invalidate the corresponding translated code. */ current_tb_invalidated |=3D tb_invalidate_phys_page(addr, pc); -#ifdef DEBUG_TB_CHECK - tb_invalidate_check(addr); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_invalidate_check(addr); + } #endif } mprotect((void *)g2h(host_start), qemu_host_page_size, --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597924173925.5842189644065; Mon, 9 Oct 2017 18:12:04 -0700 (PDT) Received: from localhost ([::1]:60554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j5T-0005bc-EG for importer@patchew.org; Mon, 09 Oct 2017 21:11:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqQ-0002Oj-C7 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqO-0004Wv-2C for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:25 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:57221) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqN-0004Wd-Po for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:23 -0400 Received: by mail-pf0-x22f.google.com with SMTP id b85so4312949pfj.13 for ; Mon, 09 Oct 2017 17:56:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 15/23] exec-all: extract tb->tc_* into a separate struct tc_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++++++++++-- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/tcg-runtime.c | 4 ++-- accel/tcg/translate-all.c | 24 ++++++++++++------------ tcg/tcg.c | 4 ++-- 5 files changed, 33 insertions(+), 25 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79f8041811..53f1835c43 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -303,6 +303,14 @@ static inline void tb_invalidate_phys_addr(AddressSpac= e *as, hwaddr addr) #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif =20 +/* + * Translation Cache-related fields of a TB. + */ +struct tb_tc { + void *ptr; /* pointer to the translated code */ + uint8_t *search; /* pointer to search data */ +}; + struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -321,8 +329,8 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - void *tc_ptr; /* pointer to the translated code */ - uint8_t *tc_search; /* pointer to search data */ + struct tb_tc tc; + /* original tb when cflags has CF_NOCACHE */ struct TranslationBlock *orig_tb; /* first and second physical page containing code. The lower bit diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9cd809d607..363dfa208a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -143,11 +143,11 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *= cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr =3D itb->tc_ptr; + uint8_t *tb_ptr =3D itb->tc.ptr; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %p [%d: " TARGET_FMT_lx "] %s\n", - itb->tc_ptr, cpu->cpu_index, itb->pc, + itb->tc.ptr, cpu->cpu_index, itb->pc, lookup_symbol(itb->pc)); =20 #if defined(DEBUG_DISAS) @@ -179,7 +179,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc_ptr, last_tb->pc, + last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, last_tb); @@ -334,7 +334,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uin= tptr_t addr) { if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset =3D tb->jmp_target_arg[n]; - uintptr_t tc_ptr =3D (uintptr_t)tb->tc_ptr; + uintptr_t tc_ptr =3D (uintptr_t)tb->tc.ptr; tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); } else { tb->jmp_target_arg[n] =3D addr; @@ -354,11 +354,11 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); + tb->tc.ptr, tb->pc, n, + tb_next->tc.ptr, tb_next->pc); =20 /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); =20 /* add in TB jmp circular list */ tb->jmp_list_next[n] =3D tb_next->jmp_list_first; diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0edd944b0..54d89100d9 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -157,9 +157,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, pc, + tb->tc.ptr, cpu->cpu_index, pc, lookup_symbol(pc)); - return tb->tc_ptr; + return tb->tc.ptr; } =20 void HELPER(exit_atomic)(CPUArchState *env) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 26efad302d..c5ce99d549 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -260,7 +260,7 @@ static target_long decode_sleb128(uint8_t **pp) which comes from the host pc of the end of the code implementing the in= sn. =20 Each line of the table is encoded as sleb128 deltas from the previous - line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. + line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. That is, the first column is seeded with the guest pc, the last column with the host pc, and the middle columns with zeros. */ =20 @@ -270,7 +270,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) uint8_t *p =3D block; int i, j, n; =20 - tb->tc_search =3D block; + tb->tc.search =3D block; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { target_ulong prev; @@ -305,9 +305,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uintptr_t searched_pc) { target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; - uintptr_t host_pc =3D (uintptr_t)tb->tc_ptr; + uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; - uint8_t *p =3D tb->tc_search; + uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER int64_t ti =3D profile_getclock(); @@ -858,7 +858,7 @@ void tb_free(TranslationBlock *tb) tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); =20 - tcg_ctx.code_gen_ptr =3D tb->tc_ptr - struct_size; + tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; tcg_ctx.tb_ctx.nb_tbs--; } } @@ -1059,7 +1059,7 @@ static inline void tb_remove_from_jmp_list(Translatio= nBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - uintptr_t addr =3D (uintptr_t)(tb->tc_ptr + tb->jmp_reset_offset[n]); + uintptr_t addr =3D (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); tb_set_jmp_target(tb, n, addr); } =20 @@ -1288,7 +1288,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 gen_code_buf =3D tcg_ctx.code_gen_ptr; - tb->tc_ptr =3D gen_code_buf; + tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; @@ -1307,7 +1307,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_intermediate_code(cpu, tb); tcg_ctx.cpu =3D NULL; =20 - trace_translate_block(tb, tb->pc, tb->tc_ptr); + trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1354,11 +1354,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); if (tcg_ctx.data_gen_ptr) { - size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc_ptr; + size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc.ptr; size_t data_size =3D gen_code_size - code_size; size_t i; =20 - log_disas(tb->tc_ptr, code_size); + log_disas(tb->tc.ptr, code_size); =20 for (i =3D 0; i < data_size; i +=3D sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) =3D=3D 8) { @@ -1372,7 +1372,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } } } else { - log_disas(tb->tc_ptr, gen_code_size); + log_disas(tb->tc.ptr, gen_code_size); } qemu_log("\n"); qemu_log_flush(); @@ -1699,7 +1699,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) while (m_min <=3D m_max) { m =3D (m_min + m_max) >> 1; tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc_ptr; + v =3D (uintptr_t)tb->tc.ptr; if (v =3D=3D tc_ptr) { return tb; } else if (tc_ptr < v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index dff9999bc6..a874bdd41f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2836,8 +2836,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 tcg_reg_alloc_start(s); =20 - s->code_buf =3D tb->tc_ptr; - s->code_ptr =3D tb->tc_ptr; + s->code_buf =3D tb->tc.ptr; + s->code_ptr =3D tb->tc.ptr; =20 #ifdef TCG_TARGET_NEED_LDST_LABELS s->ldst_labels =3D NULL; --=20 2.13.6 From nobody Sat Apr 27 12:55:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597926269585.3457347183482; Mon, 9 Oct 2017 18:12:06 -0700 (PDT) Received: from localhost ([::1]:60553 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j5S-0005aO-CH for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 16/23] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Acked-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 279 insertions(+), 273 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index f39bfb95c0..63f2cd54ab 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, t= cg_target_ulong, tcg_target_ulong); #endif =20 -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif =20 -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } =20 -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } =20 -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif =20 -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index !=3D TCG_AREG0); tci_assert(index !=3D TCG_REG_CALL_STACK); - tci_reg[index] =3D value; + regs[index] =3D value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif =20 /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value =3D tci_read_reg(**tb_ptr); + tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value =3D tci_read_reg8(**tb_ptr); + uint8_t value =3D tci_read_reg8(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value =3D tci_read_reg8s(**tb_ptr); + int8_t value =3D tci_read_reg8s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint16_t value =3D tci_read_reg16(**tb_ptr); + uint16_t value =3D tci_read_reg16(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int16_t value =3D tci_read_reg16s(**tb_ptr); + int16_t value =3D tci_read_reg16s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t value =3D tci_read_reg32(**tb_ptr); + uint32_t value =3D tci_read_reg32(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t low =3D tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low =3D tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int32_t value =3D tci_read_reg32s(**tb_ptr); + int32_t value =3D tci_read_reg32s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint64_t value =3D tci_read_reg64(**tb_ptr); + uint64_t value =3D tci_read_reg64(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(tb_ptr); + target_ulong taddr =3D tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } =20 /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r =3D **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i(tb_ptr); } else { - value =3D tci_read_reg(r); + value =3D tci_read_reg(regs, r); } return value; } =20 /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint32_t value; TCGReg r =3D **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i32(tb_ptr); } else { - value =3D tci_read_reg32(r); + value =3D tci_read_reg32(regs, r); } return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { - uint32_t low =3D tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low =3D tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint64_t value; TCGReg r =3D **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i64(tb_ptr); } else { - value =3D tci_read_reg64(r); + value =3D tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret =3D 0; =20 - tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D sp_value; tci_assert(tb_ptr); =20 for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(&tb_ptr); + t0 =3D tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ =20 case INDEX_op_ld8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i32: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_r32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_ri32(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_add2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 +=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 +=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 -=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 -=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(&tb_ptr); - tmp64 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 =3D tci_read_r32(regs, &tb_ptr); + tmp64 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ =20 case INDEX_op_ld8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i64: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st32_i64: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_r64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_ri64(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,50 +1039,50 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ @@ -1097,7 +1103,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1127,14 +1133,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 =3D *tb_ptr++; if (TCG_TARGET_REG_BITS =3D=3D 32) { t1 =3D *tb_ptr++; } - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1176,14 +1182,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1206,8 +1212,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 17/23] tcg: take .helpers out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 -- tcg/tcg.c | 10 +++++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 25662c36d4..b2d42e3136 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,8 +656,6 @@ struct TCGContext { =20 tcg_insn_unit *code_ptr; =20 - GHashTable *helpers; - #ifdef CONFIG_PROFILER /* profiling info */ int64_t tb_count1; diff --git a/tcg/tcg.c b/tcg/tcg.c index a874bdd41f..ee60798438 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -318,6 +318,7 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; +static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -328,7 +329,6 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; - GHashTable *helper_table; =20 memset(s, 0, sizeof(*s)); s->nb_globals =3D 0; @@ -356,7 +356,7 @@ void tcg_context_init(TCGContext *s) =20 /* Register helpers. */ /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - s->helpers =3D helper_table =3D g_hash_table_new(NULL, NULL); + helper_table =3D g_hash_table_new(NULL, NULL); =20 for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, @@ -982,7 +982,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg re= t, unsigned sizemask, flags; TCGHelperInfo *info; =20 - info =3D g_hash_table_lookup(s->helpers, (gpointer)func); + info =3D g_hash_table_lookup(helper_table, (gpointer)func); flags =3D info->flags; sizemask =3D info->sizemask; =20 @@ -1211,8 +1211,8 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char = *buf, static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret =3D NULL; - if (s->helpers) { - TCGHelperInfo *info =3D g_hash_table_lookup(s->helpers, (gpointer)= val); + if (helper_table) { + TCGHelperInfo *info =3D g_hash_table_lookup(helper_table, (gpointe= r)val); if (info) { ret =3D info->name; } --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597652750288.76652309139774; Mon, 9 Oct 2017 18:07:32 -0700 (PDT) Received: from localhost ([::1]:60529 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j14-0002Lv-SC for importer@patchew.org; Mon, 09 Oct 2017 21:07:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqV-0002UP-Pt for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqS-0004ZP-LS for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:31 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:43663) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqS-0004Yy-7n for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:28 -0400 Received: by mail-pf0-x234.google.com with SMTP id d2so12283331pfh.0 for ; Mon, 09 Oct 2017 17:56:28 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 18/23] tcg: allocate optimizer temps with tcg_malloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. While at it, also allocate temps_used directly as a bitmap of the required size, instead of using a bitmap of TCG_MAX_TEMPS via TCGTempSet. Performance-wise we lose about 1.12% in a translation-heavy workload such as booting+shutting down debian-arm: Performance counter stats for 'taskset -c 0 arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Ddie-on-boot.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): exec time (s) Relative slowdown wrt original (%) Suggested-by: Richard Henderson --------------------------------------------------------------- original 20.213321616 0. tcg_malloc 20.441130078 1.1270214 TCGContext 20.477846517 1.3086662 g_malloc 20.780527895 2.8061013 The other two alternatives shown in the table are: - TCGContext: embed temps[TCG_MAX_TEMPS] and TCGTempSet used_temps in TCGContext. This is simple enough but it isn't faster than using tcg_malloc; moreover, it wastes memory. - g_malloc: allocate/deallocate both temps and used_temps every time tcg_optimize is executed. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/optimize.c | 306 ++++++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 161 insertions(+), 145 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index adfc56ce62..ce422e9ff0 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -40,21 +40,18 @@ struct tcg_temp_info { tcg_target_ulong mask; }; =20 -static struct tcg_temp_info temps[TCG_MAX_TEMPS]; -static TCGTempSet temps_used; - -static inline bool temp_is_const(TCGArg arg) +static inline bool temp_is_const(const struct tcg_temp_info *temps, TCGArg= arg) { return temps[arg].is_const; } =20 -static inline bool temp_is_copy(TCGArg arg) +static inline bool temp_is_copy(const struct tcg_temp_info *temps, TCGArg = arg) { return temps[arg].next_copy !=3D arg; } =20 /* Reset TEMP's state, possibly removing the temp for the list of copies. = */ -static void reset_temp(TCGArg temp) +static void reset_temp(struct tcg_temp_info *temps, TCGArg temp) { temps[temps[temp].next_copy].prev_copy =3D temps[temp].prev_copy; temps[temps[temp].prev_copy].next_copy =3D temps[temp].next_copy; @@ -64,21 +61,16 @@ static void reset_temp(TCGArg temp) temps[temp].mask =3D -1; } =20 -/* Reset all temporaries, given that there are NB_TEMPS of them. */ -static void reset_all_temps(int nb_temps) -{ - bitmap_zero(temps_used.l, nb_temps); -} - /* Initialize and activate a temporary. */ -static void init_temp_info(TCGArg temp) +static void init_temp_info(struct tcg_temp_info *temps, + unsigned long *temps_used, TCGArg temp) { - if (!test_bit(temp, temps_used.l)) { + if (!test_bit(temp, temps_used)) { temps[temp].next_copy =3D temp; temps[temp].prev_copy =3D temp; temps[temp].is_const =3D false; temps[temp].mask =3D -1; - set_bit(temp, temps_used.l); + set_bit(temp, temps_used); } } =20 @@ -116,7 +108,8 @@ static TCGOpcode op_to_movi(TCGOpcode op) } } =20 -static TCGArg find_better_copy(TCGContext *s, TCGArg temp) +static TCGArg find_better_copy(TCGContext *s, const struct tcg_temp_info *= temps, + TCGArg temp) { TCGArg i; =20 @@ -145,7 +138,8 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg te= mp) return temp; } =20 -static bool temps_are_copies(TCGArg arg1, TCGArg arg2) +static bool temps_are_copies(const struct tcg_temp_info *temps, TCGArg arg= 1, + TCGArg arg2) { TCGArg i; =20 @@ -153,7 +147,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return true; } =20 - if (!temp_is_copy(arg1) || !temp_is_copy(arg2)) { + if (!temp_is_copy(temps, arg1) || !temp_is_copy(temps, arg2)) { return false; } =20 @@ -166,15 +160,15 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return false; } =20 -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg v= al) { TCGOpcode new_op =3D op_to_movi(op->opc); tcg_target_ulong mask; =20 op->opc =3D new_op; =20 - reset_temp(dst); + reset_temp(temps, dst); temps[dst].is_const =3D true; temps[dst].val =3D val; mask =3D val; @@ -188,10 +182,10 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op= , TCGArg *args, args[1] =3D val; } =20 -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg src) +static void tcg_opt_gen_mov(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg sr= c) { - if (temps_are_copies(dst, src)) { + if (temps_are_copies(temps, dst, src)) { tcg_op_remove(s, op); return; } @@ -201,7 +195,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T= CGArg *args, =20 op->opc =3D new_op; =20 - reset_temp(dst); + reset_temp(temps, dst); mask =3D temps[src].mask; if (TCG_TARGET_REG_BITS > 32 && new_op =3D=3D INDEX_op_mov_i32) { /* High bits of the destination are now garbage. */ @@ -463,10 +457,11 @@ static bool do_constant_folding_cond_eq(TCGCond c) =20 /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, - TCGArg y, TCGCond c) +static TCGArg +do_constant_folding_cond(const struct tcg_temp_info *temps, TCGOpcode op, + TCGArg x, TCGArg y, TCGCond c) { - if (temp_is_const(x) && temp_is_const(y)) { + if (temp_is_const(temps, x) && temp_is_const(temps, y)) { switch (op_bits(op)) { case 32: return do_constant_folding_cond_32(temps[x].val, temps[y].val,= c); @@ -475,9 +470,9 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TC= GArg x, default: tcg_abort(); } - } else if (temps_are_copies(x, y)) { + } else if (temps_are_copies(temps, x, y)) { return do_constant_folding_cond_eq(c); - } else if (temp_is_const(y) && temps[y].val =3D=3D 0) { + } else if (temp_is_const(temps, y) && temps[y].val =3D=3D 0) { switch (c) { case TCG_COND_LTU: return 0; @@ -492,15 +487,17 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, = TCGArg x, =20 /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) +static TCGArg +do_constant_folding_cond2(const struct tcg_temp_info *temps, TCGArg *p1, + TCGArg *p2, TCGCond c) { TCGArg al =3D p1[0], ah =3D p1[1]; TCGArg bl =3D p2[0], bh =3D p2[1]; =20 - if (temp_is_const(bl) && temp_is_const(bh)) { + if (temp_is_const(temps, bl) && temp_is_const(temps, bh)) { uint64_t b =3D ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[b= l].val; =20 - if (temp_is_const(al) && temp_is_const(ah)) { + if (temp_is_const(temps, al) && temp_is_const(temps, ah)) { uint64_t a; a =3D ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].va= l; return do_constant_folding_cond_64(a, b, c); @@ -516,18 +513,19 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, T= CGArg *p2, TCGCond c) } } } - if (temps_are_copies(al, bl) && temps_are_copies(ah, bh)) { + if (temps_are_copies(temps, al, bl) && temps_are_copies(temps, ah, bh)= ) { return do_constant_folding_cond_eq(c); } return 2; } =20 -static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) +static bool swap_commutative(const struct tcg_temp_info *temps, TCGArg des= t, + TCGArg *p1, TCGArg *p2) { TCGArg a1 =3D *p1, a2 =3D *p2; int sum =3D 0; - sum +=3D temp_is_const(a1); - sum -=3D temp_is_const(a2); + sum +=3D temp_is_const(temps, a1); + sum -=3D temp_is_const(temps, a2); =20 /* Prefer the constant in second argument, and then the form op a, a, b, which is better handled on non-RISC hosts. */ @@ -539,13 +537,14 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1,= TCGArg *p2) return false; } =20 -static bool swap_commutative2(TCGArg *p1, TCGArg *p2) +static bool swap_commutative2(const struct tcg_temp_info *temps, TCGArg *p= 1, + TCGArg *p2) { int sum =3D 0; - sum +=3D temp_is_const(p1[0]); - sum +=3D temp_is_const(p1[1]); - sum -=3D temp_is_const(p2[0]); - sum -=3D temp_is_const(p2[1]); + sum +=3D temp_is_const(temps, p1[0]); + sum +=3D temp_is_const(temps, p1[1]); + sum -=3D temp_is_const(temps, p2[0]); + sum -=3D temp_is_const(temps, p2[1]); if (sum > 0) { TCGArg t; t =3D p1[0], p1[0] =3D p2[0], p2[0] =3D t; @@ -558,6 +557,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { + struct tcg_temp_info *temps; + unsigned long *temps_used; int oi, oi_next, nb_temps, nb_globals; TCGArg *prev_mb_args =3D NULL; =20 @@ -568,7 +569,9 @@ void tcg_optimize(TCGContext *s) =20 nb_temps =3D s->nb_temps; nb_globals =3D s->nb_globals; - reset_all_temps(nb_temps); + temps =3D tcg_malloc(nb_temps * sizeof(*temps)); + temps_used =3D tcg_malloc(BITS_TO_LONGS(nb_temps) * sizeof(*temps_used= )); + bitmap_zero(temps_used, nb_temps); =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { tcg_target_ulong mask, partmask, affected; @@ -590,21 +593,21 @@ void tcg_optimize(TCGContext *s) for (i =3D 0; i < nb_oargs + nb_iargs; i++) { tmp =3D args[i]; if (tmp !=3D TCG_CALL_DUMMY_ARG) { - init_temp_info(tmp); + init_temp_info(temps, temps_used, tmp); } } } else { nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - init_temp_info(args[i]); + init_temp_info(temps, temps_used, args[i]); } } =20 /* Do copy propagation */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - if (temp_is_copy(args[i])) { - args[i] =3D find_better_copy(s, args[i]); + if (temp_is_copy(temps, args[i])) { + args[i] =3D find_better_copy(s, temps, args[i]); } } =20 @@ -620,44 +623,44 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(nor): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - swap_commutative(args[0], &args[1], &args[2]); + swap_commutative(temps, args[0], &args[1], &args[2]); break; CASE_OP_32_64(brcond): - if (swap_commutative(-1, &args[0], &args[1])) { + if (swap_commutative(temps, -1, &args[0], &args[1])) { args[2] =3D tcg_swap_cond(args[2]); } break; CASE_OP_32_64(setcond): - if (swap_commutative(args[0], &args[1], &args[2])) { + if (swap_commutative(temps, args[0], &args[1], &args[2])) { args[3] =3D tcg_swap_cond(args[3]); } break; CASE_OP_32_64(movcond): - if (swap_commutative(-1, &args[1], &args[2])) { + if (swap_commutative(temps, -1, &args[1], &args[2])) { args[5] =3D tcg_swap_cond(args[5]); } /* For movcond, we canonicalize the "false" input reg to match the destination reg so that the tcg backend can implement a "move if true" operation. */ - if (swap_commutative(args[0], &args[4], &args[3])) { + if (swap_commutative(temps, args[0], &args[4], &args[3])) { args[5] =3D tcg_invert_cond(args[5]); } break; CASE_OP_32_64(add2): - swap_commutative(args[0], &args[2], &args[4]); - swap_commutative(args[1], &args[3], &args[5]); + swap_commutative(temps, args[0], &args[2], &args[4]); + swap_commutative(temps, args[1], &args[3], &args[5]); break; CASE_OP_32_64(mulu2): CASE_OP_32_64(muls2): - swap_commutative(args[0], &args[2], &args[3]); + swap_commutative(temps, args[0], &args[2], &args[3]); break; case INDEX_op_brcond2_i32: - if (swap_commutative2(&args[0], &args[2])) { + if (swap_commutative2(temps, &args[0], &args[2])) { args[4] =3D tcg_swap_cond(args[4]); } break; case INDEX_op_setcond2_i32: - if (swap_commutative2(&args[1], &args[3])) { + if (swap_commutative2(temps, &args[1], &args[3])) { args[5] =3D tcg_swap_cond(args[5]); } break; @@ -673,8 +676,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(sar): CASE_OP_32_64(rotl): CASE_OP_32_64(rotr): - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temp_is_const(temps, args[1]) && temps[args[1]].val =3D=3D= 0) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -683,7 +686,7 @@ void tcg_optimize(TCGContext *s) TCGOpcode neg_op; bool have_neg; =20 - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { /* Proceed with possible constant folding. */ break; } @@ -697,9 +700,9 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0)= { + if (temp_is_const(temps, args[1]) && temps[args[1]].val = =3D=3D 0) { op->opc =3D neg_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] =3D args[2]; continue; } @@ -707,30 +710,30 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(xor): CASE_OP_32_64(nand): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D -1) { i =3D 1; goto try_not; } break; CASE_OP_32_64(nor): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0) { i =3D 1; goto try_not; } break; CASE_OP_32_64(andc): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D -1)= { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val =3D= =3D -1) { i =3D 2; goto try_not; } break; CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val =3D= =3D 0) { i =3D 2; goto try_not; } @@ -751,7 +754,7 @@ void tcg_optimize(TCGContext *s) break; } op->opc =3D not_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] =3D args[i]; continue; } @@ -771,18 +774,18 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(or): CASE_OP_32_64(xor): CASE_OP_32_64(andc): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; CASE_OP_32_64(and): CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D -1) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -819,7 +822,7 @@ void tcg_optimize(TCGContext *s) =20 CASE_OP_32_64(and): mask =3D temps[args[2]].mask; - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { and_const: affected =3D temps[args[1]].mask & ~mask; } @@ -838,7 +841,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless args[2] is constant, we can't infer anything from it. */ - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { mask =3D ~temps[args[2]].mask; goto and_const; } @@ -847,26 +850,26 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_sar_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 31; mask =3D (int32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_sar_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 63; mask =3D (int64_t)temps[args[1]].mask >> tmp; } break; =20 case INDEX_op_shr_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 31; mask =3D (uint32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_shr_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 63; mask =3D (uint64_t)temps[args[1]].mask >> tmp; } @@ -880,7 +883,7 @@ void tcg_optimize(TCGContext *s) break; =20 CASE_OP_32_64(shl): - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & (TCG_TARGET_REG_BITS - 1); mask =3D temps[args[1]].mask << tmp; } @@ -976,12 +979,12 @@ void tcg_optimize(TCGContext *s) =20 if (partmask =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_movi(s, op, args, args[0], 0); + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } if (affected =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } =20 @@ -991,8 +994,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mul): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - if ((temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0)) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if ((temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0)) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1004,8 +1007,8 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64(or): CASE_OP_32_64(and): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -1018,8 +1021,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): CASE_OP_32_64(sub): CASE_OP_32_64(xor): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1032,10 +1035,10 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64(mov): - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); break; CASE_OP_32_64(movi): - tcg_opt_gen_movi(s, op, args, args[0], args[1]); + tcg_opt_gen_movi(s, temps, op, args, args[0], args[1]); break; =20 CASE_OP_32_64(not): @@ -1051,9 +1054,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D do_constant_folding(opc, temps[args[1]].val, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; @@ -1080,66 +1083,70 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): CASE_OP_32_64(rem): CASE_OP_32_64(remu): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp =3D do_constant_folding(opc, temps[args[1]].val, temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(clz): CASE_OP_32_64(ctz): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { TCGArg v =3D temps[args[1]].val; if (v !=3D 0) { tmp =3D do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else { - tcg_opt_gen_mov(s, op, args, args[0], args[2]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[2]); } break; } goto do_default; =20 CASE_OP_32_64(deposit): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp =3D deposit64(temps[args[1]].val, args[3], args[4], temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(extract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D extract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(sextract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D sextract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(setcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[3= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[1], args[2], + args[3]); if (tmp !=3D 2) { - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(brcond): - tmp =3D do_constant_folding_cond(opc, args[0], args[1], args[2= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[0], args[1], + args[2]); if (tmp !=3D 2) { if (tmp) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_br; args[0] =3D args[3]; } else { @@ -1150,12 +1157,14 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 CASE_OP_32_64(movcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[5= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[1], args[2], + args[5]); if (tmp !=3D 2) { - tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[4 - tmp]= ); break; } - if (temp_is_const(args[3]) && temp_is_const(args[4])) { + if (temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4])) { tcg_target_ulong tv =3D temps[args[3]].val; tcg_target_ulong fv =3D temps[args[4]].val; TCGCond cond =3D args[5]; @@ -1174,8 +1183,10 @@ void tcg_optimize(TCGContext *s) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3]) - && temp_is_const(args[4]) && temp_is_const(args[5])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4]) && + temp_is_const(temps, args[5])) { uint32_t al =3D temps[args[2]].val; uint32_t ah =3D temps[args[3]].val; uint32_t bl =3D temps[args[4]].val; @@ -1194,8 +1205,8 @@ void tcg_optimize(TCGContext *s) =20 rl =3D args[0]; rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)a); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(a >> = 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1204,7 +1215,8 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_mulu2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3])) { uint32_t a =3D temps[args[2]].val; uint32_t b =3D temps[args[3]].val; uint64_t r =3D (uint64_t)a * b; @@ -1214,8 +1226,8 @@ void tcg_optimize(TCGContext *s) =20 rl =3D args[0]; rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)r); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(r >> = 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1224,11 +1236,11 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_brcond2_i32: - tmp =3D do_constant_folding_cond2(&args[0], &args[2], args[4]); + tmp =3D do_constant_folding_cond2(temps, &args[0], &args[2], a= rgs[4]); if (tmp !=3D 2) { if (tmp) { do_brcond_true: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_br; args[0] =3D args[5]; } else { @@ -1236,12 +1248,14 @@ void tcg_optimize(TCGContext *s) tcg_op_remove(s, op); } } else if ((args[4] =3D=3D TCG_COND_LT || args[4] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[2]) && temps[args[2]].val =3D= =3D 0 - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0) { + && temp_is_const(temps, args[2]) + && temps[args[2]].val =3D=3D 0 + && temp_is_const(temps, args[3]) + && temps[args[3]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_brcond_i32; args[0] =3D args[1]; args[1] =3D args[3]; @@ -1250,14 +1264,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[0], args[2], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_brcond_false; } else if (tmp =3D=3D 1) { goto do_brcond_high; } - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[1], args[3], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_brcond_false; @@ -1265,7 +1279,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_brcond_i32; args[1] =3D args[2]; args[2] =3D args[4]; @@ -1273,14 +1287,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[0], args[2], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_brcond_high; } else if (tmp =3D=3D 1) { goto do_brcond_true; } - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[1], args[3], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_brcond_low; @@ -1294,17 +1308,19 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_setcond2_i32: - tmp =3D do_constant_folding_cond2(&args[1], &args[3], args[5]); + tmp =3D do_constant_folding_cond2(temps, &args[1], &args[3], a= rgs[5]); if (tmp !=3D 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else if ((args[5] =3D=3D TCG_COND_LT || args[5] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0 - && temp_is_const(args[4]) && temps[args[4]].val =3D= =3D 0) { + && temp_is_const(temps, args[3]) + && temps[args[3]].val =3D=3D 0 + && temp_is_const(temps, args[4]) + && temps[args[4]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; args[1] =3D args[2]; @@ -1313,14 +1329,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[1], args[3], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_setcond_const; } else if (tmp =3D=3D 1) { goto do_setcond_high; } - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[2], args[4], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_setcond_high; @@ -1328,7 +1344,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_setcond_low: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; args[2] =3D args[3]; @@ -1336,14 +1352,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[1], args[3], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_setcond_high; } else if (tmp =3D=3D 1) { goto do_setcond_const; } - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[2], args[4], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_setcond_low; @@ -1360,8 +1376,8 @@ void tcg_optimize(TCGContext *s) if (!(args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS)= )) { for (i =3D 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { - reset_temp(i); + if (test_bit(i, temps_used)) { + reset_temp(temps, i); } } } @@ -1375,11 +1391,11 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); } else { do_reset_output: for (i =3D 0; i < nb_oargs; i++) { - reset_temp(args[i]); + reset_temp(temps, args[i]); /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). = */ if (i =3D=3D 0) { --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597846642259.8758778199617; Mon, 9 Oct 2017 18:10:46 -0700 (PDT) Received: from localhost ([::1]:60541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j3p-0004QI-BL for importer@patchew.org; Mon, 09 Oct 2017 21:10:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqU-0002Su-9F for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqT-0004Zg-8W for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:30 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:54345) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqT-0004ZL-1o for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:29 -0400 Received: by mail-pf0-x235.google.com with SMTP id m28so10542062pfi.11 for ; Mon, 09 Oct 2017 17:56:28 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LEPSQBFcHMdI/3CokXPsBH3v71WBctmmqRbtmcTyRnc=; b=WQLCa5OO6AMfL1N8P81y/5OglHoVjpVrDeOCeA395OJ0/1q4gpC9UWBH/dpXs01KLu jULxX+BRHx92lGHbFN3nEpqkbm5wTYj6O5f58Aqg5bndPQp9QXrRm+8Dc4Hp6eL6jOpr MHAvyWQpDTt+yffZn2yfj+g1dNpZX7FCiYjfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LEPSQBFcHMdI/3CokXPsBH3v71WBctmmqRbtmcTyRnc=; b=QOVvu0vP+J3QAnH42EKw6cVPdDxQrQv3tIstta4HN0VosxbvcKMvJHhbAuXbX4hsTj /l8Hh9JCITnqrGEnw3jUXGzZ3tO/xIwy++yTMWkP6+wDb+IgxKrQrjl83/O+mWnOSzXL Nv0mlGiarh7pyXvs8vyjYXTp5JLv3DlvhgQ6SQcDHp2QT8k4tjllO0AvkHY7mTi6ESyk rC9IMqEgUKzOYO+ieWooB6vVXwwWqPqH4Hrubs5hHbgXs+GixQ0EcwjtFxRkj7E+NvLu pfUNaGB6Rk51iHcC0WoIILLKhXWV0M5qZ6ZF6H3Y+otQJvfJCaPDRqDuKM8AckcT1MeN VnkQ== X-Gm-Message-State: AMCzsaXUKjvIoF9VE8nVD2lBdyjscFkJJic4Xu+NgaNeYw1CltHs9ziA lJFHgbRvsWKi+BD+cDEA9SBlI+T57L4= X-Google-Smtp-Source: AOwi7QBn6Zh859fxupPTQPVYzITiZmk5ethOJAHiCn+VjIL0ZhDuAgHjBWqLP0gKPHezioIwoIfskA== X-Received: by 10.99.63.199 with SMTP id m190mr10278633pga.273.1507596987730; Mon, 09 Oct 2017 17:56:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:56 -0700 Message-Id: <20171010005600.28735-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 19/23] util: move qemu_real_host_page_size/mask to osdep.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. While at it, query the host during an init constructor, which guarantees the page size will be well-defined throughout the execution of the program. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 6 ++++++ exec.c | 4 ---- util/pagesize.c | 18 ++++++++++++++++++ util/Makefile.objs | 1 + 5 files changed, 25 insertions(+), 6 deletions(-) create mode 100644 util/pagesize.c diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5654..778031c3d7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -229,8 +229,6 @@ extern int target_page_bits; /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ -extern uintptr_t qemu_real_host_page_size; -extern intptr_t qemu_real_host_page_mask; extern uintptr_t qemu_host_page_size; extern intptr_t qemu_host_page_mask; =20 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 9dd318a7dd..826650c58a 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -505,6 +505,12 @@ char *qemu_get_pid_name(pid_t pid); */ pid_t qemu_fork(Error **errp); =20 +/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even + * when intptr_t is 32-bit and we are aligning a long long. + */ +extern uintptr_t qemu_real_host_page_size; +extern intptr_t qemu_real_host_page_mask; + extern int qemu_icache_linesize; extern int qemu_dcache_linesize; =20 diff --git a/exec.c b/exec.c index 7a80460725..6378714a2b 100644 --- a/exec.c +++ b/exec.c @@ -120,8 +120,6 @@ int use_icount; =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; -uintptr_t qemu_real_host_page_size; -intptr_t qemu_real_host_page_mask; =20 bool set_preferred_target_page_bits(int bits) { @@ -3606,8 +3604,6 @@ void page_size_init(void) { /* NOTE: we can always suppose that qemu_host_page_size >=3D TARGET_PAGE_SIZE */ - qemu_real_host_page_size =3D getpagesize(); - qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; if (qemu_host_page_size =3D=3D 0) { qemu_host_page_size =3D qemu_real_host_page_size; } diff --git a/util/pagesize.c b/util/pagesize.c new file mode 100644 index 0000000000..998632cf6e --- /dev/null +++ b/util/pagesize.c @@ -0,0 +1,18 @@ +/* + * pagesize.c - query the host about its page size + * + * Copyright (C) 2017, Emilio G. Cota + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +uintptr_t qemu_real_host_page_size; +intptr_t qemu_real_host_page_mask; + +static void __attribute__((constructor)) init_real_host_page_size(void) +{ + qemu_real_host_page_size =3D getpagesize(); + qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; +} diff --git a/util/Makefile.objs b/util/Makefile.objs index 50a55ecc75..2973b0a323 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -40,6 +40,7 @@ util-obj-y +=3D buffer.o util-obj-y +=3D timed-average.o util-obj-y +=3D base64.o util-obj-y +=3D log.o +util-obj-y +=3D pagesize.o util-obj-y +=3D qdist.o util-obj-y +=3D qht.o util-obj-y +=3D range.o --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507598033686670.7368260788422; Mon, 9 Oct 2017 18:13:53 -0700 (PDT) Received: from localhost ([::1]:60558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j76-0006oA-9l for importer@patchew.org; Mon, 09 Oct 2017 21:13:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqV-0002Tv-9g for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqU-0004aV-Ig for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:31 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:50843) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqU-0004a0-Cv for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:30 -0400 Received: by mail-pf0-x233.google.com with SMTP id m63so15478329pfk.7 for ; Mon, 09 Oct 2017 17:56:30 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 20/23] osdep: introduce qemu_mprotect_rwx/none X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 2 ++ util/osdep.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 826650c58a..281782d526 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -371,6 +371,8 @@ void sigaction_invoke(struct sigaction *action, #endif =20 int qemu_madvise(void *addr, size_t len, int advice); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); =20 int qemu_open(const char *name, int flags, ...); int qemu_close(int fd); diff --git a/util/osdep.c b/util/osdep.c index a479fedc4a..0cf6d9944c 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -73,6 +73,47 @@ int qemu_madvise(void *addr, size_t len, int advice) #endif } =20 +static int qemu_mprotect__osdep(void *addr, size_t size, int prot) +{ + g_assert(!((uintptr_t)addr & ~qemu_real_host_page_mask)); + g_assert(!(size & ~qemu_real_host_page_mask)); + +#ifdef _WIN32 + DWORD old_protect; + + if (!VirtualProtect(addr, size, prot, &old_protect)) { + error_report("%s: VirtualProtect failed with error code %d", + __func__, GetLastError()); + return -1; + } + return 0; +#else + if (mprotect(addr, size, prot)) { + error_report("%s: mprotect failed: %s", __func__, strerror(errno)); + return -1; + } + return 0; +#endif +} + +int qemu_mprotect_rwx(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE); +#else + return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_= EXEC); +#endif +} + +int qemu_mprotect_none(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS); +#else + return qemu_mprotect__osdep(addr, size, PROT_NONE); +#endif +} + #ifndef _WIN32 =20 static int fcntl_op_setlk =3D -1; --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507597462234341.507044323189; Mon, 9 Oct 2017 18:04:22 -0700 (PDT) Received: from localhost ([::1]:60515 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1ixs-0008CK-Ei for importer@patchew.org; Mon, 09 Oct 2017 21:04:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqY-0002XF-HH for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqV-0004bM-Js for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:34 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:48100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqV-0004am-E7 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:31 -0400 Received: by mail-pf0-x235.google.com with SMTP id z11so5533583pfk.4 for ; Mon, 09 Oct 2017 17:56:31 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 21/23] translate-all: use qemu_protect_rwx/none helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" The helpers require the address and size to be page-aligned, so do that before calling them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 61 ++++++++++---------------------------------= ---- 1 file changed, 13 insertions(+), 48 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5ce99d549..d5195a0f5a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -600,63 +600,24 @@ static inline void *split_cross_256mb(void *buf1, siz= e_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); =20 -# ifdef _WIN32 -static inline void do_protect(void *addr, long size, int prot) -{ - DWORD old_protect; - VirtualProtect(addr, size, prot, &old_protect); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PAGE_EXECUTE_READWRITE); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PAGE_NOACCESS); -} -# else -static inline void do_protect(void *addr, long size, int prot) -{ - uintptr_t start, end; - - start =3D (uintptr_t)addr; - start &=3D qemu_real_host_page_mask; - - end =3D (uintptr_t)addr + size; - end =3D ROUND_UP(end, qemu_real_host_page_size); - - mprotect((void *)start, end - start, prot); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PROT_NONE); -} -# endif /* WIN32 */ - static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; + void *end =3D static_code_gen_buffer + sizeof(static_code_gen_buffer); size_t full_size, size; =20 - /* The size of the buffer, rounded down to end on a page boundary. */ - full_size =3D (((uintptr_t)buf + sizeof(static_code_gen_buffer)) - & qemu_real_host_page_mask) - (uintptr_t)buf; + /* page-align the beginning and end of the buffer */ + buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + end =3D QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); =20 /* Reserve a guard page. */ + full_size =3D end - buf; size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx.code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) - & qemu_real_host_page_mask) - (uintptr_t)buf; + size =3D QEMU_ALIGN_DOWN(tcg_ctx.code_gen_buffer_size, + qemu_real_host_page_size); } tcg_ctx.code_gen_buffer_size =3D size; =20 @@ -667,8 +628,12 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - map_exec(buf, size); - map_none(buf + size, qemu_real_host_page_size); + if (qemu_mprotect_rwx(buf, size)) { + abort(); + } + if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { + abort(); + } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507598028641744.7194690470133; Mon, 9 Oct 2017 18:13:48 -0700 (PDT) Received: from localhost ([::1]:60557 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j75-0006nv-RZ for importer@patchew.org; Mon, 09 Oct 2017 21:13:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqY-0002XL-JC for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqW-0004c4-T5 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:34 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:57221) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqW-0004bg-Nn for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:32 -0400 Received: by mail-pf0-x235.google.com with SMTP id b85so4313257pfj.13 for ; Mon, 09 Oct 2017 17:56:32 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 22/23] tcg: define TCG_HIGHWATER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index ee60798438..4492e1eb3f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,6 +116,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static bool tcg_out_ldst_finalize(TCGContext *s); #endif =20 +#define TCG_HIGHWATER 1024 + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -430,7 +432,7 @@ void tcg_prologue_init(TCGContext *s) /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger than we expect the code generation for any one opcode to require. = */ - s->code_gen_highwater =3D s->code_gen_buffer + (total_size - 1024); + s->code_gen_highwater =3D s->code_gen_buffer + (total_size - TCG_HIGHW= ATER); =20 tcg_register_jit(s->code_gen_buffer, total_size); =20 --=20 2.13.6 From nobody Sat Apr 27 12:55:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507598109066255.5220944393584; Mon, 9 Oct 2017 18:15:09 -0700 (PDT) Received: from localhost ([::1]:60564 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1j8R-0007hN-DG for importer@patchew.org; Mon, 09 Oct 2017 21:15:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60700) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1iqe-0002bg-6U for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1iqd-0004kR-01 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:40 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:51779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e1iqc-0004jn-Qx for qemu-devel@nongnu.org; Mon, 09 Oct 2017 20:56:38 -0400 Received: by mail-pf0-x22b.google.com with SMTP id n14so13572864pfh.8 for ; Mon, 09 Oct 2017 17:56:38 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eyzCkAldlJhlOwbAcPTVemO41jvU8FeUPJW2c1/rJgo=; b=AsbCpM3VE1gYge+uFdvDJtO8bCzXFMQicQ6X8eEK5C/OvF4qv+q3CDiTY+GoBMuuZl I2fFzAPau9H6ORnIEiIBdCNOzbn7IW7BZMatYopD1EBL9xixDH8ebAcj7L9x/qhwOuCw T4+DdKnU8XiJESkAKwQuwUB5/ngZzMIzXpmEY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eyzCkAldlJhlOwbAcPTVemO41jvU8FeUPJW2c1/rJgo=; b=Qh8w2yeATXIR4bru4arOVe0cWSlR1Zdwv87hyUeA8rV0oxoRN5XVXyiWhf9ot7BQ4e I7Foz//uvyLkZ5Ynfsir1jD0X+bnmnxIWrG9Iun5D8t9+9Mhwfu8FxppZFeNmJ//d6yq 1cundwo5u28BS5NGfGc5oatHuGMtYy+tvnF5blYHj8yuyOX+iumbGkV7l+skKT1LRnua p+xge2b8G7d/Tu2dIEDf23TgW52p2XE72z4iYIFqnuU0o/G+wdSLcObHc3HBqQ8TBZB5 P3B+PS+n6LIDXP2pkmvfoBI+FPWz1wtAjA6VZtbLTuZUog2TGeJzAIQjmjsC9Z4S5usG +5xw== X-Gm-Message-State: AMCzsaU/9FdW+SPUHC+c+/reb5jk0eYZ8JOQ2UfpHtbMJ4HfSmlmlt92 mtVZ6chYCt1mL90qdzkkDt1Z7od7ghg= X-Google-Smtp-Source: AOwi7QAX17yHT0yxwTibgCwCMDp9oV0Fi6Lp14qAN2bLEME/bZia1JoMxzfPMjByk6Y1mdcUGk3fzw== X-Received: by 10.84.133.165 with SMTP id f34mr10524941plf.387.1507596992601; Mon, 09 Oct 2017 17:56:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:56:00 -0700 Message-Id: <20171010005600.28735-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 23/23] tcg/mips: delete commented out extern keyword. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Jiang Biao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jiang Biao Delete commented out extern keyword on link_error(). Signed-off-by: Jiang Biao Message-Id: <1506762042-32145-1-git-send-email-jiang.biao2@zte.com.cn> Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index e993138930..4b55ab8856 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -36,7 +36,7 @@ #else /* To assert at compile-time that these values are never used for TCG_TARGET_REG_BITS =3D=3D 64. */ -/* extern */ int link_error(void); +int link_error(void); # define LO_OFF link_error() # define HI_OFF link_error() #endif --=20 2.13.6