From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507142867387841.721334166754; Wed, 4 Oct 2017 11:47:47 -0700 (PDT) Received: from localhost ([::1]:36448 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzohs-00034T-MR for importer@patchew.org; Wed, 04 Oct 2017 14:47:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzodp-00088m-7m for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzodo-0002Yr-GR for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:33 -0400 Received: from mail-qt0-x230.google.com ([2607:f8b0:400d:c0d::230]:53434) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzodo-0002YP-Ci for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:32 -0400 Received: by mail-qt0-x230.google.com with SMTP id 47so21026278qts.10 for ; Wed, 04 Oct 2017 11:43:32 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2606:a000:7a4a:b100::1b]) by smtp.gmail.com with ESMTPSA id o64sm3020464ywe.12.2017.10.04.11.43.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 11:43:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i7Fh4Se9dhiIADl4uo+noxozSwwCiMMdLHubKWZEqJM=; b=DgGDMw5c3G0cm5BvurzIH6nzZS4GV6+pVnNdE2G5MOWPWuGkwSY7HItaP8kM5Wa132 jlxKXZJ3ztu0Nzr+TuZRDRloIGom/1ElmsnAvkMsx2p0lyDoUkcqH72AV4DUrO3Of8A/ JMmmQ8h0N38JvqyIuL5WAST3K5ipQxKCscj3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i7Fh4Se9dhiIADl4uo+noxozSwwCiMMdLHubKWZEqJM=; b=QpWQHrY7r7ZYHy0ciSHzAcPUPDr1/O1vI35q/FwFdWn1D9kcJNobsVtDFQNxR3KQqV 0NutHbdCSJ5etNZEXuUQT1Xi1udyDL28jouEHlkTH9OnZh1whZIYODBqtrIokyr6Uhla uHpdrWNaGbePK7ZYAE3y3+yuC/4/V4Kql+nyplOy0lm9E2eBF1MPG4VziaK63quEpsX2 OEA8+ynmE1bCM0lHhQmpjfj0ljRGMv4fLi7cdWAaolMgow5LRc/DXo7Wme9F5JSiP20/ S+RSaY1ye45Udh+oRNII4dCiblIxfwHzDPUyM7VdZJpX7hn54foTA22kf8YyKVoNHBGe y1zg== X-Gm-Message-State: AMCzsaVN+acMOSDLRK65v2mdwXT9WmDYJxS+I2nQjG/HDyaKOAHKaPh7 MLLxk1dSNm8GIWeElFvvdGt+m8eDMAY= X-Google-Smtp-Source: AOwi7QCjK3NnwXwGEveZYyIahYPZdxmXIGlHJ+DUs4Pjnx42//F73W+MVseoRPoPZJsddc7WWYlAzw== X-Received: by 10.37.50.149 with SMTP id y143mr5024186yby.240.1507142611489; Wed, 04 Oct 2017 11:43:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:14 -0400 Message-Id: <20171004184325.24157-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::230 Subject: [Qemu-devel] [PATCH v1 01/12] HACK: use objdump disas X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" --- disas.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas.c b/disas.c index d6a1eb9c8e..69069a85ca 100644 --- a/disas.c +++ b/disas.c @@ -231,7 +231,7 @@ void target_disas(FILE *out, CPUState *cpu, target_ulon= g code, s.info.disassembler_options =3D (char *)"any"; s.info.print_insn =3D print_insn_ppc; #endif - if (s.info.print_insn =3D=3D NULL) { + if (1 || s.info.print_insn =3D=3D NULL) { s.info.print_insn =3D print_insn_od_target; } =20 --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507142746452779.5539126881833; Wed, 4 Oct 2017 11:45:46 -0700 (PDT) Received: from localhost ([::1]:36434 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzofg-0000zC-Lr for importer@patchew.org; Wed, 04 Oct 2017 14:45:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzodq-00089k-LT for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzodp-0002cD-Nf for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:34 -0400 Received: from mail-qt0-x233.google.com ([2607:f8b0:400d:c0d::233]:43756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzodp-0002bg-JI for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:33 -0400 Received: by mail-qt0-x233.google.com with SMTP id a43so15130923qta.0 for ; Wed, 04 Oct 2017 11:43:33 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2606:a000:7a4a:b100::1b]) by smtp.gmail.com with ESMTPSA id o64sm3020464ywe.12.2017.10.04.11.43.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 11:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3scm5MUW7GUgyfh34S1Vo3Ln+aBGgTxbTJqlG1RMo0Y=; b=hyFNsxdM7mv8C6EQ6USs0ULOxFGlpM0Bfq5kObLwQIFSzFHItPTPIW//y7xbVHvfY0 ucY16HvBwtJ85Cc7ynGtlrork8dWciqtrb18XgisA/xUaijCgY5i9mNk/jUvvvtaeBVO SXE0ckYntDUbQmLrrwtO5o3gZfqus0bbgiHqg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3scm5MUW7GUgyfh34S1Vo3Ln+aBGgTxbTJqlG1RMo0Y=; b=VmQDdvj+7fHUeUKwNNPqpwH4+cXJyLlvXHl3IZYn+XqDz7X+1RcxX3O0c5IXjl6nUn TaNeNHIXvyv3U0zs8dW0ava4BH1gD93wHpiQBy1/MECub9KqrCsCRqM/fdSxJzCiEZax RRo2t5DrGB1m9vzBVQE4n8/NwkKbKeu25r7PyQCcwO3ScSQZdOMgKpsPbackl0L/IDtj Hl5ijtko4SI7ZUxpY/NofYn/aPr/JQVteHrCcgcub5aErPh1b51Z0BFFitcbB3ZvDdM1 BsNHAboRFNm/3FTK39B999wg2DeVO7nH0sMeSj6tuCezPhMu+msHq2NlBBr+s6Q5qQzK a69g== X-Gm-Message-State: AMCzsaVjul+/jrEidcJbBd+2d2roEdOp9GIBbCoE3/jz+2utnbvSnuDz +wfZPd3I8zJhIvy0objhMJtIKjSEVLY= X-Google-Smtp-Source: AOwi7QBOmZpQdNFyhwtv9boN0+r822rs9ZmA9MSjTfjzmQFlNyoGdHctkdEjchh9mcC6qdpS06yufQ== X-Received: by 10.37.194.130 with SMTP id s124mr4787132ybf.271.1507142612679; Wed, 04 Oct 2017 11:43:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:15 -0400 Message-Id: <20171004184325.24157-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::233 Subject: [Qemu-devel] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 1 + linux-user/elfload.c | 9 +++++++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 4 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 69cb49acc3..c5c9cef834 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1312,6 +1312,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 79062882ba..003d9420b7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,14 @@ enum { ARM_HWCAP_A64_SHA1 =3D 1 << 5, ARM_HWCAP_A64_SHA2 =3D 1 << 6, ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +540,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4300de66e2..276c996e9f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1603,6 +1603,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); cpu->midr =3D 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..b05c904ad2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ } --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 04 Oct 2017 11:43:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:16 -0400 Message-Id: <20171004184325.24157-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::234 Subject: [Qemu-devel] [PATCH v1 03/12] target/arm: Decode aa64 armv8.1 scalar three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++ target/arm/advsimd_helper.c | 105 ++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 90 +++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 2 +- 4 files changed, 200 insertions(+), 1 deletion(-) create mode 100644 target/arm/advsimd_helper.c diff --git a/target/arm/helper.h b/target/arm/helper.h index 64afbac59f..ec098d8337 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -350,8 +350,12 @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i= 32, i32) =20 DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) =20 DEF_HELPER_1(neon_narrow_u8, i32, i64) DEF_HELPER_1(neon_narrow_u16, i32, i64) diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c new file mode 100644 index 0000000000..583c2b0dce --- /dev/null +++ b/target/arm/advsimd_helper.c @@ -0,0 +1,105 @@ +/* + * ARM AdvSIMD Vector Operations + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q + +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Simplify: + * =3D ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 + * =3D ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret =3D (int32_t)src1 * src2; + ret =3D ((int32_t)src3 << 15) + ret + (1 << 14); + ret >>=3D 15; + if (ret !=3D (int16_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 =3D inl_qrdmlah_s16(env, src1, src2, src3); + uint16_t e2 =3D inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 1= 6); + return deposit32(e1, 16, 16, e2); +} + +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Similarly, using subtraction: + * =3D ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 + * =3D ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret =3D (int32_t)src1 * src2; + ret =3D ((int32_t)src3 << 15) - ret + (1 << 14); + ret >>=3D 15; + if (ret !=3D (int16_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 =3D inl_qrdmlsh_s16(env, src1, src2, src3); + uint16_t e2 =3D inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 1= 6); + return deposit32(e1, 16, 16, e2); +} + +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlah_s16 above. */ + int64_t ret =3D (int64_t)src1 * src2; + ret =3D ((int64_t)src3 << 31) + ret + (1 << 30); + ret >>=3D 31; + if (ret !=3D (int32_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlsh_s16 above. */ + int64_t ret =3D (int64_t)src1 * src2; + ret =3D ((int64_t)src3 << 31) - ret + (1 << 30); + ret >>=3D 31; + if (ret !=3D (int32_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a4380bbb15..182853e3bb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7596,6 +7596,95 @@ static void disas_simd_scalar_three_reg_same(DisasCo= ntext *s, uint32_t insn) tcg_temp_free_i64(tcg_rd); } =20 +/* AdvSIMD scalar three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, + uint32_t insn) +{ + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 4); + int rm =3D extract32(insn, 16, 5); + int size =3D extract32(insn, 22, 2); + bool u =3D extract32(insn, 29, 1); + TCGv_i32 ele1, ele2, ele3; + TCGv_i64 res; + int feature; + + if (!u) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + case 0x1: /* SQRDMLSH (vector) */ + if (size !=3D 1 && size !=3D 2) { + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_1_SIMD; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + /* Do a single operation on the lowest element in the vector. + * We use the standard Neon helpers and rely on 0 OP 0 =3D=3D 0 + * with no side effects for all these operations. + * OPTME: special-purpose helpers would avoid doing some + * unnecessary work in the helper for the 16 bit cases. + */ + ele1 =3D tcg_temp_new_i32(); + ele2 =3D tcg_temp_new_i32(); + ele3 =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, ele1, rn, 0, size); + read_vec_element_i32(s, ele2, rm, 0, size); + read_vec_element_i32(s, ele3, rd, 0, size); + + switch (opcode) { + case 0x0: /* SQRDMLAH */ + if (size =3D=3D 1) { + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + case 0x1: /* SQRDMLSH */ + if (size =3D=3D 1) { + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_i32(ele1); + tcg_temp_free_i32(ele2); + + res =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(res, ele3); + tcg_temp_free_i32(ele3); + + write_fp_dreg(s, rd, res); + tcg_temp_free_i64(res); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -11184,6 +11273,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, { 0x2e000000, 0xbf208400, disas_simd_ext }, { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 847fb52ee0..c2d32988f9 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64)= )) +=3D kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D neon_helper.o iwmmxt_helper.o +obj-y +=3D neon_helper.o iwmmxt_helper.o advsimd_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-y +=3D crypto_helper.o --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 04 Oct 2017 11:43:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:17 -0400 Message-Id: <20171004184325.24157-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::230 Subject: [Qemu-devel] [PATCH v1 04/12] target/arm: Decode aa64 armv8.1 three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 9 +++++ target/arm/advsimd_helper.c | 74 +++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 84 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 167 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index ec098d8337..67583b3c2e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -542,6 +542,15 @@ DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) =20 +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index 583c2b0dce..b0f4b02a12 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -26,6 +26,16 @@ =20 #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q =20 +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) +{ + uint64_t *d =3D vd + opr_sz; + uintptr_t i; + + for (i =3D opr_sz; i < max_sz; i +=3D 8) { + *d++ =3D 0; + } +} + static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) { @@ -51,6 +61,22 @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint= 32_t src1, return deposit32(e1, 16, 16, e2); } =20 +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd; + int16_t *n =3D vn; + int16_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 2; ++i) { + d[i] =3D inl_qrdmlah_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) { @@ -76,6 +102,22 @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uin= t32_t src1, return deposit32(e1, 16, 16, e2); } =20 +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd; + int16_t *n =3D vn; + int16_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 2; ++i) { + d[i] =3D inl_qrdmlsh_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) { @@ -90,6 +132,22 @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int= 32_t src1, return ret; } =20 +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int32_t *d =3D vd; + int32_t *n =3D vn; + int32_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 4; ++i) { + d[i] =3D helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) { @@ -103,3 +161,19 @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, in= t32_t src1, } return ret; } + +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int32_t *d =3D vd; + int32_t *n =3D vn; + int32_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 4; ++i) { + d[i] =3D helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 182853e3bb..0ea47a9dff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9874,6 +9874,89 @@ static void disas_simd_three_reg_same(DisasContext *= s, uint32_t insn) } } =20 +/* AdvSIMD three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) +{ + void (*fn_gvec_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 4); + int rm =3D extract32(insn, 16, 5); + int size =3D extract32(insn, 22, 2); + bool u =3D extract32(insn, 29, 1); + bool is_q =3D extract32(insn, 30, 1); + int feature; + + if (!u) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + case 0x1: /* SQRDMLSH (vector) */ + if (size !=3D 1 && size !=3D 2) { + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_1_SIMD; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s32; + break; + default: + g_assert_not_reached(); + } + goto do_env; + + case 0x1: /* SQRDMLSH (vector) */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s32; + break; + default: + g_assert_not_reached(); + } + do_env: + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), cpu_env, + is_q ? 16 : 8, vec_full_reg_size(s), + 0, fn_gvec_ptr); + break; + + default: + g_assert_not_reached(); + } +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11261,6 +11344,7 @@ static void disas_crypto_two_reg_sha(DisasContext *= s, uint32_t insn) static const AArch64DecodeTable data_proc_simd[] =3D { /* pattern , mask , fn */ { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 04 Oct 2017 11:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:18 -0400 Message-Id: <20171004184325.24157-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::232 Subject: [Qemu-devel] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0ea47a9dff..b02aad8cd7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10749,12 +10749,23 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) is_long =3D true; /* fall through */ case 0xc: /* SQDMULH */ - case 0xd: /* SQRDMULH */ if (u) { unallocated_encoding(s); return; } break; + case 0xd: /* SQRDMULH / SQRDMLAH */ + if (u && !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + unallocated_encoding(s); + return; + } + break; + case 0xf: /* SQRDMLSH */ + if (!u || !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + unallocated_encoding(s); + return; + } + break; case 0x8: /* MUL */ if (u || is_scalar) { unallocated_encoding(s); @@ -10941,13 +10952,36 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) tcg_op, tcg_idx); } break; - case 0xd: /* SQRDMULH */ + case 0xd: /* SQRDMULH / SQRDMLAH */ + if (u) { /* SQRDMLAH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + if (size =3D=3D 1) { + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_r= es); + } else { + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_r= es); + } + } else { /* SQRDMULH */ + if (size =3D=3D 1) { + gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, + tcg_op, tcg_idx); + } else { + gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, + tcg_op, tcg_idx); + } + } + break; + case 0xf: /* SQRDMLSH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); if (size =3D=3D 1) { - gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, - tcg_op, tcg_idx); + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); } else { - gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, - tcg_op, tcg_idx); + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); } break; default: --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507143052125892.4495074522513; Wed, 4 Oct 2017 11:50:52 -0700 (PDT) Received: from localhost ([::1]:36465 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzoki-0005eR-Qe for importer@patchew.org; Wed, 04 Oct 2017 14:50:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzodw-0008Ex-2l for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzodu-0002he-Tk for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:40 -0400 Received: from mail-qt0-x236.google.com ([2607:f8b0:400d:c0d::236]:53435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzodu-0002hN-Ov for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:38 -0400 Received: by mail-qt0-x236.google.com with SMTP id 47so21026891qts.10 for ; Wed, 04 Oct 2017 11:43:38 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2606:a000:7a4a:b100::1b]) by smtp.gmail.com with ESMTPSA id o64sm3020464ywe.12.2017.10.04.11.43.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 11:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uLy8QhtDCziYI/nYjPXu3/PQS6unxv5Zdb2dNvp2c0o=; b=kwtGUiA8j2rmES0l2qCTVqtT0+WsUG7ABW0LO7EdoPKyDxBMkOywMx8KsI8djPYtPt NzqCOKodywy1HtaXbbsUzSZ0YbjW5fk+REzYVzOl3fNHmSPQYSEIBCGmJF6RLKR3u0lU ULTQ1JBvyYgUC0oEniaN5CG6TqoDFDwd2S7Q8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uLy8QhtDCziYI/nYjPXu3/PQS6unxv5Zdb2dNvp2c0o=; b=a5Jpu+/fKEZXqs0ArpIQvOPt1Bv/kXc0xNSr6J8dREGws+lRZNTXrE6EF+9hkbB+Cn 0i4k3/AYQz2Tb+c+MJ+zmZGqM1xJoGPrKy6+4aPMZKAhbHIZ6mzxbV7GlVi/mhk02znD Du6SFoBsJUWipKhEoul7bV5PgsuTWP/3WfFdqzIKpJ+fsmHj1kRZ/BeKl1/HlP+edWEV vKDJ0WYnSQ5Huc06JXcUgDxdKTukBHp11VAxyru7E3fn7IrDkWl16qMN05EtHyWbNCYs 163cIdwqp1pijzn9aJwq9Lb/ur8TraWQPA5+AewsBs3ZEzdWrqAhF3BqLd7J4o0G4537 KzGA== X-Gm-Message-State: AMCzsaVy+HyHjIhSy1pNjQI33IEmkq67HwCVhJWIpskZ68OgwBWBKK4j ahO2yeonQKiwsfhKJxkIj2Vm6cMZ5mU= X-Google-Smtp-Source: AOwi7QDlbLKVVl294BjxL5jjIcgMX+5JZwCG+Txei/mVcPmTGF3TeLQV7qELrH2oupiG4QAZUklZnQ== X-Received: by 10.37.97.83 with SMTP id v80mr4635171ybb.449.1507142617880; Wed, 04 Oct 2017 11:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:19 -0400 Message-Id: <20171004184325.24157-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::236 Subject: [Qemu-devel] [PATCH v1 06/12] target/arm: Decode aa32 armv8.1 three same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 64 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ab1a12a1b8..0cd58710b3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -25,6 +25,7 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "qemu/bitops.h" #include "arm_ldst.h" @@ -5334,9 +5335,9 @@ static void gen_neon_narrow_op(int op, int u, int siz= e, #define NEON_3R_VPMAX 20 #define NEON_3R_VPMIN 21 #define NEON_3R_VQDMULH_VQRDMULH 22 -#define NEON_3R_VPADD 23 +#define NEON_3R_VPADD_VQRDMLAH 23 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS : float fused multiply-add */ #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ @@ -5368,9 +5369,9 @@ static const uint8_t neon_3r_sizes[] =3D { [NEON_3R_VPMAX] =3D 0x7, [NEON_3R_VPMIN] =3D 0x7, [NEON_3R_VQDMULH_VQRDMULH] =3D 0x6, - [NEON_3R_VPADD] =3D 0x7, + [NEON_3R_VPADD_VQRDMLAH] =3D 0x7, [NEON_3R_SHA] =3D 0xf, /* size field encodes op type */ - [NEON_3R_VFM] =3D 0x5, /* size bit 1 encodes op */ + [NEON_3R_VFM_VQRDMLSH] =3D 0x7, /* For VFM, size bit 1 encodes op */ [NEON_3R_FLOAT_ARITH] =3D 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_MULTIPLY] =3D 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_CMP] =3D 0x5, /* size bit 1 encodes op */ @@ -5556,6 +5557,7 @@ static const uint8_t neon_2rm_sizes[] =3D { =20 static int disas_neon_data_insn(DisasContext *s, uint32_t insn) { + void (*fn_gvec_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); int op; int q; int rd, rn, rm; @@ -5600,12 +5602,12 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) if (q && ((rd | rn | rm) & 1)) { return 1; } - /* - * The SHA-1/SHA-256 3-register instructions require special treat= ment - * here, as their size field is overloaded as an op type selector,= and - * they all consume their input in a single pass. - */ - if (op =3D=3D NEON_3R_SHA) { + switch (op) { + case NEON_3R_SHA: + /* The SHA-1/SHA-256 3-register instructions require special + * treatment here, as their size field is overloaded as an + * op type selector, and they all consume their input in a + * single pass. */ if (!q) { return 1; } @@ -5642,6 +5644,53 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp3); return 0; + + case NEON_3R_VPADD_VQRDMLAH: + if (!u) { + break; /* VPADD */ + } + /* VQRDMLAH */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s32; + break; + default: + return 1; + } + do_vqrdmlx: + if (arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + int opr_sz =3D (1 + q) * 8; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), cpu_env, + opr_sz, opr_sz, 0, fn_gvec_ptr); + return 0; + } + return 1; + + case NEON_3R_VFM_VQRDMLSH: + if (!u) { + /* VFM, VFMS */ + if ((5 & (1 << size)) =3D=3D 0) { + return 1; + } + break; + } + /* VQRDMLSH */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s32; + break; + default: + return 1; + } + goto do_vqrdmlx; } if (size =3D=3D 3 && op !=3D NEON_3R_LOGIC) { /* 64-bit element instructions. */ @@ -5727,11 +5776,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) rm =3D rtmp; } break; - case NEON_3R_VPADD: - if (u) { - return 1; - } - /* Fall through */ + case NEON_3R_VPADD_VQRDMLAH: case NEON_3R_VPMAX: case NEON_3R_VPMIN: pairwise =3D 1; @@ -5765,8 +5810,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) return 1; } break; - case NEON_3R_VFM: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { + case NEON_3R_VFM_VQRDMLSH: + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { return 1; } break; @@ -5963,7 +6008,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } } break; - case NEON_3R_VPADD: + case NEON_3R_VPADD_VQRDMLAH: switch (size) { case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; @@ -6062,7 +6107,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } } break; - case NEON_3R_VFM: + case NEON_3R_VFM_VQRDMLSH: { /* VFMA, VFMS: fused multiply-add */ TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 04 Oct 2017 11:43:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:20 -0400 Message-Id: <20171004184325.24157-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::22b Subject: [Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0cd58710b3..ee1e364fb5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6941,10 +6941,42 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } neon_store_reg64(cpu_V0, rd + pass); } + break; + case 14: /* VQRDMLAH scalar */ + case 15: /* VQRDMLSH scalar */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + return 1; + } + if (u && ((rd | rn) & 1)) { + return 1; + } + tmp2 =3D neon_get_scalar(size, rm); + for (pass =3D 0; pass < (u ? 4 : 2); pass++) { + void (*fn)(TCGv_i32, TCGv_env, TCGv_i32, + TCGv_i32, TCGv_i32); =20 - + tmp =3D neon_load_reg(rn, pass); + tmp3 =3D neon_load_reg(rd, pass); + if (op =3D=3D 14) { + if (size =3D=3D 1) { + fn =3D gen_helper_neon_qrdmlah_s16; + } else { + fn =3D gen_helper_neon_qrdmlah_s32; + } + } else { + if (size =3D=3D 1) { + fn =3D gen_helper_neon_qrdmlsh_s16; + } else { + fn =3D gen_helper_neon_qrdmlsh_s32; + } + } + fn(tmp, cpu_env, tmp, tmp2, tmp3); + tcg_temp_free_i32(tmp3); + neon_store_reg(rd, pass, tmp); + } + tcg_temp_free_i32(tmp2); break; - default: /* 14 and 15 are RESERVED */ + default: return 1; } } --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150714316412311.447007197486982; Wed, 4 Oct 2017 11:52:44 -0700 (PDT) Received: from localhost ([::1]:36476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzome-0007KF-As for importer@patchew.org; Wed, 04 Oct 2017 14:52:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38278) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzody-0008Fk-Os for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzodx-0002l5-Pe for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:42 -0400 Received: from mail-qt0-x22c.google.com ([2607:f8b0:400d:c0d::22c]:48928) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzodx-0002kO-MU for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:41 -0400 Received: by mail-qt0-x22c.google.com with SMTP id d13so20372347qta.5 for ; Wed, 04 Oct 2017 11:43:41 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2606:a000:7a4a:b100::1b]) by smtp.gmail.com with ESMTPSA id o64sm3020464ywe.12.2017.10.04.11.43.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 11:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b+9rLgDBfShWST9hHmo3Upcv7Mo8cJQOAwEILtOo+vs=; b=cRCX91QxSoWGhpmaJsEchKvBp/60bDNjDoX/fODaQCNRMwLuyAl6q8qpyE9M7HlmrA LlSFzfZfnz1HcaQ6yc+r87Je2dv0PLphkaYYuaHQYvdNfVvTdYXsA586m0TDrDO0QDN/ gdzQCrU3J5J/IPayhhSX3XkhQ4qqUjnzy4wBQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b+9rLgDBfShWST9hHmo3Upcv7Mo8cJQOAwEILtOo+vs=; b=Z5xAagHd1WyB9s0tefn/zXa2gcuPA4eQg6Bi+E48lrSGLJNTAYOYuCXrYGOrmb1up2 tEeY88GW6+lGyTtMZPHn2Kw2EI/72Q4Qu0A1NnWudMd5AhPlr/Mwl2no3gxSSnFwGcrK DY+Pk/mqoSSyiaFwKeEUdeqnVTW4Q8cu/sWIjKAbajy0VaPtZtXZu5jx7RQ1f0xlFZn2 xvVHHpx2x6EIMEuWb/eg3uHIaCYysViuFAosdvrqrxiErC0Pnd+QqxvaTNvnvWd1PmbR lmBPdjcAAwiPaK9MSazBaFpHZPUZzVCi363Sfx+iOoYOa7H26NEcweAWtJ1cZ+bCijr3 i3Pg== X-Gm-Message-State: AMCzsaU9qn94kLBu1GGtOzjYIpA4CuaLyFAOKs/MzcvoJEeRns9fwqUf MNtkl/vRHOIDwvudpZdkNRGr1FeiLyE= X-Google-Smtp-Source: AOwi7QBoNH+iXU/PRLXxbzG6ZNGv9KE/6gjT5YPs+YOp/WaUZPv3Z+8/B4WmdGiSwh9QHQMQaJpdUA== X-Received: by 10.37.31.135 with SMTP id f129mr4684275ybf.237.1507142620809; Wed, 04 Oct 2017 11:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:21 -0400 Message-Id: <20171004184325.24157-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::22c Subject: [Qemu-devel] [PATCH v1 08/12] target/arm: Add ARM_FEATURE_V8_FCMA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 1 + linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 4 files changed, 4 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5c9cef834..fdf72534d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1313,6 +1313,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 003d9420b7..788e46229b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -541,6 +541,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 276c996e9f..722d2806a7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1604,6 +1604,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->midr =3D 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b05c904ad2..96320ac0d6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -227,6 +227,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ } --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507143060585729.3116434862602; Wed, 4 Oct 2017 11:51:00 -0700 (PDT) Received: from localhost ([::1]:36467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzokz-0005pd-6P for importer@patchew.org; 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Wed, 04 Oct 2017 11:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:22 -0400 Message-Id: <20171004184325.24157-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::234 Subject: [Qemu-devel] [PATCH v1 09/12] target/arm: Decode aa64 armv8.3 fcadd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 5 ++++ target/arm/advsimd_helper.c | 66 +++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 33 ++++++++++++++++++++++- 3 files changed, 103 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 67583b3c2e..350e2fa0e1 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -551,6 +551,11 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index b0f4b02a12..fe2e0cbcef 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -24,6 +24,18 @@ #include "tcg/tcg-gvec-desc.h" =20 =20 +/* Note that vector data is stored in host-endian 64-bit chunks, + so addressing units smaller than that needs a host-endian fixup. */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q =20 static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) @@ -177,3 +189,57 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void= *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + uint32_t neg_real =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D neg_real ^ 1; + uintptr_t i; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i)]; + float32 e1 =3D m[H4(i + 1)] ^ neg_imag; + float32 e2 =3D n[H4(i + 1)]; + float32 e3 =3D m[H4(i)] ^ neg_real; + + d[H4(i)] =3D float32_add(e0, e1, fpst); + d[H4(i + 1)] =3D float32_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float64 *d =3D vd; + float64 *n =3D vn; + float64 *m =3D vm; + float_status *fpst =3D vfpst; + uint64_t neg_real =3D extract64(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag =3D neg_real ^ 1; + uintptr_t i; + + neg_real <<=3D 63; + neg_imag <<=3D 63; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + float64 e0 =3D n[i]; + float64 e1 =3D m[i + 1] ^ neg_imag; + float64 e2 =3D n[i + 1]; + float64 e3 =3D m[i] ^ neg_real; + + d[i] =3D float64_add(e0, e1, fpst); + d[i + 1] =3D float64_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b02aad8cd7..f13a945c43 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9890,7 +9890,8 @@ static void disas_simd_three_reg_same_extra(DisasCont= ext *s, uint32_t insn) int size =3D extract32(insn, 22, 2); bool u =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); - int feature; + int feature, data; + TCGv_ptr fpst; =20 if (!u) { unallocated_encoding(s); @@ -9906,6 +9907,14 @@ static void disas_simd_three_reg_same_extra(DisasCon= text *s, uint32_t insn) } feature =3D ARM_FEATURE_V8_1_SIMD; break; + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + if (size !=3D 2 && (size !=3D 3 || !is_q)) { /* FIXME: fp16 suppor= t */ + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_FCMA; + break; default: unallocated_encoding(s); return; @@ -9952,6 +9961,28 @@ static void disas_simd_three_reg_same_extra(DisasCon= text *s, uint32_t insn) 0, fn_gvec_ptr); break; =20 + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + switch (size) { + case 2: + fn_gvec_ptr =3D gen_helper_gvec_fcadds; + break; + case 3: + fn_gvec_ptr =3D gen_helper_gvec_fcaddd; + break; + default: + g_assert_not_reached(); + } + data =3D extract32(opcode, 1, 1); + fpst =3D get_fpstatus_ptr(); + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), + data, fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + break; + default: g_assert_not_reached(); } --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 04 Oct 2017 11:43:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:23 -0400 Message-Id: <20171004184325.24157-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::22d Subject: [Qemu-devel] [PATCH v1 10/12] target/arm: Decode aa64 armv8.3 fcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 +++ target/arm/advsimd_helper.c | 86 ++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 119 ++++++++++++++++++++++++++++++----------= ---- 3 files changed, 176 insertions(+), 37 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 350e2fa0e1..de3cc43a7a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -556,6 +556,14 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index fe2e0cbcef..acb452df1b 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -243,3 +243,89 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i + flip)]; + float32 e1 =3D m[H4(i + flip)] ^ neg_real; + float32 e2 =3D e0; + float32 e3 =3D m[H4(i + 1 - flip)] ^ neg_imag; + + d[H4(i)] =3D float32_muladd(e0, e1, d[H4(i)], 0, fpst); + d[H4(i + 1)] =3D float32_muladd(e2, e3, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + float32 e1 =3D m[H4(flip)]; + float32 e3 =3D m[H4(1 - flip)]; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + e1 ^=3D neg_real; + e3 ^=3D neg_imag; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i + flip)]; + float32 e2 =3D e0; + + d[H4(i)] =3D float32_muladd(e0, e1, d[H4(i)], 0, fpst); + d[H4(i + 1)] =3D float32_muladd(e2, e3, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float64 *d =3D vd; + float64 *n =3D vn; + float64 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint64_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + + neg_real <<=3D 63; + neg_imag <<=3D 63; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + float64 e0 =3D n[i + flip]; + float64 e1 =3D m[i + flip] ^ neg_real; + float64 e2 =3D e0; + float64 e3 =3D m[i + 1 - flip] ^ neg_imag; + + d[i] =3D float64_muladd(e0, e1, d[i], 0, fpst); + d[i + 1] =3D float64_muladd(e2, e3, d[i + 1], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f13a945c43..b572122227 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9907,6 +9907,10 @@ static void disas_simd_three_reg_same_extra(DisasCon= text *s, uint32_t insn) } feature =3D ARM_FEATURE_V8_1_SIMD; break; + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ if (size !=3D 2 && (size !=3D 3 || !is_q)) { /* FIXME: fp16 suppor= t */ @@ -9961,6 +9965,24 @@ static void disas_simd_three_reg_same_extra(DisasCon= text *s, uint32_t insn) 0, fn_gvec_ptr); break; =20 + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ + switch (size) { + case 2: + fn_gvec_ptr =3D gen_helper_gvec_fcmlas; + break; + case 3: + fn_gvec_ptr =3D gen_helper_gvec_fcmlad; + break; + default: + g_assert_not_reached(); + } + data =3D extract32(opcode, 0, 2); + goto do_fpst; + break; + case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ switch (size) { @@ -9974,6 +9996,7 @@ static void disas_simd_three_reg_same_extra(DisasCont= ext *s, uint32_t insn) g_assert_not_reached(); } data =3D extract32(opcode, 1, 1); + do_fpst: fpst =3D get_fpstatus_ptr(); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), @@ -10753,76 +10776,75 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); bool is_long =3D false; - bool is_fp =3D false; + int is_fp =3D 0; int index; TCGv_ptr fpst; =20 - switch (opcode) { - case 0x0: /* MLA */ - case 0x4: /* MLS */ - if (!u || is_scalar) { + switch (16 * u + opcode) { + case 0x00: /* MLA */ + case 0x04: /* MLS */ + case 0x08: /* MUL */ + if (is_scalar) { unallocated_encoding(s); return; } break; - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ + case 0x02: /* SMLAL, SMLAL2 */ + case 0x12: /* UMLAL, UMLAL2 */ + case 0x06: /* SMLSL, SMLSL2 */ + case 0x16: /* UMLSL, UMLSL2 */ + case 0x0a: /* SMULL, SMULL2 */ + case 0x1a: /* UMULL, UMULL2 */ if (is_scalar) { unallocated_encoding(s); return; } is_long =3D true; break; - case 0x3: /* SQDMLAL, SQDMLAL2 */ - case 0x7: /* SQDMLSL, SQDMLSL2 */ - case 0xb: /* SQDMULL, SQDMULL2 */ + case 0x03: /* SQDMLAL, SQDMLAL2 */ + case 0x07: /* SQDMLSL, SQDMLSL2 */ + case 0x0b: /* SQDMULL, SQDMULL2 */ is_long =3D true; - /* fall through */ - case 0xc: /* SQDMULH */ - if (u) { - unallocated_encoding(s); - return; - } break; - case 0xd: /* SQRDMULH / SQRDMLAH */ - if (u && !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { - unallocated_encoding(s); - return; - } + case 0x0c: /* SQDMULH */ + case 0x0d: /* SQRDMULH */ break; - case 0xf: /* SQRDMLSH */ - if (!u || !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + case 0x1d: /* SQRDMLAH */ + case 0x1f: /* SQRDMLSH */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { unallocated_encoding(s); return; } break; - case 0x8: /* MUL */ - if (u || is_scalar) { + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + if (size !=3D 2 /* FIXME fp16 */ + || (l || !is_q) + || !arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { unallocated_encoding(s); return; } + is_fp =3D 2; break; - case 0x1: /* FMLA */ - case 0x5: /* FMLS */ - if (u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x9: /* FMUL, FMULX */ + case 0x01: /* FMLA */ + case 0x05: /* FMLS */ + case 0x09: /* FMUL */ + case 0x19: /* FMULX */ if (!extract32(size, 1, 1)) { unallocated_encoding(s); return; } - is_fp =3D true; + is_fp =3D 1; break; default: unallocated_encoding(s); return; } =20 - if (is_fp) { + switch (is_fp) { + case 1: /* normal fp */ /* low bit of size indicates single/double */ size =3D extract32(size, 0, 1) ? 3 : 2; if (size =3D=3D 2) { @@ -10835,7 +10857,15 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) index =3D h; } rm |=3D (m << 4); - } else { + break; + + case 2: /* complex fp */ + /* FIXME fp16 */ + index =3D h; + rm |=3D (m << 4); + break; + + default: /* integer */ switch (size) { case 1: index =3D h << 2 | l << 1 | m; @@ -10860,6 +10890,21 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) TCGV_UNUSED_PTR(fpst); } =20 + switch (16 * u + opcode) { + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_reg_offset(s, rm, index, MO_64), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), + extract32(insn, 13, 2), /* rot */ + gen_helper_gvec_fcmlas_idx); + tcg_temp_free_ptr(fpst); + return; + } + if (size =3D=3D 3) { TCGv_i64 tcg_idx =3D tcg_temp_new_i64(); int pass; --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 04 Oct 2017 11:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:24 -0400 Message-Id: <20171004184325.24157-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::234 Subject: [Qemu-devel] [PATCH v1 11/12] target/arm: Decode aa32 armv8.3 3-same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 69 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index ee1e364fb5..48f30e2621 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7630,6 +7630,69 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 0; } =20 +/* ARMv8.3 reclaims a portion of the LDC2/STC2 coprocessor 8 space. */ + +static int disas_neon_insn_cp8_3same(DisasContext *s, uint32_t insn) +{ + void (*fn_gvec_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); + int rd, rn, rm, rot, size, opr_sz; + TCGv_ptr fpst; + bool q; + + /* FIXME: this access check should not take precedence over UNDEF + * for invalid encodings; we will generate incorrect syndrome informat= ion + * for attempts to execute invalid vfp/neon encodings with FP disabled. + */ + if (s->fp_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + return 0; + } + if (!s->vfp_enabled) { + return 1; + } + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { + return 1; + } + + q =3D extract32(insn, 6, 1); + size =3D extract32(insn, 20, 1); + VFP_DREG_D(rd, insn); + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rd | rn | rm) & q) { + return 1; + } + + if (size =3D=3D 0) { /* FIXME: fp16 support */ + return 1; + } + + if (extract32(insn, 21, 1)) { + /* VCMLA */ + rot =3D extract32(insn, 23, 2); + fn_gvec_ptr =3D gen_helper_gvec_fcmlas; + } else if (extract32(insn, 23, 1)) { + /* VCADD */ + rot =3D extract32(insn, 24, 1); + fn_gvec_ptr =3D gen_helper_gvec_fcadds; + } else { + /* Assuming the register fields remain, only bit 24 remains undeco= ded: + * 1111_110x_0d0s_nnnn_dddd_1000_nqm0_mmmm + */ + return 1; + } + + opr_sz =3D (1 + q) * 8; + fpst =3D get_fpstatus_ptr(1); + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), fpst, + opr_sz, opr_sz, rot, fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + return 0; +} + static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; @@ -8345,6 +8408,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } } } + } else if ((insn & 0x0e000f10) =3D=3D 0x0c000800) { + /* ARMv8.3 neon ldc2/stc2 coprocessor 8 extension. */ + if (disas_neon_insn_cp8_3same(s, insn)) { + goto illegal_op; + } + return; } else if ((insn & 0x0fe00000) =3D=3D 0x0c400000) { /* Coprocessor double register transfer. */ ARCH(5TE); --=20 2.13.6 From nobody Mon Apr 29 15:22:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 04 Oct 2017 11:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:25 -0400 Message-Id: <20171004184325.24157-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::22a Subject: [Qemu-devel] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 48f30e2621..50ef2f1f21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7693,6 +7693,53 @@ static int disas_neon_insn_cp8_3same(DisasContext *s= , uint32_t insn) return 0; } =20 +/* ARMv8.3 reclaims a portion of the CDP2 coprocessor 8 space. */ + +static int disas_neon_insn_cp8_index(DisasContext *s, uint32_t insn) +{ + int rd, rn, rm, rot, size, opr_sz; + TCGv_ptr fpst; + bool q; + + /* FIXME: this access check should not take precedence over UNDEF + * for invalid encodings; we will generate incorrect syndrome informat= ion + * for attempts to execute invalid vfp/neon encodings with FP disabled. + */ + if (s->fp_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + return 0; + } + if (!s->vfp_enabled || !arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { + return 1; + } + + q =3D extract32(insn, 6, 1); + size =3D extract32(insn, 23, 1); + + if (size =3D=3D 0) { /* FIXME: fp16 support */ + return 1; + } + + VFP_DREG_D(rd, insn); + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rd | rn) & q) { + return 1; + } + + /* This entire space is VCMLA (indexed). */ + rot =3D extract32(insn, 20, 2); + opr_sz =3D (1 + q) * 8; + fpst =3D get_fpstatus_ptr(1); + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), fpst, + opr_sz, opr_sz, rot, gen_helper_gvec_fcmlas_idx); + tcg_temp_free_ptr(fpst); + return 0; +} + static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; @@ -8414,6 +8461,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) goto illegal_op; } return; + } else if ((insn & 0x0f000f10) =3D=3D 0x0e000800) { + /* ARMv8.3 neon cdp2 coprocessor 8 extension. */ + if (disas_neon_insn_cp8_index(s, insn)) { + goto illegal_op; + } + return; } else if ((insn & 0x0fe00000) =3D=3D 0x0c400000) { /* Coprocessor double register transfer. */ ARCH(5TE); --=20 2.13.6