From nobody Mon Apr 29 21:58:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15070118697211020.523320870906; Mon, 2 Oct 2017 23:24:29 -0700 (PDT) Received: from localhost ([::1]:56333 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzGcu-00025k-Au for importer@patchew.org; Tue, 03 Oct 2017 02:24:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51548) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzGc3-0001im-AQ for qemu-devel@nongnu.org; Tue, 03 Oct 2017 02:23:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzGby-0000Y1-8K for qemu-devel@nongnu.org; Tue, 03 Oct 2017 02:23:27 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45108 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dzGby-0000Wi-2s for qemu-devel@nongnu.org; Tue, 03 Oct 2017 02:23:22 -0400 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v936JAEx123387 for ; Tue, 3 Oct 2017 02:23:18 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0b-001b2d01.pphosted.com with ESMTP id 2dbwsybrmc-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 03 Oct 2017 02:23:18 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 3 Oct 2017 16:23:14 +1000 Received: from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v936NDhn38666270; Tue, 3 Oct 2017 17:23:13 +1100 Received: from d23av05.au.ibm.com (localhost [127.0.0.1]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v936NDJf017720; Tue, 3 Oct 2017 17:23:13 +1100 Received: from tpad450.in.ibm.com (tpad450.in.ibm.com [9.124.31.156]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v936NBFg017662; Tue, 3 Oct 2017 17:23:12 +1100 From: Sandipan Das To: david@gibson.dropbear.id.au, agraf@suse.de Date: Tue, 3 Oct 2017 11:53:10 +0530 X-Mailer: git-send-email 2.13.5 X-TM-AS-MML: disable x-cbid: 17100306-0048-0000-0000-0000025E86A3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17100306-0049-0000-0000-00004815B79E Message-Id: <20171003062310.9919-1-sandipan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-03_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710030095 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v3] target/ppc: Fix carry flag setting for shift algebraic instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift right algebraic instructions whenever the CA bit is to be set. This change affects the following instructions: * Shift Right Algebraic Word (sraw[.]) * Shift Right Algebraic Word Immediate (srawi[.]) * Shift Right Algebraic Doubleword (srad[.]) * Shift Right Algebraic Doubleword Immediate (sradi[.]) Signed-off-by: Sandipan Das --- v2: Add tcg_temp_free() required in gen_sraw() and gen_srad() v3: Remove explicit checking for ISA v3.0 when setting CA32 --- target/ppc/int_helper.c | 8 ++++++++ target/ppc/translate.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index da4e1a62c9..0bdd96aebe 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -231,6 +231,10 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulon= g value, ret =3D (int32_t)value >> 31; env->ca =3D (ret !=3D 0); } + + /* update CA32 for ISA v3.0 */ + env->ca32 =3D env->ca; + return (target_long)ret; } =20 @@ -257,6 +261,10 @@ target_ulong helper_srad(CPUPPCState *env, target_ulon= g value, ret =3D (int64_t)value >> 63; env->ca =3D (ret !=3D 0); } + + /* update CA32 for ISA v3.0 */ + env->ca32 =3D env->ca; + return ret; } #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 606b605ba0..c35a2027eb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2192,6 +2192,10 @@ static void gen_srawi(DisasContext *ctx) tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); tcg_gen_sari_tl(dst, dst, sh); } + + /* update CA32 for ISA v3.0 */ + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } @@ -2269,6 +2273,10 @@ static inline void gen_sradi(DisasContext *ctx, int = n) tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); tcg_gen_sari_tl(dst, src, sh); } + + /* update CA32 for ISA v3.0 */ + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } --=20 2.13.5