From nobody Sun May 5 23:42:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@gnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@gnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1506792212901373.20636702207764; Sat, 30 Sep 2017 10:23:32 -0700 (PDT) Received: from localhost ([::1]:39919 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dyLU1-0001DE-EU for importer@patchew.org; Sat, 30 Sep 2017 13:23:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dyLTB-0000u2-3Y for qemu-devel@nongnu.org; Sat, 30 Sep 2017 13:22:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dyLT8-0006Ql-Ey for qemu-devel@nongnu.org; Sat, 30 Sep 2017 13:22:29 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:58134 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dyLT8-0006QT-9j for qemu-devel@nongnu.org; Sat, 30 Sep 2017 13:22:26 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8UHIshx039258 for ; Sat, 30 Sep 2017 13:22:22 -0400 Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) by mx0a-001b2d01.pphosted.com with ESMTP id 2da7970qbr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sat, 30 Sep 2017 13:22:22 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sun, 1 Oct 2017 03:22:17 +1000 Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8UHMH2N46006306; Sun, 1 Oct 2017 04:22:17 +1100 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v8UHM7oA022439; Sun, 1 Oct 2017 04:22:08 +1100 Received: from tpad450.in.ibm.com ([9.79.182.39]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v8UHM2BM022357; Sun, 1 Oct 2017 04:22:04 +1100 From: Sandipan Das To: david@gibson.dropbear.id.au, agraf@suse.de Date: Sat, 30 Sep 2017 22:52:10 +0530 X-Mailer: git-send-email 2.13.5 X-TM-AS-MML: disable x-cbid: 17093017-0016-0000-0000-0000026606FF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17093017-0017-0000-0000-000006EBA9AD Message-Id: <20170930172210.17532-1-sandipan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-30_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709300258 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2] target/ppc: Fix carry flag setting for shift algebraic instructions X-BeenThere: qemu-devel@gnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@gnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift right algebraic instructions whenever the CA bit is to be set. This change affects the following instructions: * Shift Right Algebraic Word (sraw[.]) * Shift Right Algebraic Word Immediate (srawi[.]) * Shift Right Algebraic Doubleword (srad[.]) * Shift Right Algebraic Doubleword Immediate (sradi[.]) Signed-off-by: Sandipan Das --- v2: Add tcg_temp_free() required in gen_sraw() and gen_srad() --- target/ppc/helper.h | 4 ++-- target/ppc/int_helper.c | 10 ++++++++-- target/ppc/translate.c | 18 ++++++++++++++++-- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index bb6a94a8b3..069d65ad7b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -40,12 +40,12 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32) =20 DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_4(sraw, tl, env, tl, tl, tl) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_3(srad, tl, env, tl, tl) +DEF_HELPER_4(srad, tl, env, tl, tl, tl) DEF_HELPER_0(darn32, tl) DEF_HELPER_0(darn64, tl) #endif diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index da4e1a62c9..4f270eb49d 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -210,7 +210,7 @@ target_ulong helper_cmpb(target_ulong rs, target_ulong = rb) =20 /* shift right arithmetic helper */ target_ulong helper_sraw(CPUPPCState *env, target_ulong value, - target_ulong shift) + target_ulong shift, target_ulong is_isa300) { int32_t ret; =20 @@ -231,12 +231,15 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulo= ng value, ret =3D (int32_t)value >> 31; env->ca =3D (ret !=3D 0); } + if (is_isa300) { + env->ca32 =3D env->ca; + } return (target_long)ret; } =20 #if defined(TARGET_PPC64) target_ulong helper_srad(CPUPPCState *env, target_ulong value, - target_ulong shift) + target_ulong shift, target_ulong is_isa300) { int64_t ret; =20 @@ -257,6 +260,9 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong= value, ret =3D (int64_t)value >> 63; env->ca =3D (ret !=3D 0); } + if (is_isa300) { + env->ca32 =3D env->ca; + } return ret; } #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 606b605ba0..7618015ab7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2166,8 +2166,12 @@ static void gen_slw(DisasContext *ctx) /* sraw & sraw. */ static void gen_sraw(DisasContext *ctx) { + TCGv t0; + + t0 =3D tcg_const_tl(is_isa300(ctx)); gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); + cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0= ); + tcg_temp_free(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } @@ -2192,6 +2196,9 @@ static void gen_srawi(DisasContext *ctx) tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); tcg_gen_sari_tl(dst, dst, sh); } + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } @@ -2245,8 +2252,12 @@ static void gen_sld(DisasContext *ctx) /* srad & srad. */ static void gen_srad(DisasContext *ctx) { + TCGv t0; + + t0 =3D tcg_const_tl(is_isa300(ctx)); gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); + cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0= ); + tcg_temp_free(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } @@ -2269,6 +2280,9 @@ static inline void gen_sradi(DisasContext *ctx, int n) tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); tcg_gen_sari_tl(dst, src, sh); } + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } --=20 2.13.5