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[131.111.184.8]) by smtp.gmail.com with ESMTPSA id s3sm1624841wrc.24.2017.09.15.12.08.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Sep 2017 12:08:41 -0700 (PDT) Received: by Jamess-MacBook.local (Postfix, from userid 501) id 6728C25551A7; Fri, 15 Sep 2017 20:08:40 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jrtc27.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :references; bh=LGH4vp6VRiDp9W5F9efZgelvGwdWcGqoY+c85IFevhM=; b=dhR+Dtqj/1OMDjWMNXTW1aygDBEqTzDae44dv/2VR5v/r8ViRh++/jCpq7xgBtygyy FHy19Vt5AnUmBjQZl2TtcPW+oCo8t/MIzCsriLyEjpjkWNPZOr5gnGqgIOR53Wku+dRx m+Zavu3sFpLlEcUgXBld3sjyeuJLDgEknd5vU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:references; bh=LGH4vp6VRiDp9W5F9efZgelvGwdWcGqoY+c85IFevhM=; b=BauOtEF1CZcaEgG9Vz+YBB15CwBLatVAnjwhWDrv76bN+kfnXtD6EYCnCEgdaOMOZw XZQvzixGEipGvVkg9LH1eEZebDvoq6dtfo8382beMdbSxomQNtaI2Ok0f7KiMFh3Yxiy C+I73feTZy3e1vxDujXHDSLMwCxrO7PwJ/E2Irot8cTvljKYLLHrow0QOGTXh4gEoSl1 m+TaQb0lfuaoxgg43FproNS9J/v+orDKsPKHHyBT/z16ZVXyJWVRsvOc69Ur5FT2KZ68 zWZJEvyS0g4PITGTNd2v6W38Gw30GB8icAv5C3mZlDHe/rK+tpF8f406aHJRp2t3H/Zc hQfQ== X-Gm-Message-State: AHPjjUgBNPxM+KklGZfSzbPoWruY/sxnhBfGnStR1xWP/n7QzhOFcHyn X+0Xc9Rg6CKUWzwQQB8LPZjStQ== X-Google-Smtp-Source: AOwi7QCecub7FIBYAR4C4o9vELaGeHq0JI8m1K7ymDHq+RVkSFbBm634FE5iRsW9/KB0g1/h8xTt6w== X-Received: by 10.28.57.215 with SMTP id g206mr3758051wma.117.1505502522497; Fri, 15 Sep 2017 12:08:42 -0700 (PDT) From: James Clarke To: QEMU Developers Date: Fri, 15 Sep 2017 20:07:48 +0100 Message-Id: <20170915190748.82389-1-jrtc27@jrtc27.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: References: References: <20170915065821.16600-1-jrtc27@jrtc27.com> <2f7283ca-6ecd-165f-c572-a0f2a781aba7@amsat.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [PATCH v2] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , John Paul Adrian Glaubitz , James Clarke Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fixes: https://bugs.launchpad.net/qemu/+bug/1716767 Signed-off-by: James Clarke --- Changes since v1: * Removed all changes in v1 :) * Added syscall num argument to regpairs_aligned * Added SH4-specific implementation of regpairs_aligned to return 1 for p{read,write}64 linux-user/syscall.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9b6364a266..492c654970 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -667,18 +667,30 @@ static inline int next_free_host_timer(void) =20 /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers= */ #ifdef TARGET_ARM -static inline int regpairs_aligned(void *cpu_env) { +static inline int regpairs_aligned(void *cpu_env, int num) { return ((((CPUARMState *)cpu_env)->eabi) =3D=3D 1) ; } #elif defined(TARGET_MIPS) && (TARGET_ABI_BITS =3D=3D 32) -static inline int regpairs_aligned(void *cpu_env) { return 1; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } #elif defined(TARGET_PPC) && !defined(TARGET_PPC64) /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pa= irs * of registers which translates to the same as ARM/MIPS, because we start= with * r3 as arg1 */ -static inline int regpairs_aligned(void *cpu_env) { return 1; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } +#elif defined(TARGET_SH4) +/* SH4 doesn't align register pairs, except for p{read,write}64 */ +static inline int regpairs_aligned(void *cpu_env, int num) { + switch (num) { + case TARGET_NR_pread64: + case TARGET_NR_pwrite64: + return 1; + + default: + return 0; + } +} #else -static inline int regpairs_aligned(void *cpu_env) { return 0; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } #endif =20 #define ERRNO_TABLE_SIZE 1200 @@ -6857,7 +6869,7 @@ static inline abi_long target_truncate64(void *cpu_en= v, const char *arg1, abi_long arg3, abi_long arg4) { - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, TARGET_NR_truncate64)) { arg2 =3D arg3; arg3 =3D arg4; } @@ -6871,7 +6883,7 @@ static inline abi_long target_ftruncate64(void *cpu_e= nv, abi_long arg1, abi_long arg3, abi_long arg4) { - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, TARGET_NR_ftruncate64)) { arg2 =3D arg3; arg3 =3D arg4; } @@ -10495,7 +10507,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #endif #ifdef TARGET_NR_pread64 case TARGET_NR_pread64: - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg4 =3D arg5; arg5 =3D arg6; } @@ -10505,7 +10517,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, unlock_user(p, arg2, ret); break; case TARGET_NR_pwrite64: - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg4 =3D arg5; arg5 =3D arg6; } @@ -11275,7 +11287,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, arg6 =3D ret; #else /* 6 args: fd, offset (high, low), len (high, low), advice */ - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { /* offset is in (3,4), len in (5,6) and advice in 7 */ arg2 =3D arg3; arg3 =3D arg4; @@ -11294,7 +11306,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #ifdef TARGET_NR_fadvise64 case TARGET_NR_fadvise64: /* 5 args: fd, offset (high, low), len, advice */ - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { /* offset is in (3,4), len in 5 and advice in 6 */ arg2 =3D arg3; arg3 =3D arg4; @@ -11407,7 +11419,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #ifdef TARGET_NR_readahead case TARGET_NR_readahead: #if TARGET_ABI_BITS =3D=3D 32 - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg2 =3D arg3; arg3 =3D arg4; arg4 =3D arg5; --=20 2.13.2