Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
The following features bits have been added/removed compare to Opteron_G5
Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
xsaveopt, xsavec, xgetbv1, arat
Removed: xop, fma4, tbm
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
Changes since v2:
* limit the xlevel to 0x8000000a
Changes since v1:
* fix typo EYPC -> EPYC to reflect the correct branding name
target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ddc45ab..6617e01 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 63xx class CPU",
},
+ {
+ .name = "EPYC",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_AMD,
+ .family = 23,
+ .model = 1,
+ .stepping = 2,
+ .features[FEAT_1_EDX] =
+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+ CPUID_VME | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
+ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_SHA_NI,
+ /* Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component.
+ */
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x8000000A,
+ .model_id = "AMD EPYC Processor",
+ },
};
typedef struct PropValue {
--
2.9.4
Cc Chandu,
On 8/16/17 1:00 AM, Brijesh Singh wrote:
> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>
> The following features bits have been added/removed compare to Opteron_G5
>
> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
> xsaveopt, xsavec, xgetbv1, arat
Hi Brijesh,
Actually I wonder whether or not the support for these new instructions
have already been merged in kvm/qemu?
Regards,
Wanpeng Li
>
> Removed: xop, fma4, tbm
>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
> ---
>
> Changes since v2:
> * limit the xlevel to 0x8000000a
>
> Changes since v1:
> * fix typo EYPC -> EPYC to reflect the correct branding name
>
> target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ddc45ab..6617e01 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .xlevel = 0x8000001A,
> .model_id = "AMD Opteron 63xx class CPU",
> },
> + {
> + .name = "EPYC",
> + .level = 0xd,
> + .vendor = CPUID_VENDOR_AMD,
> + .family = 23,
> + .model = 1,
> + .stepping = 2,
> + .features[FEAT_1_EDX] =
> + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
> + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
> + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
> + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
> + CPUID_VME | CPUID_FP87,
> + .features[FEAT_1_ECX] =
> + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
> + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
> + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
> + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> + .features[FEAT_8000_0001_EDX] =
> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
> + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
> + CPUID_EXT2_SYSCALL,
> + .features[FEAT_8000_0001_ECX] =
> + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
> + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
> + .features[FEAT_7_0_EBX] =
> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
> + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
> + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
> + CPUID_7_0_EBX_SHA_NI,
> + /* Missing: XSAVES (not supported by some Linux versions,
> + * including v4.1 to v4.12).
> + * KVM doesn't yet expose any XSAVES state save component.
> + */
> + .features[FEAT_XSAVE] =
> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> + CPUID_XSAVE_XGETBV1,
> + .features[FEAT_6_EAX] =
> + CPUID_6_EAX_ARAT,
> + .xlevel = 0x8000000A,
> + .model_id = "AMD EPYC Processor",
> + },
> };
>
> typedef struct PropValue {
Hi Wanpeng,
On 08/16/2017 10:55 PM, Wanpeng Li wrote:
> Cc Chandu,
>
> On 8/16/17 1:00 AM, Brijesh Singh wrote:
>> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
>> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>>
>> The following features bits have been added/removed compare to Opteron_G5
>>
>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
>> xsaveopt, xsavec, xgetbv1, arat
>
> Hi Brijesh,
>
> Actually I wonder whether or not the support for these new instructions
> have already been merged in kvm/qemu?
>
These are new features/instructions compare to Opteron_G5. The features are not
new to the KVM. Many of these instructions are virtualized in the hardware and
does not require KVM assist. IIRC, qemu verifies the user requested CPUID
features bits with KVM supported CPUID bits and if it finds that requested CPUID
bit is not supported in the KVM then it prints warning message and remove that
feature bit.
the warning message may look like this:
"
........
warning: host doesn't support requested feature: CPUID.01H:ECX.osxsave [bit 27]
........
"
I have tested EPYC CPU with 4.13-rc1 and it does not complain on any of these feature
bits.
> Regards,
> Wanpeng Li
>
>>
>> Removed: xop, fma4, tbm
>>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <rth@twiddle.net>
>> Cc: Eduardo Habkost <ehabkost@redhat.com>
>> Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
>> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
>> ---
>>
>> Changes since v2:
>> * limit the xlevel to 0x8000000a
>>
>> Changes since v1:
>> * fix typo EYPC -> EPYC to reflect the correct branding name
>>
>> target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index ddc45ab..6617e01 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> .xlevel = 0x8000001A,
>> .model_id = "AMD Opteron 63xx class CPU",
>> },
>> + {
>> + .name = "EPYC",
>> + .level = 0xd,
>> + .vendor = CPUID_VENDOR_AMD,
>> + .family = 23,
>> + .model = 1,
>> + .stepping = 2,
>> + .features[FEAT_1_EDX] =
>> + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
>> + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
>> + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
>> + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
>> + CPUID_VME | CPUID_FP87,
>> + .features[FEAT_1_ECX] =
>> + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
>> + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
>> + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>> + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
>> + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
>> + .features[FEAT_8000_0001_EDX] =
>> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
>> + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
>> + CPUID_EXT2_SYSCALL,
>> + .features[FEAT_8000_0001_ECX] =
>> + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
>> + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
>> + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
>> + .features[FEAT_7_0_EBX] =
>> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
>> + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
>> + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
>> + CPUID_7_0_EBX_SHA_NI,
>> + /* Missing: XSAVES (not supported by some Linux versions,
>> + * including v4.1 to v4.12).
>> + * KVM doesn't yet expose any XSAVES state save component.
>> + */
>> + .features[FEAT_XSAVE] =
>> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
>> + CPUID_XSAVE_XGETBV1,
>> + .features[FEAT_6_EAX] =
>> + CPUID_6_EAX_ARAT,
>> + .xlevel = 0x8000000A,
>> + .model_id = "AMD EPYC Processor",
>> + },
>> };
>>
>> typedef struct PropValue {
>
On 15/08/2017 19:00, Brijesh Singh wrote: > > The following features bits have been added/removed compare to Opteron_G5 > > Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw, > fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha > xsaveopt, xsavec, xgetbv1, arat > > Removed: xop, fma4, tbm Interesting, why were these removed? Do we want to add "topoext" support too? What about mwaitx? Thanks, Paolo
Hi Paolo, On 08/17/2017 11:45 AM, Paolo Bonzini wrote: > On 15/08/2017 19:00, Brijesh Singh wrote: >> >> The following features bits have been added/removed compare to Opteron_G5 >> >> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw, >> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha >> xsaveopt, xsavec, xgetbv1, arat >> >> Removed: xop, fma4, tbm > > Interesting, why were these removed? > I don't know exact reason why these were removed - I am going with whatever is listed as supported feature bit in PPR [1], but I will ask around and let you know. I believe some of these instruction are superseded with newer instructions (e.g fma4->fma) [1] http://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf > Do we want to add "topoext" support too? What about mwaitx? > Looking at PPR I think we can safely enable "topoext" - it is listed as fixed to 1 but "mwaitx" support depends on the MSR condition. If host BIOS does not set the MSR then we may not able to use "mwaitx" feature. Actually, I was trying to ensure that in this patch I do not use a feature which is not supported by KVM. Looking at kvm_cpuid_8000_0001_ecx_x86_features [2] hinted me that both "topoext" and "mwaitx" was not supported hence I skipped it. I can add comment to remind us. http://elixir.free-electrons.com/linux/latest/source/arch/x86/kvm/cpuid.c#L360 -Brijesh
Hi Paolo, On 8/17/17 1:37 PM, Brijesh Singh wrote: > On 08/17/2017 11:45 AM, Paolo Bonzini wrote: >> On 15/08/2017 19:00, Brijesh Singh wrote: >>> >>> The following features bits have been added/removed compare to >>> Opteron_G5 >>> >>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw, >>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, >>> clfshopt, sha >>> xsaveopt, xsavec, xgetbv1, arat >>> >>> Removed: xop, fma4, tbm >> >> Interesting, why were these removed? >> > > I don't know exact reason why these were removed - I am going with > whatever is > listed as supported feature bit in PPR [1], but I will ask around and > let you > know. I believe some of these instruction are superseded with newer > instructions > (e.g fma4->fma) > > [1] > http://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf > > I checked with CPU team, it seems those instruction sets were never really used, I believe AMD came up with them but they were superseded by SSE4/AVX extensions. -Brijesh
Hi Eduardo and Paolo,
Please let me know if want me to address something else in this patch.
After this patch is accepted, I am planning to submit similar patch to
to libvirt to create EPYC CPU.
- Brijesh
On 08/15/2017 12:00 PM, Brijesh Singh wrote:
> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>
> The following features bits have been added/removed compare to Opteron_G5
>
> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
> xsaveopt, xsavec, xgetbv1, arat
>
> Removed: xop, fma4, tbm
>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
> ---
>
> Changes since v2:
> * limit the xlevel to 0x8000000a
>
> Changes since v1:
> * fix typo EYPC -> EPYC to reflect the correct branding name
>
> target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ddc45ab..6617e01 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .xlevel = 0x8000001A,
> .model_id = "AMD Opteron 63xx class CPU",
> },
> + {
> + .name = "EPYC",
> + .level = 0xd,
> + .vendor = CPUID_VENDOR_AMD,
> + .family = 23,
> + .model = 1,
> + .stepping = 2,
> + .features[FEAT_1_EDX] =
> + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
> + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
> + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
> + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
> + CPUID_VME | CPUID_FP87,
> + .features[FEAT_1_ECX] =
> + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
> + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
> + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
> + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> + .features[FEAT_8000_0001_EDX] =
> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
> + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
> + CPUID_EXT2_SYSCALL,
> + .features[FEAT_8000_0001_ECX] =
> + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
> + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
> + .features[FEAT_7_0_EBX] =
> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
> + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
> + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
> + CPUID_7_0_EBX_SHA_NI,
> + /* Missing: XSAVES (not supported by some Linux versions,
> + * including v4.1 to v4.12).
> + * KVM doesn't yet expose any XSAVES state save component.
> + */
> + .features[FEAT_XSAVE] =
> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> + CPUID_XSAVE_XGETBV1,
> + .features[FEAT_6_EAX] =
> + CPUID_6_EAX_ARAT,
> + .xlevel = 0x8000000A,
> + .model_id = "AMD EPYC Processor",
> + },
> };
>
> typedef struct PropValue {
>
On 22/08/2017 16:44, Brijesh Singh wrote:
> Hi Eduardo and Paolo,
>
> Please let me know if want me to address something else in this patch.
>
> After this patch is accepted, I am planning to submit similar patch to
> to libvirt to create EPYC CPU.
It looks good to me, but Eduardo is the maintainer and may spot
something missing. :)
QEMU is now in freeze, but the patch can easily go in at the beginning
of 2.11.
Paolo
> - Brijesh
>
> On 08/15/2017 12:00 PM, Brijesh Singh wrote:
>> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
>> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>>
>> The following features bits have been added/removed compare to Opteron_G5
>>
>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt,
>> sha
>> xsaveopt, xsavec, xgetbv1, arat
>>
>> Removed: xop, fma4, tbm
>>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <rth@twiddle.net>
>> Cc: Eduardo Habkost <ehabkost@redhat.com>
>> Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
>> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
>> ---
>>
>> Changes since v2:
>> * limit the xlevel to 0x8000000a
>>
>> Changes since v1:
>> * fix typo EYPC -> EPYC to reflect the correct branding name
>>
>> target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index ddc45ab..6617e01 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> .xlevel = 0x8000001A,
>> .model_id = "AMD Opteron 63xx class CPU",
>> },
>> + {
>> + .name = "EPYC",
>> + .level = 0xd,
>> + .vendor = CPUID_VENDOR_AMD,
>> + .family = 23,
>> + .model = 1,
>> + .stepping = 2,
>> + .features[FEAT_1_EDX] =
>> + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> CPUID_CLFLUSH |
>> + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
>> CPUID_PGE |
>> + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> CPUID_MCE |
>> + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
>> + CPUID_VME | CPUID_FP87,
>> + .features[FEAT_1_ECX] =
>> + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
>> + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
>> + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>> + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
>> + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
>> + .features[FEAT_8000_0001_EDX] =
>> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
>> + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
>> + CPUID_EXT2_SYSCALL,
>> + .features[FEAT_8000_0001_ECX] =
>> + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
>> + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
>> + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
>> + .features[FEAT_7_0_EBX] =
>> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
>> CPUID_7_0_EBX_AVX2 |
>> + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
>> CPUID_7_0_EBX_RDSEED |
>> + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
>> CPUID_7_0_EBX_CLFLUSHOPT |
>> + CPUID_7_0_EBX_SHA_NI,
>> + /* Missing: XSAVES (not supported by some Linux versions,
>> + * including v4.1 to v4.12).
>> + * KVM doesn't yet expose any XSAVES state save component.
>> + */
>> + .features[FEAT_XSAVE] =
>> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
>> + CPUID_XSAVE_XGETBV1,
>> + .features[FEAT_6_EAX] =
>> + CPUID_6_EAX_ARAT,
>> + .xlevel = 0x8000000A,
>> + .model_id = "AMD EPYC Processor",
>> + },
>> };
>> typedef struct PropValue {
>>
On Tue, Aug 22, 2017 at 05:49:30PM +0200, Paolo Bonzini wrote: > On 22/08/2017 16:44, Brijesh Singh wrote: > > Hi Eduardo and Paolo, > > > > Please let me know if want me to address something else in this patch. > > > > After this patch is accepted, I am planning to submit similar patch to > > to libvirt to create EPYC CPU. > > It looks good to me, but Eduardo is the maintainer and may spot > something missing. :) > > QEMU is now in freeze, but the patch can easily go in at the beginning > of 2.11. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> I'm queueing it for 2.11 on my x86-next branch. -- Eduardo
Hi,
On Tue, Aug 15, 2017 at 12:00:51PM -0500, Brijesh Singh wrote:
> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>
> The following features bits have been added/removed compare to Opteron_G5
>
> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
> xsaveopt, xsavec, xgetbv1, arat
>
> Removed: xop, fma4, tbm
>
[...]
> + {
> + .name = "EPYC",
> + .level = 0xd,
> + .vendor = CPUID_VENDOR_AMD,
> + .family = 23,
> + .model = 1,
> + .stepping = 2,
These f/m/s values trigger model-specific code in Windows 10
guests[1], and I couldn't find any public information that allow
us to fix the problem.
Windows 10 tries to set bit 15 of MSRC001_102C, in code that
looks like workarounds for CPU Erratas.
I found a Revision Guide for family 17h[2], but it has no mention
of MSRC001_102C at all.
Can AMD help us fix this?
If we are unable to fix it, I plan to work around it by changing
EPYC's family/model/stepping to the values in Opteron_G5 on QEMU
3.0.
[1] Details can be seen at:
https://bugzilla.redhat.com/show_bug.cgi?id=1592276
https://bugzilla.redhat.com/show_bug.cgi?id=1593190#c12
[2] https://developer.amd.com/wp-content/resources/55449_1.12.pdf
--
Eduardo
On 27/06/2018 16:48, Eduardo Habkost wrote:
> Hi,
>
> On Tue, Aug 15, 2017 at 12:00:51PM -0500, Brijesh Singh wrote:
>> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
>> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>>
>> The following features bits have been added/removed compare to Opteron_G5
>>
>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
>> xsaveopt, xsavec, xgetbv1, arat
>>
>> Removed: xop, fma4, tbm
>>
> [...]
>> + {
>> + .name = "EPYC",
>> + .level = 0xd,
>> + .vendor = CPUID_VENDOR_AMD,
>> + .family = 23,
>> + .model = 1,
>> + .stepping = 2,
>
> These f/m/s values trigger model-specific code in Windows 10
> guests[1], and I couldn't find any public information that allow
> us to fix the problem.
At least family 17h should be set for EPYC processors.
> Windows 10 tries to set bit 15 of MSRC001_102C, in code that
> looks like workarounds for CPU Erratas.
>
> I found a Revision Guide for family 17h[2], but it has no mention
> of MSRC001_102C at all.
I also found a "Processor Programming Reference"
(https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf)
but it's not there either.
It's okay I think if KVM is modified to either return zero and ignore
writes, or return 0x8000, but I'd like confirmation from AMD too.
Paolo
Hi Eduardo,
On 06/27/2018 09:48 AM, Eduardo Habkost wrote:
> Hi,
>
> On Tue, Aug 15, 2017 at 12:00:51PM -0500, Brijesh Singh wrote:
>> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
>> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>>
>> The following features bits have been added/removed compare to Opteron_G5
>>
>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
>> xsaveopt, xsavec, xgetbv1, arat
>>
>> Removed: xop, fma4, tbm
>>
> [...]
>> + {
>> + .name = "EPYC",
>> + .level = 0xd,
>> + .vendor = CPUID_VENDOR_AMD,
>> + .family = 23,
>> + .model = 1,
>> + .stepping = 2,
>
> These f/m/s values trigger model-specific code in Windows 10
> guests[1], and I couldn't find any public information that allow
> us to fix the problem.
> > Windows 10 tries to set bit 15 of MSRC001_102C, in code that
> looks like workarounds for CPU Erratas.
>
> I found a Revision Guide for family 17h[2], but it has no mention
> of MSRC001_102C at all.
>
> Can AMD help us fix this?
>
IIRC, someone at AMD was looking into this. I will ask around and
update you.
> If we are unable to fix it, I plan to work around it by changing
> EPYC's family/model/stepping to the values in Opteron_G5 on QEMU
> 3.0.
I hope we find the correct definition of MSR and update the
document so that we don't need to workaround it in KVM/Qemu.
>
> [1] Details can be seen at:
> https://bugzilla.redhat.com/show_bug.cgi?id=1592276
> https://bugzilla.redhat.com/show_bug.cgi?id=1593190#c12
> [2] https://developer.amd.com/wp-content/resources/55449_1.12.pdf
>
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