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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id e198sm6394041pfh.36.2017.08.12.08.41.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 Aug 2017 08:41:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=nfUiRuuW2ZaqbgUQZyDm9sycQ/8BCH8lzVvBBPXGEgc=; b=HLUbgPWVTcLmIkt2XQYtVSu2FNDIa6yX/sIYrz0mqFLocza5UWvVMMrLpT8tDzlwlX 8a5NzQSyR/XM17aFLU+opsatu7k50RzfmlxbQ3qtbQ+C9rxFfU3WjHEZIcEAVu9EP5Rf gyXuppgXLtvi8znx1LAn6lcFuu1dp5Yioz06kDKs7Sq58CQ49+8VVMq8A8cZaLnHefdt lY7PiB9Da1qXpHJB8gVgw4SqezJB5cwftjBKcJXyPllmEWux/89LCSAH37PKWyRHjR5A n8jfziY8YB9LO8WeUskeBYTj39jHT6cGNzcXT5UPJ9L42Trvfp5JrS/wvzMW4AVKvF8K Afzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nfUiRuuW2ZaqbgUQZyDm9sycQ/8BCH8lzVvBBPXGEgc=; b=lKND7I0451jy5FX79ig2J9ezbPaQFPzPT90LjJERvlgbBxqxcIAM/yvWGMAVDs3lXd PB70hJFtTIRTzbUdBUcsGTh+9XvlpogESKgCMTYweQPtG40yqSrYPh1QbYCBt6FbETGm UdvXB7QgF6BZmgL7B+vu6go3wmzDssASWj0vDhpTAVnDvaRFoeS1RG7FUQPY+LNHm5Q+ Ur2b8TwdAaUfNYCmHFqlHPzUAh7/yfRdLWUauRbAmSBBN278ob0Z40lZ+9F8vfUtKX5W X+lQIREiSc97r/PcRypvdRW5ymaRaFK6nse59qRF77RmvZRdzABhpmN+lqZ6GlIf9SNT xSDw== X-Gm-Message-State: AHYfb5jGuDD+zkR4o3ktle/ZHY87NJi+1SfKQ9zdLVNOWbBYRpBNuJAv FFCLvZr1yzo2DcUAdUQ= X-Received: by 10.98.129.197 with SMTP id t188mr19433352pfd.318.1502552495578; Sat, 12 Aug 2017 08:41:35 -0700 (PDT) From: Richard Henderson X-Google-Original-From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 Aug 2017 08:41:31 -0700 Message-Id: <20170812154131.29372-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH] target/arm: Correct load/store exclusive pairing and alignment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SetExclusiveMonitors in the pseudocode is on the address + width, and says nothing about the manner of the load. Therefore ldxp w0, w1, [x2] vs ldxr x0, [x2] must record the same metadata so that either may pair with stxp w3, w0, w1, [x2] vs stxr w3, x0, [x2] Fix this by ignoring cpu_exclusive_high except for 64-bit LDXP/STXP. Also note that we were not providing the required single-copy atomic semantics for 32-bit LDXP. This is trivially fixed alongside the cpu_exclusive_val change. At the same time, exclusive loads require the same alignment as exclusive stores. For 64-bit LDXP, this means adding MO_ALIGN_16; for the others adding MO_ALIGN. Reported-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Tested-by: Alistair Francis --- target/arm/translate-a64.c | 65 +++++++++++++++++++++++++++++-------------= ---- 1 file changed, 41 insertions(+), 24 deletions(-) --- I have not yet constructed test cases for all of the combinations listed above. I wanted to put this into your hands so that you could test against your existing code using LDXP/STXP. r~ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..f3643ac8dc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1853,29 +1853,45 @@ static void disas_b_exc_sys(DisasContext *s, uint32= _t insn) static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - TCGMemOp memop =3D s->be_data + size; + int idx =3D get_mem_index(s); + TCGMemOp memop =3D s->be_data; =20 g_assert(size <=3D 3); - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); - if (is_pair) { - TCGv_i64 addr2 =3D tcg_temp_new_i64(); - TCGv_i64 hitmp =3D tcg_temp_new_i64(); - g_assert(size >=3D 2); - tcg_gen_addi_i64(addr2, addr, 1 << size); - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); - tcg_temp_free_i64(addr2); - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); - tcg_temp_free_i64(hitmp); - } + if (size =3D=3D 2) { + /* The pair must be single-copy atomic for the doubleword. */ + memop |=3D MO_64 | MO_ALIGN; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32= , 32); + } else { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32,= 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); + } + } else { + /* The pair must be single-copy atomic for *each* doubleword, + but not the entire quadword. It must, however, be aligned.= */ + TCGv_i64 addr2; =20 - tcg_gen_mov_i64(cpu_exclusive_val, tmp); - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); + memop |=3D MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, + memop | MO_ALIGN_16); =20 - tcg_temp_free_i64(tmp); + addr2 =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(addr2, addr, 8); + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + tcg_temp_free_i64(addr2); + + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); + } + } else { + memop |=3D size | MO_ALIGN; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + } tcg_gen_mov_i64(cpu_exclusive_addr, addr); } =20 @@ -1908,14 +1924,15 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, tmp =3D tcg_temp_new_i64(); if (is_pair) { if (size =3D=3D 2) { - TCGv_i64 val =3D tcg_temp_new_i64(); - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_hig= h); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); + } else { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); + } + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); - tcg_temp_free_i64(val); + MO_64 | MO_ALIGN | s->be_data); + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data =3D=3D MO_LE) { gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), cpu_reg(s, rt2)); --=20 2.13.4