From nobody Sat Apr 27 18:01:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502260317449295.03690481209776; Tue, 8 Aug 2017 23:31:57 -0700 (PDT) Received: from localhost ([::1]:45887 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKX6-0007ve-6M for importer@patchew.org; Wed, 09 Aug 2017 02:31:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37070) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUV-00064D-2H for qemu-devel@nongnu.org; Wed, 09 Aug 2017 02:29:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUT-00075f-H8 for qemu-devel@nongnu.org; Wed, 09 Aug 2017 02:29:15 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46323) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKUO-00070a-FG; Wed, 09 Aug 2017 02:29:08 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2DBA921D8E; Wed, 9 Aug 2017 02:29:08 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:29:08 -0400 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id BE5147E4EA; Wed, 9 Aug 2017 02:29:04 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=GNDR9v AWMtBkJSHNWfHfTP0dAWDNQ4A24GlGMzS/HTE=; b=Jm6SYB99QtOLhJTExMaFwj YT+KsU5B9Rj+ZLf8lVrDvAPF59UNM4SnXYc2Fu60C2sohnT39D3iz7HiKWUVBnuZ mpSP6uIGquIyNrWxpLdDI0uUTQvFisWhCJJGLoIwImGHuF1UjB62BAzAmsGhTF1g Fth5MzzEVZUk3LecahNW2goX7kwvnLg7FK/EdGyJ0fR8SQ2Za7fQASp3TcjuFxYt W/PGR8ThnkGelYxXaerc9Hs6G4mFMr30xVRAinEzLBwhTWgvkzVxNvtj+EomkqLv nb2llqBEhiqRW+SdA88c0GsD8E0kmPPcQG+dLgn4z0OfwusEIuMMSJ6DCEcIRcAQ == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=GNDR9vAWMtBkJSHNWfHfTP0dAWDNQ4A24GlGMzS/H TE=; b=dqGLmE/3WW2auXadagzWBkO+erkgutMijd9/oxliUv/kcURIggiTefLXJ Xg9cOcJFCx8Iz7lGyEvvKeVC0vsmK+kQ7eAdD6Op8G+hL+LaaXAFekJuMmGQN/3+ UiinTm4nMfkKatxBxSkBtEaiEIZsttxm/d3/lwGnAyDAMQGxxqSLjkaUCGWOuu6p kzBQjG003H/8nwsFOrAf3RZMjt74EQ+b54azneAfjTheZhWNEyq874v18Ocv8mlr qYtxdJlDegN7W1jBE4mbU9zFlC9MQ2qasHEnIhJz9TA13I/RMJ8t4hz+2vtnPswl h+cyc95W8e/jn8ivKMkm61s805WdQ== X-ME-Sender: X-Sasl-enc: ZU1C114svhnd1gywXlZDwGaDCqnAj4irrggN3aF2tm9D 1502260147 From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Wed, 9 Aug 2017 15:58:26 +0930 Message-Id: <20170809062828.3673-2-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com, Andrew Jeffery , openbmc@lists.ozlabs.org, f4bug@amsat.org, qemu-devel@nongnu.org, joel@jms.id.au, clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The reset width register controls how the pulse on the SoC's WDTRST{1,2} pins behaves. A pulse is emitted if the external reset bit is set in WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns to configure push-pull/open-drain and active-high/active-low behaviours and thus needs some special handling in the write path. As some of the capabilities depend on the SoC version a silicon-rev property is introduced, which is used to guard version-specific behaviour. Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater --- hw/watchdog/wdt_aspeed.c | 93 +++++++++++++++++++++++++++++++++++-= ---- include/hw/watchdog/wdt_aspeed.h | 2 + 2 files changed, 84 insertions(+), 11 deletions(-) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 8bbe579b6b66..22bce364d7b5 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -8,16 +8,19 @@ */ =20 #include "qemu/osdep.h" + +#include "qapi/error.h" #include "qemu/log.h" +#include "qemu/timer.h" #include "sysemu/watchdog.h" +#include "hw/misc/aspeed_scu.h" #include "hw/sysbus.h" -#include "qemu/timer.h" #include "hw/watchdog/wdt_aspeed.h" =20 -#define WDT_STATUS (0x00 / 4) -#define WDT_RELOAD_VALUE (0x04 / 4) -#define WDT_RESTART (0x08 / 4) -#define WDT_CTRL (0x0C / 4) +#define WDT_STATUS (0x00 / 4) +#define WDT_RELOAD_VALUE (0x04 / 4) +#define WDT_RESTART (0x08 / 4) +#define WDT_CTRL (0x0C / 4) #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) #define WDT_CTRL_1MHZ_CLK BIT(4) @@ -25,18 +28,41 @@ #define WDT_CTRL_WDT_INTR BIT(2) #define WDT_CTRL_RESET_SYSTEM BIT(1) #define WDT_CTRL_ENABLE BIT(0) +#define WDT_RESET_WIDTH (0x18 / 4) +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) +#define WDT_POLARITY_MASK (0xFF << 24) +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) +#define WDT_DRIVE_TYPE_MASK (0xFF << 24) +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) =20 -#define WDT_TIMEOUT_STATUS (0x10 / 4) -#define WDT_TIMEOUT_CLEAR (0x14 / 4) -#define WDT_RESET_WDITH (0x18 / 4) +#define WDT_TIMEOUT_STATUS (0x10 / 4) +#define WDT_TIMEOUT_CLEAR (0x14 / 4) =20 -#define WDT_RESTART_MAGIC 0x4755 +#define WDT_RESTART_MAGIC 0x4755 =20 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) { return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; } =20 +static bool is_ast2500(const AspeedWDTState *s) +{ + switch (s->silicon_rev) { + case AST2500_A0_SILICON_REV: + case AST2500_A1_SILICON_REV: + return true; + case AST2400_A0_SILICON_REV: + case AST2400_A1_SILICON_REV: + default: + break; + } + + return false; +} + static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) { AspeedWDTState *s =3D ASPEED_WDT(opaque); @@ -55,9 +81,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr off= set, unsigned size) return 0; case WDT_CTRL: return s->regs[WDT_CTRL]; + case WDT_RESET_WIDTH: + return s->regs[WDT_RESET_WIDTH]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: - case WDT_RESET_WDITH: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented read at offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -119,9 +146,27 @@ static void aspeed_wdt_write(void *opaque, hwaddr offs= et, uint64_t data, timer_del(s->timer); } break; + case WDT_RESET_WIDTH: + { + uint32_t property =3D data & WDT_POLARITY_MASK; + + if (property && is_ast2500(s)) { + if (property =3D=3D WDT_ACTIVE_HIGH_MAGIC) { + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_ACTIVE_HIGH; + } else if (property =3D=3D WDT_ACTIVE_LOW_MAGIC) { + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_ACTIVE_HIGH; + } else if (property =3D=3D WDT_PUSH_PULL_MAGIC) { + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_PUSH_PULL; + } else if (property =3D=3D WDT_OPEN_DRAIN_MAGIC) { + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_PUSH_PULL; + } + } + s->regs[WDT_RESET_WIDTH] &=3D ~s->ext_pulse_width_mask; + s->regs[WDT_RESET_WIDTH] |=3D data & s->ext_pulse_width_mask; + break; + } case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: - case WDT_RESET_WDITH: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented write at offset 0x%" HWADDR_PRIx= "\n", __func__, offset); @@ -167,6 +212,7 @@ static void aspeed_wdt_reset(DeviceState *dev) s->regs[WDT_RELOAD_VALUE] =3D 0x03EF1480; s->regs[WDT_RESTART] =3D 0; s->regs[WDT_CTRL] =3D 0; + s->regs[WDT_RESET_WIDTH] =3D 0xFF; =20 timer_del(s->timer); } @@ -187,6 +233,25 @@ static void aspeed_wdt_realize(DeviceState *dev, Error= **errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); AspeedWDTState *s =3D ASPEED_WDT(dev); =20 + if (!is_supported_silicon_rev(s->silicon_rev)) { + error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, + s->silicon_rev); + return; + } + + switch (s->silicon_rev) { + case AST2400_A0_SILICON_REV: + case AST2400_A1_SILICON_REV: + s->ext_pulse_width_mask =3D 0xff; + break; + case AST2500_A0_SILICON_REV: + case AST2500_A1_SILICON_REV: + s->ext_pulse_width_mask =3D 0xfffff; + break; + default: + g_assert_not_reached(); + } + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired= , dev); =20 /* FIXME: This setting should be derived from the SCU hw strapping @@ -199,6 +264,11 @@ static void aspeed_wdt_realize(DeviceState *dev, Error= **errp) sysbus_init_mmio(sbd, &s->iomem); } =20 +static Property aspeed_wdt_properties[] =3D { + DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_wdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -207,6 +277,7 @@ static void aspeed_wdt_class_init(ObjectClass *klass, v= oid *data) dc->reset =3D aspeed_wdt_reset; set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->vmsd =3D &vmstate_aspeed_wdt; + dc->props =3D aspeed_wdt_properties; } =20 static const TypeInfo aspeed_wdt_info =3D { diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_asp= eed.h index 080c2231222e..7de3e5c224fb 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { uint32_t regs[ASPEED_WDT_REGS_MAX]; =20 uint32_t pclk_freq; + uint32_t silicon_rev; + uint32_t ext_pulse_width_mask; } AspeedWDTState; =20 #endif /* ASPEED_WDT_H */ --=20 2.11.0 From nobody Sat Apr 27 18:01:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=uzkJPqWJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2 Eg=; b=iJsVEs2rNkve9hzB53n83/540vLaOjuIIUJpievNU+ogWoVFnz2nrcZb6 pLSrhkKTgwt1ninRqinv/EocardHS9JkXyTkXoqlJQzZw1eZc2/D5RnYzcd6ngvv xwg7Yh/H21ZSDg1h7T2ksNLKOzTUJerkSsD8o32/Z0Mvo63dwJua1ZPkntnzsiIV WJPojo3cfjuQgE+bm5yWWLtohFfdbZqM1AyzpFQ7nSCk6OOIsdq5UbE3uaFz6dt4 ZTiND/XpehKk+/cqIWyuKYZjYR6TS0JPp/ptRTTRnEG+puPf2cT/sD/O6Xrch/Rl sWoS/68Tu/Z27DBm8/RfUwZ/F3e6A== X-ME-Sender: X-Sasl-enc: tTMzAZynhKDKbaPvkMIe+Qk0KQeNohPjhIulxVqiyMr+ 1502260150 From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Wed, 9 Aug 2017 15:58:27 +0930 Message-Id: <20170809062828.3673-3-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com, Andrew Jeffery , openbmc@lists.ozlabs.org, qemu-devel@nongnu.org, f4bug@amsat.org, joel@jms.id.au, clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 3034849c80bf..79804e1ee652 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", + sc->info->silicon_rev); } =20 object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); --=20 2.11.0 From nobody Sat Apr 27 18:01:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502260424124468.5366945584618; Tue, 8 Aug 2017 23:33:44 -0700 (PDT) Received: from localhost ([::1]:45892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKYo-0000Gr-VZ for importer@patchew.org; Wed, 09 Aug 2017 02:33:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUb-0006AU-Vx for qemu-devel@nongnu.org; Wed, 09 Aug 2017 02:29:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUb-0007C2-1E for qemu-devel@nongnu.org; Wed, 09 Aug 2017 02:29:22 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:37551) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKUW-00078O-Hi; Wed, 09 Aug 2017 02:29:16 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 33E8021D94; Wed, 9 Aug 2017 02:29:16 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:29:16 -0400 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 87B997E4EA; Wed, 9 Aug 2017 02:29:12 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=uzkJPq WJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2Eg=; b=Xb6mpwXIPKUtOUan33+fYL L/SDOpXbz/zkzMyv5CW17cRox7fvXWCGgw54ZF9BYcwiZmq+VVhp7Y0sK901pUDq DjNZfccf0n8N+EyR0rP1QxDd/B+iXd3DKpIbHSOQxWCK5EqtuIhLB9xbmRDE2fzz FI+s75/vFu0TH30ruJWXQcR8WKwH3Dl9KnWtxj+WcrS2qm72c1NxB9hm94F1TK2l vp6yJVYzyhUEYd+yyBAjtQNKUXhv6/LwO4pRLVrLUJm8vmXPDPcSJSglIqjSy74G aAp5QNmwsWC1QXKYhI+iZuG/yJHIryVRYjSeg8YC0F2RKAXe62sOYKX7PAgBGuLA == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=uzkJPqWJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2 Eg=; b=o+NmTluxJduFUK2GS50lpjwEg3qbwsvUd2YUCfeBFK49wZjo3kgmY0M6e y/zQocURtsJVYiDV/D1TbOiRGAhcQvOi6NXP72dXckEgxHyEsf/F3pSxk31PzLtp dJf681C8GrmVj7WqMh4vMOZpTYVpA7WcGWRKXWB1yZxvYuVPdGkL6N28zB2Vwfd4 cNnfhZfbqH1BoybIphGp/qoGFxZdd4WR5nkqf6vwEUAryeO35hvAvxjp9WtMMERs SD0w9Af4f6Z9bDk7CMbzICWJLjYEkhVssCIxmXBeBolYdGyD4hoKicgx2YugzPhu +9HQYBPB2Kv9ewIKN3pzGTkxtbUTQ== X-ME-Sender: X-Sasl-enc: RVCtiwK1GOosjdI/Fu7vDvXKZ2dhAy+/pq7OHJNhdLpb 1502260155 From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Wed, 9 Aug 2017 15:58:28 +0930 Message-Id: <20170809062828.3673-4-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH for 2.11 v2 2/2] aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com, Andrew Jeffery , openbmc@lists.ozlabs.org, f4bug@amsat.org, qemu-devel@nongnu.org, joel@jms.id.au, clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 3034849c80bf..79804e1ee652 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", + sc->info->silicon_rev); } =20 object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); --=20 2.11.0