From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502217636561632.362071986685; Tue, 8 Aug 2017 11:40:36 -0700 (PDT) Received: from localhost ([::1]:44054 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Qg-0003lN-IM for importer@patchew.org; Tue, 08 Aug 2017 14:40:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Ji-00066H-OV for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1df9Jg-0002Sk-Hh for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58504) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1df9JZ-0002Lc-3t; Tue, 08 Aug 2017 14:33:13 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1399B40812; Tue, 8 Aug 2017 18:33:12 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 83AA560317; Tue, 8 Aug 2017 18:33:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1399B40812 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:32:58 -0400 Message-Id: <20170808183306.27474-2-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 08 Aug 2017 18:33:12 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 1/9] IDE: replace DEBUG_IDE with tracing system X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Out with the old, in with the new. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Makefile.objs | 1 + hw/ide/cmd646.c | 10 +++----- hw/ide/core.c | 65 +++++++++++++++++++------------------------= ---- hw/ide/pci.c | 17 ++++--------- hw/ide/piix.c | 11 ++++---- hw/ide/trace-events | 33 ++++++++++++++++++++++++ hw/ide/via.c | 10 +++----- include/hw/ide/internal.h | 1 - 8 files changed, 78 insertions(+), 70 deletions(-) create mode 100644 hw/ide/trace-events diff --git a/Makefile.objs b/Makefile.objs index 24a4ea0..967c092 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -153,6 +153,7 @@ trace-events-subdirs +=3D hw/acpi trace-events-subdirs +=3D hw/arm trace-events-subdirs +=3D hw/alpha trace-events-subdirs +=3D hw/xen +trace-events-subdirs +=3D hw/ide trace-events-subdirs +=3D ui trace-events-subdirs +=3D audio trace-events-subdirs +=3D net diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 9ebb8d4..86b2a8f 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -32,6 +32,7 @@ #include "sysemu/dma.h" =20 #include "hw/ide/pci.h" +#include "trace.h" =20 /* CMD646 specific */ #define CFR 0x50 @@ -195,9 +196,8 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr, val =3D 0xff; break; } -#ifdef DEBUG_IDE - printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val); -#endif + + trace_bmdma_read_cmd646(addr, val); return val; } =20 @@ -211,9 +211,7 @@ static void bmdma_write(void *opaque, hwaddr addr, return; } =20 -#ifdef DEBUG_IDE - printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val= ); -#endif + trace_bmdma_write_cmd646(addr, val); switch(addr & 3) { case 0: bmdma_cmd_writeb(bm, val); diff --git a/hw/ide/core.c b/hw/ide/core.c index 0b48b64..53fa084 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -36,6 +36,7 @@ #include "qemu/cutils.h" =20 #include "hw/ide/internal.h" +#include "trace.h" =20 /* These values were based on a Seagate ST3500418AS but have been modified to make more sense in QEMU */ @@ -656,10 +657,7 @@ void ide_cancel_dma_sync(IDEState *s) * write requests) pending and we can avoid to drain. */ QLIST_FOREACH(req, &s->buffered_requests, list) { if (!req->orphaned) { -#ifdef DEBUG_IDE - printf("%s: invoking cb %p of buffered request %p with" - " -ECANCELED\n", __func__, req->original_cb, req); -#endif + trace_ide_cancel_dma_sync_buffered(req->original_cb, req); req->original_cb(req->original_opaque, -ECANCELED); } req->orphaned =3D true; @@ -678,9 +676,7 @@ void ide_cancel_dma_sync(IDEState *s) * aio operation with preadv/pwritev. */ if (s->bus->dma->aiocb) { -#ifdef DEBUG_IDE - printf("%s: draining all remaining requests", __func__); -#endif + trace_ide_cancel_dma_sync_remaining(); blk_drain(s->blk); assert(s->bus->dma->aiocb =3D=3D NULL); } @@ -741,9 +737,7 @@ static void ide_sector_read(IDEState *s) n =3D s->req_nb_sectors; } =20 -#if defined(DEBUG_IDE) - printf("sector=3D%" PRId64 "\n", sector_num); -#endif + trace_ide_sector_read(sector_num, n); =20 if (!ide_sect_range_ok(s, sector_num, n)) { ide_rw_error(s); @@ -1005,14 +999,14 @@ static void ide_sector_write(IDEState *s) =20 s->status =3D READY_STAT | SEEK_STAT | BUSY_STAT; sector_num =3D ide_get_sector(s); -#if defined(DEBUG_IDE) - printf("sector=3D%" PRId64 "\n", sector_num); -#endif + n =3D s->nsector; if (n > s->req_nb_sectors) { n =3D s->req_nb_sectors; } =20 + trace_ide_sector_write(sector_num, n); + if (!ide_sect_range_ok(s, sector_num, n)) { ide_rw_error(s); block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE); @@ -1186,18 +1180,17 @@ static void ide_clear_hob(IDEBus *bus) void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) { IDEBus *bus =3D opaque; + IDEState *s =3D idebus_active_if(bus); + int reg_num =3D addr & 7; =20 -#ifdef DEBUG_IDE - printf("IDE: write addr=3D0x%x val=3D0x%02x\n", addr, val); -#endif - - addr &=3D 7; + trace_ide_ioport_write(addr, val, bus, s); =20 /* ignore writes to command block while busy with previous command */ - if (addr !=3D 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STA= T))) + if (reg_num !=3D 7 && (s->status & (BUSY_STAT|DRQ_STAT))) { return; + } =20 - switch(addr) { + switch(reg_num) { case 0: break; case 1: @@ -1253,9 +1246,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, ui= nt32_t val) =20 static void ide_reset(IDEState *s) { -#ifdef DEBUG_IDE - printf("ide: reset\n"); -#endif + trace_ide_reset(s); =20 if (s->pio_aiocb) { blk_aio_cancel(s->pio_aiocb); @@ -2013,10 +2004,9 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) IDEState *s; bool complete; =20 -#if defined(DEBUG_IDE) - printf("ide: CMD=3D%02x\n", val); -#endif s =3D idebus_active_if(bus); + trace_ide_exec_cmd(bus, s, val); + /* ignore commands to non existent slave */ if (s !=3D bus->ifs && !s->blk) { return; @@ -2054,18 +2044,18 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) } } =20 -uint32_t ide_ioport_read(void *opaque, uint32_t addr1) +uint32_t ide_ioport_read(void *opaque, uint32_t addr) { IDEBus *bus =3D opaque; IDEState *s =3D idebus_active_if(bus); - uint32_t addr; + uint32_t reg_num; int ret, hob; =20 - addr =3D addr1 & 7; + reg_num =3D addr & 7; /* FIXME: HOB readback uses bit 7, but it's always set right now */ //hob =3D s->select & (1 << 7); hob =3D 0; - switch(addr) { + switch(reg_num) { case 0: ret =3D 0xff; break; @@ -2133,9 +2123,8 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr1) qemu_irq_lower(bus->irq); break; } -#ifdef DEBUG_IDE - printf("ide: read addr=3D0x%x val=3D%02x\n", addr1, ret); -#endif + + trace_ide_ioport_read(addr, ret, bus, s); return ret; } =20 @@ -2151,9 +2140,8 @@ uint32_t ide_status_read(void *opaque, uint32_t addr) } else { ret =3D s->status; } -#ifdef DEBUG_IDE - printf("ide: read status addr=3D0x%x val=3D%02x\n", addr, ret); -#endif + + trace_ide_status_read(addr, ret, bus, s); return ret; } =20 @@ -2163,9 +2151,8 @@ void ide_cmd_write(void *opaque, uint32_t addr, uint3= 2_t val) IDEState *s; int i; =20 -#ifdef DEBUG_IDE - printf("ide: write control addr=3D0x%x val=3D%02x\n", addr, val); -#endif + trace_ide_cmd_write(addr, val, bus); + /* common for both drives */ if (!(bus->cmd & IDE_CMD_RESET) && (val & IDE_CMD_RESET)) { diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 3cfb510..f2dcc0e 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -31,6 +31,7 @@ #include "sysemu/dma.h" #include "qemu/error-report.h" #include "hw/ide/pci.h" +#include "trace.h" =20 #define BMDMA_PAGE_SIZE 4096 =20 @@ -196,9 +197,7 @@ static void bmdma_reset(IDEDMA *dma) { BMDMAState *bm =3D DO_UPCAST(BMDMAState, dma, dma); =20 -#ifdef DEBUG_IDE - printf("ide: dma_reset\n"); -#endif + trace_bmdma_reset(); bmdma_cancel(bm); bm->cmd =3D 0; bm->status =3D 0; @@ -227,9 +226,7 @@ static void bmdma_irq(void *opaque, int n, int level) =20 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val) { -#ifdef DEBUG_IDE - printf("%s: 0x%08x\n", __func__, val); -#endif + trace_bmdma_cmd_writeb(val); =20 /* Ignore writes to SSBM if it keeps the old value */ if ((val & BM_CMD_START) !=3D (bm->cmd & BM_CMD_START)) { @@ -258,9 +255,7 @@ static uint64_t bmdma_addr_read(void *opaque, hwaddr ad= dr, uint64_t data; =20 data =3D (bm->addr >> (addr * 8)) & mask; -#ifdef DEBUG_IDE - printf("%s: 0x%08x\n", __func__, (unsigned)data); -#endif + trace_bmdma_addr_read(data); return data; } =20 @@ -271,9 +266,7 @@ static void bmdma_addr_write(void *opaque, hwaddr addr, int shift =3D addr * 8; uint32_t mask =3D (1ULL << (width * 8)) - 1; =20 -#ifdef DEBUG_IDE - printf("%s: 0x%08x\n", __func__, (unsigned)data); -#endif + trace_bmdma_addr_write(data); bm->addr &=3D ~(mask << shift); bm->addr |=3D ((data & mask) << shift) & ~3; } diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 7e2d767..dfb21f6 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -33,6 +33,7 @@ #include "sysemu/dma.h" =20 #include "hw/ide/pci.h" +#include "trace.h" =20 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) { @@ -54,9 +55,8 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr, uns= igned size) val =3D 0xff; break; } -#ifdef DEBUG_IDE - printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val); -#endif + + trace_bmdma_read(addr, val); return val; } =20 @@ -69,9 +69,8 @@ static void bmdma_write(void *opaque, hwaddr addr, return; } =20 -#ifdef DEBUG_IDE - printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val); -#endif + trace_bmdma_write(addr, val); + switch(addr & 3) { case 0: bmdma_cmd_writeb(bm, val); diff --git a/hw/ide/trace-events b/hw/ide/trace-events new file mode 100644 index 0000000..68ad96a --- /dev/null +++ b/hw/ide/trace-events @@ -0,0 +1,33 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/ide/core.c +# portio +ide_ioport_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO= rd @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p" +ide_ioport_write(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO= wr @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p" +ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p;= IDEState %p" +ide_cmd_write(uint32_t addr, uint32_t val, void *bus) = "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus= %p" +# misc +ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; = state %p; cmd 0x%02x" +ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffe= red request %p with -ECANCELED" +ide_cancel_dma_sync_remaining(void) "draining all remaining requests" +ide_sector_read(int64_t sector_num, int nsectors) "sector=3D%"PRId64" nsec= tors=3D%d" +ide_sector_write(int64_t sector_num, int nsectors) "sector=3D%"PRId64" nse= ctors=3D%d" +ide_reset(void *s) "IDEstate %p" + +# hw/ide/pci.c +bmdma_reset(void) "" +bmdma_cmd_writeb(uint32_t val) "val: 0x%08x" +bmdma_addr_read(uint64_t data) "data: 0x%016"PRIx64 +bmdma_addr_write(uint64_t data) "data: 0x%016"PRIx64 + +# hw/ide/piix.c +bmdma_read(uint64_t addr, uint8_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x" +bmdma_write(uint64_t addr, uint8_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02= x" + +# hw/ide/cmd646.c +bmdma_read_cmd646(uint64_t addr, uint32_t val) "bmdma: readb 0x%"PRIx64" := 0x%02x" +bmdma_write_cmd646(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64"= : 0x%02"PRIx64 + +# hw/ide/via.c +bmdma_read_via(uint64_t addr, uint32_t val) "bmdma: readb 0x%"PRIx64" : 0x= %02x" +bmdma_write_via(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : = 0x%02"PRIx64 diff --git a/hw/ide/via.c b/hw/ide/via.c index 5b32ecb..35c3059 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -33,6 +33,7 @@ #include "sysemu/dma.h" =20 #include "hw/ide/pci.h" +#include "trace.h" =20 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) @@ -55,9 +56,8 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr, val =3D 0xff; break; } -#ifdef DEBUG_IDE - printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); -#endif + + trace_bmdma_read_via(addr, val); return val; } =20 @@ -70,9 +70,7 @@ static void bmdma_write(void *opaque, hwaddr addr, return; } =20 -#ifdef DEBUG_IDE - printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); -#endif + trace_bmdma_write_via(addr, val); switch (addr & 3) { case 0: bmdma_cmd_writeb(bm, val); diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 482a951..4a92f0a 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -14,7 +14,6 @@ #include "block/scsi.h" =20 /* debug IDE devices */ -//#define DEBUG_IDE //#define DEBUG_IDE_ATAPI //#define DEBUG_AIO #define USE_DMA_CDROM --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Tue, 08 Aug 2017 14:33:13 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BCCBC4081F; Tue, 8 Aug 2017 18:33:12 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3DA1460464; Tue, 8 Aug 2017 18:33:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com BCCBC4081F Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:32:59 -0400 Message-Id: <20170808183306.27474-3-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 08 Aug 2017 18:33:12 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 2/9] IDE: Add register hints to tracing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Name the registers for tracing purposes. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/core.c | 88 +++++++++++++++++++++++++++++++++++++++++--------= ---- hw/ide/trace-events | 4 +-- 2 files changed, 70 insertions(+), 22 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 53fa084..6235bdf 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -1177,13 +1177,37 @@ static void ide_clear_hob(IDEBus *bus) bus->ifs[1].select &=3D ~(1 << 7); } =20 +/* IOport [W]rite [R]egisters */ +enum ATA_IOPORT_WR { + ATA_IOPORT_WR_DATA =3D 0, + ATA_IOPORT_WR_FEATURES =3D 1, + ATA_IOPORT_WR_SECTOR_COUNT =3D 2, + ATA_IOPORT_WR_SECTOR_NUMBER =3D 3, + ATA_IOPORT_WR_CYLINDER_LOW =3D 4, + ATA_IOPORT_WR_CYLINDER_HIGH =3D 5, + ATA_IOPORT_WR_DEVICE_HEAD =3D 6, + ATA_IOPORT_WR_COMMAND =3D 7, + ATA_IOPORT_WR_NUM_REGISTERS, +}; + +const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] =3D { + [ATA_IOPORT_WR_DATA] =3D "Data", + [ATA_IOPORT_WR_FEATURES] =3D "Features", + [ATA_IOPORT_WR_SECTOR_COUNT] =3D "Sector Count", + [ATA_IOPORT_WR_SECTOR_NUMBER] =3D "Sector Number", + [ATA_IOPORT_WR_CYLINDER_LOW] =3D "Cylinder Low", + [ATA_IOPORT_WR_CYLINDER_HIGH] =3D "Cylinder High", + [ATA_IOPORT_WR_DEVICE_HEAD] =3D "Device/Head", + [ATA_IOPORT_WR_COMMAND] =3D "Command" +}; + void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) { IDEBus *bus =3D opaque; IDEState *s =3D idebus_active_if(bus); int reg_num =3D addr & 7; =20 - trace_ide_ioport_write(addr, val, bus, s); + trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, = s); =20 /* ignore writes to command block while busy with previous command */ if (reg_num !=3D 7 && (s->status & (BUSY_STAT|DRQ_STAT))) { @@ -1193,43 +1217,43 @@ void ide_ioport_write(void *opaque, uint32_t addr, = uint32_t val) switch(reg_num) { case 0: break; - case 1: - ide_clear_hob(bus); + case ATA_IOPORT_WR_FEATURES: + ide_clear_hob(bus); /* NOTE: data is written to the two drives */ - bus->ifs[0].hob_feature =3D bus->ifs[0].feature; - bus->ifs[1].hob_feature =3D bus->ifs[1].feature; + bus->ifs[0].hob_feature =3D bus->ifs[0].feature; + bus->ifs[1].hob_feature =3D bus->ifs[1].feature; bus->ifs[0].feature =3D val; bus->ifs[1].feature =3D val; break; - case 2: + case ATA_IOPORT_WR_SECTOR_COUNT: ide_clear_hob(bus); bus->ifs[0].hob_nsector =3D bus->ifs[0].nsector; bus->ifs[1].hob_nsector =3D bus->ifs[1].nsector; bus->ifs[0].nsector =3D val; bus->ifs[1].nsector =3D val; break; - case 3: + case ATA_IOPORT_WR_SECTOR_NUMBER: ide_clear_hob(bus); bus->ifs[0].hob_sector =3D bus->ifs[0].sector; bus->ifs[1].hob_sector =3D bus->ifs[1].sector; bus->ifs[0].sector =3D val; bus->ifs[1].sector =3D val; break; - case 4: + case ATA_IOPORT_WR_CYLINDER_LOW: ide_clear_hob(bus); bus->ifs[0].hob_lcyl =3D bus->ifs[0].lcyl; bus->ifs[1].hob_lcyl =3D bus->ifs[1].lcyl; bus->ifs[0].lcyl =3D val; bus->ifs[1].lcyl =3D val; break; - case 5: + case ATA_IOPORT_WR_CYLINDER_HIGH: ide_clear_hob(bus); bus->ifs[0].hob_hcyl =3D bus->ifs[0].hcyl; bus->ifs[1].hob_hcyl =3D bus->ifs[1].hcyl; bus->ifs[0].hcyl =3D val; bus->ifs[1].hcyl =3D val; break; - case 6: + case ATA_IOPORT_WR_DEVICE_HEAD: /* FIXME: HOB readback uses bit 7 */ bus->ifs[0].select =3D (val & ~0x10) | 0xa0; bus->ifs[1].select =3D (val | 0x10) | 0xa0; @@ -1237,7 +1261,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, ui= nt32_t val) bus->unit =3D (val >> 4) & 1; break; default: - case 7: + case ATA_IOPORT_WR_COMMAND: /* command */ ide_exec_cmd(bus, val); break; @@ -2044,6 +2068,30 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) } } =20 +/* IOport [R]ead [R]egisters */ +enum ATA_IOPORT_RR { + ATA_IOPORT_RR_DATA =3D 0, + ATA_IOPORT_RR_ERROR =3D 1, + ATA_IOPORT_RR_SECTOR_COUNT =3D 2, + ATA_IOPORT_RR_SECTOR_NUMBER =3D 3, + ATA_IOPORT_RR_CYLINDER_LOW =3D 4, + ATA_IOPORT_RR_CYLINDER_HIGH =3D 5, + ATA_IOPORT_RR_DEVICE_HEAD =3D 6, + ATA_IOPORT_RR_STATUS =3D 7, + ATA_IOPORT_RR_NUM_REGISTERS, +}; + +const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] =3D { + [ATA_IOPORT_RR_DATA] =3D "Data", + [ATA_IOPORT_RR_ERROR] =3D "Error", + [ATA_IOPORT_RR_SECTOR_COUNT] =3D "Sector Count", + [ATA_IOPORT_RR_SECTOR_NUMBER] =3D "Sector Number", + [ATA_IOPORT_RR_CYLINDER_LOW] =3D "Cylinder Low", + [ATA_IOPORT_RR_CYLINDER_HIGH] =3D "Cylinder High", + [ATA_IOPORT_RR_DEVICE_HEAD] =3D "Device/Head", + [ATA_IOPORT_RR_STATUS] =3D "Status" +}; + uint32_t ide_ioport_read(void *opaque, uint32_t addr) { IDEBus *bus =3D opaque; @@ -2056,10 +2104,10 @@ uint32_t ide_ioport_read(void *opaque, uint32_t add= r) //hob =3D s->select & (1 << 7); hob =3D 0; switch(reg_num) { - case 0: + case ATA_IOPORT_RR_DATA: ret =3D 0xff; break; - case 1: + case ATA_IOPORT_RR_ERROR: if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || (s !=3D bus->ifs && !s->blk)) { ret =3D 0; @@ -2069,7 +2117,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) ret =3D s->hob_feature; } break; - case 2: + case ATA_IOPORT_RR_SECTOR_COUNT: if (!bus->ifs[0].blk && !bus->ifs[1].blk) { ret =3D 0; } else if (!hob) { @@ -2078,7 +2126,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) ret =3D s->hob_nsector; } break; - case 3: + case ATA_IOPORT_RR_SECTOR_NUMBER: if (!bus->ifs[0].blk && !bus->ifs[1].blk) { ret =3D 0; } else if (!hob) { @@ -2087,7 +2135,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) ret =3D s->hob_sector; } break; - case 4: + case ATA_IOPORT_RR_CYLINDER_LOW: if (!bus->ifs[0].blk && !bus->ifs[1].blk) { ret =3D 0; } else if (!hob) { @@ -2096,7 +2144,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) ret =3D s->hob_lcyl; } break; - case 5: + case ATA_IOPORT_RR_CYLINDER_HIGH: if (!bus->ifs[0].blk && !bus->ifs[1].blk) { ret =3D 0; } else if (!hob) { @@ -2105,7 +2153,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) ret =3D s->hob_hcyl; } break; - case 6: + case ATA_IOPORT_RR_DEVICE_HEAD: if (!bus->ifs[0].blk && !bus->ifs[1].blk) { ret =3D 0; } else { @@ -2113,7 +2161,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) } break; default: - case 7: + case ATA_IOPORT_RR_STATUS: if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || (s !=3D bus->ifs && !s->blk)) { ret =3D 0; @@ -2124,7 +2172,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr) break; } =20 - trace_ide_ioport_read(addr, ret, bus, s); + trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s= ); return ret; } =20 diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 68ad96a..6c156ac 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -2,8 +2,8 @@ =20 # hw/ide/core.c # portio -ide_ioport_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO= rd @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p" -ide_ioport_write(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO= wr @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p" +ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, v= oid *s) "IDE PIO rd @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState= %p" +ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, = void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState= %p" ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p;= IDEState %p" ide_cmd_write(uint32_t addr, uint32_t val, void *bus) = "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus= %p" # misc --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502217340894228.96430786594283; Tue, 8 Aug 2017 11:35:40 -0700 (PDT) Received: from localhost ([::1]:44030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Lv-00084V-FJ for importer@patchew.org; Tue, 08 Aug 2017 14:35:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Jg-00063x-QZ for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1df9Jf-0002Rm-N7 for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56532) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1df9Ja-0002Mm-Hd; Tue, 08 Aug 2017 14:33:14 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 710CD44BF5; Tue, 8 Aug 2017 18:33:13 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id E64EF60317; Tue, 8 Aug 2017 18:33:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 710CD44BF5 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:00 -0400 Message-Id: <20170808183306.27474-4-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 08 Aug 2017 18:33:13 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 3/9] IDE: add tracing for data ports X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To be used sparingly, but still interesting in the case of small firmwares designed to reproduce bugs in QEMU IDE. Signed-off-by: John Snow Reviewed-by: Eric Blake --- hw/ide/core.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 6235bdf..29848ff 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2251,6 +2251,8 @@ void ide_data_writew(void *opaque, uint32_t addr, uin= t32_t val) IDEState *s =3D idebus_active_if(bus); uint8_t *p; =20 + trace_ide_data_writew(addr, val, bus, s); + /* PIO data access allowed only when DRQ bit is set. The result of a w= rite * during PIO out is indeterminate, just ignore it. */ if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { @@ -2296,6 +2298,8 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr) s->status &=3D ~DRQ_STAT; s->end_transfer_func(s); } + + trace_ide_data_readw(addr, ret, bus, s); return ret; } =20 @@ -2305,6 +2309,8 @@ void ide_data_writel(void *opaque, uint32_t addr, uin= t32_t val) IDEState *s =3D idebus_active_if(bus); uint8_t *p; =20 + trace_ide_data_writel(addr, val, bus, s); + /* PIO data access allowed only when DRQ bit is set. The result of a w= rite * during PIO out is indeterminate, just ignore it. */ if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { @@ -2335,7 +2341,8 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr) /* PIO data access allowed only when DRQ bit is set. The result of a r= ead * during PIO in is indeterminate, return 0 and don't move forward. */ if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { - return 0; + ret =3D 0; + goto out; } =20 p =3D s->data_ptr; @@ -2350,6 +2357,9 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr) s->status &=3D ~DRQ_STAT; s->end_transfer_func(s); } + +out: + trace_ide_data_readl(addr, ret, bus, s); return ret; } =20 --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502217327271559.2086394720629; Tue, 8 Aug 2017 11:35:27 -0700 (PDT) Received: from localhost ([::1]:44022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Lh-0007of-Qj for importer@patchew.org; Tue, 08 Aug 2017 14:35:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Jh-00065E-Oa for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1df9Jf-0002Rt-O9 for qemu-devel@nongnu.org; Tue, 08 Aug 2017 14:33:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47136) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1df9Jb-0002Nm-6H; Tue, 08 Aug 2017 14:33:15 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 303CD90905; Tue, 8 Aug 2017 18:33:14 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9E04760464; Tue, 8 Aug 2017 18:33:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 303CD90905 Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:01 -0400 Message-Id: <20170808183306.27474-5-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 08 Aug 2017 18:33:14 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 4/9] ATAPI: Replace DEBUG_IDE_ATAPI with tracing events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Goodbye, printfs. Hello, fancy printfs. Signed-off-by: John Snow Reviewed-by: Eric Blake --- hw/ide/atapi.c | 64 +++++++++++++++++--------------------------= ---- hw/ide/trace-events | 19 ++++++++++++++ include/hw/ide/internal.h | 1 - 3 files changed, 42 insertions(+), 42 deletions(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index fc1d19c..37fa699 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -27,6 +27,7 @@ #include "hw/ide/internal.h" #include "hw/scsi/scsi.h" #include "sysemu/block-backend.h" +#include "trace.h" =20 #define ATAPI_SECTOR_BITS (2 + BDRV_SECTOR_BITS) #define ATAPI_SECTOR_SIZE (1 << ATAPI_SECTOR_BITS) @@ -116,9 +117,7 @@ cd_read_sector_sync(IDEState *s) block_acct_start(blk_get_stats(s->blk), &s->acct, ATAPI_SECTOR_SIZE, BLOCK_ACCT_READ); =20 -#ifdef DEBUG_IDE_ATAPI - printf("cd_read_sector_sync: lba=3D%d\n", s->lba); -#endif + trace_cd_read_sector_sync(s->lba); =20 switch (s->cd_sector_size) { case 2048: @@ -152,9 +151,7 @@ static void cd_read_sector_cb(void *opaque, int ret) { IDEState *s =3D opaque; =20 -#ifdef DEBUG_IDE_ATAPI - printf("cd_read_sector_cb: lba=3D%d ret=3D%d\n", s->lba, ret); -#endif + trace_cd_read_sector_cb(s->lba, ret); =20 if (ret < 0) { block_acct_failed(blk_get_stats(s->blk), &s->acct); @@ -188,9 +185,7 @@ static int cd_read_sector(IDEState *s) s->iov.iov_len =3D ATAPI_SECTOR_SIZE; qemu_iovec_init_external(&s->qiov, &s->iov, 1); =20 -#ifdef DEBUG_IDE_ATAPI - printf("cd_read_sector: lba=3D%d\n", s->lba); -#endif + trace_cd_read_sector(s->lba); =20 block_acct_start(blk_get_stats(s->blk), &s->acct, ATAPI_SECTOR_SIZE, BLOCK_ACCT_READ); @@ -213,9 +208,7 @@ void ide_atapi_cmd_ok(IDEState *s) =20 void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc) { -#ifdef DEBUG_IDE_ATAPI - printf("atapi_cmd_error: sense=3D0x%x asc=3D0x%x\n", sense_key, asc); -#endif + trace_ide_atapi_cmd_error(s, sense_key, asc); s->error =3D sense_key << 4; s->status =3D READY_STAT | ERR_STAT; s->nsector =3D (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REA= SON_CD; @@ -252,19 +245,14 @@ static uint16_t atapi_byte_count_limit(IDEState *s) void ide_atapi_cmd_reply_end(IDEState *s) { int byte_count_limit, size, ret; -#ifdef DEBUG_IDE_ATAPI - printf("reply: tx_size=3D%d elem_tx_size=3D%d index=3D%d\n", - s->packet_transfer_size, - s->elementary_transfer_size, - s->io_buffer_index); -#endif + trace_ide_atapi_cmd_reply_end(s, s->packet_transfer_size, + s->elementary_transfer_size, + s->io_buffer_index); if (s->packet_transfer_size <=3D 0) { /* end of transfer */ ide_atapi_cmd_ok(s); ide_set_irq(s->bus); -#ifdef DEBUG_IDE_ATAPI - printf("end of transfer, status=3D0x%x\n", s->status); -#endif + trace_ide_atapi_cmd_reply_end_eot(s, s->status); } else { /* see if a new sector must be read */ if (s->lba !=3D -1 && s->io_buffer_index >=3D s->cd_sector_size) { @@ -300,9 +288,7 @@ void ide_atapi_cmd_reply_end(IDEState *s) /* a new transfer is needed */ s->nsector =3D (s->nsector & ~7) | ATAPI_INT_REASON_IO; byte_count_limit =3D atapi_byte_count_limit(s); -#ifdef DEBUG_IDE_ATAPI - printf("byte_count_limit=3D%d\n", byte_count_limit); -#endif + trace_ide_atapi_cmd_reply_end_bcl(s, byte_count_limit); size =3D s->packet_transfer_size; if (size > byte_count_limit) { /* byte count limit must be even if this case */ @@ -324,9 +310,7 @@ void ide_atapi_cmd_reply_end(IDEState *s) ide_transfer_start(s, s->io_buffer + s->io_buffer_index - size, size, ide_atapi_cmd_reply_end); ide_set_irq(s->bus); -#ifdef DEBUG_IDE_ATAPI - printf("status=3D0x%x\n", s->status); -#endif + trace_ide_atapi_cmd_reply_end_new(s, s->status); } } } @@ -368,9 +352,7 @@ static void ide_atapi_cmd_read_pio(IDEState *s, int lba= , int nb_sectors, =20 static void ide_atapi_cmd_check_status(IDEState *s) { -#ifdef DEBUG_IDE_ATAPI - printf("atapi_cmd_check_status\n"); -#endif + trace_ide_atapi_cmd_check_status(s); s->error =3D MC_ERR | (UNIT_ATTENTION << 4); s->status =3D ERR_STAT; s->nsector =3D 0; @@ -477,10 +459,8 @@ static void ide_atapi_cmd_read_dma(IDEState *s, int lb= a, int nb_sectors, static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors, int sector_size) { -#ifdef DEBUG_IDE_ATAPI - printf("read %s: LBA=3D%d nb_sectors=3D%d\n", s->atapi_dma ? "dma" : "= pio", - lba, nb_sectors); -#endif + trace_ide_atapi_cmd_read(s, s->atapi_dma ? "dma" : "pio", + lba, nb_sectors); if (s->atapi_dma) { ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size); } else { @@ -1330,16 +1310,18 @@ void ide_atapi_cmd(IDEState *s) uint8_t *buf =3D s->io_buffer; const struct AtapiCmd *cmd =3D &atapi_cmd_table[s->io_buffer[0]]; =20 -#ifdef DEBUG_IDE_ATAPI - { + trace_ide_atapi_cmd(s, s->io_buffer[0]); + + if (TRACE_IDE_ATAPI_CMD_PACKET_ENABLED) { + /* Each pretty-printed byte needs two bytes and a space; */ + char *ppacket =3D g_malloc(ATAPI_PACKET_SIZE * 3 + 1); int i; - printf("ATAPI limit=3D0x%x packet:", s->lcyl | (s->hcyl << 8)); - for(i =3D 0; i < ATAPI_PACKET_SIZE; i++) { - printf(" %02x", buf[i]); + for (i =3D 0; i < ATAPI_PACKET_SIZE; i++) { + sprintf(ppacket + (i * 3), "%02x ", buf[i]); } - printf("\n"); + trace_ide_atapi_cmd_packet(s, s->lcyl | (s->hcyl << 8), ppacket); + g_free(ppacket); } -#endif =20 /* * If there's a UNIT_ATTENTION condition pending, only command flagged= with diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 6c156ac..ade1e76 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -6,6 +6,10 @@ ide_ioport_read(uint32_t addr, const char *reg, uint32_t v= al, void *bus, void *s ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, = void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState= %p" ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p;= IDEState %p" ide_cmd_write(uint32_t addr, uint32_t val, void *bus) = "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus= %p" +ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p;= IDEState %p" +ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO wr @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p;= IDEState %p" +ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p;= IDEState %p" +ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO wr @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p;= IDEState %p" # misc ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; = state %p; cmd 0x%02x" ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffe= red request %p with -ECANCELED" @@ -31,3 +35,18 @@ bmdma_write_cmd646(uint64_t addr, uint64_t val) "bmdma: = writeb 0x%"PRIx64" : 0x% # hw/ide/via.c bmdma_read_via(uint64_t addr, uint32_t val) "bmdma: readb 0x%"PRIx64" : 0x= %02x" bmdma_write_via(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : = 0x%02"PRIx64 + +# hw/ide/atapi.c +cd_read_sector_sync(int lba) "lba=3D%d" +cd_read_sector_cb(int lba, int ret) "lba=3D%d ret=3D%d" +cd_read_sector(int lba) "lba=3D%d" +ide_atapi_cmd_error(void *s, int sense_key, int asc) "IDEState: %p; sense= =3D0x%x asc=3D0x%x" +ide_atapi_cmd_reply_end(void *s, int tx_size, int elem_tx_size, int32_t in= dex) "IDEState %p; reply: tx_size=3D%d elem_tx_size=3D%d index=3D%"PRId32 +ide_atapi_cmd_reply_end_eot(void *s, int status) "IDEState: %p; end of tra= nsfer, status=3D0x%x" +ide_atapi_cmd_reply_end_bcl(void *s, int bcl) "IDEState: %p; byte_count_li= mit=3D%d" +ide_atapi_cmd_reply_end_new(void *s, int status) "IDEState: %p; new transf= er started, status=3D0x%x" +ide_atapi_cmd_check_status(void *s) "IDEState: %p" +ide_atapi_cmd_read(void *s, const char *method, int lba, int nb_sectors) "= IDEState: %p; read %s: LBA=3D%d nb_sectors=3D%d" +ide_atapi_cmd(void *s, uint8_t cmd) "IDEState: %p; cmd: 0x%02x" +# Warning: Verbose +ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEStat= e: %p; limit=3D0x%x packet: %s" \ No newline at end of file diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 4a92f0a..74efe8a 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -14,7 +14,6 @@ #include "block/scsi.h" =20 /* debug IDE devices */ -//#define DEBUG_IDE_ATAPI //#define DEBUG_AIO #define USE_DMA_CDROM =20 --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 08 Aug 2017 14:33:16 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E526CC0003B7; Tue, 8 Aug 2017 18:33:14 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5C8B660464; Tue, 8 Aug 2017 18:33:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com E526CC0003B7 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:02 -0400 Message-Id: <20170808183306.27474-6-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 08 Aug 2017 18:33:15 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 5/9] IDE: replace DEBUG_AIO with trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/atapi.c | 5 +---- hw/ide/core.c | 17 ++++++++++------- hw/ide/trace-events | 3 +++ include/hw/ide/internal.h | 7 +++++-- 4 files changed, 19 insertions(+), 13 deletions(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index 37fa699..b8fc51e 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -416,10 +416,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, in= t ret) s->io_buffer_size =3D n * 2048; data_offset =3D 0; } -#ifdef DEBUG_AIO - printf("aio_read_cd: lba=3D%u n=3D%d\n", s->lba, n); -#endif - + trace_ide_atapi_cmd_read_dma_cb_aio(s, s->lba, n); s->bus->dma->iov.iov_base =3D (void *)(s->io_buffer + data_offset); s->bus->dma->iov.iov_len =3D n * ATAPI_SECTOR_SIZE; qemu_iovec_init_external(&s->bus->dma->qiov, &s->bus->dma->iov, 1); diff --git a/hw/ide/core.c b/hw/ide/core.c index 29848ff..1358029 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -58,6 +58,13 @@ static const int smart_attributes[][12] =3D { { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x= 32}, }; =20 +const char *IDE_DMA_CMD_lookup[IDE_DMA__END] =3D { + [IDE_DMA_READ] =3D "DMA_READ", + [IDE_DMA_WRITE] =3D "DMA_WRITE", + [IDE_DMA_TRIM] =3D "DMA TRIM", + [IDE_DMA_ATAPI] =3D "DMA ATAPI" +}; + static void ide_dummy_transfer_stop(IDEState *s); =20 static void padstr(char *str, const char *src, int len) @@ -860,10 +867,8 @@ static void ide_dma_cb(void *opaque, int ret) goto eot; } =20 -#ifdef DEBUG_AIO - printf("ide_dma_cb: sector_num=3D%" PRId64 " n=3D%d, cmd_cmd=3D%d\n", - sector_num, n, s->dma_cmd); -#endif + trace_ide_dma_cb(s, sector_num, n, + IDE_DMA_CMD_lookup[s->dma_cmd]); =20 if ((s->dma_cmd =3D=3D IDE_DMA_READ || s->dma_cmd =3D=3D IDE_DMA_WRITE= ) && !ide_sect_range_ok(s, sector_num, n)) { @@ -2383,9 +2388,7 @@ void ide_bus_reset(IDEBus *bus) =20 /* pending async DMA */ if (bus->dma->aiocb) { -#ifdef DEBUG_AIO - printf("aio_cancel\n"); -#endif + trace_ide_bus_reset_aio(); blk_aio_cancel(bus->dma->aiocb); bus->dma->aiocb =3D NULL; } diff --git a/hw/ide/trace-events b/hw/ide/trace-events index ade1e76..6e33cb3 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -17,6 +17,8 @@ ide_cancel_dma_sync_remaining(void) "draining all remaini= ng requests" ide_sector_read(int64_t sector_num, int nsectors) "sector=3D%"PRId64" nsec= tors=3D%d" ide_sector_write(int64_t sector_num, int nsectors) "sector=3D%"PRId64" nse= ctors=3D%d" ide_reset(void *s) "IDEstate %p" +ide_bus_reset_aio(void) "aio_cancel" +ide_dma_cb(void *s, int64_t sector_num, int n, const char *dma) "IDEState = %p; sector_num=3D%"PRId64" n=3D%d cmd=3D%s" =20 # hw/ide/pci.c bmdma_reset(void) "" @@ -48,5 +50,6 @@ ide_atapi_cmd_reply_end_new(void *s, int status) "IDEStat= e: %p; new transfer sta ide_atapi_cmd_check_status(void *s) "IDEState: %p" ide_atapi_cmd_read(void *s, const char *method, int lba, int nb_sectors) "= IDEState: %p; read %s: LBA=3D%d nb_sectors=3D%d" ide_atapi_cmd(void *s, uint8_t cmd) "IDEState: %p; cmd: 0x%02x" +ide_atapi_cmd_read_dma_cb_aio(void *s, int lba, int n) "IDEState: %p; aio = read: lba=3D%d n=3D%d" # Warning: Verbose ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEStat= e: %p; limit=3D0x%x packet: %s" \ No newline at end of file diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 74efe8a..97e97a2 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -14,7 +14,6 @@ #include "block/scsi.h" =20 /* debug IDE devices */ -//#define DEBUG_AIO #define USE_DMA_CDROM =20 typedef struct IDEBus IDEBus; @@ -333,12 +332,16 @@ struct unreported_events { }; =20 enum ide_dma_cmd { - IDE_DMA_READ, + IDE_DMA__BEGIN =3D 0, + IDE_DMA_READ =3D IDE_DMA__BEGIN, IDE_DMA_WRITE, IDE_DMA_TRIM, IDE_DMA_ATAPI, + IDE_DMA__END }; =20 +extern const char *IDE_DMA_CMD_lookup[IDE_DMA__END]; + #define ide_cmd_is_read(s) \ ((s)->dma_cmd =3D=3D IDE_DMA_READ) =20 --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502217711316864.5612007527533; Tue, 8 Aug 2017 11:41:51 -0700 (PDT) Received: from localhost ([::1]:44059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Rt-00054d-U1 for importer@patchew.org; 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Tue, 8 Aug 2017 18:33:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B297511471D Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:03 -0400 Message-Id: <20170808183306.27474-7-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 08 Aug 2017 18:33:15 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 6/9] AHCI: Replace DPRINTF with trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are a few hangers-on that will be dealt with individually in forthcoming patches. Signed-off-by: John Snow --- hw/ide/ahci.c | 157 +++++++++++++++++++++++-------------------------= ---- hw/ide/trace-events | 52 ++++++++++++++++- 2 files changed, 119 insertions(+), 90 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 406a1b5..d5acceb 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -35,6 +35,7 @@ #include "hw/ide/ahci_internal.h" =20 #define DEBUG_AHCI 0 +#include "trace.h" =20 #define DPRINTF(port, fmt, ...) \ do { \ @@ -114,9 +115,9 @@ static uint32_t ahci_port_read(AHCIState *s, int port,= int offset) default: val =3D 0; } - DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); - return val; =20 + trace_ahci_port_read(s, port, offset, val); + return val; } =20 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) @@ -125,7 +126,7 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *de= v) PCIDevice *pci_dev =3D (PCIDevice *) object_dynamic_cast(OBJECT(dev_st= ate), TYPE_PCI_DEVICE= ); =20 - DPRINTF(0, "raise irq\n"); + trace_ahci_irq_raise(s); =20 if (pci_dev && msi_enabled(pci_dev)) { msi_notify(pci_dev, 0); @@ -140,7 +141,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *de= v) PCIDevice *pci_dev =3D (PCIDevice *) object_dynamic_cast(OBJECT(dev_st= ate), TYPE_PCI_DEVICE= ); =20 - DPRINTF(0, "lower irq\n"); + trace_ahci_irq_lower(s); =20 if (!pci_dev || !msi_enabled(pci_dev)) { qemu_irq_lower(s->irq); @@ -150,8 +151,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *de= v) static void ahci_check_irq(AHCIState *s) { int i; - - DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); + uint32_t old_irq =3D s->control_regs.irqstatus; =20 s->control_regs.irqstatus =3D 0; for (i =3D 0; i < s->ports; i++) { @@ -160,7 +160,7 @@ static void ahci_check_irq(AHCIState *s) s->control_regs.irqstatus |=3D (1 << i); } } - + trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); if (s->control_regs.irqstatus && (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { ahci_irq_raise(s, NULL); @@ -240,7 +240,7 @@ static void ahci_port_write(AHCIState *s, int port, in= t offset, uint32_t val) { AHCIPortRegs *pr =3D &s->dev[port].port_regs; =20 - DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); + trace_ahci_port_write(s, port, offset, val); switch (offset) { case PORT_LST_ADDR: pr->lst_addr =3D val; @@ -341,8 +341,6 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr a= ddr) val =3D s->control_regs.version; break; } - - DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); } else if ((addr >=3D AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { @@ -350,6 +348,7 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr a= ddr) addr & AHCI_PORT_ADDR_OFFSET_MASK); } =20 + trace_ahci_mem_read_32(s, addr, val); return val; } =20 @@ -379,8 +378,7 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr= , unsigned size) val =3D (hi << 32 | lo) >> (ofst * 8); } =20 - DPRINTF(-1, "addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx64 ", size=3D%d\= n", - addr, val, size); + trace_ahci_mem_read(opaque, size, addr, val); return val; } =20 @@ -390,8 +388,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr, { AHCIState *s =3D opaque; =20 - DPRINTF(-1, "addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx64 ", size=3D%d\= n", - addr, val, size); + trace_ahci_mem_write(s, size, addr, val); =20 /* Only aligned reads are allowed on AHCI */ if (addr & 3) { @@ -401,15 +398,12 @@ static void ahci_mem_write(void *opaque, hwaddr addr, } =20 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { - DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr,= val); - switch (addr) { case HOST_CAP: /* R/WO, RO */ /* FIXME handle R/WO */ break; case HOST_CTL: /* R/W */ if (val & HOST_CTL_RESET) { - DPRINTF(-1, "HBA Reset\n"); ahci_reset(s); } else { s->control_regs.ghc =3D (val & 0x3) | HOST_CTL_AHCI_EN; @@ -427,7 +421,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr, /* FIXME report write? */ break; default: - DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)= addr); + trace_ahci_mem_write_unknown(s, addr); } } else if ((addr >=3D AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + @@ -559,7 +553,8 @@ static void ahci_set_signature(AHCIDevice *ad, uint32_t= sig) s->sector =3D sig >> 8 & 0xFF; s->nsector =3D sig & 0xFF; =20 - DPRINTF(ad->port_no, "set hcyl:lcyl:sect:nsect =3D 0x%08x\n", sig); + trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, + s->lcyl, s->hcyl, sig); } =20 static void ahci_reset_port(AHCIState *s, int port) @@ -569,7 +564,7 @@ static void ahci_reset_port(AHCIState *s, int port) IDEState *ide_state =3D &d->port.ifs[0]; int i; =20 - DPRINTF(port, "reset port\n"); + trace_ahci_reset_port(s, port); =20 ide_bus_reset(&d->port); ide_state->ncq_queues =3D AHCI_MAX_CMDS; @@ -655,7 +650,7 @@ static bool ahci_map_fis_address(AHCIDevice *ad) static void ahci_unmap_fis_address(AHCIDevice *ad) { if (ad->res_fis =3D=3D NULL) { - DPRINTF(ad->port_no, "Attempt to unmap NULL FIS address\n"); + trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); return; } ad->port_regs.cmd &=3D ~PORT_CMD_FIS_ON; @@ -682,7 +677,7 @@ static bool ahci_map_clb_address(AHCIDevice *ad) static void ahci_unmap_clb_address(AHCIDevice *ad) { if (ad->lst =3D=3D NULL) { - DPRINTF(ad->port_no, "Attempt to unmap NULL CLB address\n"); + trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); return; } ad->port_regs.cmd &=3D ~PORT_CMD_LIST_ON; @@ -854,20 +849,22 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUS= GList *sglist, IDEBus *bus =3D &ad->port; BusState *qbus =3D BUS(bus); =20 + trace_ahci_populate_sglist(ad->hba, ad->port_no); + if (!prdtl) { - DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); + trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); return -1; } =20 /* map PRDT */ if (!(prdt =3D dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, DMA_DIRECTION_TO_DEVICE))){ - DPRINTF(ad->port_no, "map failed\n"); + trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); return -1; } =20 if (prdt_len < real_prdt_len) { - DPRINTF(ad->port_no, "mapped less than expected\n"); + trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); r =3D -1; goto out; } @@ -886,9 +883,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGL= ist *sglist, sum +=3D tbl_entry_size; } if ((off_idx =3D=3D -1) || (off_pos < 0) || (off_pos > tbl_entry_s= ize)) { - DPRINTF(ad->port_no, "%s: Incorrect offset! " - "off_idx: %d, off_pos: %"PRId64"\n", - __func__, off_idx, off_pos); + trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, + off_idx, off_pos); r =3D -1; goto out; } @@ -934,8 +930,8 @@ static void ncq_finish(NCQTransferState *ncq_tfs) =20 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); =20 - DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", - ncq_tfs->tag); + trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, + ncq_tfs->tag); =20 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), &ncq_tfs->acct); @@ -999,12 +995,8 @@ static void execute_ncq_command(NCQTransferState *ncq_= tfs) =20 switch (ncq_tfs->cmd) { case READ_FPDMA_QUEUED: - DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", tag %d\n= ", - ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag); - - DPRINTF(port, "tag %d aio read %"PRId64"\n", - ncq_tfs->tag, ncq_tfs->lba); - + trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, + ncq_tfs->sector_count, ncq_tfs->lba= ); dma_acct_start(ide_state->blk, &ncq_tfs->acct, &ncq_tfs->sglist, BLOCK_ACCT_READ); ncq_tfs->aiocb =3D dma_blk_read(ide_state->blk, &ncq_tfs->sglist, @@ -1013,12 +1005,8 @@ static void execute_ncq_command(NCQTransferState *nc= q_tfs) ncq_cb, ncq_tfs); break; case WRITE_FPDMA_QUEUED: - DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", - ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag); - - DPRINTF(port, "tag %d aio write %"PRId64"\n", - ncq_tfs->tag, ncq_tfs->lba); - + trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, + ncq_tfs->sector_count, ncq_tfs->lba= ); dma_acct_start(ide_state->blk, &ncq_tfs->acct, &ncq_tfs->sglist, BLOCK_ACCT_WRITE); ncq_tfs->aiocb =3D dma_blk_write(ide_state->blk, &ncq_tfs->sglist, @@ -1027,8 +1015,8 @@ static void execute_ncq_command(NCQTransferState *ncq= _tfs) ncq_cb, ncq_tfs); break; default: - DPRINTF(port, "error: unsupported NCQ command (0x%02x) received\n", - ncq_tfs->cmd); + trace_execute_ncq_command_unsup(ad->hba, port, + ncq_tfs->tag, ncq_tfs->cmd); ncq_err(ncq_tfs); } } @@ -1038,7 +1026,6 @@ static void process_ncq_command(AHCIState *s, int por= t, uint8_t *cmd_fis, uint8_t slot) { AHCIDevice *ad =3D &s->dev[port]; - IDEState *ide_state =3D &ad->port.ifs[0]; NCQFrame *ncq_fis =3D (NCQFrame*)cmd_fis; uint8_t tag =3D ncq_fis->tag >> 3; NCQTransferState *ncq_tfs =3D &ad->ncq_tfs[tag]; @@ -1066,21 +1053,20 @@ static void process_ncq_command(AHCIState *s, int p= ort, uint8_t *cmd_fis, =20 /* Sanity-check the NCQ packet */ if (tag !=3D slot) { - DPRINTF(port, "Warn: NCQ slot (%d) did not match the given tag (%d= )\n", - slot, tag); + trace_process_ncq_command_mismatch(s, port, tag, slot); } =20 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { - DPRINTF(port, "Warn: Attempt to use NCQ auxiliary fields.\n"); + trace_process_ncq_command_aux(s, port, tag); } if (ncq_fis->prio || ncq_fis->icc) { - DPRINTF(port, "Warn: Unsupported attempt to use PRIO/ICC fields\n"= ); + trace_process_ncq_command_prioicc(s, port, tag); } if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { - DPRINTF(port, "Warn: Unsupported attempt to use Force Unit Access\= n"); + trace_process_ncq_command_fua(s, port, tag); } if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { - DPRINTF(port, "Warn: Unsupported attempt to use Rebuild Assist\n"); + trace_process_ncq_command_rarc(s, port, tag); } =20 ncq_tfs->sector_count =3D ((ncq_fis->sector_count_high << 8) | @@ -1099,16 +1085,14 @@ static void process_ncq_command(AHCIState *s, int p= ort, uint8_t *cmd_fis, ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW); return; } else if (ncq_tfs->sglist.size !=3D size) { - DPRINTF(port, "Warn: PRDTL (0x%zx)" - " does not match requested size (0x%zx)", - ncq_tfs->sglist.size, size); + trace_process_ncq_command_large(s, port, tag, + ncq_tfs->sglist.size, size); } =20 - DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " - "drive max %"PRId64"\n", - ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 1, - ide_state->nb_sectors - 1); - + trace_process_ncq_command(s, port, tag, + ncq_fis->command, + ncq_tfs->lba, + ncq_tfs->lba + ncq_tfs->sector_count - 1); execute_ncq_command(ncq_tfs); } =20 @@ -1129,16 +1113,14 @@ static void handle_reg_h2d_fis(AHCIState *s, int po= rt, uint16_t opts =3D le16_to_cpu(cmd->opts); =20 if (cmd_fis[1] & 0x0F) { - DPRINTF(port, "Port Multiplier not supported." - " cmd_fis[0]=3D%02x cmd_fis[1]=3D%02x cmd_fis[2]=3D%02x\n", - cmd_fis[0], cmd_fis[1], cmd_fis[2]); + trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], + cmd_fis[2], cmd_fis[3]); return; } =20 if (cmd_fis[1] & 0x70) { - DPRINTF(port, "Reserved flags set in H2D Register FIS." - " cmd_fis[0]=3D%02x cmd_fis[1]=3D%02x cmd_fis[2]=3D%02x\n", - cmd_fis[0], cmd_fis[1], cmd_fis[2]); + trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], + cmd_fis[2], cmd_fis[3]); return; } =20 @@ -1216,12 +1198,12 @@ static int handle_cmd(AHCIState *s, int port, uint8= _t slot) =20 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { /* Engine currently busy, try again later */ - DPRINTF(port, "engine busy\n"); + trace_handle_cmd_busy(s, port); return -1; } =20 if (!s->dev[port].lst) { - DPRINTF(port, "error: lst not given but cmd handled"); + trace_handle_cmd_nolist(s, port); return -1; } cmd =3D get_cmd_header(s, port, slot); @@ -1231,7 +1213,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t= slot) /* The device we are working for */ ide_state =3D &s->dev[port].port.ifs[0]; if (!ide_state->blk) { - DPRINTF(port, "error: guest accessed unused port"); + trace_handle_cmd_badport(s, port); return -1; } =20 @@ -1240,13 +1222,11 @@ static int handle_cmd(AHCIState *s, int port, uint8= _t slot) cmd_fis =3D dma_memory_map(s->as, tbl_addr, &cmd_len, DMA_DIRECTION_FROM_DEVICE); if (!cmd_fis) { - DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); + trace_handle_cmd_badfis(s, port); return -1; } else if (cmd_len !=3D 0x80) { ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR); - DPRINTF(port, "error: dma_memory_map failed: " - "(len(%02"PRIx64") !=3D 0x80)\n", - cmd_len); + trace_handle_cmd_badmap(s, port, cmd_len); goto out; } debug_print_fis(cmd_fis, 0x80); @@ -1256,9 +1236,8 @@ static int handle_cmd(AHCIState *s, int port, uint8_t= slot) handle_reg_h2d_fis(s, port, slot, cmd_fis); break; default: - DPRINTF(port, "unknown command cmd_fis[0]=3D%02x cmd_fis[1]=3D= %02x " - "cmd_fis[2]=3D%02x\n", cmd_fis[0], cmd_fis[1], - cmd_fis[2]); + trace_handle_cmd_unhandled_fis(s, port, + cmd_fis[0], cmd_fis[1], cmd_fis= [2]); break; } =20 @@ -1299,9 +1278,9 @@ static void ahci_start_transfer(IDEDMA *dma) has_sglist =3D 1; } =20 - DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", - is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", - has_sglist ? "" : "o"); + trace_ahci_start_transfer(ad->hba, ad->port_no, is_write ? "writ" : "r= ead", + size, is_atapi ? "atapi" : "ata", + has_sglist ? "" : "o"); =20 if (has_sglist && size) { if (is_write) { @@ -1330,7 +1309,7 @@ static void ahci_start_dma(IDEDMA *dma, IDEState *s, BlockCompletionFunc *dma_cb) { AHCIDevice *ad =3D DO_UPCAST(AHCIDevice, dma, dma); - DPRINTF(ad->port_no, "\n"); + trace_ahci_start_dma(ad->hba, ad->port_no); s->io_buffer_offset =3D 0; dma_cb(s, 0); } @@ -1368,12 +1347,12 @@ static int32_t ahci_dma_prepare_buf(IDEDMA *dma, in= t32_t limit) =20 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, limit, s->io_buffer_offset) =3D=3D -1) { - DPRINTF(ad->port_no, "ahci_dma_prepare_buf failed.\n"); + trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); return -1; } s->io_buffer_size =3D s->sg.size; =20 - DPRINTF(ad->port_no, "len=3D%#x\n", s->io_buffer_size); + trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_s= ize); return s->io_buffer_size; } =20 @@ -1409,11 +1388,9 @@ static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) =20 /* free sglist, update byte count */ dma_buf_commit(s, l); - s->io_buffer_index +=3D l; =20 - DPRINTF(ad->port_no, "len=3D%#x\n", l); - + trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); return 1; } =20 @@ -1421,7 +1398,7 @@ static void ahci_cmd_done(IDEDMA *dma) { AHCIDevice *ad =3D DO_UPCAST(AHCIDevice, dma, dma); =20 - DPRINTF(ad->port_no, "cmd done\n"); + trace_ahci_cmd_done(ad->hba, ad->port_no); =20 /* update d2h status */ ahci_write_fis_d2h(ad); @@ -1505,6 +1482,8 @@ void ahci_reset(AHCIState *s) AHCIPortRegs *pr; int i; =20 + trace_ahci_reset(s); + s->control_regs.irqstatus =3D 0; /* AHCI Enable (AE) * The implementation of this bit is dependent upon the value of the @@ -1755,6 +1734,7 @@ static uint64_t allwinner_ahci_mem_read(void *opaque,= hwaddr addr, unsigned size) { AllwinnerAHCIState *a =3D opaque; + AHCIState *s =3D &(SYSBUS_AHCI(a)->ahci); uint64_t val =3D a->regs[addr/4]; =20 switch (addr / 4) { @@ -1765,8 +1745,7 @@ static uint64_t allwinner_ahci_mem_read(void *opaque,= hwaddr addr, val &=3D ~(0x1 << 24); break; } - DPRINTF(-1, "addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx64 ", size=3D%d\= n", - addr, val, size); + trace_allwinner_ahci_mem_read(s, a, addr, val, size); return val; } =20 @@ -1774,9 +1753,9 @@ static void allwinner_ahci_mem_write(void *opaque, hw= addr addr, uint64_t val, unsigned size) { AllwinnerAHCIState *a =3D opaque; + AHCIState *s =3D &(SYSBUS_AHCI(a)->ahci); =20 - DPRINTF(-1, "addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx64 ", size=3D%d\= n", - addr, val, size); + trace_allwinner_ahci_mem_write(s, a, addr, val, size); a->regs[addr/4] =3D val; } =20 diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 6e33cb3..e1a0457 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -52,4 +52,54 @@ ide_atapi_cmd_read(void *s, const char *method, int lba,= int nb_sectors) "IDESta ide_atapi_cmd(void *s, uint8_t cmd) "IDEState: %p; cmd: 0x%02x" ide_atapi_cmd_read_dma_cb_aio(void *s, int lba, int n) "IDEState: %p; aio = read: lba=3D%d n=3D%d" # Warning: Verbose -ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEStat= e: %p; limit=3D0x%x packet: %s" \ No newline at end of file +ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEStat= e: %p; limit=3D0x%x packet: %s" + +# hw/ide/ahci.c +ahci_port_read(void *s, int port, int offset, uint32_t ret) "ahci(%p)[%d]:= port read @ 0x%x: 0x%08x" +ahci_irq_raise(void *s) "ahci(%p): raise irq" +ahci_irq_lower(void *s) "ahci(%p): lower irq" +ahci_check_irq(void *s, uint32_t old, uint32_t new) "ahci(%p): check irq 0= x%08x --> 0x%08x" + +ahci_port_write(void *s, int port, int offset, uint32_t val) "ahci(%p)[%d]= : port write @ 0x%x: 0x%08x" +ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) "ahci(%p): mem read= @ 0x%"PRIx64": 0x%08x" +ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(%= p): read%u @ 0x%"PRIx64": 0x%016"PRIx64 +ahci_mem_write(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(= %p): write%u @ 0x%"PRIx64": 0x%016"PRIx64 +ahci_mem_write_unknown(void *s, uint64_t addr) "ahci(%p): write to unknown= register 0x%"PRIx64 +ahci_set_signature(void *s, int port, uint8_t nsector, uint8_t sector, uin= t8_t lcyl, uint8_t hcyl, uint32_t sig) "ahci(%p)[%d]: set signature sector:= 0x%02x nsector:0x%02x lcyl:0x%02x hcyl:0x%02x (cumulatively: 0x%08x)" +ahci_reset_port(void *s, int port) "ahci(%p)[%d]: reset port" +ahci_unmap_fis_address_null(void *s, int port) "ahci(%p)[%d]: Attempt to u= nmap NULL FIS address" +ahci_unmap_clb_address_null(void *s, int port) "ahci(%p)[%d]: Attempt to u= nmap NULL CLB address" +ahci_populate_sglist(void *s, int port) "ahci(%p)[%d]" +ahci_populate_sglist_no_prdtl(void *s, int port, uint16_t opts) "ahci(%p)[= %d]: no sg list given by guest: 0x%04x" +ahci_populate_sglist_no_map(void *s, int port) "ahci(%p)[%d]: DMA mapping = failed" +ahci_populate_sglist_short_map(void *s, int port) "ahci(%p)[%d]: mapped le= ss than expected" +ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t of= f_pos) "ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %"PRId64 +ncq_finish(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: NCQ tran= sfer finished" +execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_= t lba) "ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %"PRId64 +execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64= _t lba) "ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %"PRId64 +execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) "ah= ci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received" +process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot)= "ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag" +process_ncq_command_aux(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:= %d]: Warn: Attempt to use NCQ auxiliary fields" +process_ncq_command_prioicc(void *s, int port, uint8_t tag) "ahci(%p)[%d][= tag:%d]: Warn: Unsupported attempt to use PRIO/ICC fields" +process_ncq_command_fua(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:= %d]: Warn: Unsupported attempt to use Force Unit Access" +process_ncq_command_rarc(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag= :%d]: Warn: Unsupported attempt to use Rebuild Assist" +process_ncq_command_large(void *s, int port, uint8_t tag, size_t prdtl, si= ze_t size) "ahci(%p)[%d][tag:%d]: Warn: PRDTL (0x%zx) does not match reques= ted size (0x%zx)" +process_ncq_command(void *s, int port, uint8_t tag, uint8_t cmd, uint64_t = lba, uint64_t end) "ahci(%p)[%d][tag:%d]: NCQ op 0x%02x on sectors [%"PRId6= 4",%"PRId64"]" +handle_reg_h2d_fis_pmp(void *s, int port, char b0, char b1, char b2) "ahci= (%p)[%d]: Port Multiplier not supported, FIS: 0x%02x-%02x-%02x" +handle_reg_h2d_fis_res(void *s, int port, char b0, char b1, char b2) "ahci= (%p)[%d]: Reserved flags set in H2D Register FIS, FIS: 0x%02x-%02x-%02x" +handle_cmd_busy(void *s, int port) "ahci(%p)[%d]: engine busy" +handle_cmd_nolist(void *s, int port) "ahci(%p)[%d]: handle_cmd called with= out s->dev[port].lst" +handle_cmd_badport(void *s, int port) "ahci(%p)[%d]: guest accessed unused= port" +handle_cmd_badfis(void *s, int port) "ahci(%p)[%d]: guest provided an inva= lid cmd FIS" +handle_cmd_badmap(void *s, int port, uint64_t len) "ahci(%p)[%d]: dma_memo= ry_map failed, 0x%02"PRIx64" !=3D 0x80" +handle_cmd_unhandled_fis(void *s, int port, uint8_t b0, uint8_t b1, uint8_= t b2) "ahci(%p)[%d]: unhandled FIS type. cmd_fis: 0x%02x-%02x-%02x" +ahci_start_transfer(void *s, int port, const char *rw, uint32_t size, cons= t char *tgt, const char *sgl) "ahci(%p)[%d]: %sing %d bytes on %s w/%s sgli= st" +ahci_start_dma(void *s, int port) "ahci(%p)[%d]: start dma" +ahci_dma_prepare_buf(void *s, int port, int32_t io_buffer_size, int32_t li= mit) "ahci(%p)[%d]: prepare buf limit=3D%"PRId32" prepared=3D%"PRId32 +ahci_dma_prepare_buf_fail(void *s, int port) "ahci(%p)[%d]: sglist populat= ion failed" +ahci_dma_rw_buf(void *s, int port, int l) "ahci(%p)[%d] len=3D0x%x" +ahci_cmd_done(void *s, int port) "ahci(%p)[%d]: cmd done" +ahci_reset(void *s) "ahci(%p): HBA reset" +allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, uns= igned size) "ahci(%p): read a=3D%p addr=3D0x%"HWADDR_PRIx" val=3D0x%"PRIx64= ", size=3D%d" +allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, un= signed size) "ahci(%p): write a=3D%p addr=3D0x%"HWADDR_PRIx" val=3D0x%"PRIx= 64", size=3D%d" + --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org 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(int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6B1C2539EE; Tue, 8 Aug 2017 18:33:16 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id DD1AE60464; Tue, 8 Aug 2017 18:33:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 6B1C2539EE Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:04 -0400 Message-Id: <20170808183306.27474-8-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 08 Aug 2017 18:33:16 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 7/9] AHCI: Rework IRQ constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Create a new enum so that we can name the IRQ bits, which will make debuggi= ng them a little nicer if we can print them out. Not handled in this patch, but this will make it possible to get a nice debug printf detailing exactly whi= ch status bits are set, as it can be multiple at any given time. As a consequence of this patch, it is no longer possible to set multiple IRQ codes at once, but nothing was utilizing this ability anyway. Signed-off-by: John Snow --- hw/ide/ahci.c | 49 ++++++++++++++++++++++++++++++++++++++--------= --- hw/ide/ahci_internal.h | 44 +++++++++++++++++++++++++++++++++++--------- hw/ide/trace-events | 2 +- 3 files changed, 74 insertions(+), 21 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index d5acceb..c5a9b69 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad); static void ahci_unmap_clb_address(AHCIDevice *ad); static void ahci_unmap_fis_address(AHCIDevice *ad); =20 +static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] =3D { + [AHCI_PORT_IRQ_BIT_DHRS] =3D "DHRS", + [AHCI_PORT_IRQ_BIT_PSS] =3D "PSS", + [AHCI_PORT_IRQ_BIT_DSS] =3D "DSS", + [AHCI_PORT_IRQ_BIT_SDBS] =3D "SDBS", + [AHCI_PORT_IRQ_BIT_UFS] =3D "UFS", + [AHCI_PORT_IRQ_BIT_DPS] =3D "DPS", + [AHCI_PORT_IRQ_BIT_PCS] =3D "PCS", + [AHCI_PORT_IRQ_BIT_DMPS] =3D "DMPS", + [8 ... 21] =3D "RESERVED", + [AHCI_PORT_IRQ_BIT_PRCS] =3D "PRCS", + [AHCI_PORT_IRQ_BIT_IPMS] =3D "IPMS", + [AHCI_PORT_IRQ_BIT_OFS] =3D "OFS", + [25] =3D "RESERVED", + [AHCI_PORT_IRQ_BIT_INFS] =3D "INFS", + [AHCI_PORT_IRQ_BIT_IFS] =3D "IFS", + [AHCI_PORT_IRQ_BIT_HBDS] =3D "HBDS", + [AHCI_PORT_IRQ_BIT_HBFS] =3D "HBFS", + [AHCI_PORT_IRQ_BIT_TFES] =3D "TFES", + [AHCI_PORT_IRQ_BIT_CPDS] =3D "CPDS" +}; =20 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) { @@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s) } =20 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, - int irq_type) + enum AHCIPortIRQ irqbit) { - DPRINTF(d->port_no, "trigger irq %#x -> %x\n", - irq_type, d->port_regs.irq_mask & irq_type); + g_assert(irqbit >=3D 0 && irqbit < 32); + uint32_t irq =3D 1U << irqbit; + uint32_t irqstat =3D d->port_regs.irq_stat | irq; =20 - d->port_regs.irq_stat |=3D irq_type; + trace_ahci_trigger_irq(s, d->port_no, + AHCIPortIRQ_lookup[irqbit], irq, + d->port_regs.irq_stat, irqstat, + irqstat & d->port_regs.irq_mask); + + d->port_regs.irq_stat =3D irqstat; ahci_check_irq(s); } =20 @@ -718,7 +745,7 @@ static void ahci_write_fis_sdb(AHCIState *s, NCQTransfe= rState *ncq_tfs) =20 /* Trigger IRQ if interrupt bit is set (which currently, it always is)= */ if (sdb_fis->flags & 0x40) { - ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS); + ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); } } =20 @@ -761,10 +788,10 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16= _t len) ad->port.ifs[0].status; =20 if (pio_fis[2] & ERR_STAT) { - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); } =20 - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS); + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); } =20 static bool ahci_write_fis_d2h(AHCIDevice *ad) @@ -804,10 +831,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad) ad->port.ifs[0].status; =20 if (d2h_fis[2] & ERR_STAT) { - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); } =20 - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); return true; } =20 @@ -1082,7 +1109,7 @@ static void process_ncq_command(AHCIState *s, int por= t, uint8_t *cmd_fis, "is smaller than the requested size (0x%zx)", ncq_tfs->sglist.size, size); ncq_err(ncq_tfs); - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW); + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); return; } else if (ncq_tfs->sglist.size !=3D size) { trace_process_ncq_command_large(s, port, tag, @@ -1225,7 +1252,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t= slot) trace_handle_cmd_badfis(s, port); return -1; } else if (cmd_len !=3D 0x80) { - ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR); + ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); trace_handle_cmd_badmap(s, port, cmd_len); goto out; } diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 1e21169..7e67add 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -91,6 +91,31 @@ #define PORT_CMD_ISSUE 0x38 /* command issue */ #define PORT_RESERVED 0x3c /* reserved */ =20 +/* Port interrupt bit descriptors */ +enum AHCIPortIRQ { + AHCI_PORT_IRQ_BIT_DHRS =3D 0, + AHCI_PORT_IRQ_BIT_PSS =3D 1, + AHCI_PORT_IRQ_BIT_DSS =3D 2, + AHCI_PORT_IRQ_BIT_SDBS =3D 3, + AHCI_PORT_IRQ_BIT_UFS =3D 4, + AHCI_PORT_IRQ_BIT_DPS =3D 5, + AHCI_PORT_IRQ_BIT_PCS =3D 6, + AHCI_PORT_IRQ_BIT_DMPS =3D 7, + /* RESERVED */ + AHCI_PORT_IRQ_BIT_PRCS =3D 22, + AHCI_PORT_IRQ_BIT_IPMS =3D 23, + AHCI_PORT_IRQ_BIT_OFS =3D 24, + /* RESERVED */ + AHCI_PORT_IRQ_BIT_INFS =3D 26, + AHCI_PORT_IRQ_BIT_IFS =3D 27, + AHCI_PORT_IRQ_BIT_HBDS =3D 28, + AHCI_PORT_IRQ_BIT_HBFS =3D 29, + AHCI_PORT_IRQ_BIT_TFES =3D 30, + AHCI_PORT_IRQ_BIT_CPDS =3D 31, + AHCI_PORT_IRQ__END =3D 32 +}; + + /* PORT_IRQ_{STAT,MASK} bits */ #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */ #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ @@ -98,18 +123,19 @@ #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ + /* reserved */ #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/= G */ #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ - #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ -#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ -#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ -#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ -#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ -#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ -#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ -#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ -#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + /* reserved */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status = */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ =20 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | = \ PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | = \ diff --git a/hw/ide/trace-events b/hw/ide/trace-events index e1a0457..5b321e1 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -59,7 +59,7 @@ ahci_port_read(void *s, int port, int offset, uint32_t re= t) "ahci(%p)[%d]: port ahci_irq_raise(void *s) "ahci(%p): raise irq" ahci_irq_lower(void *s) "ahci(%p): lower irq" ahci_check_irq(void *s, uint32_t old, uint32_t new) "ahci(%p): check irq 0= x%08x --> 0x%08x" - +ahci_trigger_irq(void *s, int port, const char *name, uint32_t val, uint32= _t old, uint32_t new, uint32_t effective) "ahci(%p)[%d]: trigger irq +%s (0= x%08x); irqstat: 0x%08x --> 0x%08x; effective: 0x%08x" ahci_port_write(void *s, int port, int offset, uint32_t val) "ahci(%p)[%d]= : port write @ 0x%x: 0x%08x" ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) "ahci(%p): mem read= @ 0x%"PRIx64": 0x%08x" ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(%= p): read%u @ 0x%"PRIx64": 0x%016"PRIx64 --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15022175056694.536192924949091; Tue, 8 Aug 2017 11:38:25 -0700 (PDT) Received: from localhost ([::1]:44040 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df9Oa-0001qU-Ez for importer@patchew.org; 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Tue, 8 Aug 2017 18:33:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2413F4DD4B Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:05 -0400 Message-Id: <20170808183306.27474-9-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 08 Aug 2017 18:33:17 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 8/9] AHCI: pretty-print FIS to buffer instead of stderr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The current FIS printing routines dump the FIS to screen. adjust this such that it dumps to buffer instead, then use this ability to have FIS dump mechanisms via trace-events instead of compiled defines. Signed-off-by: John Snow --- hw/ide/ahci.c | 54 +++++++++++++++++++++++++++++++++++++++++++------= ---- hw/ide/trace-events | 3 +++ 2 files changed, 47 insertions(+), 10 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index c5a9b69..1a4d4db 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -644,20 +644,45 @@ static void ahci_reset_port(AHCIState *s, int port) ahci_init_d2h(d); } =20 -static void debug_print_fis(uint8_t *fis, int cmd_len) +/* Buffer pretty output based on a raw FIS structure. */ +static void ahci_pretty_buffer_fis(uint8_t *fis, int cmd_len, char **out) { -#if DEBUG_AHCI + size_t bufsize; + char *pbuf; + char *pptr; + size_t lines =3D DIV_ROUND_UP(cmd_len, 16); + const char *preamble =3D "FIS:"; int i; =20 - fprintf(stderr, "fis:"); + /* Total amount of memory to store FISes in HBA memory */ + g_assert_cmpint(cmd_len, <=3D, 0x100); + g_assert(out); + + /* Printed like: + * FIS:\n + * 0x00: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee \n + * 0x10: ff \n + * \0 + * + * Four bytes for the preamble, seven for each line prefix (including a + * newline to start a new line), three bytes for each source byte, + * a trailing newline and a terminal null byte. + */ + + bufsize =3D strlen(preamble) + ((6 + 1) * lines) + (3 * cmd_len) + 1 += 1; + pbuf =3D g_malloc(bufsize); + pptr =3D pbuf; + pptr +=3D sprintf(pptr, "%s", preamble); for (i =3D 0; i < cmd_len; i++) { if ((i & 0xf) =3D=3D 0) { - fprintf(stderr, "\n%02x:",i); + pptr +=3D sprintf(pptr, "\n0x%02x: ", i); } - fprintf(stderr, "%02x ",fis[i]); + pptr +=3D sprintf(pptr, "%02x ", fis[i]); } - fprintf(stderr, "\n"); -#endif + pptr +=3D sprintf(pptr, "\n"); + pptr +=3D 1; /* \0 */ + g_assert(pbuf + bufsize =3D=3D pptr); + *out =3D pbuf; } =20 static bool ahci_map_fis_address(AHCIDevice *ad) @@ -1201,7 +1226,12 @@ static void handle_reg_h2d_fis(AHCIState *s, int por= t, * table to ide_state->io_buffer */ if (opts & AHCI_CMD_ATAPI) { memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x= 10); - debug_print_fis(ide_state->io_buffer, 0x10); + if (TRACE_HANDLE_REG_H2D_FIS_DUMP_ENABLED) { + char *pretty_fis; + ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10, &pretty_fis= ); + trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); + g_free(pretty_fis); + } s->dev[port].done_atapi_packet =3D false; /* XXX send PIO setup FIS */ } @@ -1256,8 +1286,12 @@ static int handle_cmd(AHCIState *s, int port, uint8_= t slot) trace_handle_cmd_badmap(s, port, cmd_len); goto out; } - debug_print_fis(cmd_fis, 0x80); - + if (TRACE_HANDLE_CMD_FIS_DUMP_ENABLED) { + char *pretty_fis; + ahci_pretty_buffer_fis(cmd_fis, 0x80, &pretty_fis); + trace_handle_cmd_fis_dump(s, port, pretty_fis); + g_free(pretty_fis); + } switch (cmd_fis[0]) { case SATA_FIS_TYPE_REGISTER_H2D: handle_reg_h2d_fis(s, port, slot, cmd_fis); diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 5b321e1..082e804 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -103,3 +103,6 @@ ahci_reset(void *s) "ahci(%p): HBA reset" allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, uns= igned size) "ahci(%p): read a=3D%p addr=3D0x%"HWADDR_PRIx" val=3D0x%"PRIx64= ", size=3D%d" allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, un= signed size) "ahci(%p): write a=3D%p addr=3D0x%"HWADDR_PRIx" val=3D0x%"PRIx= 64", size=3D%d" =20 +# Warning: Verbose +handle_reg_h2d_fis_dump(void *s, int port, char *fis) "ahci(%p)[%d]: %s" +handle_cmd_fis_dump(void *s, int port, char *fis) "ahci(%p)[%d]: %s" --=20 2.9.4 From nobody Fri May 3 06:42:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Tue, 08 Aug 2017 14:33:19 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0537B6529; Tue, 8 Aug 2017 18:33:18 +0000 (UTC) Received: from probe.redhat.com (ovpn-123-63.rdu2.redhat.com [10.10.123.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4DBF960317; Tue, 8 Aug 2017 18:33:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 0537B6529 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com From: John Snow To: qemu-block@nongnu.org Date: Tue, 8 Aug 2017 14:33:06 -0400 Message-Id: <20170808183306.27474-10-jsnow@redhat.com> In-Reply-To: <20170808183306.27474-1-jsnow@redhat.com> References: <20170808183306.27474-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 08 Aug 2017 18:33:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 9/9] AHCI: remove DPRINTF macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/ahci.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 1a4d4db..ce2010c 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -34,17 +34,8 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci_internal.h" =20 -#define DEBUG_AHCI 0 #include "trace.h" =20 -#define DPRINTF(port, fmt, ...) \ -do { \ - if (DEBUG_AHCI) { \ - fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \ - fprintf(stderr, fmt, ## __VA_ARGS__); \ - } \ -} while (0) - static void check_cmd(AHCIState *s, int port); static int handle_cmd(AHCIState *s, int port, uint8_t slot); static void ahci_reset_port(AHCIState *s, int port); --=20 2.9.4