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[14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=miUTY/1IvdDVFUGVNS8sieb9FMBqD10m7EeKX58HUi0=; b=FuUDhU12uRQiwiw1N5k2J642/NRjFiGOhGL4zCme3FB4Z30WSOPxmjZkGq4DhxH3cQ lrsYqNRYt97HWhIG18ShS2aRQWNaiuq6Fp81eYG2WMeMIVNQDJmOH6+w6a83lj6XH4CX RErxuKPd9JqldL8zF6OOWbx6OhPlwlBUOztddhiPPFw34pd4ScxSrslf0uuHZcof3xB8 UPA7mruK8b++DJnZ9rzkjiH6zQyjsL+eE4D/hcTLmKICMvDKs1A48S6UpdgzmlAZABwL 0tmCayzstvmkgV9OaAnss97gJyvf1f0wZyLCsmeIpvBWyeAYeDH/PxsWbFAN8Vad/Kkm J8Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=miUTY/1IvdDVFUGVNS8sieb9FMBqD10m7EeKX58HUi0=; b=qpiAwbKfYS9pzCdwWapNjfvSUqg/oAk116hRcp6K1Dc91PhEHG0S3damHJXvzZPG7s qh5IRKVcWn9rTOStWJpmKp3DKEaXqVpeAvgNV2qCE67T/VRqwREBliTMvL7CODBJmfE2 ZLUVkr+1XbPfKNn4peqMpRQ2zYb6Ll0TGlsVMamrQ0RrHXGuFO6GFisQbtPNknuaZJxq BFHU2pOqd7pJeQJJl2fH05XTOPNQAFO+C/5fueNbgcmOMgqahf8v8oRYhTi4b2Ka96Z0 Y8GTEIhm/RskjGx+umuL9BLZU7FTZ8XuGl0wH7excJ/aTcgV95cdFTmyuLstl3nJGdmr qVEA== X-Gm-Message-State: AIVw110tP3DrxS+XCzVotiTwc4s9hoDradc9q3LUad7P7EBGwA0ZCpj5 1pL2729iu+69v17dsPk= X-Received: by 10.99.53.13 with SMTP id c13mr1164951pga.68.1500439531613; Tue, 18 Jul 2017 21:45:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:15 -1000 Message-Id: <20170719044522.21114-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 1/8] target/alpha: Remove amask from tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This value is constant for the cpu and does not need to be stored within the TB. Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 9 ------- target/alpha/translate.c | 70 ++++++++++++++++++++++++++------------------= ---- 2 files changed, 38 insertions(+), 41 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 691ac00..aa83417 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -487,14 +487,6 @@ enum { TB_FLAGS_PAL_MODE =3D 1, TB_FLAGS_FEN =3D 2, TB_FLAGS_USER_MODE =3D 8, - - TB_FLAGS_AMASK_SHIFT =3D 4, - TB_FLAGS_AMASK_BWX =3D AMASK_BWX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_FIX =3D AMASK_FIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_CIX =3D AMASK_CIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_MVI =3D AMASK_MVI << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_TRAP =3D AMASK_TRAP << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_PREFETCH =3D AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT, }; =20 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, @@ -513,7 +505,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, if (env->fen) { flags |=3D TB_FLAGS_FEN; } - flags |=3D env->amask << TB_FLAGS_AMASK_SHIFT; =20 *pflags =3D flags; } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e..4a627fc 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -51,14 +51,15 @@ struct DisasContext { #endif int mem_idx; =20 + /* implver and amask values for this CPU. */ + int implver; + int amask; + /* Current rounding mode for this TB. */ int tb_rm; /* Current flush-to-zero setting for this TB. */ int tb_ftz; =20 - /* implver value for this CPU. */ - int implver; - /* The set of registers active in the current context. */ TCGv *ir; =20 @@ -1442,6 +1443,13 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv v= b, int regno) } \ } while (0) =20 +#define REQUIRE_AMASK(FLAG) \ + do { \ + if ((ctx->amask & AMASK_##FLAG) =3D=3D 0) { \ + goto invalid_opc; \ + } \ + } while (0) + #define REQUIRE_TB_FLAG(FLAG) \ do { \ if ((ctx->tb->flags & (FLAG)) =3D=3D 0) { \ @@ -1532,7 +1540,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) =20 case 0x0A: /* LDBU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: @@ -1541,17 +1549,17 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) break; case 0x0C: /* LDWU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); break; case 0x0D: /* STW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: @@ -1832,10 +1840,7 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) case 0x61: /* AMASK */ REQUIRE_REG_31(ra); - { - uint64_t amask =3D ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; - tcg_gen_andi_i64(vc, vb, ~amask); - } + tcg_gen_andi_i64(vc, vb, ~ctx->amask); break; case 0x64: /* CMOVLE */ @@ -2048,7 +2053,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) break; =20 case 0x14: - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); vc =3D dest_fpr(ctx, rc); switch (fpfn) { /* fn11 & 0x3F */ case 0x04: @@ -2525,14 +2530,14 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) vc =3D dest_gpr(ctx, rc); if (fn7 =3D=3D 0x70) { /* FTOIT */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); va =3D load_fpr(ctx, ra); tcg_gen_mov_i64(vc, va); break; } else if (fn7 =3D=3D 0x78) { /* FTOIS */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); t32 =3D tcg_temp_new_i32(); va =3D load_fpr(ctx, ra); @@ -2546,117 +2551,117 @@ static ExitStatus translate_one(DisasContext *ctx= , uint32_t insn) switch (fn7) { case 0x00: /* SEXTB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext8s_i64(vc, vb); break; case 0x01: /* SEXTW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext16s_i64(vc, vb); break; case 0x30: /* CTPOP */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctpop_i64(vc, vb); break; case 0x31: /* PERR */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_NO_LIT; va =3D load_gpr(ctx, ra); gen_helper_perr(vc, va, vb); break; case 0x32: /* CTLZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_clzi_i64(vc, vb, 64); break; case 0x33: /* CTTZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctzi_i64(vc, vb, 64); break; case 0x34: /* UNPKBW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbw(vc, vb); break; case 0x35: /* UNPKBL */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbl(vc, vb); break; case 0x36: /* PKWB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pkwb(vc, vb); break; case 0x37: /* PKLB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pklb(vc, vb); break; case 0x38: /* MINSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsb8(vc, va, vb); break; case 0x39: /* MINSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsw4(vc, va, vb); break; case 0x3A: /* MINUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minub8(vc, va, vb); break; case 0x3B: /* MINUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minuw4(vc, va, vb); break; case 0x3C: /* MAXUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxub8(vc, va, vb); break; case 0x3D: /* MAXUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxuw4(vc, va, vb); break; case 0x3E: /* MAXSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsb8(vc, va, vb); break; case 0x3F: /* MAXSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsw4(vc, va, vb); break; @@ -2929,6 +2934,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.pc =3D pc_start; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; + ctx.amask =3D env->amask; ctx.singlestep_enabled =3D cs->singlestep_enabled; =20 #ifdef CONFIG_USER_ONLY --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9wjYMABW10s8ot6Dn69LZSglWywx9eG5LER7fEqX6Zk=; b=HJvgCD2ikp0JTmXWqoS/u1l1XQJ3qasev77bqJq7Eq8Tb7OT0PB/eZMVgVlj4KO8Be EpLE6O9h5nHV62QO2oCiMc5mpPm/rZlTUjHEs1sUkH/RoqN4jaf6ewRTQ2MAAiQZ7Q8t M5xpoOTQqSUk1cCBv9hk7wFxRfSSeQ2uKrpp3nAf74rCtPLJtUTxdVJqHBmo1zApHQfL nbeKhTcS1hO1wlgB2QBSW6DIY9D4EyCEQg0wa5GELrcM85K129crw/ONXdVKECf1iAcu VfB1UydqLequP5u5HeJ5yx5D8NenVe6yoSKkrAWpN1bXa5UWlj91cGnfM223IuHFyH2R sj/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=9wjYMABW10s8ot6Dn69LZSglWywx9eG5LER7fEqX6Zk=; b=nKhEzUc+OC21ecIgBukBMByOBEHClKBEvo92NvDElKD0NhBdsF/2tvc5xwqf6uuBBA 8QTHe2C0gQ3ENP2W/uA5FuhaHli1HHkdEt6ANC1JaLJQbGy7YpBpupDP875u7TocI2SO ZjmgikmZlxFTB3hgrUYUog9cAYwX1OXvOhlVl3LKx2LokAd85WRxXOWDKoDxWALOQ3lH TByK6iW+GOa6Rgm+PpmpVF5QyZVozqtl1t0d0epCLd/OUTf/COGdKrp+uRJnx9Wc95tx 3GuQ6OQFUdVGopb1h/r/IXVCAyK/+M4eY+YACuv3kfbIX1MnKuh/AYzNpoeBzHs0gThM fAGQ== X-Gm-Message-State: AIVw1100/97zDAPTa15Wa+jevupMI9ypHr9a4KU2BjngCogD7XZbYt5M CqAqzHkmbAk8PyfSadU= X-Received: by 10.99.115.8 with SMTP id o8mr1173421pgc.38.1500439534214; Tue, 18 Jul 2017 21:45:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:16 -1000 Message-Id: <20170719044522.21114-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 2/8] target/alpha: Copy tb->flags into DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4a627fc..48be19a 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -49,6 +49,7 @@ struct DisasContext { #ifndef CONFIG_USER_ONLY uint64_t palbr; #endif + uint32_t tbflags; int mem_idx; =20 /* implver and amask values for this CPU. */ @@ -452,7 +453,7 @@ static ExitStatus gen_store_conditional(DisasContext *c= tx, int ra, int rb, static bool in_superpage(DisasContext *ctx, int64_t addr) { #ifndef CONFIG_USER_ONLY - return ((ctx->tb->flags & TB_FLAGS_USER_MODE) =3D=3D 0 + return ((ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0 && addr >> TARGET_VIRT_ADDR_SPACE_BITS =3D=3D -1 && ((addr >> 41) & 3) =3D=3D 2); #else @@ -1167,7 +1168,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ - if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) =3D=3D 0) { + if (palcode < 0x40 && (ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0) { TCGv tmp; switch (palcode) { case 0x01: @@ -1258,7 +1259,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) uint64_t exc_addr =3D ctx->pc; uint64_t entry =3D ctx->palbr; =20 - if (ctx->tb->flags & TB_FLAGS_PAL_MODE) { + if (ctx->tbflags & TB_FLAGS_PAL_MODE) { exc_addr |=3D 1; } else { tcg_gen_movi_i64(tmp, 1); @@ -1452,7 +1453,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb= , int regno) =20 #define REQUIRE_TB_FLAG(FLAG) \ do { \ - if ((ctx->tb->flags & (FLAG)) =3D=3D 0) { \ + if ((ctx->tbflags & (FLAG)) =3D=3D 0) { \ goto invalid_opc; \ } \ } while (0) @@ -2932,6 +2933,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) =20 ctx.tb =3D tb; ctx.pc =3D pc_start; + ctx.tbflags =3D tb->flags; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; ctx.amask =3D env->amask; @@ -2941,7 +2943,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.ir =3D cpu_std_ir; #else ctx.palbr =3D env->palbr; - ctx.ir =3D (tb->flags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx.ir =3D (ctx.tbflags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif =20 /* ??? Every TB begins with unset rounding mode, to be initialized on --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150043979986958.539354834307574; Tue, 18 Jul 2017 21:49:59 -0700 (PDT) Received: from localhost ([::1]:59861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgvh-0008P0-Bp for importer@patchew.org; Wed, 19 Jul 2017 00:49:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgrm-0004cj-Lu for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXgri-0006bR-Qj for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:42 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXgri-0006b8-HR for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:38 -0400 Received: by mail-pf0-x244.google.com with SMTP id o88so5062822pfk.1 for ; Tue, 18 Jul 2017 21:45:38 -0700 (PDT) Received: from bigtime.twiddle.net (14-203-207-215.tpgi.com.au. [14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=CVBx+eME1bmguRxgJCfRhSpoi6uLwhasLtkIQInbkPQ=; b=NCBb7cT87WIG5l/rczhkii6UBhg1i80wplnC0vri3xGyVBXmncSP0z6b1iYx2modRk vrZFaaPecYQeNsDr1j1ftq93va3yFFyFqhRnM3yXM78cZzSIXvm0w8VRbWMc/p2KFFk7 H1Z8/7ilfQYjRVIXoWcQL6Vy2NeZN8MpZT1xCO1fQWzsR8epd2jVWoPJWVagMg+63+eR ba2gt693/+ELsBRuJy0+EQ5SD0P4fb3+qKjMbZU2p7XYaml5lbLqwSpLzSiRIm/umzq0 I67JGWf1AKVyKJkDDcQk6pNnytwRoDln7r4k9Ss9x6mun1XqhBYgcxOt1lMLSeqKD2JU ub9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=CVBx+eME1bmguRxgJCfRhSpoi6uLwhasLtkIQInbkPQ=; b=K+YY6kF9/RpSqInyVQIdNrUusWXOd/Kjwo5+8NMXObImtjvFpZKZIIdncLugDXQqg/ s0UmvIKdpibPdPyGQwPjGl6xRsWUnP3SvOZa3ypgh7V8poPpHM69bmEZxa5pYq2tgr7w IPeB+KQQ99hYZC6QfzranpDWdLG4paC1zBhSmaTsz2XUx6cjdNUFgqNd1hxGcRpS28Iy KRaRn2MyprTlvzceM6wUrAJtJt0KfXL9312N99I5XSKlj6unu4PaP8xGduAzLsdjqKqe D3gmnE1s+B2taBcs1DfDeLzp4UcLCevX6JXR2tp+v7l0JCupuG3RgW9cbxcrwJESG2Lx WO3g== X-Gm-Message-State: AIVw1115oqBAXDzy8XXF783vmcxjoreWN+poK6ZcpSbLp4Jfhx7wkkHd Xbeex6dlPURhBiVrC2U= X-Received: by 10.84.210.79 with SMTP id z73mr643697plh.151.1500439537126; Tue, 18 Jul 2017 21:45:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:17 -1000 Message-Id: <20170719044522.21114-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 3/8] target/alpha: Merge several flag bytes into ENV->FLAGS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 70 +++++++++++++++++-------------------- hw/alpha/dp264.c | 1 - linux-user/main.c | 25 +++++++------ target/alpha/cpu.c | 7 ++-- target/alpha/helper.c | 12 +++---- target/alpha/machine.c | 10 ++---- target/alpha/translate.c | 91 +++++++++++++++++++++++++++++++-------------= ---- 7 files changed, 117 insertions(+), 99 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index aa83417..e95be2b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -242,13 +242,11 @@ struct CPUAlphaState { uint8_t fpcr_dyn_round; uint8_t fpcr_flush_to_zero; =20 - /* The Internal Processor Registers. Some of these we assume always - exist for use in user-mode. */ - uint8_t ps; - uint8_t intr_flag; - uint8_t pal_mode; - uint8_t fen; + /* Mask of PALmode, Processor State et al. Most of this gets copied + into the TranslatorBlock flags and controls code generation. */ + uint32_t flags; =20 + /* The high 32-bits of the processor cycle counter. */ uint32_t pcc_ofs; =20 /* These pass data from the exception logic in the translator and @@ -398,24 +396,37 @@ enum { }; =20 /* Processor status constants. */ -enum { - /* Low 3 bits are interrupt mask level. */ - PS_INT_MASK =3D 7, +/* Low 3 bits are interrupt mask level. */ +#define PS_INT_MASK 7u =20 - /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; - The Unix PALcode only uses bit 4. */ - PS_USER_MODE =3D 8 -}; +/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; + The Unix PALcode only uses bit 4. */ +#define PS_USER_MODE 8u + +/* CPUAlphaState->flags constants. These are layed out so that we + can set or reset the pieces individually by assigning to the byte, + or manipulated as a whole. */ + +#define ENV_FLAG_PAL_SHIFT 0 +#define ENV_FLAG_PS_SHIFT 8 +#define ENV_FLAG_RX_SHIFT 16 +#define ENV_FLAG_FEN_SHIFT 24 + +#define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) +#define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) +#define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) +#define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) + +#define ENV_FLAG_TB_MASK \ + (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { - if (env->pal_mode) { - return MMU_KERNEL_IDX; - } else if (env->ps & PS_USER_MODE) { - return MMU_USER_IDX; - } else { - return MMU_KERNEL_IDX; + int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; + if (env->flags & ENV_FLAG_PAL_MODE) { + ret =3D MMU_KERNEL_IDX; } + return ret; } =20 enum { @@ -482,31 +493,12 @@ QEMU_NORETURN void alpha_cpu_unassigned_access(CPUSta= te *cpu, hwaddr addr, int unused, unsigned size); #endif =20 -/* Bits in TB->FLAGS that control how translation is processed. */ -enum { - TB_FLAGS_PAL_MODE =3D 1, - TB_FLAGS_FEN =3D 2, - TB_FLAGS_USER_MODE =3D 8, -}; - static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *p= flags) { - int flags =3D 0; - *pc =3D env->pc; *cs_base =3D 0; - - if (env->pal_mode) { - flags =3D TB_FLAGS_PAL_MODE; - } else { - flags =3D env->ps & PS_USER_MODE; - } - if (env->fen) { - flags |=3D TB_FLAGS_FEN; - } - - *pflags =3D flags; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; } =20 #endif /* ALPHA_CPU_H */ diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 85405da..3b307ad 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -123,7 +123,6 @@ static void clipper_init(MachineState *machine) =20 /* Start all cpus at the PALcode RESET entry point. */ for (i =3D 0; i < smp_cpus; ++i) { - cpus[i]->env.pal_mode =3D 1; cpus[i]->env.pc =3D palcode_entry; cpus[i]->env.palbr =3D palcode_entry; } diff --git a/linux-user/main.c b/linux-user/main.c index ad03c9e..2b38d39 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3037,16 +3037,13 @@ void cpu_loop(CPUAlphaState *env) abi_long sysret; =20 while (1) { + bool arch_interrupt =3D true; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - /* All of the traps imply a transition through PALcode, which - implies an REI instruction has been executed. Which means - that the intr_flag should be cleared. */ - env->intr_flag =3D 0; - switch (trapnr) { case EXCP_RESET: fprintf(stderr, "Reset requested. Exit\n"); @@ -3063,7 +3060,6 @@ void cpu_loop(CPUAlphaState *env) exit(EXIT_FAILURE); break; case EXCP_MMFAULT: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID @@ -3072,7 +3068,6 @@ void cpu_loop(CPUAlphaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGN: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; info.si_code =3D TARGET_BUS_ADRALN; @@ -3081,7 +3076,6 @@ void cpu_loop(CPUAlphaState *env) break; case EXCP_OPCDEC: do_sigill: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGILL; info.si_errno =3D 0; info.si_code =3D TARGET_ILL_ILLOPC; @@ -3089,7 +3083,6 @@ void cpu_loop(CPUAlphaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_ARITH: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; info.si_code =3D TARGET_FPE_FLTINV; @@ -3100,7 +3093,6 @@ void cpu_loop(CPUAlphaState *env) /* No-op. Linux simply re-enables the FPU. */ break; case EXCP_CALL_PAL: - env->lock_addr =3D -1; switch (env->error_code) { case 0x80: /* BPT */ @@ -3197,10 +3189,11 @@ void cpu_loop(CPUAlphaState *env) case EXCP_DEBUG: info.si_signo =3D gdb_handlesig(cs, TARGET_SIGTRAP); if (info.si_signo) { - env->lock_addr =3D -1; info.si_errno =3D 0; info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + arch_interrupt =3D false; } break; case EXCP_INTERRUPT: @@ -3208,6 +3201,7 @@ void cpu_loop(CPUAlphaState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: printf ("Unhandled trap: 0x%x\n", trapnr); @@ -3215,6 +3209,15 @@ void cpu_loop(CPUAlphaState *env) exit(EXIT_FAILURE); } process_pending_signals (env); + + /* Most of the traps imply a transition through PALcode, which + implies an REI instruction has been executed. Which means + that RX and LOCK_ADDR should be cleared. But there are a + few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->flags &=3D ~ENV_FLAG_RX_FLAG; + env->lock_addr =3D -1; + } } } #endif /* TARGET_ALPHA */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 8186c9d..76150f4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -276,14 +276,15 @@ static void alpha_cpu_initfn(Object *obj) =20 alpha_translate_init(); =20 + env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) - env->ps =3D PS_USER_MODE; + env->flags =3D ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | FPCR_UNFD | FPCR_INED | FPCR_DNOD | FPCR_DYN_NORMAL)); +#else + env->flags =3D ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; #endif - env->lock_addr =3D -1; - env->fen =3D 1; } =20 static void alpha_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index a5c3088..34121f4 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -81,7 +81,7 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val) static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg) { #ifndef CONFIG_USER_ONLY - if (env->pal_mode) { + if (env->flags & ENV_FLAG_PAL_MODE) { if (reg >=3D 8 && reg <=3D 14) { return &env->shadow[reg - 8]; } else if (reg =3D=3D 25) { @@ -364,13 +364,13 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 /* Remember where the exception happened. Emulate real hardware in that the low bit of the PC indicates PALmode. */ - env->exc_addr =3D env->pc | env->pal_mode; + env->exc_addr =3D env->pc | (env->flags & ENV_FLAG_PAL_MODE); =20 /* Continue execution at the PALcode entry point. */ env->pc =3D env->palbr + i; =20 /* Switch to PALmode. */ - env->pal_mode =3D 1; + env->flags |=3D ENV_FLAG_PAL_MODE; #endif /* !USER_ONLY */ } =20 @@ -381,14 +381,14 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) int idx =3D -1; =20 /* We never take interrupts while in PALmode. */ - if (env->pal_mode) { + if (env->flags & ENV_FLAG_PAL_MODE) { return false; } =20 /* Fall through the switch, collecting the highest priority interrupt that isn't masked by the processor status IPL. */ /* ??? This hard-codes the OSF/1 interrupt levels. */ - switch (env->ps & PS_INT_MASK) { + switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx =3D EXCP_DEV_INTERRUPT; @@ -432,7 +432,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, int i; =20 cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", - env->pc, env->ps); + env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i =3D 0; i < 31; i++) { cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, linux_reg_names[i], cpu_alpha_load_gr(env, i)); diff --git a/target/alpha/machine.c b/target/alpha/machine.c index a102645..0914ba5 100644 --- a/target/alpha/machine.c +++ b/target/alpha/machine.c @@ -48,11 +48,7 @@ static VMStateField vmstate_env_fields[] =3D { VMSTATE_UINTTL(lock_addr, CPUAlphaState), VMSTATE_UINTTL(lock_value, CPUAlphaState), =20 - VMSTATE_UINT8(ps, CPUAlphaState), - VMSTATE_UINT8(intr_flag, CPUAlphaState), - VMSTATE_UINT8(pal_mode, CPUAlphaState), - VMSTATE_UINT8(fen, CPUAlphaState), - + VMSTATE_UINT32(flags, CPUAlphaState), VMSTATE_UINT32(pcc_ofs, CPUAlphaState), =20 VMSTATE_UINTTL(trap_arg0, CPUAlphaState), @@ -74,8 +70,8 @@ static VMStateField vmstate_env_fields[] =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D vmstate_env_fields, }; =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 48be19a..140d6f3 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -269,6 +269,27 @@ static TCGv dest_fpr(DisasContext *ctx, unsigned reg) } } =20 +static int get_flag_ofs(unsigned shift) +{ + int ofs =3D offsetof(CPUAlphaState, flags); +#ifdef HOST_WORDS_BIGENDIAN + ofs +=3D 3 - (shift / 8); +#else + ofs +=3D shift / 8; +#endif + return ofs; +} + +static void ld_flag_byte(TCGv val, unsigned shift) +{ + tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift)); +} + +static void st_flag_byte(TCGv val, unsigned shift) +{ + tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift)); +} + static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; @@ -453,7 +474,7 @@ static ExitStatus gen_store_conditional(DisasContext *c= tx, int ra, int rb, static bool in_superpage(DisasContext *ctx, int64_t addr) { #ifndef CONFIG_USER_ONLY - return ((ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0 + return ((ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0 && addr >> TARGET_VIRT_ADDR_SPACE_BITS =3D=3D -1 && ((addr >> 41) & 3) =3D=3D 2); #else @@ -1125,16 +1146,15 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, T= CGv va, int rb, bool islit, =20 static void gen_rx(DisasContext *ctx, int ra, int set) { - TCGv_i32 tmp; + TCGv tmp; =20 if (ra !=3D 31) { - tcg_gen_ld8u_i64(ctx->ir[ra], cpu_env, - offsetof(CPUAlphaState, intr_flag)); + ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); } =20 - tmp =3D tcg_const_i32(set); - tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); - tcg_temp_free_i32(tmp); + tmp =3D tcg_const_i64(set); + st_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); + tcg_temp_free(tmp); } =20 static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) @@ -1168,7 +1188,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ - if (palcode < 0x40 && (ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0) { + if (palcode < 0x40 && (ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0) { TCGv tmp; switch (palcode) { case 0x01: @@ -1199,13 +1219,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) /* SWPIPL */ /* Note that we already know we're in kernel mode, so we know that PS only contains the 3 IPL bits. */ - tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env, - offsetof(CPUAlphaState, ps)); + ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); =20 /* But make sure and store only the 3 IPL bits from the user. = */ tmp =3D tcg_temp_new(); tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps)); + st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); tcg_temp_free(tmp); =20 /* Allow interrupts to be recognized right away. */ @@ -1214,9 +1233,9 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 case 0x36: /* RDPS */ - tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env, - offsetof(CPUAlphaState, ps)); + ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); break; + case 0x38: /* WRUSP */ tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, @@ -1259,11 +1278,11 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) uint64_t exc_addr =3D ctx->pc; uint64_t entry =3D ctx->palbr; =20 - if (ctx->tbflags & TB_FLAGS_PAL_MODE) { + if (ctx->tbflags & ENV_FLAG_PAL_MODE) { exc_addr |=3D 1; } else { tcg_gen_movi_i64(tmp, 1); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode= )); + st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); } =20 tcg_gen_movi_i64(tmp, exc_addr); @@ -1293,14 +1312,11 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) =20 #ifndef CONFIG_USER_ONLY =20 -#define PR_BYTE 0x100000 #define PR_LONG 0x200000 =20 static int cpu_pr_data(int pr) { switch (pr) { - case 0: return offsetof(CPUAlphaState, ps) | PR_BYTE; - case 1: return offsetof(CPUAlphaState, fen) | PR_BYTE; case 2: return offsetof(CPUAlphaState, pcc_ofs) | PR_LONG; case 3: return offsetof(CPUAlphaState, trap_arg0); case 4: return offsetof(CPUAlphaState, trap_arg1); @@ -1350,14 +1366,19 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv = va, int regno) } break; =20 + case 0: /* PS */ + ld_flag_byte(va, ENV_FLAG_PS_SHIFT); + break; + case 1: /* FEN */ + ld_flag_byte(va, ENV_FLAG_FEN_SHIFT); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ data =3D cpu_pr_data(regno); if (data =3D=3D 0) { tcg_gen_movi_i64(va, 0); - } else if (data & PR_BYTE) { - tcg_gen_ld8u_i64(va, cpu_env, data & ~PR_BYTE); } else if (data & PR_LONG) { tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG); } else { @@ -1417,14 +1438,19 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv = vb, int regno) tcg_gen_mov_i64(cpu_std_ir[regno], vb); break; =20 + case 0: /* PS */ + st_flag_byte(vb, ENV_FLAG_PS_SHIFT); + break; + case 1: /* FEN */ + st_flag_byte(vb, ENV_FLAG_FEN_SHIFT); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ data =3D cpu_pr_data(regno); if (data !=3D 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(vb, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { + if (data & PR_LONG) { tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG); } else { tcg_gen_st_i64(vb, cpu_env, data); @@ -2430,7 +2456,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x19: /* HW_MFPR (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); va =3D dest_gpr(ctx, ra); ret =3D gen_mfpr(ctx, va, insn & 0xffff); break; @@ -2452,7 +2478,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1B: /* HW_LD (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); { TCGv addr =3D tcg_temp_new(); vb =3D load_gpr(ctx, rb); @@ -2674,7 +2700,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1D: /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); vb =3D load_gpr(ctx, rb); ret =3D gen_mtpr(ctx, vb, insn & 0xffff); break; @@ -2685,7 +2711,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1E: /* HW_RET (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); if (rb =3D=3D 31) { /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our @@ -2695,12 +2721,13 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) } else { vb =3D load_gpr(ctx, rb); } + tcg_gen_movi_i64(cpu_lock_addr, -1); tmp =3D tcg_temp_new(); tcg_gen_movi_i64(tmp, 0); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); - tcg_gen_movi_i64(cpu_lock_addr, -1); + st_flag_byte(tmp, ENV_FLAG_RX_SHIFT); tcg_gen_andi_i64(tmp, vb, 1); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode)); + st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); + tcg_temp_free(tmp); tcg_gen_andi_i64(cpu_pc, vb, ~3); /* Allow interrupts to be recognized right away. */ ret =3D EXIT_PC_UPDATED_NOCHAIN; @@ -2712,7 +2739,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1F: /* HW_ST (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); { switch ((insn >> 12) & 0xF) { case 0x0: @@ -2943,7 +2970,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.ir =3D cpu_std_ir; #else ctx.palbr =3D env->palbr; - ctx.ir =3D (ctx.tbflags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx.ir =3D (ctx.tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif =20 /* ??? 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[14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DNcQfZghpd+7kFLkdbkNc5dh3BmkT3FVWtVCzO5Jnk8=; b=L4t0Zc2GLlAe1DvDd7tJkCB+f17FaKgNez/fvweJYcdFvsCxMEMvAw4/m1UR0cXbF0 wAmloCQqIbdA1gGC4qciYck0p5zR7sCqLt6GkgjmEMNDxm5b+gicI10c7u+3VWF3qMUV ImBfBcyZYQ1ch2YGruFZfTd58ZIHvwXAmNAO+V5OjK79gPm+n2hRVCI9d6uVC+1zFZyr 53+GQZgfHKzOgKMOa3BHSdoi+QZnejaRY04xhB1VcZYeJ2vP2jJyYl+lWUmRTxeEPPXv GC9k4dCW/THSy/edr6/pe1CstSOXmX5l5HThqCTQaqXkWwr3GiY3qzuRhy5VBOd2vXXQ gL9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=DNcQfZghpd+7kFLkdbkNc5dh3BmkT3FVWtVCzO5Jnk8=; b=mLN2Uje2rxpt+bezpQw7NFcOzAvZargrfUV3mgpBbN5fFclsiAlfYFq1J79I6zBjcU 4/tiavxJ6DC7gtiEsDowXn3vysrLjYTXIM8qccjsj3HkCrYKISJgnqRpWHRvB4fbthJh LRAk4ypcerrDOBYgQ39Ri5eVUZlh4DXh4FiQoWGjeVpNnyzgByFsvhTeAaNkNE9paVWa ba4s+xhr6WJOBfvNSbYTdU397j/jW3MJSTg6FbhuvH8fsMtyMIPBOZ3lFMxDNioRQTPF i8T2CQNMUC75QxUfPO4BZlP6dK6RaG701qGP9TwizSQXMfZwNZQMECzVqC23QhLJjs1N 7wXA== X-Gm-Message-State: AIVw111IKoNnHNGTTorp/RL5/MBclBLDOUqS9MqrrYSCgfmgAy8wsNbl zvef+rFY227hb4C44ok= X-Received: by 10.98.11.135 with SMTP id 7mr1091241pfl.45.1500439539528; Tue, 18 Jul 2017 21:45:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:18 -1000 Message-Id: <20170719044522.21114-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 4/8] target/alpha: Fix temp leak in gen_bcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 140d6f3..d684a7b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -565,16 +565,16 @@ static ExitStatus gen_bcond_internal(DisasContext *ct= x, TCGCond cond, static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp, int mask) { - TCGv cmp_tmp; - if (mask) { - cmp_tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(cmp_tmp, load_gpr(ctx, ra), 1); - } else { - cmp_tmp =3D load_gpr(ctx, ra); - } + TCGv tmp =3D tcg_temp_new(); + ExitStatus ret; =20 - return gen_bcond_internal(ctx, cond, cmp_tmp, disp); + tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); + ret =3D gen_bcond_internal(ctx, cond, tmp, disp); + tcg_temp_free(tmp); + return ret; + } + return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), disp); } =20 /* Fold -0.0 for comparison with COND. */ --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15004397849251019.3539172240363; Tue, 18 Jul 2017 21:49:44 -0700 (PDT) Received: from localhost ([::1]:59860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgvf-0008O0-NW for importer@patchew.org; Wed, 19 Jul 2017 00:49:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgro-0004e4-NI for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXgrn-0006ca-DQ for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:44 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXgrn-0006cK-2x for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:43 -0400 Received: by mail-pg0-x243.google.com with SMTP id y129so5392063pgy.3 for ; Tue, 18 Jul 2017 21:45:42 -0700 (PDT) Received: from bigtime.twiddle.net (14-203-207-215.tpgi.com.au. [14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=t/l93Z+IXblkkualPI8Qn0bW8laD6OAVQywyA5mfQP0=; b=bgOvQTcgXnbc8BEWbhNCWEs9fHa7gCSX8DBedLTtXyZ12ZTh2Sp+42Ru169qFuhc1Q bJ2STdKVdlBnpSjxypksV8cjYgZ5dU1RlPsBBStz1Z8XzxOju3jlHXSP60tldsno3uOn 2Rw5bIcBsGeQPJEBj9rcHBErSxJvJn/vYcA+j20RiZg7FssMUEL5YR3jDDMYwJznr3d/ TnyPBPmerDBgVxr7hgP8vVDkONonhA08tqbNUc0rdjTmwI8zoMgxSiC4XtgC8XFFNo+j 9HwLY+qX6mLHmt0CAkK2w6ulFULrnTULxLg9ic2AtwApx/0HPx2I9WpkOfmkwxuYwsPZ rvCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=t/l93Z+IXblkkualPI8Qn0bW8laD6OAVQywyA5mfQP0=; b=UtsHr2IvaoGKTNu7rIDt/R92JHEJ5W4Sve/SRK023hfGLduuA3tYcLLcJZrChOhh96 w5WNzecos6aUYoVbf7R/C7JXC6KjhzAsdP4YajDYUHLubadjC5VcMqQEvSFxKtds7Az/ buQe8XasIPEH6hNNJ7T8f6RR8zj405GbqgmcUbIzMj0cWVJ44BKm+3W9XXSvjx8LfUx5 S/1/BS4lyWzwpKd/KIZ2Arc0XnfUi43BHlXElS5g4s001GwABnBS3Fi+qCkxv7SkDj6f fYle36R+OpJSI1bkXumTwFYHVQY4Fa/fYsH5bIqf74IJgZ+9BdiEDN6oH3m+WTR+Sk7o LG3w== X-Gm-Message-State: AIVw112rqOX8H2BMFq7KyJfQDmyDRapzK0Po3H8YksfN5SKkPCf8/sWf C7AkL1AHEELvuGc4x5g= X-Received: by 10.98.17.84 with SMTP id z81mr1167731pfi.38.1500439541978; Tue, 18 Jul 2017 21:45:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:19 -1000 Message-Id: <20170719044522.21114-6-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 5/8] target/alpha: Fix temp leak in gen_mtpr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index d684a7b..5e37b1a 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1392,7 +1392,6 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va= , int regno) =20 static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) { - TCGv tmp; int data; =20 switch (regno) { @@ -1408,9 +1407,12 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv v= b, int regno) =20 case 253: /* WAIT */ - tmp =3D tcg_const_i64(1); - tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); + { + TCGv_i32 tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + } return gen_excp(ctx, EXCP_HALTED, 0); =20 case 252: --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15004396572111023.8632130179737; Tue, 18 Jul 2017 21:47:37 -0700 (PDT) Received: from localhost ([::1]:59855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgtc-00066L-3P for importer@patchew.org; Wed, 19 Jul 2017 00:47:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgrt-0004j3-Pz for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXgrq-0006dD-3p for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:49 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:33654) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXgrp-0006d2-Qe for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:46 -0400 Received: by mail-pg0-x242.google.com with SMTP id z1so5409883pgs.0 for ; Tue, 18 Jul 2017 21:45:45 -0700 (PDT) Received: from bigtime.twiddle.net (14-203-207-215.tpgi.com.au. [14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KJ29nMouEnB9OzDbyz7Ca9azLD1Akpys+uhs6KG+wgM=; b=REPUKxDV8W1+vvbjQVNOhXFA44o5t17TT5f/v05DhyGIzCQ7s4xoqDd+/KGjlUecgM 5VBkvEs1OXvj8QyrcDfAHF2OOjwRoxqs/kixuBY1roLWtgiyU51BPPQN2VdqCLhcUEg+ xsPoEvK68HdraDCoTiBV4gbyRMX1r1YMBOUZqcYdNXTeoBYdd7UQ/1Z9vPADSiCwmEdZ t8dbjPjH6l2a85sZGidgLhyvz2wL4ruQv/enSfP/2GXdOOOmDcI3jbALCWrD5yUzov+d gE4UNPjTMABmJ0OlxGIVO8XZp/22lxsT6ARrogwGNloN5ZYJAWzvpoM9SsUFOGlvxNza gHew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KJ29nMouEnB9OzDbyz7Ca9azLD1Akpys+uhs6KG+wgM=; b=Nncphc1SQ9JR8dVe1ccs2JjrpcAkokKEuXntd2YoFR891UwaFNpj0TyUhefEiY9/hG djUlYNFy52OJkh6LvvN8546wC7IHgHFnP/OlyN9sNNGNG4Hm7m0Cny8UF2BO0NY6AFc+ Nd7gB0dIGnc3rOxisQrLmjVEnV70h5kjxZZLRbLd3lrCXb7SzdwySE4obJZVTuXXKWEc WbA4pleai27JHLKtr/eMLGFLp463HHthU8GziS0nyTpXyNCKDZJP2+YCcwgTB26PPuMV p6ezTCYln3uaeMbQSatIYU7D3GYJnpA9KBucTm3MHaaEI9RkHiQdOHOoru+y2LEd2O9s r7GQ== X-Gm-Message-State: AIVw113dNQkqIB+4pNH5p9qgKiMg5LTQS1mhF4tot5CYRPXkh/8dxss/ ugW1n4WRwuEpwhchyOY= X-Received: by 10.98.204.204 with SMTP id j73mr1102249pfk.11.1500439544593; Tue, 18 Jul 2017 21:45:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:20 -1000 Message-Id: <20170719044522.21114-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 6/8] target/alpha: Fix temp leak in gen_call_pal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5e37b1a..326af7f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1189,7 +1189,6 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ if (palcode < 0x40 && (ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0) { - TCGv tmp; switch (palcode) { case 0x01: /* CFLUSH */ @@ -1222,10 +1221,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); =20 /* But make sure and store only the 3 IPL bits from the user. = */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); - st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); - tcg_temp_free(tmp); + { + TCGv tmp =3D tcg_temp_new(); + tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); + st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); + tcg_temp_free(tmp); + } =20 /* Allow interrupts to be recognized right away. */ tcg_gen_movi_i64(cpu_pc, ctx->pc); @@ -1254,9 +1255,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, in= t palcode) =20 case 0x3E: /* WTINT */ - tmp =3D tcg_const_i64(1); - tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); + { + TCGv_i32 tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + } tcg_gen_movi_i64(ctx->ir[IR_V0], 0); return gen_excp(ctx, EXCP_HALTED, 0); =20 --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500439886917737.6255028406592; Tue, 18 Jul 2017 21:51:26 -0700 (PDT) Received: from localhost ([::1]:59873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgxJ-0001MH-M3 for importer@patchew.org; Wed, 19 Jul 2017 00:51:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39568) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgrt-0004j6-Qn for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXgrs-0006dd-DI for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:49 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:35852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXgrs-0006dU-7g for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:48 -0400 Received: by mail-pf0-x243.google.com with SMTP id a11so5068007pfj.3 for ; Tue, 18 Jul 2017 21:45:48 -0700 (PDT) Received: from bigtime.twiddle.net (14-203-207-215.tpgi.com.au. [14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=91yHyZD/4ZNhFNyTcDmmHyFRqwUOPI8BMJbCbfgHRDM=; b=NBCkNCVAXo5QAATcfHvXOPx4ZYbEVUh1d9RMusyBYL2OEy2Z7Fbuat0ADzzDQgdRAf StNebb5CTECYZ/lW3TGdtt7jaoUVPssNJrAjOjeVTv2CM5yVh7D6lDZ9It/7cYB7dgy0 x1qrioxZcHv1oH0dtlQGDED+a5nFdeQJ1wJoLyLQQU5xug/uDr+AswyaGrHsnllm7X/u tzbQeAC201qEne1S4fKpPmWlovWv9NDXiUk17aZTJfJqvEX0DWMzXAkcLqxC+xfrGMiN RO60Az2MIkR98rOgOzGJ3fxyQg3O/l99NbWeO/13AuSpspsRB3wgPlwuUI1s0bDhA+wP jD9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=91yHyZD/4ZNhFNyTcDmmHyFRqwUOPI8BMJbCbfgHRDM=; b=Fw4IxEf9rXaOghgmeDVFlpnsYSrwkGDmrLpL+nhBdfexfdPMkm97NqawFW8Z/U3H3C t3E46fNzhkWmL5aoCFP1b3y/I4v1jnBVWjrEvMGdmIj2CuphgkhqbhelVxKaAYNaeLkR NR3rya9h8qP0WyodM/kMgl4F+dfU/M3P/Yci+RdxSMYZxjwsg/BCQolBCUxiiOsnDCwS qlhw2mLEoNoRwNaZNF8PXDTF0s3LUcHhVJnYa1h/78G67gdK4SHYlwsnlFecMolCawGX a0IHTN5d61EsmhEMjfZTkqQlSP+Dmr3DTYNwEzrDBWyGoKLBsLPu/jnsWweubHqpdGj2 qXTg== X-Gm-Message-State: AIVw1101bgk21CPQbPp2Uy15Qmw0bbxSQcWTeUp/+xLrUDq9tQ7YXRq4 2eD9LL/Lzfpe+v7G5Qg= X-Received: by 10.98.156.14 with SMTP id f14mr1097212pfe.77.1500439547010; Tue, 18 Jul 2017 21:45:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:21 -1000 Message-Id: <20170719044522.21114-8-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 7/8] target/alpha: Fix temp leak in gen_fbcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 326af7f..aaaf28f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -613,8 +613,12 @@ static ExitStatus gen_fbcond(DisasContext *ctx, TCGCon= d cond, int ra, int32_t disp) { TCGv cmp_tmp =3D tcg_temp_new(); + ExitStatus ret; + gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); - return gen_bcond_internal(ctx, cond, cmp_tmp, disp); + ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, disp); + tcg_temp_free(cmp_tmp); + return ret; } =20 static void gen_fcmov(DisasContext *ctx, TCGCond cond, int ra, int rb, int= rc) --=20 2.9.4 From nobody Thu May 2 09:30:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500439906296943.5389832331723; Tue, 18 Jul 2017 21:51:46 -0700 (PDT) Received: from localhost ([::1]:59875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgxc-0001ZK-7J for importer@patchew.org; Wed, 19 Jul 2017 00:51:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXgrv-0004kV-CL for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXgru-0006eT-KS for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:51 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:35858) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXgru-0006eF-ES for qemu-devel@nongnu.org; Wed, 19 Jul 2017 00:45:50 -0400 Received: by mail-pf0-x243.google.com with SMTP id a11so5068098pfj.3 for ; Tue, 18 Jul 2017 21:45:50 -0700 (PDT) Received: from bigtime.twiddle.net (14-203-207-215.tpgi.com.au. [14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=TVeWA3pot3m34g1jzYAH16EB0LxgbDDNbsQoYDAak78=; b=iFw7FVpV17geF2UNwHQCKjuB38XTCZ0WPV+Ic4H+9cXf/9oe91Ft2cMF7RZn3s9N2L VRIyBwghT3ghn8Ir/DMygZNcY8rNSI6nWz0tdXjApH5uKyMh9wof8Gy0TgUsBnjd+fsn S+g2LkleLwUvWvIv8gLoJK8TtW0oyJPiP7HL1jbTsRJS1DrJA8uY+q4VU2uSP5z7Qmir ZVKZqR70qhKnEiacDv4YOeSIVMQ7jyB0Q48CG+GSixq3u/o4YdYC5wRuz7tAzqyoJBti ILynUsgeUbOKzXXNPKhri3ArDkmXFAvngJgNZ1PdlkOVrmljgI+TDb7np6N/ldiV/L1X kV9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=TVeWA3pot3m34g1jzYAH16EB0LxgbDDNbsQoYDAak78=; b=Vm4yMr20rAr83Wb3F6pjLhbtEl2JVVEqPeuiXBJZQARsGhAn3vzkAPfRSc6x+bfFHu IzdxLVz4We1raxFV8V75XhKOQ+JrtD4l6biewqxFYVahFYOMLhUv17m1r2CjWSRbTTTw 3eJq2BGvPq3SPhgU+KSixdMto2WRovnyszUHOI+eAMecc2GOWDKNLhiNz27eARbA2OqZ sUQRAdC6bNh/2EE2yJv+q1wNRZGWxVOt6avyWkHPsLJxEFjHWjEt9geUlYJPeNTkVLEI B8lGeP8vN7TtOGlT/jQ+yxKRk73R4y6MgpqPov1x9VXztaHYApSzpMRX9898J9I9h+P/ I0uA== X-Gm-Message-State: AIVw110JT6Xf4GWtA7ZGucrRGvNRH5+BU5vlLLSWCJiYLD33GEoXdOIR ZIuv9sVEBH6ng58WqCc= X-Received: by 10.101.85.14 with SMTP id f14mr1130764pgr.45.1500439549364; Tue, 18 Jul 2017 21:45:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:22 -1000 Message-Id: <20170719044522.21114-9-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 8/8] target/alpha: Log temp leaks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index aaaf28f..90e6d52 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3013,6 +3013,8 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) } =20 gen_tb_start(tb); + tcg_clear_temp_count(); + do { tcg_gen_insn_start(ctx.pc); num_insns++; @@ -3035,6 +3037,10 @@ void gen_intermediate_code(CPUAlphaState *env, struc= t TranslationBlock *tb) ret =3D translate_one(ctxp, insn); free_context_temps(ctxp); =20 + if (tcg_check_temp_count()) { + qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", ctx.pc= ); + } + /* If we reach a page boundary, are single stepping, or exhaust instruction count, stop generation. */ if (ret =3D=3D NO_EXIT --=20 2.9.4