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[14.203.207.215]) by smtp.gmail.com with ESMTPSA id e123sm7334569pfa.96.2017.07.18.21.40.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=oqGnMu1bNsb6nFz/w7wlPORXIHlhYVmPzPqOgeRGyl8=; b=b9gKZYG7OYlrYy9c4a1wn1e4j8qTPerLgTngOCnaKYSL4hDdG3hzNloELciD34sRah IuzmhBIr2NkU90JELQP2OUO6jn21chnx1JV1oM1FiP3thRCnPrxseOiJCRIHfdTLg6Ee ORmNCfGM2TJ3iSMIS1Iez8FtSvUbB3dKAbQZH9XnpJckNm02+MM39tA8gWaDri/oFJdS ysqX8E081ClEHWrM+XcTCZnH2MPRASduis3Z+2bspG3Jd7GLBqGm2z2ixqceZCzd3GK5 5o6NoIf9RtdtEiUBwDC7nBvAHMQE/WFhvR3cf2rTeilhW595sjrSainZtrMjR0KTrf3D QqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=oqGnMu1bNsb6nFz/w7wlPORXIHlhYVmPzPqOgeRGyl8=; b=Ejq8ADmVQ71CULPr23DrfIM4jbo4SrJp9GHp01mjR4hov2F8VTyceMFzerp22hnQIt INYmYAHzqOzW21s3plSeZuWXc29iYI4lAoCdzfS/VYDKysc1wWo0Eu4l7J9Hel7Uyogy 1aXp0t7HIyI5fb+REW1QgrGkyJURcfHUDHGf+w9Ix1pBWVp8FHkmYGqSDY1KWWWAWuyD MNywoSoOz28aDi1poNmKfYjmHjXgn/rx4ycDuywIGyK/sTaEH0iVvR/hCphv9nYLb+Pw PdARtTvYvIMGawpeLurly0sijmroF/b2XVNJVr4hR9DWTk+fQfzOgF1tI+qnHk6yAZZE nWoQ== X-Gm-Message-State: AIVw111SnI5ILFa8jPkZpIwKMbC4OaSeXe4FucIubEKzuyrqddNpoAF6 1zeIF3LY7b6UQ8Vt11Y= X-Received: by 10.99.112.3 with SMTP id l3mr1044561pgc.143.1500439227372; Tue, 18 Jul 2017 21:40:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:40:18 -1000 Message-Id: <20170719044018.18063-1-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH for-2.10] util: Introduce include/qemu/cpuid.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clang 3.9 passes the CONFIG_AVX2_OPT configure test. However, the supplied does not contain the bit_AVX2 define that we use when detecting whether the routine can be enabled. Introduce a qemu-specific header that uses the compiler's definition of __cpuid et al, but supplies any missing bit_* definitions needed. This avoids introducing any extra ifdefs to util/bufferiszero.c, and allows quite a few to be removed from tcg/i386/tcg-target.inc.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- Peter, this is the clang 3.9 problem I mentioned the other day, when attempting to reproduce the other clang 3.8 problem. r~ --- include/qemu/cpuid.h | 57 +++++++++++++++++++++++++++++++++++++++++++= ++++ tcg/i386/tcg-target.inc.c | 36 +++++++----------------------- util/bufferiszero.c | 7 +++--- configure | 43 +++++++++++++++++++---------------- 4 files changed, 92 insertions(+), 51 deletions(-) create mode 100644 include/qemu/cpuid.h diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h new file mode 100644 index 0000000..6930170 --- /dev/null +++ b/include/qemu/cpuid.h @@ -0,0 +1,57 @@ +/* cpuid.h: Macros to identify the properties of an x86 host. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_CPUID_H +#define QEMU_CPUID_H + +#ifndef CONFIG_CPUID_H +# error " is unusable with this compiler" +#endif + +#include + +/* Cover the uses that we have within qemu. */ +/* ??? Irritating that we have the same information in target/i386/. */ + +/* Leaf 1, %edx */ +#ifndef bit_CMOV +#define bit_CMOV (1 << 15) +#endif +#ifndef bit_SSE2 +#define bit_SSE2 (1 << 26) +#endif + +/* Leaf 1, %ecx */ +#ifndef bit_SSE4_1 +#define bit_SSE4_1 (1 << 19) +#endif +#ifndef bit_MOVBE +#define bit_MOVBE (1 << 22) +#endif +#ifndef bit_OSXSAVE +#define bit_OSXSAVE (1 << 27) +#endif +#ifndef bit_AVX +#define bit_AVX (1 << 28) +#endif + +/* Leaf 7, %ebx */ +#ifndef bit_BMI +#define bit_BMI (1 << 3) +#endif +#ifndef bit_AVX2 +#define bit_AVX2 (1 << 5) +#endif +#ifndef bit_BMI2 +#define bit_BMI2 (1 << 8) +#endif + +/* Leaf 0x80000001, %ecx */ +#ifndef bit_LZCNT +#define bit_LZCNT (1 << 5) +#endif + +#endif /* QEMU_CPUID_H */ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 01e3b4e..e4b120a 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -109,40 +109,30 @@ static const int tcg_target_call_oarg_regs[] =3D { detection, as we're not going to go so far as our own inline assembly. If not available, default values will be assumed. */ #if defined(CONFIG_CPUID_H) -#include +#include "qemu/cpuid.h" #endif =20 -/* For 32-bit, we are going to attempt to determine at runtime whether cmov - is available. */ +/* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS =3D=3D 64 # define have_cmov 1 -#elif defined(CONFIG_CPUID_H) && defined(bit_CMOV) +#elif defined(CONFIG_CPUID_H) static bool have_cmov; #else # define have_cmov 0 #endif =20 -/* If bit_MOVBE is defined in cpuid.h (added in GCC version 4.6), we are - going to attempt to determine at runtime whether movbe is available. */ -#if defined(CONFIG_CPUID_H) && defined(bit_MOVBE) -static bool have_movbe; -#else -# define have_movbe 0 -#endif - /* We need these symbols in tcg-target.h, and we can't properly conditiona= lize it there. Therefore we always define the variable. */ bool have_bmi1; bool have_popcnt; =20 -#if defined(CONFIG_CPUID_H) && defined(bit_BMI2) +#ifdef CONFIG_CPUID_H +static bool have_movbe; static bool have_bmi2; -#else -# define have_bmi2 0 -#endif -#if defined(CONFIG_CPUID_H) && defined(bit_LZCNT) static bool have_lzcnt; #else +# define have_movbe 0 +# define have_bmi2 0 # define have_lzcnt 0 #endif =20 @@ -2619,36 +2609,26 @@ static void tcg_target_init(TCGContext *s) available, we'll use a small forward branch. */ have_cmov =3D (d & bit_CMOV) !=3D 0; #endif -#ifndef have_movbe /* MOVBE is only available on Intel Atom and Haswell CPUs, so we need to probe for it. */ have_movbe =3D (c & bit_MOVBE) !=3D 0; -#endif -#ifdef bit_POPCNT have_popcnt =3D (c & bit_POPCNT) !=3D 0; -#endif } =20 if (max >=3D 7) { /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ __cpuid_count(7, 0, a, b, c, d); -#ifdef bit_BMI have_bmi1 =3D (b & bit_BMI) !=3D 0; -#endif -#ifndef have_bmi2 have_bmi2 =3D (b & bit_BMI2) !=3D 0; -#endif } -#endif =20 -#ifndef have_lzcnt max =3D __get_cpuid_max(0x8000000, 0); if (max >=3D 1) { __cpuid(0x80000001, a, b, c, d); /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs.= */ have_lzcnt =3D (c & bit_LZCNT) !=3D 0; } -#endif +#endif /* CONFIG_CPUID_H */ =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xfff= f); diff --git a/util/bufferiszero.c b/util/bufferiszero.c index eb974b7..2178d8a 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -197,7 +197,7 @@ buffer_zero_avx2(const void *buf, size_t len) =20 /* Make sure that these variables are appropriately initialized when * SSE2 is enabled on the compiler command-line, but the compiler is - * too old to support . + * too old to support CONFIG_AVX2_OPT. */ #ifdef CONFIG_AVX2_OPT # define INIT_CACHE 0 @@ -231,7 +231,8 @@ static void init_accel(unsigned cache) } =20 #ifdef CONFIG_AVX2_OPT -#include +#include "qemu/cpuid.h" + static void __attribute__((constructor)) init_cpuid_cache(void) { int max =3D __get_cpuid_max(0, NULL); @@ -243,7 +244,6 @@ static void __attribute__((constructor)) init_cpuid_cac= he(void) if (d & bit_SSE2) { cache |=3D CACHE_SSE2; } -#ifdef CONFIG_AVX2_OPT if (c & bit_SSE4_1) { cache |=3D CACHE_SSE4; } @@ -257,7 +257,6 @@ static void __attribute__((constructor)) init_cpuid_cac= he(void) cache |=3D CACHE_AVX2; } } -#endif } cpuid_cache =3D cache; init_accel(cache); diff --git a/configure b/configure index e8798ce..63a890e 100755 --- a/configure +++ b/configure @@ -358,6 +358,7 @@ libusb=3D"" usb_redir=3D"" opengl=3D"" opengl_dmabuf=3D"no" +cpuid_h=3D"no" avx2_opt=3D"no" zlib=3D"yes" lzo=3D"" @@ -1932,24 +1933,6 @@ EOF fi fi =20 -########################################## -# avx2 optimization requirement check - -cat > $TMPC << EOF -#pragma GCC push_options -#pragma GCC target("avx2") -#include -#include -static int bar(void *a) { - __m256i x =3D *(__m256i *)a; - return _mm256_testz_si256(x, x); -} -int main(int argc, char *argv[]) { return bar(argv[0]); } -EOF -if compile_object "" ; then - avx2_opt=3D"yes" -fi - ######################################### # zlib check =20 @@ -4629,7 +4612,6 @@ fi ######################################## # check if cpuid.h is usable. =20 -cpuid_h=3Dno cat > $TMPC << EOF #include int main(void) { @@ -4651,6 +4633,29 @@ if compile_prog "" "" ; then cpuid_h=3Dyes fi =20 +########################################## +# avx2 optimization requirement check +# +# There is no point enabling this if cpuid.h is not usable, +# since we won't be able to select the new routines. + +if test $cpuid_h =3D yes; then + cat > $TMPC << EOF +#pragma GCC push_options +#pragma GCC target("avx2") +#include +#include +static int bar(void *a) { + __m256i x =3D *(__m256i *)a; + return _mm256_testz_si256(x, x); +} +int main(int argc, char *argv[]) { return bar(argv[0]); } +EOF + if compile_object "" ; then + avx2_opt=3D"yes" + fi +fi + ######################################## # check if __[u]int128_t is usable. =20 --=20 2.9.4