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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.42.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xqx1Vh/Vc+F2jmpWT8l+QuKO2hRbi0zShSOmDW6EvAw=; b=Dri4H0+LZ3nLlVDNC3X2S/cEh2FDXNpDZ5WI/KVCyRS7ig8WGr8L5uM/2XfBYkGRme DfBRL/DQGrntZ2Q/mNMg1ItIR9h9j5WSwlQcjsoch8YH3jTXim2guW7WnPrQumD12phc Qi3g0waBuiBwWVH4bva/7n3lmgFTUu/5/eqlrs3yJpKgWy7n0kOCaVUTJJAl6Pqc0k+p z7yhNUSfhXM26KlGCBypL6N0iPQtQWQpjQa/do11WV70/044f7/0hLpVBu6F1iFxvhLu sF1YNwxzDtWBbOdz7Hk3kcx2nmPb/IIGu0ObWhINCgVhfVjZPxKvObfBhOQDEtycsVpW 2vNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Xqx1Vh/Vc+F2jmpWT8l+QuKO2hRbi0zShSOmDW6EvAw=; b=hui0dWppuZ8XAiGJ55QY6ZlXvZNzkk22HKxOHKQpJgOgmcaeS3mkS7r/oRX4P7ijea JkfgpZsD/DZG+gH7Yn8zV6ogsR7xOUE8XWp2eKgEeJH+bkQoZQuotS+SRnffMwsUtNzB 6PUxIzGsJlZZ52tzQhP9uiWFpnM1Mk4xa8momu73PWOSzEGkifcd7xLPD9lqU7if93E5 IyDFupvGTK66l/AGro1V6WiuGUt/ZhWmYd1uAuhB5Vtzvfj/zGpr2UhYFTmjqnXEV87i W6QjcfO6JmMxnQuzd7hsPBB35CtYBhSYxfGTf95kZubPW5ByzeLkAwLuXZriZldNY8r9 Jt/A== X-Gm-Message-State: AIVw111bDyaDxjjTzTHrF2cSc4Re0+/kkWZBNt2fGHvN1pHqYtrJXvEH FJdmTa6jnHGpVYdaeik= X-Received: by 10.84.143.36 with SMTP id 33mr19923501ply.171.1500111772720; Sat, 15 Jul 2017 02:42:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:10 -1000 Message-Id: <20170715094243.28371-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v14 01/34] Pass generic CPUState to gen_intermediate_code() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Needed to implement a target-agnostic gen_intermediate_code() in the future. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: David Gibson Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- include/exec/exec-all.h | 2 +- target/arm/translate.h | 4 ++-- accel/tcg/translate-all.c | 2 +- target/alpha/translate.c | 5 ++--- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 6 +++--- target/cris/translate.c | 7 +++---- target/hppa/translate.c | 5 ++--- target/i386/translate.c | 5 ++--- target/lm32/translate.c | 4 ++-- target/m68k/translate.c | 5 ++--- target/microblaze/translate.c | 4 ++-- target/mips/translate.c | 5 ++--- target/moxie/translate.c | 4 ++-- target/nios2/translate.c | 5 ++--- target/openrisc/translate.c | 4 ++-- target/ppc/translate.c | 5 ++--- target/s390x/translate.c | 5 ++--- target/sh4/translate.c | 5 ++--- target/sparc/translate.c | 5 ++--- target/tilegx/translate.c | 5 ++--- target/tricore/translate.c | 5 ++--- target/unicore32/translate.c | 5 ++--- target/xtensa/translate.c | 5 ++--- 24 files changed, 49 insertions(+), 64 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bf8da2a..48d9d11 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t; =20 #include "qemu/log.h" =20 -void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index 15d383d..e5da614 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -146,7 +146,7 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -155,7 +155,7 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock= *tb) +static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) { } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4e1831c..02b357f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1273,7 +1273,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(&tcg_ctx); =20 tcg_ctx.cpu =3D ENV_GET_CPU(env); - gen_intermediate_code(env, tb); + gen_intermediate_code(cpu, tb); tcg_ctx.cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc_ptr); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e..7b39101 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2911,10 +2911,9 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) return ret; } =20 -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUAlphaState *env =3D cs->env_ptr; DisasContext ctx, *ctxp =3D &ctx; target_ulong pc_start; target_ulong pc_mask; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e55547d..f9bd1a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,10 +11190,10 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) +void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) { - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cs->env_ptr; + ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; target_ulong next_page_start; diff --git a/target/arm/translate.c b/target/arm/translate.c index 0862f9e..e80cc35 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { + CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; target_ulong next_page_start; @@ -11804,7 +11804,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cpu, tb); + gen_intermediate_code_a64(cs, tb); return; } =20 diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca..12b96eb 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *en= v, DisasContext *dc) */ =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - CRISCPU *cpu =3D cris_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUCRISState *env =3D cs->env_ptr; uint32_t pc_start; unsigned int insn_len; struct DisasContext ctx; @@ -3105,7 +3104,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) * delayslot, like in real hw. */ pc_start =3D tb->pc & ~1; - dc->cpu =3D cpu; + dc->cpu =3D cris_env_get_cpu(env); dc->tb =3D tb; =20 dc->is_jmp =3D DISAS_NEXT; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e10abc5..900870c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) return gen_illegal(ctx); } =20 -void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUHPPAState *env =3D cs->env_ptr; DisasContext ctx; ExitStatus ret; int num_insns, max_insns, i; diff --git a/target/i386/translate.c b/target/i386/translate.c index ed3b896..cab9e32 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8378,10 +8378,9 @@ void tcg_x86_init(void) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_ptr; uint32_t flags; diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 692882f..f68f372 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_= t ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { + CPULM32State *env =3D cs->env_ptr; LM32CPU *cpu =3D lm32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t next_page_start; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3a519b7..9161df2 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5519,10 +5519,9 @@ static void disas_m68k_insn(CPUM68KState * env, Disa= sContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUM68KState *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; int pc_offset; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index cb65d1e..a24373c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1625,10 +1625,10 @@ static inline void decode(DisasContext *dc, uint32_= t ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { + CPUMBState *env =3D cs->env_ptr; MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc =3D &ctx; diff --git a/target/mips/translate.c b/target/mips/translate.c index befb87f..7a45aa6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -19882,10 +19882,9 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUMIPSState *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; target_ulong next_page_start; diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 0660b44..3cfd232 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ct= x) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { + CPUMoxieState *env =3D cs->env_ptr; MoxieCPU *cpu =3D moxie_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2f3c2e5..8b97d65 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t e= xcp) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUNios2State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e49518e..a014131 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, O= penRISCCPU *cpu) } } =20 -void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock = *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { + CPUOpenRISCState *env =3D cs->env_ptr; OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t next_page_start; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c0cd64d..acb6e88 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7203,10 +7203,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, } =20 /*************************************************************************= ****/ -void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D cs->env_ptr; DisasContext ctx, *ctxp =3D &ctx; opc_handler_t **table, *handler; target_ulong pc_start; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 592d6b0..cd8c38d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5764,10 +5764,9 @@ static ExitStatus translate_one(CPUS390XState *env, = DisasContext *s) return ret; } =20 -void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - S390CPU *cpu =3D s390_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUS390XState *env =3D cs->env_ptr; DisasContext dc; target_ulong pc_start; uint64_t next_page_start; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8bc132b..1a5ca39 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1815,10 +1815,9 @@ static void decode_opc(DisasContext * ctx) } } =20 -void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUSH4State *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d..293b9c6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5747,10 +5747,9 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) } } =20 -void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock * tb) { - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUSPARCState *env =3D cs->env_ptr; target_ulong pc_start, last_pc; DisasContext dc1, *dc =3D &dc1; int num_insns; diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ff2ef7b..ace2830 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, = uint64_t bundle) } } =20 -void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - TileGXCPU *cpu =3D tilegx_env_get_cpu(env); + CPUTLGState *env =3D cs->env_ptr; DisasContext ctx; DisasContext *dc =3D &ctx; - CPUState *cs =3D CPU(cpu); uint64_t pc_start =3D tb->pc; uint64_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; int num_insns =3D 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ddd2dd0..4e4198e 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasCo= ntext *ctx, int *is_branch) } } =20 -void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *= tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - TriCoreCPU *cpu =3D tricore_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUTriCoreState *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 666a201..8f30cff 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, = DisasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUUniCore32State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; uint32_t next_page_start; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 2630024..f3f0ff5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, Di= sasContext *dc) } } =20 -void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUXtensaState *env =3D cs->env_ptr; DisasContext dc; int insn_count =3D 0; int max_insns =3D tb->cflags & CF_COUNT_MASK; --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500111902678289.0432416549023; Sat, 15 Jul 2017 02:45:02 -0700 (PDT) Received: from localhost ([::1]:41308 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJdF-0005eH-7z for importer@patchew.org; Sat, 15 Jul 2017 05:45:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbE-0003XP-QY for qemu-devel@nongnu.org; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.42.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:42:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LXXYENNpcpmx9J7RuDYXQd/DGQCn8pPpfpNDrv1YARE=; b=q3pGC0Gk6WVJXdkRknjd4MD2muB3KfYK04da9X3zkexsgCuTebbph7YLkMHcPiHuzT aHTsVhxr6oWEG8LY6vhkbUQvMsNP+R2O0yC1xUnlRlLRXNVtwVqU1VtiL8fxOqrchdG3 gP1EswZGGdwNbMNlkUh49kHJ/cSnpj2hF9EpQsOIF/tvPL8OeUpUy6EctnmJQG4UbHBh 1qbWXzLu0Kj7sEZ0+e7wDD9gYX7kEE26IL8paTv4Mx5JDqvRBE9j08Wac0JWZXE0wNxc Kc0kpoq31y9Y02H8mMII7MWPqxi7VWCFsRotuLzmdl0CoRv5R96Pdw2Pg3E8IFkyKmyP t3ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=LXXYENNpcpmx9J7RuDYXQd/DGQCn8pPpfpNDrv1YARE=; b=b0wB/cXeuvUcwm3SbOXJ/LkAZsBHgzKNAI9w+H3uWboqVpcRz5A9mw/O4fCOJpV1wx iREUb4Wx9xhfV3PZadfzqskDGncqQ1/HneAJKajTUUF+KoPNfvyDf/2IF2f7Bz4aYRsF 9IWaFoE5DiM6Ls1sCVjCQ5VaSi2u4+bmw08D97O1Fl3I4iRW8wECnVQf1RVv2kNjqaOS mSBMLl4HviSMHaQSOOeinvGOguvPD+8/xa9+F499Wolf03iYhWlgFhX+pcFPcVWiWdVK riGRMLnIijk/qdbEpvlJDlEUkRIHTtuGFwhSLqfvDXuTr7ExLYxvoPLX3B5lAvfhavWy KxCQ== X-Gm-Message-State: AIVw1101ROJmP/FXiFGCvjYj4VlrWivWsZfz2kLFTV5epAAdPuNbfBJS pedr3KD6xQBLyHKipJ0= X-Received: by 10.84.216.92 with SMTP id f28mr20441946plj.199.1500111774650; Sat, 15 Jul 2017 02:42:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:11 -1000 Message-Id: <20170715094243.28371-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 02/34] tcg: Add generic DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova --- include/exec/exec-all.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 48d9d11..6760078 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -40,6 +40,7 @@ typedef ram_addr_t tb_page_addr_t; #define DISAS_JUMP 1 /* only pc was modified dynamically */ #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP 3 /* only pc was modified statically */ +#define DISAS_NORETURN 4 /* the tb has already been exited */ =20 #include "qemu/log.h" =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112084410112.41769961962109; Sat, 15 Jul 2017 02:48:04 -0700 (PDT) Received: from localhost ([::1]:41321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJgA-0007n9-Mk for importer@patchew.org; Sat, 15 Jul 2017 05:48:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38030) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbH-0003YL-4S for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbG-0003Bv-0x for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:42:59 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34579) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbF-0003Bj-PP for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:42:57 -0400 Received: by mail-pf0-x242.google.com with SMTP id c24so13734652pfe.1 for ; Sat, 15 Jul 2017 02:42:57 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.42.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:42:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wwCYZXiHrg9w0eaYio5ZyAUvIB1FH9ld5+bP3Xy8kaI=; b=PtB430MX5Zu+rxaQxLoqELTS+m0I3KP5ZjU6XPNs1Lalg6Bb9WqWPrP6S3FMTSfFXi IdqkwDpwhzDQyejiGQ6IeUaKhm/xt6XwwspXlU6qq/IipYInQvKe7CCPNmElGJehhGdh XUGfJIk1AccG1Xw2WyUnOySBfPzWKx8eXfsoiqKLO0pj3DtTE9fo78criDVsF9cWONX0 kY5rtRqgj8IAnTE4CzfrLZRGBqO4RJ18o9/Qk4ftpzEiamxQ3stsvraLpTBuPzTNFPal C+SvAraUB148B0rlUQAghqRkQ9ylInNVEsRDNPpfCuoaDBUW7Z6kT5+5zOU0L3WkmYlT BuGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wwCYZXiHrg9w0eaYio5ZyAUvIB1FH9ld5+bP3Xy8kaI=; b=GAqpeHx1w+O6+CpP6YZxAUgMzHhRMJ/fk3MTC0zZTOwNC5WzTmo79tRSAsCEal7xsa oohvOI2XjiwM5Mf6Od+jw8atResdjLikgTt9l6WVEOHb6Km1UYi+n80Iu8ddDa03v3YH CZCboNlwnlc+KNVsl8ovMH9xXqCNyBsNEcZ/UKF+h6nX/+kmIZT1lH9LCUa/51zS0hXL Gt0Y2vFOQC18T6W4GRRRrIT+gqyOvfekcqfsaHFMBOMAQoXsDClZ4RQbJ9EKFwneFru+ 4LCDLz+UKSDT5YjuyTX29g5Hu1J/qqL5wwJL7lRndWc5c1SuEeFPj5CLHAoUlHlBzNTx ounQ== X-Gm-Message-State: AIVw1130rwIYxIqyh7y9Pau7gtVwhTLx4o1WK/pYv2oQ6MYd/zDi4erh cEqu3oR0TeEwxUNnk/k= X-Received: by 10.84.215.157 with SMTP id l29mr3854667pli.177.1500111776475; Sat, 15 Jul 2017 02:42:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:12 -1000 Message-Id: <20170715094243.28371-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v14 03/34] target/i386: Use generic DISAS_* enumerators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack segment modifying cases, we have not yet exited the TB (therefore DISAS_NORETURN feels wrong), but intend to exit. The caller of gen_movl_seg_T0 currently checks for any non-zero value, therefore DISAS_TOO_MANY seems acceptable for that usage. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/i386/translate.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index cab9e32..3ffbf1b 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -31,6 +31,7 @@ #include "trace-tcg.h" #include "exec/log.h" =20 +#define DISAS_TOO_MANY 5 =20 #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 @@ -2153,6 +2154,7 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + s->is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2173,7 +2175,6 @@ static inline void gen_jcc(DisasContext *s, int b, =20 gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp =3D DISAS_TB_JUMP; } else { l1 =3D gen_new_label(); l2 =3D gen_new_label(); @@ -2243,12 +2244,14 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { + s->is_jmp =3D DISAS_TOO_MANY; + } } else { gen_op_movl_seg_T0_vm(seg_reg); - if (seg_reg =3D=3D R_SS) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS) { + s->is_jmp =3D DISAS_TOO_MANY; + } } } =20 @@ -2420,7 +2423,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2458,7 +2461,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2466,7 +2469,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2541,7 +2544,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -2580,7 +2583,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong = eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp =3D DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -6942,7 +6944,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7187,7 +7189,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7370,7 +7372,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112091835674.4104827949998; Sat, 15 Jul 2017 02:48:11 -0700 (PDT) Received: from localhost ([::1]:41323 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJgI-0007ve-HC for importer@patchew.org; Sat, 15 Jul 2017 05:48:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbL-0003aB-4y for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbI-0003Ck-1b for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:03 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbH-0003CF-Q6 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:42:59 -0400 Received: by mail-pf0-x244.google.com with SMTP id q85so13697534pfq.2 for ; Sat, 15 Jul 2017 02:42:59 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.42.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=heIcfDW4p6yjTT3+UC0W+4spSAhL6XuXLL6EfLZTAZ8=; b=quwu8M9UYCqvjyJ5ivI5gQ4KXoX2dX3YTBHDguK5TaoC0ipF8V6/D2qyuLXfhCSc9G HgpyiOxkd1n69FhvukC0DjmwbDaZdCczw1Se5m+O6+Mp2cKE3IqvjnMsJjP2JLZ0QOsL 9ydIZOTrNsM6IO/3TnOc3YGw7r3M5ntmamSBUpsGCkA70DGQNdEjCaNtlOUPMcWerbLW 9P3ed2C5TJgpAbOTA4BLlyxw1oZNayonaYNgVlSMF2sVvotlbLEblovnJdx6Jrr/Zvz1 u/lNlMOIMNzh6sU/kSX0zT0OOsqI9KxWO8eE3hMF6X31Hjc3jZ5N+HduaNgZGxK8nlTk FPmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=heIcfDW4p6yjTT3+UC0W+4spSAhL6XuXLL6EfLZTAZ8=; b=j3ImpeSFILioEschHKy5nWRaQAsh89CFa8JhLXSxHKer3rcEgCuH6LjdPtIZMaEozX yT8kcwjmh6Fl+YjT+00K2SxYPFMtj/LYfzuE27rH3Wr5S3pKBhH8HO3Z1shE7cdr2/dL STNSTyRAbUFoc7qSZ183HDNfxvVeQr725YV82CUgkyO+AIrDTCjWOL2QZ62hjX+mVvto MP0sunwqF8aSHHxWdaZ8p/dQ6iot7y9GESdU2JMsDpzgr/GlzKgQJjxRvl3RGwYbRuNg OHTtEnV7GhOaOULtE602Ml1mR7ugXAEDDhmKbGL6rnOPwU9IZH5X6qp4YB0oBZpSwwvS GjQw== X-Gm-Message-State: AIVw1106fPVu2hgkf0e49M8L8Gabr+w3XUEiYiX7X1uAqXg7Fk0UbGrt 0Ijn4Zxz+Vx/V9shTlo= X-Received: by 10.99.147.19 with SMTP id b19mr9487708pge.67.1500111778531; Sat, 15 Jul 2017 02:42:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:13 -1000 Message-Id: <20170715094243.28371-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 04/34] target/arm: Use DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.h | 8 ++------ target/arm/translate-a64.c | 37 ++++++++++++++++++++----------------- target/arm/translate.c | 15 ++++++++------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index e5da614..08ff0b3 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,12 +124,8 @@ static void disas_set_insn_syndrome(DisasContext *s, u= int32_t syn) * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 -/* For instructions which unconditionally cause an exception we can skip - * emitting unreachable code at the end of the TB in the A64 decoder - */ -#define DISAS_EXC 6 +#define DISAS_WFI 5 +#define DISAS_SWI 6 /* WFE */ #define DISAS_WFE 7 #define DISAS_HVC 8 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f9bd1a9..342ff7c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -371,7 +371,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { @@ -380,7 +380,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } } } @@ -11316,7 +11316,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) assert(num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11343,21 +11343,25 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp !=3D DISAS_EXC) { + if (unlikely(cs->singlestep_enabled || dc->ss_active)) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code = as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp !=3D DISAS_TB_JUMP); - if (dc->is_jmp !=3D DISAS_JUMP) { + switch (dc->is_jmp) { + default: gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); + /* fall through */ + case DISAS_JUMP: + if (cs->singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; } } else { switch (dc->is_jmp) { @@ -11374,8 +11378,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) case DISAS_EXIT: tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: case DISAS_SWI: break; case DISAS_WFE: diff --git a/target/arm/translate.c b/target/arm/translate.c index e80cc35..fea76fb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -1182,7 +1182,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1191,7 +1191,7 @@ static void gen_exception_insn(DisasContext *s, int o= ffset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -4179,7 +4179,7 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) gen_bx_im(s, dest); } else { gen_goto_tb(s, 0, dest); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } } =20 @@ -11936,7 +11936,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } #endif @@ -12081,6 +12081,8 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + case DISAS_NORETURN: + break; } } else { /* While branches must always occur at the end of an IT block, @@ -12105,8 +12107,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* indicate that the hash table must be used to find the next = TB */ tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: /* nothing more to generate */ break; case DISAS_WFI: --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.42.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u2IT8Xo+u0/WqLoLvCNxUtEkoHYcgNk9sOk6Gytqel4=; b=eGaPjsjuuBoe8Xvk47B2dVXhTdyS4I3V7peRI27XW5d5nDTcXhmqX9I2+PWdUdpLJ9 nLC+zlQnuNS4BKpSpIVVtRSUYk/UOGvW4US5WYO4InZHJSvPG0JzQQpq1R/fOsh22Ve1 SqzgGQdrjvuwmnnP+DPaQoc8vzQ/vSI975jq2aUUJSvIJDu+SvX2umhf7tELdzzWnsjm 973uoOo7/TotZxiYR0JRhm03lLza5SJ9aMe4wSsyin/etLBTlcjr6f20IsGJrXU/+TgV CG0c34g9IMHi1NHJ9iYFic821RY7H3rBANVN1yJmKU7XSK3MVpo+YAtBnV4z3MP+FlB4 lacA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=u2IT8Xo+u0/WqLoLvCNxUtEkoHYcgNk9sOk6Gytqel4=; b=RSXPCc1XFf5ZPVlu19zdugzs6713CihC5Na24fDBEfgp9cDSdRaDI1+rOfNTqkCYSK jF+hmDTxXK+vCc0hSecUIjYQDROkIp1cu/0eH8h/YwkIa3T8ZSOI02wVbHpNrY74TZwC g1YgFJ6UK77uX9iUheiR8ebDlOVxf9dOIrov3teuFnR4+RJEwEqm+HOG40Y3Q+4A7cRj QySNk5pkIXiZysIzMsq7u5nrhy+NNLlTLUpX+2+r+UaZbAZDU33NZFVCUdUJP6TietPn Eu/q5w6eLTfN8LVAVReiMcYsNECww4i3OWVUZbGPlt6i5tubDONMIzOb59r/EuFsw4Qu Gy4A== X-Gm-Message-State: AIVw112jDvNMkv/ZUWpbVZ+5RI+UPKdzOh64VoajxFApXU91gBYQNFq+ YhiAhh1ZncqKSrug39k= X-Received: by 10.99.149.83 with SMTP id t19mr19189815pgn.247.1500111780523; Sat, 15 Jul 2017 02:43:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:14 -1000 Message-Id: <20170715094243.28371-6-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 05/34] target: [tcg] Use a generic enum for DISAS_ values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 7 ------- include/exec/translator.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate.h | 23 ++++++++++++++--------- target/cris/translate.c | 7 ++++++- target/i386/translate.c | 3 +-- target/lm32/translate.c | 6 ++++++ target/m68k/translate.c | 7 ++++++- target/microblaze/translate.c | 6 ++++++ target/nios2/translate.c | 6 ++++++ target/openrisc/translate.c | 6 ++++++ target/s390x/translate.c | 3 ++- target/unicore32/translate.c | 7 ++++++- target/xtensa/translate.c | 4 ++++ 13 files changed, 103 insertions(+), 22 deletions(-) create mode 100644 include/exec/translator.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6760078..ba6c641 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,13 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif =20 -/* is_jmp field values */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_UPDATE 2 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP 3 /* only pc was modified statically */ -#define DISAS_NORETURN 4 /* the tb has already been exited */ - #include "qemu/log.h" =20 void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000..b51b8f8 --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,40 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_NORETURN: Following code is dead. + * @DISAS_TARGET_*: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_NORETURN, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 08ff0b3..cca3c37 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; @@ -119,26 +122,28 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) s->insn_start_idx =3D 0; } =20 -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 5 -#define DISAS_SWI 6 +#define DISAS_WFI DISAS_TARGET_2 +#define DISAS_SWI DISAS_TARGET_3 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_4 +#define DISAS_HVC DISAS_TARGET_5 +#define DISAS_SMC DISAS_TARGET_6 +#define DISAS_YIELD DISAS_TARGET_7 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_8 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_9 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/cris/translate.c b/target/cris/translate.c index 12b96eb..38a999e 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" =20 #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) =20 -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 =20 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index 3ffbf1b..11bc455 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -31,8 +32,6 @@ #include "trace-tcg.h" #include "exec/log.h" =20 -#define DISAS_TOO_MANY 5 - #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f68f372..65bc9c0 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" =20 #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ =20 #define MEM_INDEX 0 =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9161df2..d980c5e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } =20 -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically = */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a24373c..bd43a42 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" =20 #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d65..6b09618 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a014131..112db1a 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index cd8c38d..6ed3837 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -76,7 +76,8 @@ typedef struct { } u; } DisasCompare; =20 -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 =20 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 8f30cff..6c094d5 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 =20 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f3f0ff5..d7bf07e 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" =20 =20 +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically= */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500111976254421.6748350037574; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=v7WGv3BH4klOGL4TNykm0pjMZLu7EoBx9oZhVsyhFVo=; b=iqnT/Zp+nNdN3wapj1Tv2hXx8fo+xYm2Ozf26u0lC6fsLWSdQ/gvL8qzMmL5tl+Wlu dMbH+xlnDumQKRo3gFCH5XY0IZ6eWQ8t1LXxxjLbSBKBWpLMNeX1m4qsga42yIxiuMtV riFhS5UxcWJuplht64PJqXDWhyY4wVfv1gdIbK3IK+32GLRiXAHqhNrBZLKMb/kOIabC q5Ofl9ym9OjFtrgLL6f37FFkAqJ78wEgU9kjG2mFFgSngQzjOmSSaEXD3/O4mNDB2RhC JwfnMnzDNTFNbG4JSz1OpUZ3ikNQlFyLEmcYyqjEgY2ZYbL8shW9hZB/gCPpK0CFMqO1 uWIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=v7WGv3BH4klOGL4TNykm0pjMZLu7EoBx9oZhVsyhFVo=; b=WZQUbQ36pjHjyQfCgbo1NZTJEaMj0/XChkN/LmuhQ78iM7/Gdk53UUzJbsntjP9i68 EJF45r4/BAwfkCNWR5/hKQc+iR5gFpKeRZLe/ULlDEMI6K0iuCdTBxESwFV+DMfemOcb mIZymsQAVZTOe5ie1lh3qtt/G30rwYj3xY6JLrYVuPSlecNaxFvPTL3EFSkaFpbF+K5R Ybi4CwTbfLcat2YBXNJLiVmmx77o57+XCEgNOBQ4hpjelsmH1KMGN/CA/o0HypqtqhCJ Q4nYY7Um1t6sQzMcPR3tuIgZr1keKW1wNCAvDAFSOtNq8fmr4CxaQkNoPDejicqb1SGd R62w== X-Gm-Message-State: AIVw111y95zSkr2iJsifiUa1ogLiK4//oF44dVISFjWQGU6bk1aN+JDb KzVqLcfLbI55LdF6sLQ= X-Received: by 10.84.143.34 with SMTP id 31mr20509167ply.198.1500111782337; Sat, 15 Jul 2017 02:43:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:15 -1000 Message-Id: <20170715094243.28371-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 06/34] target/arm: Delay check for magic kernel page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fea76fb..2ae68ce 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11930,17 +11930,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) 0); num_insns++; =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; - break; - } -#endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -11972,6 +11961,17 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_io_start(); } =20 +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->is_jmp =3D DISAS_NORETURN; + break; + } +#endif + if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112329896361.9573270663999; Sat, 15 Jul 2017 02:52:09 -0700 (PDT) Received: from localhost ([::1]:41337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJk8-0003Px-Id for importer@patchew.org; Sat, 15 Jul 2017 05:52:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38088) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbO-0003df-RV for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbO-0003Ev-4j for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:06 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34919) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbN-0003Ei-W7 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:06 -0400 Received: by mail-pg0-x242.google.com with SMTP id d193so13339788pgc.2 for ; Sat, 15 Jul 2017 02:43:05 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kclu/7ee07serOTh5ukskPzO5W/o6EAAB8FQoMP1pHY=; b=TrkcUd3QMaC+nn5FrTf8ThatnUMvaRkSbspeHpclZtMaM9Z7yXLoLRyWoOxxvIHY4F snMKLGEl5NYxpq24bZRtlAzvAldN8oYXUYwqteIHnoB69GLK264BHY7MO/g2g2IVvrYC USaO3IbcjCz0EauLyJldqmNTlmDANvN+7Y5QpEhiTt8bBMK/uryLgZJ1MXSlQuifMvez bsaZA2ZEodoG15jcH3apF2BSVmHrKcA49yqXBsyZHDU6Nm5bLYL4WnWKIvEw0KzMCzMp Ok98d8C7caT/PJhCoDlldogWHbR+Zlyt5+dUZjDkQGp8EW8AN2E7fgkHX4hdowROBCTy flbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Kclu/7ee07serOTh5ukskPzO5W/o6EAAB8FQoMP1pHY=; b=bo3m6f0a5unMRCqA9uGYNn8kBHH7DmfVsvXuXXTyNkAX4bgDbaToK2ED8hq8l2YKVu A9UliCbQ7sM70a+hLjv2tRVjYMvLDA80O4NSOPc71LKxuCFQxdIMrxxMJIpi8nhtA/RC wp4o5EvectQqXE/ZGvj7cBbwIgNLsjJRA6FKSqZWFmtjBK2OZFXMBtTpz9gAVTypm7ne jsTVqw21g4b8SmwpPPxcCxr5pENSuNMHNDIdKX44SDIoIVUITRUabqgfDrSdxIlPpqJo fbkWoyg3Ov+JhMHzsnAIkZwcp52lIlHsPbHCEexNaKUHtGgFBLxtwoDTvPPZ9U9hY8kU R4oA== X-Gm-Message-State: AIVw111YIcfTMP3g99vGhHCnOYGLT7Ux2++XVe3wihVPSOlKaAVscrRY FUEJC0TkzGDJzO37lcQ= X-Received: by 10.84.197.129 with SMTP id n1mr20304340pld.32.1500111784896; Sat, 15 Jul 2017 02:43:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:16 -1000 Message-Id: <20170715094243.28371-8-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 07/34] target/arm: Set is_jmp properly after single-stepping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have generated an exception, so use DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 1 + target/arm/translate.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 342ff7c..657684b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11285,6 +11285,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) dc->is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + dc->is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we diff --git a/target/arm/translate.c b/target/arm/translate.c index 2ae68ce..83e5491 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11942,6 +11942,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + dc->is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we @@ -11986,7 +11987,8 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) assert(num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - goto done_generating; + dc->is_jmp =3D DISAS_NORETURN; + break; } =20 if (dc->thumb) { --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112268269879.3291867010622; Sat, 15 Jul 2017 02:51:08 -0700 (PDT) Received: from localhost ([::1]:41335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJj8-0002c8-O9 for importer@patchew.org; Sat, 15 Jul 2017 05:51:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbR-0003h9-Vl for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbQ-0003GD-DL for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:10 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:35606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbQ-0003FO-4d for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:08 -0400 Received: by mail-pf0-x243.google.com with SMTP id q85so13697829pfq.2 for ; Sat, 15 Jul 2017 02:43:07 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lz5OJXQ+u3T7YIFTgNkAkQwujaHjIMhKyDdhbQS1/fk=; b=pLFME3OucnPOdrokeCofNIaOzsHv3U5q+bYXDcMzS+GZYrMJxtyfGwl05us4iceIR5 4lN8oaHz9M6FZs92aMrJJ9YcPfEhEpSyW799zPf1RYPD/E57Grs4RyZDp6Pu49iCslQl LJzhkfiTYKUBA3Eh1H9v9TjYSRxEHlIsWE7sd/sB4vIRFfzsC6EdH/LCBKDMOtXX23Hc GkBxFkNQZRF2LO0uYNZXAXF9SQZ99AzynVcjSHx/ZaJUnz0CycwMeOvb7/EF0z7c+iY3 QxquOxbWWYQtRsV7hdYDCur2RpwRo/8hPaUn6cS6NiS7ZylH8HkzD1D7R0Vqse3Zp1ag AkCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Lz5OJXQ+u3T7YIFTgNkAkQwujaHjIMhKyDdhbQS1/fk=; b=ev3rE3HpC2Q9xDAR8jRwuTCqGceOyBUGJNtohTggRyCnLpJOU/M3l2dQkpy3ooLDQ9 GhxFMlczy1O0sHyiyBafIVdRu7IsPrIx4wCqmruuqMZv4LnrzHOWYfUlRgqyHFqRpMaA JF/GZvsUXx2jplJYCqf+mIzrMKPMf3HzYHW+ru8JvpKmA9TwjVF/m7y2tPeyrxVA17YN plntKE6HY/C3DKm2b7uDJOq+CQej8Jjn/BxpeLp+c74GoOBdwBjyWguRef8KWW5HvfUj wUi/95shDGpxWsXIkTys0ZQlEuKdO7KhK817LnwrMJ1XhkxqUla3kO1sfaqY3uWmWVUG RjlA== X-Gm-Message-State: AIVw111I4l6HpvUjpHjWcm+AGGX2hML+FzPvxk0P6KvudXGqzJbp/mKS 710do0nLCgi6hPqcNk4= X-Received: by 10.98.46.131 with SMTP id u125mr9574826pfu.238.1500111786895; Sat, 15 Jul 2017 02:43:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:17 -1000 Message-Id: <20170715094243.28371-9-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v14 08/34] tcg: Add generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002073981.22386.9870422422367410100.stgit@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed tcg_check_temp_count from generic loop. Moved gen_io_end to exactly match gen_io_start. Use qemu_log instead of error_report for temporary leaks. Moved TB size/icount assignments before disas_log.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- include/exec/translator.h | 101 +++++++++++++++++++++++++++++++++++ accel/tcg/translator.c | 133 ++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/Makefile.objs | 1 + 3 files changed, 235 insertions(+) create mode 100644 accel/tcg/translator.c diff --git a/include/exec/translator.h b/include/exec/translator.h index b51b8f8..aa84376 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -10,6 +10,19 @@ #ifndef EXEC__TRANSLATOR_H #define EXEC__TRANSLATOR_H =20 +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + /** * DisasJumpType: * @DISAS_NEXT: Next instruction in program order. @@ -37,4 +50,92 @@ typedef enum DisasJumpType { DISAS_TARGET_11, } DisasJumpType; =20 +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: + * Initialize the target-specific portions of DisasContext struct. + * The generic DisasContextBase has already been initialized. + * Return max_insns, modified as necessary by db->tb->flags. + * + * @tb_start: + * Emit any code required before the start of the main loop, + * after the generic gen_tb_start(). + * + * @insn_start: + * Emit the tcg_gen_insn_start opcode. + * + * @breakpoint_check: + * When called, the breakpoint has already been checked to match the = PC, + * but the target may decide the breakpoint missed the address + * (e.g., due to conditions encoded in their flags). Return true to + * indicate that the breakpoint did hit, in which case no more breakp= oints + * are checked. If the breakpoint did hit, emit any code required to + * signal the exception, and set db->is_jmp as necessary to terminate + * the main loop. + * + * @translate_insn: + * Disassemble one instruction and set db->pc_next for the start + * of the following instruction. Set db->is_jmp as necessary to + * terminate the main loop. + * + * @tb_stop: + * Emit any opcodes required to exit the TB, based on db->is_jmp. + * + * @disas_log: + * Print instruction disassembly to log. + */ +typedef struct TranslatorOps { + int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, + int max_insns); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, + const CPUBreakpoint *bp); + void (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translator_loop: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When set by #TranslatorOps::insn_start. + * - When set by #TranslatorOps::translate_insn. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + +void translator_loop_temp_check(DisasContextBase *db); + #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000..cb7ba96 --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,133 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + +void translator_loop_temp_check(DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + qemu_log("warning: TCG temporary leaks before " + TARGET_FMT_lx "\n", db->pc_next); + } +} + +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb =3D tb; + db->pc_first =3D tb->pc; + db->pc_next =3D db->pc_first; + db->is_jmp =3D DISAS_NEXT; + db->num_insns =3D 0; + db->singlestep_enabled =3D cpu->singlestep_enabled; + + /* Instruction counting */ + max_insns =3D db->tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + + max_insns =3D ops->init_disas_context(db, cpu, max_insns); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + /* Reset the temp count so that we can identify leaks */ + tcg_clear_temp_count(); + + /* Start translating. */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit = */ + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D db->pc_next) { + if (ops->breakpoint_check(db, cpu, bp)) { + break; + } + } + } + /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate + that only one more instruction is to be executed. Otherwise + it should use DISAS_NORETURN when generating an exception, + but may use a DISAS_TARGET_* value for Something Else. */ + if (db->is_jmp > DISAS_TOO_MANY) { + break; + } + } + + /* Disassemble one instruction. The translate_insn hook should + update db->pc_next and db->is_jmp to indicate what should be + done next -- either exiting this loop or locate the start of + the next instruction. */ + if (db->num_insns =3D=3D max_insns && (db->tb->cflags & CF_LAST_IO= )) { + /* Accept I/O on the last instruction. */ + gen_io_start(); + ops->translate_insn(db, cpu); + gen_io_end(); + } else { + ops->translate_insn(db, cpu); + } + + /* Stop translation if translate_insn so indicated. */ + if (db->is_jmp !=3D DISAS_NEXT) { + break; + } + + /* Stop translation if the output buffer is full, + or we have executed all of the allowed instructions. */ + if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + db->is_jmp =3D DISAS_TOO_MANY; + break; + } + } + + /* Emit code to exit the TB, as indicated by db->is_jmp. */ + ops->tb_stop(db, cpu); + gen_tb_end(db->tb, db->num_insns); + + /* The disas_log hook may use these values rather than recompute. */ + db->tb->size =3D db->pc_next - db->pc_first; + db->tb->icount =3D db->num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif +} diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 70cd474..22642e6 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o obj-y +=3D cpu-exec.o cpu-exec-common.o translate-all.o +obj-y +=3D translator.o --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112088893661.658031998681; Sat, 15 Jul 2017 02:48:08 -0700 (PDT) Received: from localhost ([::1]:41322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJgF-0007qu-GP for importer@patchew.org; Sat, 15 Jul 2017 05:48:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbV-0003k6-8H for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbS-0003Gi-N5 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:13 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbS-0003GS-DQ for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:10 -0400 Received: by mail-pf0-x244.google.com with SMTP id q85so13697918pfq.2 for ; Sat, 15 Jul 2017 02:43:10 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4c0udQdzhxkHR9XThcAHbTCOHaJuVWKX/eGrus9eUEU=; b=jcLOcQAD2f8mb2r68W0O38pRi3V2f4kiEM5QvcHW25W2aURks+Mvr8Rt/Z6g3E5Bnk uavhw2MnaAA1M7BjxfP8+gAmsZCBGNYQYT7evXpzLfMrSEB3Nwdu2CWsalzHQmjTBtUr 8KtbBZ/fGctFv1j910KwIKhP/kUBrPuS42X6XnXMVg15A89SRkydQZbpzHD1xcdFZuK7 DpHF1lNOSjVKK+w0goXudCf0b+mcz2IiEOXt9vnOViNYxLjE/bga9qz2frPb0+R16w26 pBIDQN1Ol9SeQzNgKrvOXacn6B43UtWeoY7240rxetJPLkKIZj5h95YiYRVQIT1Gj/7S YelQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4c0udQdzhxkHR9XThcAHbTCOHaJuVWKX/eGrus9eUEU=; b=j+ao+EYei2AgYfXwV71DjMkswHeUmkj7YTXvhw/Jw8omM4upLg3DsR0fsDWwqUCjMN MMXVs8tBw1GxNCzsVmCYqni0TdvqfYp6l6KWynMWsMu9ARAGj8P6KzI1p3pxHJGcN1OM hKkXPVyfs8sWnrmS/t991s62OfE7mVdPGsSFzInpp3ZH847gUUdWD2QZwC/McsKUFxtQ WHylTfzyNskvMUO1U7S6KtnHUG8gyEUQGr3MxF9046m77auNbTprku8zbETqDX2ZVQ3U lh4/lSCl9XUzx+8m4yUkABiQYmnSkdW0uNP3XQq0e95fwYNMQD6wFQIkIpomRnY9SK9n 4gQQ== X-Gm-Message-State: AIVw11360EMmfmFtVWoZjNd4nLoVSB69ZZRvUs1HGwOZ1heKduwlTlcT 1hv451HCfPTlQRV6c74= X-Received: by 10.98.95.67 with SMTP id t64mr9625554pfb.127.1500111789090; Sat, 15 Jul 2017 02:43:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:18 -1000 Message-Id: <20170715094243.28371-10-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 09/34] target/i386: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 140 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 69 insertions(+), 71 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 11bc455..7825593 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -95,6 +95,8 @@ static int x86_64_hregs; #endif =20 typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -102,8 +104,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc =3D eip + cs_base */ - int is_jmp; /* 1 =3D means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -124,12 +124,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_MA= SK) || (pc & TARGET_PAGE_MASK) =3D=3D (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2152,8 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); - s->is_jmp =3D DISAS_NORETURN; + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); + s->base.is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2244,12 +2242,12 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) stop as a special handling must be done to disable hardware interrupts for the next instruction */ if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } else { gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg =3D=3D R_SS) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } } @@ -2422,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2460,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2468,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2524,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bo= ol recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } =20 - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2543,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -4416,7 +4414,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } } =20 -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong pc_start) @@ -5376,7 +5374,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5391,7 +5389,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, ot =3D gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5442,7 +5440,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5651,7 +5649,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6307,7 +6305,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6322,7 +6320,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6338,14 +6336,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6359,14 +6357,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6377,14 +6375,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6397,14 +6395,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6943,7 +6941,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7112,11 +7110,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7188,7 +7186,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7371,7 +7369,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ @@ -7571,11 +7569,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7940,24 +7938,24 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8383,15 +8381,13 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) { CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong pc_ptr; uint32_t flags; - target_ulong pc_start; target_ulong cs_base; int num_insns; int max_insns; =20 /* generate intermediate code */ - pc_start =3D tb->pc; + dc->base.pc_first =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; =20 @@ -8404,11 +8400,11 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->tb =3D tb; + dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8458,8 +8454,8 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 - dc->is_jmp =3D DISAS_NEXT; - pc_ptr =3D pc_start; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_next =3D dc->base.pc_first; num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -8471,37 +8467,38 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) =20 gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); + gen_debug(dc, dc->base.pc_next - dc->cs_base); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - pc_ptr +=3D 1; + dc->base.pc_next +=3D 1; goto done_generating; } if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } =20 - pc_ptr =3D disas_insn(env, dc, pc_ptr); + dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); /* stop translation if indicated */ - if (dc->is_jmp) + if (dc->base.is_jmp) { break; + } /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - if (dc->tf || dc->singlestep_enabled || + if (dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8512,23 +8509,23 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) because an exception hasn't stopped this code. */ if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - !=3D ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MA= SK) - || (pc_ptr & ~TARGET_PAGE_MASK) =3D=3D 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (pc_ptr - pc_start) >=3D (TARGET_PAGE_SIZE - 32) || + (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8540,24 +8537,25 @@ done_generating: =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags =3D 2; else #endif disas_flags =3D !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, + disas_flags); qemu_log("\n"); qemu_log_unlock(); } #endif =20 - tb->size =3D pc_ptr - pc_start; + tb->size =3D dc->base.pc_next - dc->base.pc_first; tb->icount =3D num_insns; } =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112254820168.24272208879984; Sat, 15 Jul 2017 02:50:54 -0700 (PDT) Received: from localhost ([::1]:41333 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJiv-0002TY-C8 for importer@patchew.org; Sat, 15 Jul 2017 05:50:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbV-0003kH-BR for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbU-0003H7-DY for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:13 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:34601) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbU-0003Gx-4o for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:12 -0400 Received: by mail-pf0-x243.google.com with SMTP id c24so13735174pfe.1 for ; Sat, 15 Jul 2017 02:43:11 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=huiUbK/j2lt2KTO1aTEYque+0UAabLXYeyaG29XgHis=; b=XMHDdTi3Tog4BrZCsrBxTTVTyCqvDu0iySq5QhYPY7oD0pmhHbMmaLdK2APwna+1jH n6LiPUuacxvX1E2G9pciGJuTy6wycUHr4YnJfFjUaYbq/6t77tl1cq2IB+/f8rfHvIgd SCUpHtdUeYydBvoiQQUTetpE0+1wzubhy8xOzfRMaqBRjgg8V23S7lIphpFb300MCLD5 veaPHZR1w61dBObw4uv8ZDLfrC7XjEv3QpF1Hi1j9prwv6v7PWg+Yv7LHT/El1nRYVI8 i9WI34sp0+jGvEUY4EFNrmUjQ0dslEWcSCKkntnKNFyQMOpk9to29cvbYslzaWLf9lda /tuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=huiUbK/j2lt2KTO1aTEYque+0UAabLXYeyaG29XgHis=; b=bxEXsy92MIQdMC1Dw/Ix2eSZTGW7L6p89cccje7CojuTTkcoRwAAtdklFWblq5Z8eB gMcgbC1qtfU4Gfj30UwPX7YRe/6g77qniymXmulw2/5vv1GSrFJQQibmGrqvPNAzGGE4 FWFp+pK3idZYX0LPfrhrxp6ev+ZoybUZSN0XaZh5Zo+z0DhlJEXdK4tlZt75CzWHhpmG Q5jHaDzpJtHN7eiu1VXdC7/B1fze82LWYSH2gAcCUXA55PX+v37p/+2opf7oPnhNEeTb o9FC1ajN0AqIbMoD0j3NJtK4K6RQ2oxfdSikKv/jLa1sQ9ZSnlQcohgubtJ0OCaBjV50 /bqw== X-Gm-Message-State: AIVw111IexBNcE3bKmLxWsVFRAFBjCtTlscLY6iyyzli09bs5ynHdlTp YJ7PVcYx+8WDrPoUnKs= X-Received: by 10.98.160.28 with SMTP id r28mr9361991pfe.86.1500111790968; Sat, 15 Jul 2017 02:43:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:19 -1000 Message-Id: <20170715094243.28371-11-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v14 10/34] target/i386: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/i386/translate.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 7825593..651abca 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8376,20 +8376,13 @@ void tcg_x86_init(void) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cpu, + int max_insns) { - CPUX86State *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first =3D tb->pc; - cs_base =3D tb->cs_base; - flags =3D tb->flags; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUX86State *env =3D cpu->env_ptr; + uint32_t flags =3D dc->base.tb->flags; + target_ulong cs_base =3D dc->base.tb->cs_base; =20 dc->pe =3D (flags >> HF_PE_SHIFT) & 1; dc->code32 =3D (flags >> HF_CS32_SHIFT) & 1; @@ -8400,11 +8393,9 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8422,7 +8413,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags =3D flags; - dc->jmp_opt =3D !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt =3D !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8434,7 +8425,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt =3D !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT= ); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8454,9 +8445,24 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUX86State *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.tb =3D tb; dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_first =3D tb->pc; dc->base.pc_next =3D dc->base.pc_first; - num_insns =3D 0; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -8464,7 +8470,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); =20 + num_insns =3D 0; gen_tb_start(tb); for(;;) { tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); @@ -8497,7 +8505,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112426816759.5464881908416; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LXaru3e9YhVYrUhEwcfT1+GMd8vo3U+7AuznLQjaVvg=; b=ZahgSyPsuphzIAaBsgAL0pjSoIuJ+JwwwKHa+R+Sdv50sIP9YkMTs0NGZ3tb01ttYv GanH9P8BRLlj6yokwNH0KtRMELIQKJk2mRixfEdAQAcpOw9h46Zka0xm/3ly6hLMsi1a w7tUBZ74ifYMqxwwnZWNyPiTozWnOsG/lb3stmIcGf9ifUhoo3APd0y+eJUNfMgZOAe0 OSerBVnFskeRqSAk2EhqjcP6tO9rGpH5/6fXm5E3vv4EESusHJqC2p4jdsajSMnI/Ag/ ObYW7otgoJ+l3nBmcftyBkscUtAN8i3hjwgMIqkst1YMGaH4UtxF43OP2q0zchr4bhvv 89Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LXaru3e9YhVYrUhEwcfT1+GMd8vo3U+7AuznLQjaVvg=; b=FHRFTCPaREVr5UNSEARLccw9aPCvkaRptD2/vWHlGEMgYsel+c7CqALHSoPJkPbAmp lpXc8+j+7iUNXKSBJg76RuXGGb0WFOtHaoDOp2XTMrp6d62UoiQHY0nPn2OpqRupPY+F G0SbcpYTffLn3WhYmH5pMOKmA3JhH6PPh84+XP2Monpm3ASEFmh71F83YlG2Vv/jICmK a8U14CDYzbriDMZeS+lP3WxRsPnaChysL1bytKdBN827ilAvmc65w4OiAgbmV5u+pl+v +g75SGWWm8fdbyvUMJozp6d+zq3zFwqdB5qC5sMTVeT8S46gnZn2Hppj4lIRsCtCz7Gq nChQ== X-Gm-Message-State: AIVw112svLA6+IZ6SSXl4IGUhxyG1sy5/gbkkj3838z1eCbejU0lmVKS OcOrO/kg8ErF1MuVs/g= X-Received: by 10.98.14.205 with SMTP id 74mr9669430pfo.178.1500111792777; Sat, 15 Jul 2017 02:43:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:20 -1000 Message-Id: <20170715094243.28371-12-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v14 11/34] target/i386: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 651abca..6e1243a 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8448,6 +8448,13 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8475,7 +8482,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) num_insns =3D 0; gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_tr_insn_start(&dc->base, cs); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112263358341.79248389766974; Sat, 15 Jul 2017 02:51:03 -0700 (PDT) Received: from localhost ([::1]:41334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJj4-0002ZG-1x for importer@patchew.org; Sat, 15 Jul 2017 05:51:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbY-0003ln-SQ for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbX-0003Ir-Vh for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:16 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35619) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbX-0003Ia-PK for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:15 -0400 Received: by mail-pf0-x242.google.com with SMTP id q85so13698128pfq.2 for ; Sat, 15 Jul 2017 02:43:15 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v14 12/34] target/i386: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 6e1243a..a009710 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8455,6 +8455,26 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8485,18 +8505,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) i386_tr_insn_start(&dc->base, cs); num_insns++; =20 - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } } + if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -8547,7 +8570,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); -done_generating: gen_tb_end(tb, num_insns); =20 #ifdef DEBUG_DISAS --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112502513119.08249114611465; Sat, 15 Jul 2017 02:55:02 -0700 (PDT) Received: from localhost ([::1]:41347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJmv-0006Mq-5z for importer@patchew.org; Sat, 15 Jul 2017 05:55:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbb-0003oF-Bg for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJba-0003Ji-Bi for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:19 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:34941) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJba-0003JB-3D for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:18 -0400 Received: by mail-pg0-x241.google.com with SMTP id d193so13340199pgc.2 for ; Sat, 15 Jul 2017 02:43:17 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RE69wV6VWPhzFFjrBIvRdF+WRIeayO7KbixQ4AEVnLE=; b=dE6RhBuLKkT/YtkXL/gbnA2kXdf82feYfUzMlCkCXf6fIUnewnEf1Ur1CJSjyva87/ vHYIeeumK1yRLra5cpb0FB7neMynbVK+r8GFbSBrahjOMAQLEF/P66JotmMkDXQjiBZD rddW3PMXbjFT67QpL+OxzRbj3Ak41QB3zNXI5jeo8t+IYB9bTAV+SNYh5vRqhrKqKGoP 7Zz4oYS6VvT/A6zfWJjgLzZJlIrk3g9LoGsvYoAPR4Vj2okkoH/DjuFvNMQRiu+2skDL zK1UN+/JbQj26FIU91TIzXaWbJFYZxIieVnEtw3Cw9h1VEOFpoXyb7RYulwhH+sSbamh S7bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RE69wV6VWPhzFFjrBIvRdF+WRIeayO7KbixQ4AEVnLE=; b=IO2s2X1gzw9UejxwWaGp621uIKJZStQLtVyXwlQYQnjrw4QqpRkdiaPgP5jJ/IBTtb iZkN3SfFtOBhPSffY96BxmZf1O1LRT85uFhIbtWu8U2sozqkdwP7vWdPxdvPjqmy9HZ8 MG82jo8QqRw3YSIgCgE2FYt+6kRWtZknOYssyrg0X0JYSRbaHKHrfucPyJpA7vUq8lQu eQx+2rHeUlNMiDw/0ct13holYolHoWKV6f0pKOggWXeENRYsJKirHUghj2dw270pDWv/ JCoxlxC87hLSs/EKZmhc2s+X34sIOTFisDXAOlu+BzmfQVgm80+sFd6rvYODrPLvr3jt 8CUA== X-Gm-Message-State: AIVw110M6VdANgj2VZ0kNtEDV3hpRGu3cpc4PHmHnltrTquaJj4RxEpV jAqSGUyU+gmHGvt1asE= X-Received: by 10.84.163.75 with SMTP id n11mr20322423plg.186.1500111796937; Sat, 15 Jul 2017 02:43:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:22 -1000 Message-Id: <20170715094243.28371-14-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v14 13/34] target/i386: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 66 +++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index a009710..d350699 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4416,15 +4416,16 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, =20 /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { + CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; prefixes =3D 0; @@ -8475,10 +8476,46 @@ static bool i386_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, } } =20 +static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_next =3D disas_insn(dc, cpu); + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + chance to happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + dc->base.pc_next =3D pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; @@ -8524,39 +8561,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); + i386_tr_translate_insn(&dc->base, cs); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112436360396.81334617939217; Sat, 15 Jul 2017 02:53:56 -0700 (PDT) Received: from localhost ([::1]:41345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJlr-0004hH-4r for importer@patchew.org; Sat, 15 Jul 2017 05:53:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbe-0003rd-LL for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbc-0003K7-1j for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:22 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36176) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbb-0003Jx-Rn for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:19 -0400 Received: by mail-pg0-x242.google.com with SMTP id y129so13365547pgy.3 for ; Sat, 15 Jul 2017 02:43:19 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mvhIU7DX/mMTo28o5nf9x91G/4ismitFOm/iYo00IMI=; b=Zd8paXne1JLkzMrkCHJNb/WaUTafF+csSduFrKQd+PBaQedK5IYuqRejjNw/jtLVb6 ClwD6IlZCZIlT3vBrCqbFopfQNMr79JacWKNPPE3dUKfcj+ra1aeuV86T+TvKZn12EgX hK71N/McLvf+k3hPqUNiVu1eLhMdASESrXdCt4GBiaxo9SAAqK82/qFAerF0xwRkTy+w EzVpMRVfPZH/q1NlZ7G3XQP1WoCkoyyivgf9wf8e7k7M/1ME5wVWZWCmox4fpuMdhaKY 7PVwXtiG5nkGI8IgFad0SFGsl+dLyOT4cUQJXuAOGFbPy4fnsmUAO5W8rzlePDQYKbp/ fuqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mvhIU7DX/mMTo28o5nf9x91G/4ismitFOm/iYo00IMI=; b=SrFZeXgD8JFjSIXIV+qzIMXhmYNZyV0LCF8gZenjR80yNMQYD9GL7jMeVVODUfw2EE ZqyArfQhhSPnBDrKmw6LQl4cSrcfrqIZabZjB42WlVLQe2SHhq5yQo/l5SdVdBMp6DqL JXDug7Pwtz1+7b50IM1tIDCowY/iHIIhr6LBxatEmu1wMg6E1908gnbz+S8datSNpqX5 1kzrV149SnsFIP+2AhBqaIou++7PQj11COH/F39nb5+QGRXmZPUtwAD0d266AN7bvViR 2tPd/sSdGWe6XExStpqEX7CXwVQiLdYCVPs+uevkAjxXx4U6KoFcIfxZtX/mv8wEIt/F q+hw== X-Gm-Message-State: AIVw112va3lew9S83yl67FBuE8tBuMsCmvtPBOzJYYi+/BpqIHlOpXk5 9iCF8kba0zkT+BZGNHU= X-Received: by 10.84.128.47 with SMTP id 44mr20142998pla.213.1500111798735; Sat, 15 Jul 2017 02:43:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:23 -1000 Message-Id: <20170715094243.28371-15-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 14/34] target/i386: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002219289.22386.17959138704858928730.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index d350699..8238533 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8487,8 +8487,6 @@ static void i386_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cpu) /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a chance to happen */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) @@ -8501,18 +8499,24 @@ static void i386_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D pc_next; } =20 +static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp =3D=3D DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8569,23 +8573,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* if single step mode, we generate only one instruction and generate an exception */ if (dc->base.singlestep_enabled) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || num_insns >=3D max_insns) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } if (singlestep) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } } + i386_tr_tb_stop(&dc->base, cs); if (tb->cflags & CF_LAST_IO) gen_io_end(); gen_tb_end(tb, num_insns); --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112667319633.4306932991843; Sat, 15 Jul 2017 02:57:47 -0700 (PDT) Received: from localhost ([::1]:41360 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJpZ-0000Ae-VJ for importer@patchew.org; Sat, 15 Jul 2017 05:57:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38188) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbe-0003rw-W7 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbe-0003Ky-5G for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:23 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33228) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbd-0003Kb-VZ for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:22 -0400 Received: by mail-pf0-x241.google.com with SMTP id e199so13713442pfh.0 for ; Sat, 15 Jul 2017 02:43:21 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QeFObtym/yKHlVDYLK+1IEUjmhbgAkZ4JeDEvZSEIiU=; b=pSD2kCmtOrpRG+zcJMTBKsL2vYgifM2mF9mO4ZMx2SJobKhXRf2jAzk4n9oDZzSuu0 PH7dcAJwTyFUlMmjaQ0TbG70YK6ZiK+tc1k7agx8GN2pab0g6+yVgbByJvmZxPcFMDLe QRuYVyT7sHZN7z4oY2rRtMGkXAqU9ZzORr2CmE66GNXlC89qU1DxRhp47Xsg4qKFMcTg EfLZmFJ1WlMnUWcIrkX6YZUOf+whB7rnnbY7UWmx1OE9fLy9WIYTv12XUk+1ZlwYLf7d K+JB4miMiiCRaA7O+DEQSG2RpkVjhSI6evGHpSJ7iJVrYyJbeT7ZS25t3LtHps+9AZVz zu6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QeFObtym/yKHlVDYLK+1IEUjmhbgAkZ4JeDEvZSEIiU=; b=QaKJmgEJoWyegfiWlw1wMzVFYbpHXOyEUCmVP8y0UAJPV8czzaf4FfDSRLQhLlEyKh 56+mLf+8fUaxEJAFpnwG9yL8E74hiPpyFSMpHe88QvPyk/aew9yhbC5T/ckgWXiz1cV9 1BKy4dHNagDlVrjxSrfILqmcHaZ+JrnICzxuL+6yjPh0jS7EUSnIbYG4w6ngskrqhjlj fGppJjCiKTlvRKUg+JQE4Ec6Yr+llhSLGf26JJf7s94ziMefz+v4sNvMw681sujMqgDt Cx1ds6vWgMr6iXRfxTM8qvbq4u6YZq1y/VBARSrc3UK7S1BFSGRak9uquUQ0JP1qFIFG Tg4w== X-Gm-Message-State: AIVw111ysvRrHjB/wIuZEg5RXajT+OPDmzbWHiMWqHPlK0UmMmta6eQ2 /SwWzC3eLvb5I0JQFyY= X-Received: by 10.84.225.5 with SMTP id t5mr21161014plj.108.1500111800774; Sat, 15 Jul 2017 02:43:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:24 -1000 Message-Id: <20170715094243.28371-16-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v14 15/34] target/i386: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 8238533..8e7212c 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8517,6 +8517,21 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) } } =20 +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + int disas_flags =3D !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) { + disas_flags =3D 2; + } +#endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8592,28 +8607,19 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_end(); gen_tb_end(tb, num_insns); =20 + tb->size =3D dc->base.pc_next - dc->base.pc_first; + tb->icount =3D num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags =3D 2; - else -#endif - disas_flags =3D !dc->code32; - log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, - disas_flags); + i386_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112605723758.2900825933456; Sat, 15 Jul 2017 02:56:45 -0700 (PDT) Received: from localhost ([::1]:41359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJoa-0007pl-8O for importer@patchew.org; Sat, 15 Jul 2017 05:56:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbh-0003td-3G for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbg-0003M8-3U for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:25 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:35633) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbf-0003Lq-Rq for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:24 -0400 Received: by mail-pf0-x241.google.com with SMTP id q85so13698480pfq.2 for ; Sat, 15 Jul 2017 02:43:23 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SIThr3pLDPuA/EmM8Jpki8+2jpRMljAmrD1Irz77WgQ=; b=YsRSKuNJKtjet0t3swREULYnhS4IDn70bpcSCrnIYnIRH6x0cN5PrFtrgDyw4VHMWf 8m/hudpvQ7r7SR2KQI8VU3JzAw+hwJ5X+NtYQzwNfkVrUQbjgz87BzCHVNGldWTpbWEF Py6WbnO/muCz1/UdBbfBglSPXbQtlfltXeGsimV7Sbvi3ZxFS1Dw5sHQ1qr0C1NmhV72 X1jUlpvjeTCuZHDm/04SZoUsICZvaxMJugPXBzBKakp8Pt44bPD/kyv4nGKSZZriBz2D cAMlTsyC0hsY5QIDH6bbU0GjWsoqQJlKBv/xH/NzBnTdRZOL3UXgjdz1Tq1Lnevokhgk XybQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SIThr3pLDPuA/EmM8Jpki8+2jpRMljAmrD1Irz77WgQ=; b=FEAglVQH6+KExjK42SbbzyZfTQDdKTDknjoBtbd4rfaBk4nhmRJ66Wh2C+AiqL3Wf3 nEX9J9UDZC1fLfQDgHH0CoTEp9WvGgtMwUG2y8kEKXqlJs9+wIYMf5BPuJlQPWwQZftq wMwkO6NOSN07UMuvlzB/kpCZlYBqzJNTYUHQDlbSznwqe/d5fW0fk8XZqarWV/5M1chX pLfc0nl2KxNlm8VM9E6hZwS+FTlp6v04BYghm3zNkCKnuIP5yJ+xpLEzrTKP6ZuN6A3O rjCaKpwdEj1rUUSB9pG8XU9UmLhJ0PTEKXfarsdjZ0HraG2wcdXc7O4ZCgBSmut7XIBW HYcw== X-Gm-Message-State: AIVw1123wbg/TSQ11tjiQQ9JvNTQ8l+wHH60AktfV2YOEo0KRDXIj0Uv Lr+/fOJLnUI9Rg5YTQc= X-Received: by 10.101.86.68 with SMTP id m4mr19688139pgs.46.1500111802687; Sat, 15 Jul 2017 02:43:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:25 -1000 Message-Id: <20170715094243.28371-17-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v14 16/34] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 106 +++++++++-----------------------------------= ---- 1 file changed, 19 insertions(+), 87 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 8e7212c..2bd667e 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8449,6 +8449,10 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8468,7 +8472,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cpu, /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. = */ dc->base.pc_next +=3D 1; return true; } else { @@ -8532,94 +8536,22 @@ static void i386_tr_disas_log(const DisasContextBas= e *dcbase, log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) -{ - DisasContext dc1, *dc =3D &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.tb =3D tb; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); - - num_insns =3D 0; - gen_tb_start(tb); - for(;;) { - i386_tr_insn_start(&dc->base, cs); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - } - - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - i386_tr_translate_insn(&dc->base, cs); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >=3D max_insns) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - } - i386_tr_tb_stop(&dc->base, cs); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); - gen_tb_end(tb, num_insns); +static const TranslatorOps i386_tr_ops =3D { + .init_disas_context =3D i386_tr_init_disas_context, + .tb_start =3D i386_tr_tb_start, + .insn_start =3D i386_tr_insn_start, + .breakpoint_check =3D i386_tr_breakpoint_check, + .translate_insn =3D i386_tr_translate_insn, + .tb_stop =3D i386_tr_tb_stop, + .disas_log =3D i386_tr_disas_log, +}; =20 - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112942736788.6732699086666; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nQe5JwXzH8c291UENwbaRM4FY3j2U2o6hP2CgFZI8F0=; b=llTNZX3mtg5t+aJF1nXIFMXipQDkVq4q7yiKM9Z+T9BDN2nUpZ2psza1IRPg7CP2c1 SXsI1rXwppOMDqphOagHXt55P0xtPUD9XUR8aZgkDB1MEc7QyLj93XWF2DJX9A1rOtBJ S6TGoJKSU8vbspirszl79qh80M/uY93ygfCufpuYQYFspaZsALo/TYWjbbOJopzMvZP/ LJqFyEoJyuxygnqbPgueG0ryQPwbry8tsIOuiz8eg9OYJpKtnz3XOritvuQ5tdk+dPsn rWP+jKtSVakq/sArerjs9HZsX8BWGJm89MC6UOpy6dGdSphYi5eiUxetH0FUPU3pcR0m QV6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nQe5JwXzH8c291UENwbaRM4FY3j2U2o6hP2CgFZI8F0=; b=nrTqvCv/v2AA7V+MFReng3w4PY5cq6ayqbVqFWoyS7G1R9cLIuDpUw254V5aOOUcbo k2jk53oEJ/oIK1CKdBs/snkwYsHhK1uSAWaq4yxqj/XF5TrVUskEE5NZDEYvH/oOagHs DGjx4w6oIr979iUNcEvKXN2wWCXP1kCvTXnfq4nuVfEO8a0fYfSq3kK3oUcuZYpwV9BK 4rO1H0hQqypoy25J94TGjKNpORPIHzlq4CUUZCUdpBzuUqnxVbCRm1xemuhzzLrTZmc9 G5uS9Qi+nG3xQahNw+eM+V/Nix01MMUTpqbdaa/7fJ7OBvwaU4dKXtmxl0Mrp/1OZRjv VIRw== X-Gm-Message-State: AIVw112gpLbrto4NGxJkZAC5vNsQ3lYFqPw6tz51oHkRH4lvestU7rpl u9HkQNRjThO6Wsw0DyE= X-Received: by 10.99.114.19 with SMTP id n19mr19022385pgc.81.1500111805328; Sat, 15 Jul 2017 02:43:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:26 -1000 Message-Id: <20170715094243.28371-18-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v14 17/34] target/arm: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 11 +++-- target/arm/translate-a64.c | 117 ++++++++++++++++++++++-------------------= --- target/arm/translate.c | 118 ++++++++++++++++++++++-------------------= ---- 3 files changed, 122 insertions(+), 124 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index cca3c37..4cbf7cd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -6,9 +6,10 @@ =20 /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. = */ @@ -16,8 +17,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -147,7 +146,8 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -156,7 +156,8 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) +static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, + TranslationBlock *tb) { } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 657684b..57dbf8c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n= , uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_= IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags = & CF_LAST_IO)) { return false; } =20 #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)= ) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n= , uint64_t dest) { TranslationBlock *tb; =20 - tb =3D s->tb; + tb =3D s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } return; case 4: /* SEV */ @@ -1393,7 +1393,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * a self-modified code correctly and also to take * any pending interrupts immediately. */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; return; default: unallocated_encoding(s); @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ gen_a64_set_pc_im(s->pc); - s->is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } } =20 @@ -1788,7 +1788,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } gen_helper_exception_return(cpu_env); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; return; case 5: /* DRPS */ if (rn !=3D 0x1f) { @@ -1802,7 +1802,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* C3.2 Branches, exception generating and system instructions */ @@ -11190,23 +11190,23 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) { CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); target_ulong next_page_start; - int num_insns; int max_insns; =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 1; @@ -11217,17 +11217,17 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 =3D ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 =3D ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); + dc->tbi0 =3D ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 =3D ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D cpu->cp_regs; @@ -11248,16 +11248,15 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 init_tmp_a64_array(dc); =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; + max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11270,9 +11269,9 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) tcg_clear_temp_count(); =20 do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11282,15 +11281,15 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_a64_set_pc_im(dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order + included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting - tb->size below does the right thing. */ + dc->base.tb->size below does the right thing. = */ dc->pc +=3D 4; goto done_generating; } @@ -11299,7 +11298,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { gen_io_start(); } =20 @@ -11314,10 +11313,10 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11333,14 +11332,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && dc->pc < next_page_start && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 @@ -11350,7 +11349,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { default: gen_a64_set_pc_im(dc->pc); /* fall through */ @@ -11365,7 +11364,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) break; } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -11405,20 +11404,20 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 83e5491..02ada60 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i3= 2 var) * We choose to ignore [1:0] in ARM mode for all architecture vers= ions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } =20 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -928,7 +928,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) { TCGv_i32 tmp; =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; if (s->thumb !=3D (addr & 1)) { tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -941,7 +941,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -955,11 +955,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 v= ar) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp =3D DISAS_BX_EXCRET; + s->base.is_jmp =3D DISAS_BX_EXCRET; } } =20 @@ -1159,7 +1159,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm =3D imm16; gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_HVC; + s->base.is_jmp =3D DISAS_HVC; } =20 static inline void gen_smc(DisasContext *s) @@ -1174,7 +1174,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_SMC; + s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) @@ -1182,7 +1182,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1191,14 +1191,14 @@ static void gen_exception_insn(DisasContext *s, int= offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 static inline void gen_hlt(DisasContext *s, int imm) @@ -4143,7 +4143,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK)= || + return (s->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_= MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); #else return true; @@ -4163,7 +4163,7 @@ static void gen_goto_tb(DisasContext *s, int n, targe= t_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); @@ -4179,7 +4179,7 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) gen_bx_im(s, dest); } else { gen_goto_tb(s, 0, dest); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } } =20 @@ -4430,7 +4430,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4452,7 +4452,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 /* Store value to PC as for an exception return (ie don't @@ -4475,7 +4475,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) */ gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* Generate an old-style exception return. Marks pc as dead. */ @@ -4498,17 +4498,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } break; case 4: /* sev */ @@ -7647,13 +7647,13 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return 0; default: break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { gen_io_start(); } =20 @@ -7744,7 +7744,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -8058,7 +8058,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8146,7 +8146,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* setend */ if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { @@ -9519,7 +9519,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) tmp =3D load_cpu_field(spsr); gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } } break; @@ -9557,7 +9557,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 24); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; default: illegal_op: @@ -11619,7 +11619,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) ARCH(6); if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } break; case 3: @@ -11713,7 +11713,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 8); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11792,9 +11792,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; bool end_of_page; =20 @@ -11804,17 +11802,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cs, tb); + gen_intermediate_code_a64(&dc->base, cs, tb); return; } =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 0; @@ -11871,8 +11870,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11924,11 +11922,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11939,10 +11937,10 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be e= xecuted */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we @@ -11958,7 +11956,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { gen_io_start(); } =20 @@ -11968,7 +11966,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } #endif @@ -11984,10 +11982,10 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } =20 @@ -12007,7 +12005,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) disas_arm_insn(dc, insn); } =20 - if (dc->condjmp && !dc->is_jmp) { + if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -12034,11 +12032,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) end_of_page =3D (dc->pc >=3D next_page_start) || ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); =20 - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !is_singlestepping(dc) && !singlestep && !end_of_page && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { @@ -12053,7 +12051,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp =3D=3D DISAS_BX_EXCRET) { + if (dc->base.is_jmp =3D=3D DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12062,7 +12060,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12095,7 +12093,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this co= de. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -12151,22 +12149,22 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112771345930.6695795874991; Sat, 15 Jul 2017 02:59:31 -0700 (PDT) Received: from localhost ([::1]:41367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJrG-0001Zh-3j for importer@patchew.org; Sat, 15 Jul 2017 05:59:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbn-0003yq-SL for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbk-0003Ns-PV for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:31 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34625) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbk-0003Nk-HM for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:28 -0400 Received: by mail-pf0-x244.google.com with SMTP id c24so13735809pfe.1 for ; Sat, 15 Jul 2017 02:43:28 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NO5yxr155ZUy9joPICwvS40DLVXdYJK14SGM6x/yM64=; b=caftdEx0LU0WEf2OK/2IploOD3umq8x2ljGyQ8w+nUTi3XcS+SCpT/WARF4QvUyNVa 9Q+5oRJ09BgLoI1k8f1x778sCTw/C5h4peUfLiDlvfxUi4qCg+a3pdrNry+jfIR54ghQ /CXbPjSrgI7bQRauCz0CldweepxfOpSEVhPQHQ70DtVhhm3JxjGDEKMpetc1clU/AvFy ovaLND3zgfp/5xsoaj1YdeoihgASmfPxOK1BhCN50TsMUSTnzQ0LJYMa3dNhPThiFwbU Ej8Q9BNzX6sXj8VZoFRd+f5Qg0R6UywoQu9BHJ/pueSRwXsaXbPFIG041jVZmlmmtzt5 COyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NO5yxr155ZUy9joPICwvS40DLVXdYJK14SGM6x/yM64=; b=g6+GC/SEsaEbX04cdm5iM8mgD8Xbe6kA4mIwflJqnBSdLuBJOjCqyKSm5ntkdrvf/4 yjJe1yd2AJIFRYBa0QnBAKvV4xa35kEtP4z3xwvKZZHxSr9puBvepmlTOKfjwHu1vQkj Nj0GE/DxDRlQU3hVznzDSZWMX9OnS3oSKJOKvqQoZCvF0RgKFi1cbn2laVvV55XTVnHS JdSY2nzCSIiiyrjl9W/mbV6s3rcaro46pZobM0T5JuQdBMaNZsp7a563JjR5U/TRF3aG Wm4Tr75NN0X1rIKz5jRA2VNGZlFm4I73uPaZ4UQtRin1PpfYC7BBW5nMIcalOd8sqmnJ 628g== X-Gm-Message-State: AIVw111eRd9CMTzfoVucJlzUo76egKs6Lp/DHYaWug8WgHWQ8wgZy8GB AUdCJLyk+LSTRDB7bTM= X-Received: by 10.98.102.129 with SMTP id s1mr2344859pfj.239.1500111807368; Sat, 15 Jul 2017 02:43:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:27 -1000 Message-Id: <20170715094243.28371-19-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 18/34] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 88 ++++++++++++++++++++++++++++------------------= ---- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 02ada60..de9c456 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11786,32 +11786,12 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) return false; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11822,23 +11802,23 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; + dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -11857,11 +11837,12 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11870,6 +11851,36 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); + + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11878,6 +11889,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112591970303.16018764833314; Sat, 15 Jul 2017 02:56:31 -0700 (PDT) Received: from localhost ([::1]:41358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJoL-0007gP-QQ for importer@patchew.org; Sat, 15 Jul 2017 05:56:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbn-0003yt-SZ for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbm-0003Od-Ga for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:31 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36468) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbm-0003O7-A5 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:30 -0400 Received: by mail-pf0-x244.google.com with SMTP id z6so13727100pfk.3 for ; Sat, 15 Jul 2017 02:43:30 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4SOJSvvJusu4yG7zEAxkAE0LIdgTkp1JMVmc1ECklg=; b=EKn+wOfRmKthsS+wxbDT5xl2CZtHyldNbsRXm4tez04E1vpdugMkjxFnZJJUSqbxVH jQu87t4SBT1ULnk/4BJUV0d1Urex6SRap5EFYRybnN1+bwG0U1cAmxjRpIWf06CCz8XL pJecFYGtE9geueLwxhI/ty8SDdIDVWiFvfbhx1obLj/y4Bg6qS/bj0tT3R/C5mrqqNGM wCfqrS4YUxQWMnxWVpKNVw/exnRl4wDyBmuE++f8A8BwbTQ9In/hnigFkDJodRHIxzMr qF6mMRzI7kgi9yntQxmUnvztwaV0VeSNva6GccSv9EEHdpkmk/bspx27w5uIWjL5y3UR 8eew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=c4SOJSvvJusu4yG7zEAxkAE0LIdgTkp1JMVmc1ECklg=; b=mF08KA/0qWYWhYG3kfAVNqfX3n3FiK5uf54FjwdMtBSqP59S20ZurXBB9rsbKlHVli /EX+jri+H8iJoNMDGvXleLqmdv/nytesfj18ddtlv3HcsVXWCd3DexCZ0l2d1h5C7SzO rXmiKQH31Zc4ATBVmYaSE9dBgw/ot5+QEwAJhh9lsBVz3wvHMsH4jCHlP4pAc2aw2g1U czgXxyvzbpSLUE4YEzDeEDzrjHR5P1U1kIEbhaIBwoVfXGReLePUEk220Qgpqnu2rFqY 2edmAwpq50ObPu1ei/tmNlf+QARrHgVXutajbhMJXYXfXOoGMt+S61yb39UyuopKpCwV 7z/Q== X-Gm-Message-State: AIVw113nVDdNwZ5hhGwZ+IQd0tHC6lIPkq8IoRVBOW3ndw+VwP3NWioH UPHRO5DxL38yx+P+skQ= X-Received: by 10.98.74.221 with SMTP id c90mr9608999pfj.218.1500111809170; Sat, 15 Jul 2017 02:43:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:28 -1000 Message-Id: <20170715094243.28371-20-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 19/34] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 57dbf8c..e9bea91 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + CPUARMState *env =3D cpu->env_ptr; + ARMCPU *arm_cpu =3D arm_env_get_cpu(env); =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; - dc->cp_regs =3D cpu->cp_regs; + dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 /* Single step state. The code-generation logic here is: @@ -11255,6 +11246,24 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, =20 init_tmp_a64_array(dc); =20 + return max_insns; +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11263,6 +11272,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500113093433519.1583768330623; Sat, 15 Jul 2017 03:04:53 -0700 (PDT) Received: from localhost ([::1]:41391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJwS-0007cu-3n for importer@patchew.org; Sat, 15 Jul 2017 06:04:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbp-000437-QI for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbo-0003Qi-DQ for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:33 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:35645) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbo-0003QG-5i for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:32 -0400 Received: by mail-pf0-x241.google.com with SMTP id q85so13698692pfq.2 for ; Sat, 15 Jul 2017 02:43:32 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VDR1caK9PH2mHP3KczBdrLfwciXkpit7/DT6v8fS6tA=; b=g5Rw6LvdjsDAAIN0Wg55DzR1rvP9VNNEjkLAOFqselHSj+T5+R0JpVDoB3AnToXO1g Qu6B2pkP1SMcsrOmBsI8fl9NR2pi7zH7IVjyRlNufbBpBO4HUf6wrcJDS3Z5KDyEjSwA /ZsPYuuY3SJ9aBTpJoyYROSA2+t9nm9lTQrfjQTaNeAfsRylVhHU3Fj5JNSBQNg2ZT8i cfqttP/FIVmIZt2O0jrL0o6s+sq6GyJvlBI+ZS9ylpoitME12bVWrLHjS836jb0MEjWf haNfJUe9ueLaIyJVt+VmcpS/pkRYKwT61mBYVj+vkL0yq6wLaEzwk6PaQ7siILZCCBw+ nxxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VDR1caK9PH2mHP3KczBdrLfwciXkpit7/DT6v8fS6tA=; b=eeaDUJdAAj6sO7avVy8DGzLjRwJYZoqhzLFnJgg8iMH5ozZ/mzGfkVEPDvDd82HiM2 gAcX28VP+BIoOo3g7WPrLKGgShmMuvUy1GU44zowCTYt4bSeCi3QOfY2dbjiNzf4CH0P qnZQ2HaN38y6sn4oPHSE98we2An8YeJJB5TEb/KMow+QoAKpXoMV2uZ8M6nh7YxM13Bl fX9iIMrqokTZ2VRGrzXH7JU/BOC9WHFOpf0edx5wii7NWuX960VCAOhwEDyEkwWP+VGd fAPeIy3a8M8Cyn9FY5wQST6R1qrP1IFgUgdN6XO0Z1V5lun4eRfPskxn4ScMH/5c91BN Y+pA== X-Gm-Message-State: AIVw113qCRZWt4PCOtN6nb1EH5LBFwncZBAO+89rDIUg9nerKDpL/xVM uhwrXoQ5Qfz3cn3eD00= X-Received: by 10.98.75.73 with SMTP id y70mr1528230pfa.167.1500111810973; Sat, 15 Jul 2017 02:43:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:29 -1000 Message-Id: <20170715094243.28371-21-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v14 20/34] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index de9c456..f5d69db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11855,6 +11855,49 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, return max_insns; } =20 +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condex= ec + * bits back to the CPUARMState for every instruction in an IT block. = So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wron= g. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11894,45 +11937,8 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_tb_start(tb); =20 tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); =20 - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condex= ec - * bits back to the CPUARMState for every instruction in an IT block. = So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wron= g. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112759137966.2019461594826; Sat, 15 Jul 2017 02:59:19 -0700 (PDT) Received: from localhost ([::1]:41366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJr3-0001OH-Rb for importer@patchew.org; Sat, 15 Jul 2017 05:59:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbr-00047l-Cd for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbq-0003Ra-F5 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:35 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbq-0003R7-AB for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:34 -0400 Received: by mail-pg0-x244.google.com with SMTP id d193so13340758pgc.2 for ; Sat, 15 Jul 2017 02:43:34 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cGpDsKayLq11Li1Eqw0zIIWdM1NNWRX+udVOX057hfE=; b=ten/VnMCnsF6Ga5Hlfo3Ew/1ejDCQuGHhBxGuBVP8eWz/z0Do4adjp5wbDQoFbi0x5 2zgtUBebtevCJDT8USdcA6awh3xyKWoGh47xyhi2hNQBi2vUNDCIxAqk4UcoxIPDqk6y 3/0AHa4efLe6vWS7XfelpRkG9vEOVcuHQgkc+xQxlI9vnBgDqq0wsRNdp8EIku0YYaPe maFMnxkNuovcFXOzZk6g22lZMkbdIZchuRT3kv/rMp/wWnu8XxuArOmfiphPJTRloKfY m2o8FUVAmXW3U5GD1quouDFqYp5uTSQBAWrY628/Kv36lV/l6z/ejl4YWDqAPUVLd5ue tlQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cGpDsKayLq11Li1Eqw0zIIWdM1NNWRX+udVOX057hfE=; b=EFOsa6BkZq4LslrHMYp2PJ5XoVS+H9O87AnteMhpkwkn7hdAJydsQqQmljTaK5IYaa 92rcYtSaKi7Kb3UggxSKSNbsRWMHqzRZFDfMdHCAQgHj1tI06CR/n9zSFWgNkVJIlKLW 6b1MhuLXv5Fc/N2T/+6GHkATIqWaY44Oj+LYnTWiVbblDgTQrCvPoVbVCn3bOoIH/Zc6 rU9mEh1M6J4R91k794aV2KoWp26G92BEQezxcjiN4r2Yrc+Yzs5X+hhJRczjuIzRKy0c GkGKksHiBieQkRP9auuAOi4Z1v86rjiNFtr8H1fuqwdKi2iaaX15cnDu6nFpuSWKNfB8 yPqw== X-Gm-Message-State: AIVw111UYIwf7nqbDNFyFGKDZQeM/PJHYG2/uQvVjcQXcNIMhlpvfWST Y1krRTNiYZjHm/0nWWk= X-Received: by 10.99.124.72 with SMTP id l8mr19489679pgn.90.1500111813093; Sat, 15 Jul 2017 02:43:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:30 -1000 Message-Id: <20170715094243.28371-22-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v14 21/34] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5d69db..5e09682 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11898,6 +11898,16 @@ static void arm_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) } } =20 +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11941,10 +11951,7 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), - 0); + arm_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150011283322011.720768207823198; Sat, 15 Jul 2017 03:00:33 -0700 (PDT) Received: from localhost ([::1]:41369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJsF-0002V1-Jo for importer@patchew.org; Sat, 15 Jul 2017 06:00:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38292) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbt-00049K-IU for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbs-0003Ss-CT for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:37 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36204) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbs-0003SX-5A for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:36 -0400 Received: by mail-pg0-x243.google.com with SMTP id y129so13366092pgy.3 for ; Sat, 15 Jul 2017 02:43:36 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JzDraqfJlm6zr+oB9vjFRKwS1eMbCDVypDaKvzqeD8g=; b=W+hz/1NlILp7IDUB5erDUo7oSO7a3YB0SqBH5UVrgRD//vzD7d3y9pMjs4qZKqY68o vEtmnSdexDYgYhb5SJisvRcCOzuHa0QduPDgn3nPXsfE6PlvkCnWjwBpZSftL5CDmLNx g4znYvsu/MjHpKv+7Vs/hRlYqAcdWhgvPXeW3qcINg8IEirE4fziCgv7n/IKRYfLFAnU 0gWh4WoZeeHnBSKX+YdgsBc5c3bGo4CXUr0QoqD9T2S0JUA6LKWQD+hhezyYgKHa9Py+ shNKYD5Liz4CqRFDQFtkPm26LATAI0f7p6xbZlrITxnPade57PQiLkZySRNuC7nBJVcl I16A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JzDraqfJlm6zr+oB9vjFRKwS1eMbCDVypDaKvzqeD8g=; b=PPLCjliqMT9TjxQF/u8CxHBIEOq5/NSaANaQI8xBvWTxX1gMO8c7dx8QIA/QMbkFA8 9LjilBzgVeOTieWaUYsVlnvsXCnxroBdotPxJDzYFF7QIGyJKMEzZQBgAAaenltwQrRG slLEz1GDmIM5SJn+OHa5cmbN/VR4SYtXrErgkkP5B+W7RxeowGkZ9JZcyz3qLsEneAGR 2kqjMyKX4oYJyLEKmzB5dIt8wkBAVVZS+fbK1snO/727Mw/15mlc67HWA/giajGvqznh X+YltMo8RlHAcHPxJh8AKhE6kDHr2UEzbGRlbzDt7uXbn+0UVDF/NqiPaNV5s0te5xxZ s3sQ== X-Gm-Message-State: AIVw110B3kafI4hd4MfTCUmwKdvblz6CH6Exh3LXxPWE6ZxKR01qU/+G BlOePHQGtUgfl0ikB7k= X-Received: by 10.101.91.15 with SMTP id y15mr19579183pgq.88.1500111814896; Sat, 15 Jul 2017 02:43:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:31 -1000 Message-Id: <20170715094243.28371-23-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v14 22/34] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 +++++++-- target/arm/translate.c | 56 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 44 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e9bea91..dca5825 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11249,6 +11249,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11280,8 +11288,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e09682..15bd9e7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11908,6 +11908,33 @@ static void arm_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) 0); } =20 +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11956,29 +11983,15 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { @@ -12100,6 +12113,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12120,6 +12134,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_UPDATE: @@ -12173,7 +12188,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WhyxoCzEQSXdeoMa7zkoZRJPzYAuyILLZsb9qGEte4s=; b=gcwNvhtHIA5X0yvk83JwXdUDTRQMYwW+quQbEwwA2ILptTAJqIrj6ycsKMyeQnh8QJ 5LUz37Y4zMldKlNm8ir3u2jbn8xtBb4oK6nsd8YWw/tQYW4QgX4B9IfAWQlISdySqns9 ncUtb4J7wiX+3z5L0hN5fYhpUwBL0rPH9uYoOeQflfxeZbaeyV+nUUFkl+u+bM+nujwv igZZnQpUKKMrtx38caFramGKoRMACKQ0IvxOljoW7DEKGLfLzeteEDpjf/N1Kuq9nV77 fSbIA7fcu0gMC2I7UXA0s2uZKurHEVlIBYItCor3Hz08C9QLi2/3ww4wOU7W8AwmG8AQ U1rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=WhyxoCzEQSXdeoMa7zkoZRJPzYAuyILLZsb9qGEte4s=; b=QtwAKLZY2lkvUn7ds85lMiLM7O3VUJipPOIlkUCkgXmsP3i1aCuD4C89xeypfMbKm4 mrIvc5LEJ+oSoG7uXlCQKW5GE+YAhHQt3k16WFzkBVbo5s4xJuvL/XSl2PKb/KI1y9sc 0WJ/CGDQYlG4jvTz+CU18/v4kbJf6A6vUr8eFuMw5GDkfRbnTmslZVbRylMtktgW4l9N K6xAzOwa0ER0pzfNGOwbplVIvKMqHoJjt9U/ScGgDbN1E7NehDJw79xMlyyASR2Xxe4J vVljBx903rEKwrgptyCrnjvF+aAyZNa6TQrCP62JNzduAcatp/4S/J5C7f2F4retue/f 4Maw== X-Gm-Message-State: AIVw110ezh7NHoktsLk9ow49mFdZG5hpPktoAlhgjxQjJIgn93WmoXZr 8b8ePj4/hDkE8sFKX8I= X-Received: by 10.99.63.206 with SMTP id m197mr18956411pga.170.1500111816781; Sat, 15 Jul 2017 02:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:32 -1000 Message-Id: <20170715094243.28371-24-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v14 23/34] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++-------------= ---- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dca5825..1541bf0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11257,6 +11257,30 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11293,26 +11317,15 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. = */ - dc->pc +=3D 4; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { @@ -11383,6 +11396,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; default: @@ -11420,7 +11434,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500113378014985.761773174626; Sat, 15 Jul 2017 03:09:38 -0700 (PDT) Received: from localhost ([::1]:41418 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWK12-0003NU-EN for importer@patchew.org; Sat, 15 Jul 2017 06:09:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbx-0004OY-Jc for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbw-0003UE-6c for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:41 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34983) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbv-0003Tt-U2 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:40 -0400 Received: by mail-pg0-x242.google.com with SMTP id d193so13340960pgc.2 for ; Sat, 15 Jul 2017 02:43:39 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JCdxqsbG2Dhkm50TPJ1vcc+/SCPESqkYVZX6UVT+jf4=; b=E3utK3dALhi0kiTzTFXWLIcfu/DMyrojCM8CIpmZFh+lv8epkItlDXs6PBtT2ymv+Z D+QY/sZrocUCylVxtXjesvkU3IhneW+MmBnRSdEFF0Cdu0AhzFZINcBnrDN+1CQXSjz2 llt+8I+cmV3Fcis7fh98LKPev+4XJdMEUuhm7kuihEoHHtgLfQNpFV66eOnTzwZhrOoy iWKLd6eTgQW8rP+fazy3dvaeEQCVuf1m5sh1wdv4aQF6W+a0d0KWFhFPWP7EzO8XNINq FZn4R8cRVYW+CmN4G4tLbxtHC5Fuqu6YAExRl+RLMMUQhAaQg+GZc+3Ar1ThS0P2najA ZDFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JCdxqsbG2Dhkm50TPJ1vcc+/SCPESqkYVZX6UVT+jf4=; b=MvubdxvMTHRbXsVHiP2fc9sUOLcB7PtfD1z1O0YGBXqvEL39d9W2zvtCoPXPO6WUen s4t1+IbryciAED7Ofy7jBMdIarUFY/V1TNjGoOyz6pB49/7JMm+B6eLAfWghDy0KStEs lqDUyY+x/SA1hhpdq0t3TyNg69BKWnhi+bZ/eaQI8AkMra2nbaHvR+CWIi//G4pPZEkC xFa/SPZt2MwJuB9hTWBHo6eQUMSl3an0iAMwcN8I5OJVDuB7kZdwgwWGv2HqXf60icfS OfsLKHXnVdUdZ7wQIENo8yZylAxOhX5wJicCxow4b4UgSOikwkHs/h/JEUgr/gslMOzu FAxw== X-Gm-Message-State: AIVw112uuOAGK7EHSlcQoq8DOo22XdRok626S5JC0F0fo/iG6fEYv5U0 dpgbMKmM20aXOEaEslE= X-Received: by 10.98.34.15 with SMTP id i15mr9677133pfi.119.1500111818678; Sat, 15 Jul 2017 02:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:33 -1000 Message-Id: <20170715094243.28371-25-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 24/34] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.h | 1 + target/arm/translate.c | 165 +++++++++++++++++++++++++++------------------= ---- 2 files changed, 91 insertions(+), 75 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 4cbf7cd..65e0c74 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; =20 target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 15bd9e7..ae1ed5f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11842,6 +11842,8 @@ static int arm_tr_init_disas_context(DisasContextBa= se *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); @@ -11935,14 +11937,93 @@ static bool arm_tr_breakpoint_check(DisasContextB= ase *dcbase, CPUState *cpu, return true; } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } +#endif + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond =3D (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + } else { + unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp =3D 0; + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several time= s. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->pc >=3D dc->next_page_start) || + ((dc->pc >=3D dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new pag= e, + * or if it spans between this page and the next. This means t= hat + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit= insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; =20 /* generate intermediate code */ =20 @@ -11961,7 +12042,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11998,83 +12078,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) gen_io_start(); } =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } -#endif - - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp =3D 0; - } + arm_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page =3D (dc->pc >=3D next_page_start) || - ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112922322237.3262069516436; Sat, 15 Jul 2017 03:02:02 -0700 (PDT) Received: from localhost ([::1]:41383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJtg-0003za-Pg for importer@patchew.org; Sat, 15 Jul 2017 06:02:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38357) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbz-0004Uo-EF for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJby-0003WP-1F for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:43 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34643) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbx-0003Ui-Pc for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:41 -0400 Received: by mail-pf0-x242.google.com with SMTP id c24so13736182pfe.1 for ; Sat, 15 Jul 2017 02:43:41 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zyEtXDWfeoQZUHVKSmzuldu8S8sl26LD5I2ouLjZIbc=; b=h2re/hphCO6+G0/YNX/BC8XoVQG+svBa4/bI3Y8WcSZL7vji/q82D6ViuuVFdAlwLO 2u5W/EDtWRTpHtjyZLRm1NeOC8hkkNEuyKCWgkaLgNqFa9WzZwZCikM6O4CzwZtWQ/5j dUFzRBALqywoo/14Bfz31Nm3f88pLfDvZxB2UkXwrFKd2ALOFoJGlVXKmd6pIPgpCIvK j+HICkWKehemQ5p4E6Ff6VdITy7XGS4bDYRjjU6PqlcOSmFuaCxjlcvqYcj1ZpqCym9J LR49im1URpxaGAtbrFB8C2uqOaYE/qWNq2D5TO86fITs06EQrzrlNgAzwfBhvvbRozz3 itMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zyEtXDWfeoQZUHVKSmzuldu8S8sl26LD5I2ouLjZIbc=; b=NnAMVcUjeglsn0b/r2tx5w8H/2MiBQqJDFMJ7yN835OpuRERx25kOLfrvK/Np+SA7a tFIn4px+MBzZRdcMjSoEZmtD2IUO4nOpnd0pGXBwbWW823T+ehr1iQFjZae1zK8YwWiS IZqyrPhweWIQ9tu4Cjc2EWevhEPZRQlEaV2wkmNu8adz2NOH19k8AD3VLUczzw8jfM3z eXQkxQvSKFq3rhH1OfIhtqDoCPDBkVD6ngbbN/PNeOuD68uUMudHuQhU4nAgYTss5EJ1 qZKHxVMRNEog4g6rnYq5jIYggkCoGvPN6kBbJrO2HdRUpZMEWen65bBu2H+gcScZJnhH 6YDA== X-Gm-Message-State: AIVw113e6s0uvzUaBwBggfTI/X34aE8lW1/iebQzgGbIkoBoLH/MpQoM Riuj5KVVHodufmNWCIE= X-Received: by 10.98.95.67 with SMTP id t64mr9627121pfb.127.1500111820578; Sat, 15 Jul 2017 02:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:34 -1000 Message-Id: <20170715094243.28371-26-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v14 25/34] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++--------------= ---- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1541bf0..a92a3ec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11244,6 +11244,9 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); =20 return max_insns; @@ -11281,12 +11284,43 @@ static bool aarch64_tr_breakpoint_check(DisasCont= extBase *dcbase, CPUState *cpu, return true; } =20 +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->ss_active || dc->pc >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; =20 dc->base.tb =3D tb; @@ -11296,7 +11330,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11332,42 +11365,24 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || + singlestep || dc->base.num_insns >=3D max_insn= s)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); =20 if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112502589206.912681935573; Sat, 15 Jul 2017 02:55:02 -0700 (PDT) Received: from localhost ([::1]:41348 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJmv-0006NY-8r for importer@patchew.org; Sat, 15 Jul 2017 05:55:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJc1-0004Vs-4h for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbz-0003X4-Tn for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:45 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35660) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbz-0003Wk-LK for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:43 -0400 Received: by mail-pf0-x244.google.com with SMTP id q85so13699022pfq.2 for ; Sat, 15 Jul 2017 02:43:43 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iCItBJ/3DohuCditn/jNDn7RbsEIoWKxQtn9YgJB25s=; b=RWBENYraB+oc1V+xe3poWsmi4EBhfxTdGYvl83ZtpqCATBFfGAPhytmLVJIBQnXrCY 6d+Gmmtq5pBF/CQV7v+D7O1UaMusiaIA5D34XUFKthKplPRg0DMbipv1yoPuarxwvyti Dr3fg4pVo0YEIRoDm/lvZBIAP0lO/0MxjVU7tYodmS5wlSVbZS2jDvLoR46DjelxwUHw UJD1/sDJTgp47m1oTPTDQfBfF6ZiirLRxeEIYiI+GbXEEZgQI8xbb/fe515ZEgeolKQZ +b0699eoeRnf8Gokxj/vQXBd7/KH4y1sd5IBRphyKKjfgmts8yL8rce7HjW/99yVPat6 lsnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iCItBJ/3DohuCditn/jNDn7RbsEIoWKxQtn9YgJB25s=; b=gxX77DpdewTp2B65mJdNhqZvkcjwa89dFvT7DI7Mj0ht/P2GllKdxgwA75AqbpXeGB zuqfY2YyZ2t2o+gCO/O1hmKZ2eUPFtzsBjVbBXa0yts8MgX9oHXGjhUtzwqDSpFHWV+q s5LdSQO2ecJVN0wReTMGO6Kw9BMMC26hA7nMHzlbKimlAPxtB+vMxExV3BZPTriynEh2 U6pDYiOfNdgkLevCccOqQ2uu60CF9huEVXIzC1D/nlXlYYhrvKCAK2q9pLXvmjOJl0kB 9pj7GQTE9qLv2QAa51bpyR9oSaT4G+BsKILHR+IxNySyw0cKkhvGMP21NqgHq5EmsgOP 2mKQ== X-Gm-Message-State: AIVw1118ApFcR98FyXJvWIVVqWk+xn4In3iYHd3IBMoW2A0rAA1+uPm7 MLc1csms7xoorXaNfiE= X-Received: by 10.84.192.131 with SMTP id c3mr21200769pld.9.1500111822531; Sat, 15 Jul 2017 02:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:35 -1000 Message-Id: <20170715094243.28371-27-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 26/34] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.c | 162 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 85 insertions(+), 77 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ae1ed5f..a934641 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12019,85 +12019,13 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12135,6 +12063,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + break; case DISAS_NORETURN: break; } @@ -12202,6 +12131,85 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tp6n2IvJiBB/RLDLWI/3uFakXoA34ZOuaCEGeuZ0BKY=; b=eeILPWxTLgbrPPDr7v95WjW4X39LQiX1YvAt6/ASlLF2z2AVPr0zfyhoMD1BQ4oPL/ iI1xYc6FCouKd4+LiH/qYxvKPzICcS4J4kh9rOOmSL8R4/E+MM0CwM5/fnEZOxEthGx9 NAfU8/sBoBhiBzNqa9OpbMzoo+Vb5Qfomi4OkA/oMi/eSJzeDpcpml/WWWR0QryglE7Q peAsMN2/AsMkyTa2L9iJkTnKNb0ZLGNsVYCyoFf6oisz3r+2mpvv4V7O4qXnnsM6aDrV +yWqD8vcFGNbz3N3j7SF1Uf7W3BOxdkUtwLCb926vuhO9gBanjVlk0LlXcEkVllwgXdQ ejQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Tp6n2IvJiBB/RLDLWI/3uFakXoA34ZOuaCEGeuZ0BKY=; b=CxIRX1qdbA5x+wjuOVMDFlnr5AEzksuk0wHGsZX6KNH8qg2FDoPuMLTX4XuqlifCsB ZLX24J7tm2Rd+0xnM/XQIDVsietyxaOWBSlGCIaUKWsF3977XkK7nl7Tck12KNJxj/Q+ Gx+pFjVG/UXDG1KU9/3fQzDnqfU+Yjx2KwINi+iulrWeN5Le7ES5bpdvZBU3Foq5byKA 2WrFx2Q4MQeHF+FIilrt3fPxYGwnIR/d//rd6UBbJ9xRjvxHvDTnXAEyAywl1u7Dg/k9 78y5bIO8aoCpdYOp2tTah5Bh6whprt2zeclYaL1aDfsAda9XPNOA2GTyQ9k5RAv5Kcej nRww== X-Gm-Message-State: AIVw110m6InNT6Nf15wKYIzTiy97uvnoO+v7qH6yHYK71Yw3fswwEChL k7QeITbvUjk0Q5wnh1g= X-Received: by 10.84.216.6 with SMTP id m6mr4024976pli.299.1500111824328; Sat, 15 Jul 2017 02:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:36 -1000 Message-Id: <20170715094243.28371-28-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v14 27/34] target/arm: [tcg, a64] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Message-Id: <150002558503.22386.1149037590886263349.stgit@frigg.lan> Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 127 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 67 insertions(+), 60 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a92a3ec..588f048 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11317,6 +11317,72 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 +static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { + /* Note that this means single stepping WFI doesn't halt the CPU. + * For conditional branch insns this is harmless unreachable code = as + * gen_goto_tb() has already handled emitting the debug exception + * (and thus a tb-jump is not possible when singlestepping). + */ + switch (dc->base.is_jmp) { + default: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; + } + } else { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(cpu_pc); + break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_NORETURN: + case DISAS_SWI: + break; + case DISAS_WFE: + gen_a64_set_pc_im(dc->pc); + gen_helper_wfe(cpu_env); + break; + case DISAS_YIELD: + gen_a64_set_pc_im(dc->pc); + gen_helper_yield(cpu_env); + break; + case DISAS_WFI: + /* This is a special case because we don't want to just halt t= he CPU + * if trying to debug across a WFI. + */ + gen_a64_set_pc_im(dc->pc); + gen_helper_wfi(cpu_env); + /* The helper doesn't necessarily throw an exception, but we + * must go back to the main loop to check for interrupts anywa= y. + */ + tcg_gen_exit_tb(0); + break; + } + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11388,66 +11454,7 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active)) { - /* Note that this means single stepping WFI doesn't halt the CPU. - * For conditional branch insns this is harmless unreachable code = as - * gen_goto_tb() has already handled emitting the debug exception - * (and thus a tb-jump is not possible when singlestepping). - */ - switch (dc->base.is_jmp) { - default: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); - } - break; - case DISAS_NORETURN: - break; - } - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->pc); - break; - default: - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); - break; - case DISAS_EXIT: - tcg_gen_exit_tb(0); - break; - case DISAS_NORETURN: - case DISAS_SWI: - break; - case DISAS_WFE: - gen_a64_set_pc_im(dc->pc); - gen_helper_wfe(cpu_env); - break; - case DISAS_YIELD: - gen_a64_set_pc_im(dc->pc); - gen_helper_yield(cpu_env); - break; - case DISAS_WFI: - /* This is a special case because we don't want to just halt t= he CPU - * if trying to debug across a WFI. - */ - gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); - /* The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ - tcg_gen_exit_tb(0); - break; - } - } + aarch64_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500113210243284.6461555759844; Sat, 15 Jul 2017 03:06:50 -0700 (PDT) Received: from localhost ([::1]:41402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJyJ-0000il-KH for importer@patchew.org; Sat, 15 Jul 2017 06:06:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJc6-0004fO-8a for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJc3-0003Z4-B6 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:50 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34397) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJc3-0003Yj-5G for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:47 -0400 Received: by mail-pg0-x242.google.com with SMTP id j186so13347343pge.1 for ; Sat, 15 Jul 2017 02:43:47 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HzWmrsY+uWXjB8oud6OcrY0mV1OTpXC1WCJSv5GGo20=; b=Fj6oxXgv/GA56FNYuul/7OF1pjGVVUaQ48QKJVjBM5FM2JWS/d4SlG0HkLPjo46gJu j8kC0lXiWWQmbVUlG7K2h1Y9UVcv7uSdeH/dGAAAypDV+s9Ib/LEmUIbx9+4yWn1kdD2 P44NZxE2PGgeeIihSAkhias5Q1ld9LURlU6otGzPLztQqu9t19/3X68SXraXVNFbounW Use5IMMAHe+eXJGi2VF/hI3KFEUXoU0jwXbWUWSFL1kXxMLly8Z23h9Hj6lp93/3Q1ye dMrsSzZhaBZmEFNmy/y4Vbb3WEmMEel42kuXIV0irOwkrbIuQ/hg1Lf7VqI5P+3K3Pxm C+Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HzWmrsY+uWXjB8oud6OcrY0mV1OTpXC1WCJSv5GGo20=; b=Jqv/VjFe9WROXtrEJsWR3pFD8FxwBeBz8F4tZSbqC+MoDhL+lpggQQxwdrmkL1cR43 oDHiJ/wo6U3QSWcT7F64PklMOW1t2sx9G5XXdQLneTOH3gh4I2M8ixZbM2dwNBsRQ+sa OSy5RhXw8Z3DysksJ+Bs/1TGA2VxJWp7y/GHfaawTWsPMF1+W1NDTYIJ+XBdxMG15G8E 1czdNB0jD5+t61v2yngI7O6T3CkZmC4a5siLwMOlF6xdgRxxO+GgG+Sn6UFKB5fcs+yZ A+HkYuVIgq/ynV9+S5k5I2f2EVCju7mgZNW1SzWY8PbckSmZej6Rgv9lBDHtPx5Jk0zt nP3w== X-Gm-Message-State: AIVw110U5NRkWXzLzbzm1NQDe9JyxUeyv+a7Zo8iZsn2hJyAShYPif3D wSS/ECwh3vdWty4C0yY= X-Received: by 10.84.232.13 with SMTP id h13mr19886953plk.278.1500111826064; Sat, 15 Jul 2017 02:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:37 -1000 Message-Id: <20170715094243.28371-29-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 28/34] target/arm: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a934641..4ea5f70 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12133,6 +12133,15 @@ static void arm_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cpu) } } =20 +static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + dc->thumb | (dc->sctlr_b << 1)); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -12213,20 +12222,19 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) =20 gen_tb_end(tb, dc->base.num_insns); =20 + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - dc->thumb | (dc->sctlr_b << 1)); + arm_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112998942418.46866550529285; Sat, 15 Jul 2017 03:03:18 -0700 (PDT) Received: from localhost ([::1]:41386 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJut-00059S-Ii for importer@patchew.org; Sat, 15 Jul 2017 06:03:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJc6-0004fh-I0 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJc5-0003Zs-HF for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:50 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:36492) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJc5-0003Zj-BW for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:49 -0400 Received: by mail-pf0-x243.google.com with SMTP id z6so13727710pfk.3 for ; Sat, 15 Jul 2017 02:43:49 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zic6SKxQsA1NZiqHGgiIhFNq972E/R5FNPWJ65fVxMw=; b=gkLK+nWhaiAdcIY74Z5dxrkdpCeoW9bhcNf1mUlB9uwMA1g3DaFo7NKXUFUjof27OX p3QTEvA2ml+cKPr8exb7otTiz+ziS5GuFFBlr5VQHW3bCfC5jP/pyL2Paf0yXZgLzAdX cR7JfSlXgijJyesmwPEnimuZ6GX35hq9e7LsDBzXtuVvvzt1DlGDj5m8L0HF4mXHIlR1 FSX8gR9i6K3y2TGybm22Fnc83FGCppcqZEC4WBDkp2hTpPDR/O0kXv396GzECk3l3lX2 Ykg46/0JjNB2IUh5Yl2aQ7/3/4GB903W2QO/keRePaHmWFL6i08ydLQpSFCYXnSi1LIr 0B1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Zic6SKxQsA1NZiqHGgiIhFNq972E/R5FNPWJ65fVxMw=; b=ekKFajZ9aJUe6kcY6c8i7MMIIpcLTxZahwjNXxM/GPX17fZ+CXXgcWii/OSPSsLgS/ tm60Hwx9H6F7ltJ4Dg4r2yzvHS6wgwJLOh1u7sANzP/v7UZcJgkx1N6mP8vPXGwpthIE uEX3VQizGLDxCq39sS1egn0KKC8ZbebDEsbOvxgkzWxDi/UB84soOuPWzaKcbOx/omgw GZKe2sp0qnl0q1Gwnu1B0/6NslOCHc6qo+8yFDF++9GB2kFLw4QDVUyhJ8wB/KX4tWI5 5/vv+oQXPbK7EdzkeKAE5piLzmoomYKjd/SxeTpdGYM7+W4An0YcJZhGKG99WjG6RJKg F0zg== X-Gm-Message-State: AIVw1129j2WKHE/VmTJy1V4fzVbl3ttA7WIB0knSP8cRDWFurPInOnrx a//JeSQ3uPPCNYfpa7U= X-Received: by 10.99.2.213 with SMTP id 204mr19137774pgc.180.1500111828228; Sat, 15 Jul 2017 02:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:38 -1000 Message-Id: <20170715094243.28371-30-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v14 29/34] target/arm: [tcg, a64] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Message-Id: <150002606914.22386.15524101311003685068.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 588f048..6259ed0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11383,6 +11383,16 @@ static void aarch64_tr_tb_stop(DisasContextBase *d= cbase, CPUState *cpu) } } =20 +static void aarch64_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11458,18 +11468,17 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, =20 gen_tb_end(tb, dc->base.num_insns); =20 + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); + aarch64_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; } --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112668980632.4517673475435; Sat, 15 Jul 2017 02:57:48 -0700 (PDT) Received: from localhost ([::1]:41361 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJpb-0000Bz-ML for importer@patchew.org; Sat, 15 Jul 2017 05:57:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJc9-0004iY-EW for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJc7-0003as-Ty for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:53 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34662) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJc7-0003ae-LH for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:51 -0400 Received: by mail-pf0-x244.google.com with SMTP id c24so13736604pfe.1 for ; Sat, 15 Jul 2017 02:43:51 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v14 30/34] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan> Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.h | 8 +--- target/arm/translate-a64.c | 107 ++++++++---------------------------------= -- target/arm/translate.c | 110 ++++++++++-------------------------------= ---- 3 files changed, 42 insertions(+), 183 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 65e0c74..73a42ae 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -147,21 +147,15 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6259ed0..1aa4c14 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11252,6 +11252,11 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ + tcg_clear_temp_count(); +} + static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -11315,6 +11320,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -11381,6 +11387,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void aarch64_tr_disas_log(const DisasContextBase *dcbase, @@ -11393,92 +11402,12 @@ static void aarch64_tr_disas_log(const DisasConte= xtBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { - gen_io_start(); - } - - aarch64_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || - singlestep || dc->base.num_insns >=3D max_insn= s)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - aarch64_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif -} +const TranslatorOps aarch64_translator_ops =3D { + .init_disas_context =3D aarch64_tr_init_disas_context, + .tb_start =3D aarch64_tr_tb_start, + .insn_start =3D aarch64_tr_insn_start, + .breakpoint_check =3D aarch64_tr_breakpoint_check, + .translate_insn =3D aarch64_tr_translate_insn, + .tb_stop =3D aarch64_tr_tb_stop, + .disas_log =3D aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ea5f70..4b1230b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11897,7 +11897,9 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); + tcg_temp_free_i32(tmp); } + tcg_clear_temp_count(); } =20 static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -12017,6 +12019,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12131,6 +12134,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12142,99 +12148,29 @@ static void arm_tr_disas_log(const DisasContextBa= se *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } =20 +static const TranslatorOps arm_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D arm_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; + DisasContext dc; + const TranslatorOps *ops =3D &arm_translator_ops; =20 - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ +#ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - arm_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); + ops =3D &aarch64_translator_ops; } #endif + + translator_loop(ops, &dc.base, cpu, tb); } =20 static const char *cpu_mode_names[16] =3D { --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500113134125568.6760301199956; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=egeu+YlPzYvIryMSwbo5grgbi5RzuGxh+QQaTCRWf7c=; b=ADOh6VJmJVlPKiKTedHSuEhQbtGGqu4IMu44ldZYj7OKy0Dv5tSJfsOhAdk884v0cB 0m8OUo+6yOfhGPNBp+EGF81CILcdxmyYtuyxIrcc904hTsTC9GdOJTU0HdgmbaLiI9PG KXnLlTN8ZLLxZBts6HTdbkUOt6+PUCzYseFUHXDpWalMtpWBQlTmGa9fPENXle385Nut 6w5lGOoMYmLKTNl0gpERblxea/rXvlCRnzcTwgnxvETjeJiOU3xLxuco6DTaT/fCYlv1 g7mgeYcWAyRP3Gwwj2/3WQnXf29UrG+lwQOpdKkJk2YaUew68hQbXeynO3WRCgkOIHQW Cfeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=egeu+YlPzYvIryMSwbo5grgbi5RzuGxh+QQaTCRWf7c=; b=Up+YnIMgAFK4IYZUY/r52PD922lpQhswP2/qVXzZRuWKqG9zNAMNsU86yZao0CoLPM ApWXLUPhbey1MmXTi4u4Nr8cfQdlyqlEDc/lHxtQhWqom6pEc0xE0KEVAePC+hATc1OS VxmyQWwhg9Bxi93pplWUXcp74mfALM6IZx5H9RLpI7p6ltwB2sABt2d2S/MQ7XT1THlS PqfgKrbgiQ+AIx/cOtL54S8g3BoTSSZ9EfEnE63915is7tMC15fyI5vt6lsSEEIKPMaW MWeRTqViI/jpBYJZdifhSQD2hB9xa8kbikEC9p8g3NH0GvcPblQwjhRvYDq2O9b2QQDr l4uQ== X-Gm-Message-State: AIVw112buJoGGv2ZLRIQA9b/ZPcRkO5nKMuNYqZNlFNRR+19hq8r+4sw eHe/YBimbKzxMYYhvwU= X-Received: by 10.98.152.86 with SMTP id q83mr570820pfd.149.1500111832271; Sat, 15 Jul 2017 02:43:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:40 -1000 Message-Id: <20170715094243.28371-32-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v14 31/34] target/arm: [a64] Move page and ss checks to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1aa4c14..41e5cc3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11196,6 +11196,7 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + int bound; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11244,8 +11245,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 - dc->next_page_start =3D - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound =3D 1; + } + max_insns =3D MIN(max_insns, bound); =20 init_tmp_a64_array(dc); =20 @@ -11313,12 +11320,6 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - if (dc->ss_active || dc->pc >=3D dc->next_page_start) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } - dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112833118401.5568080376628; Sat, 15 Jul 2017 03:00:33 -0700 (PDT) Received: from localhost ([::1]:41370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJsF-0002Vo-TJ for importer@patchew.org; Sat, 15 Jul 2017 06:00:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJcC-0004lG-5U for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:44:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJcB-0003d7-Bm for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:56 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33061) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJcB-0003cz-5z for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:55 -0400 Received: by mail-pg0-x244.google.com with SMTP id 123so1669002pgd.0 for ; Sat, 15 Jul 2017 02:43:55 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=BjE7VVtGAEBD2JNqHzvOaUlT+zl5Z0KzSpupYg2dJIE=; b=MnBocNxOxKHor0Tasx00PqQNJyy7sCnY1SzlzoIwq984gTJ2ct56rIG7NGQOEv5Mli top5NBvYr+hLJdNCy73+K6BLhK+tY7qWc8540kJUQm/SfqdDA9C4OKXPmu0B1VbziBEQ H2gV0hBSPpyf+K0m/FNpPASaBrgaTcb6yxTRD0pI4STvqkEvWydBy6oFMg8l56wAeket xW/DxUquLYBWNOASR61+QksLmSekxSFU7+OlvHZJBIuOMe2qoxdd/3rCVZuRaau3SOIK C06bIqDJtsqHpI+pId4L2xUAAPetAA7xvdBgGbtJp0pcE2sbZSUnsukpJq+qsDJ6+fz1 043g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=BjE7VVtGAEBD2JNqHzvOaUlT+zl5Z0KzSpupYg2dJIE=; b=YvhX9mTWSP1XYFJ3IB8YGQL9m/IRLm+Ih2E2iD2ghQ/Qlt7EQKFIN5BEr6WCoouxOG 9eQD1KjaiSnWKTvUs75GCj+OLj0Dp35ZsIBeqWpMnS6aaGoAIMpam1Q/9Z6ZA8rSL/sP 0Te03WVxNcZ+yggyJPZASs2w9DpYjq3wMFcc/XyrFFgsj6yJHnzz6DYs74o+cGKoOTei rPhTPzw5zLOQsdPBn5Al+drzoZoUAnNZ89wiloIl302FVEjf7IpdDvnat1cVDtwjFhmq muPwj+XiniGSCRUlamBZaDaESnYZBMDkb4ZKPes3OmKTvGph3dZNDpE+FdP2B89NOQLt UZZg== X-Gm-Message-State: AIVw110nubn0/nqLBC4nCIaRqLBhsEtXCl/l5BYIKf7nkvn7w6ot7vem atht89JHKO+PBbPoR4o= X-Received: by 10.98.94.5 with SMTP id s5mr9542848pfb.138.1500111834086; Sat, 15 Jul 2017 02:43:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:41 -1000 Message-Id: <20170715094243.28371-33-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v14 32/34] target/arm: Move ss check to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can check for single-step just once. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4b1230b..ebe1c1a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11845,6 +11845,11 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, dc->next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 + /* If architectural single step active, limit to 1. */ + if (is_singlestepping(dc)) { + max_insns =3D 1; + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -12000,11 +12005,9 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ =20 - if (is_singlestepping(dc)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else if ((dc->pc >=3D dc->next_page_start) || - ((dc->pc >=3D dc->next_page_start - 3) && - insn_crosses_page(env, dc))) { + if (dc->pc >=3D dc->next_page_start || + (dc->pc >=3D dc->next_page_start - 3 && + insn_crosses_page(env, dc))) { /* We want to stop the TB if the next insn starts in a new pag= e, * or if it spans between this page and the next. This means t= hat * if we're looking at the last halfword in the page we need to --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500112998416141.75153270370083; Sat, 15 Jul 2017 03:03:18 -0700 (PDT) Received: from localhost ([::1]:41385 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJuu-000599-4a for importer@patchew.org; Sat, 15 Jul 2017 06:03:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJcG-0004nX-5G for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:44:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJcD-0003eU-EL for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:59 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34412) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJcD-0003dp-6U for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:57 -0400 Received: by mail-pg0-x243.google.com with SMTP id j186so13347641pge.1 for ; Sat, 15 Jul 2017 02:43:57 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=hgkRWlHheRzOSQRPPG25gT6IHlZZjWkX4uJCZO9Xo5Q=; b=SGDugFuUKha498hjLcc9TyNv0NIA9q50LCAzyNyEUKRbKC4PJHwVdHXGMYgnbfgJ8I hecztKbqMsnmyi33SRyK9SNy0Qa9GDrXQjfpLzOxNvAKfAyd8rTnmdvpivzrcKZJN/hh nDA4v5gG3iNlGTUqbOon6bO7i3qommkV639iE/aMWOhztqaQSzawjEkwha44Z3yC9sx9 9lKHxe1Zt71TxLKf7UBSnYzHW/WKpp03Zdqk/ALZ1X3PapSUrlPN7vTgyoLTXXjKUXAb fB6oE8cKZdGzkYm++N0ys0n9MlAMya5BcpdJ5SXcUQtVlD27V2fKuSnVJyZSymFtGDWK zU7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=hgkRWlHheRzOSQRPPG25gT6IHlZZjWkX4uJCZO9Xo5Q=; b=mTlgTqbOTw+f78WKc2lNgdieNSFyJIAEDtjUIIVReoCMn+f4KG2GUYk2PSH16fbBjg dWs52XC+crT/1KeVOU8/ydEHDhwxtXTO0DTOFIy7iGzITOJV+2u3hhY79FjluS1KWnOE oNsamOwa3XHfLbk+T5oyDZms123NY+AJcVC49U7Oqp8zyB6PZaDLlF3SirtW1Yr67diI 4FSUYj+VVI6IABnTw3Bqfx/3hsM4gSOttm0KvB0kdTZJZr1QTHtFujHZxDMtyr1e24HS u0vFSxOPFHs8TaQPum044QqkqnVxZm3cK1BSY6OeH9heNOgdAcBKV5y5KekC9fH+Wbs8 3Qyg== X-Gm-Message-State: AIVw1117v5uYgEhtfj0mARpe7DXUk+ZjYtnwgnpQ/7vBdIt9bsxmp7cW DLodSWdK+SCQXTVvkVA= X-Received: by 10.98.201.75 with SMTP id k72mr9308018pfg.99.1500111835963; Sat, 15 Jul 2017 02:43:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:42 -1000 Message-Id: <20170715094243.28371-34-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v14 33/34] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.c | 134 +++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 86 insertions(+), 48 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ebe1c1a..d7c3c10 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11944,20 +11944,17 @@ static bool arm_tr_breakpoint_check(DisasContextB= ase *dcbase, CPUState *cpu, return true; } =20 -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; - #ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_NORETURN; - return; - } + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_NORETURN; + return true; + } #endif =20 if (dc->ss_active && !dc->pstate_ss) { @@ -11975,54 +11972,82 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } =20 - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); + return false; +} + +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } + dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); +} =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >=3D dc->next_page_start || - (dc->pc >=3D dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new pag= e, - * or if it spans between this page and the next. This means t= hat - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit= insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp =3D DISAS_TOO_MANY; +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond =3D ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; } } =20 - dc->base.pc_next =3D dc->pc; - translator_loop_temp_check(&dc->base); + arm_post_translate_insn(env, dc); } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12161,12 +12186,25 @@ static const TranslatorOps arm_translator_ops =3D= { .disas_log =3D arm_tr_disas_log, }; =20 +static const TranslatorOps thumb_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D thumb_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; =20 + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops =3D &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops =3D &aarch64_translator_ops; --=20 2.9.4 From nobody Fri Mar 29 13:52:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500113273746583.108145084899; Sat, 15 Jul 2017 03:07:53 -0700 (PDT) Received: from localhost ([::1]:41404 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJzM-0001QG-HI for importer@patchew.org; Sat, 15 Jul 2017 06:07:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJcO-0004t1-Em for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:44:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJcL-0003gr-CK for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:44:08 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:35011) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJcL-0003gg-6A for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:44:05 -0400 Received: by mail-pg0-x241.google.com with SMTP id d193so13341581pgc.2 for ; Sat, 15 Jul 2017 02:44:05 -0700 (PDT) Received: from bigtime.twiddle.net (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=j3R+p+oPOnq5dTGx6JZ3a+KhuWMx0dZxBbJW+mMpSTo=; b=vaaDsJB2YHz3BH3rOqfStFxkZLtjeTyKpDUy0wELbIjEwz5o9TLs+YPkvLF10pNa7d wVf2vEwtuLS2JYr9UFPLQ2pxDaE31My+EGhY1f/zquuIkgQFZzoDjoiazss2D8r+1yOY wd6jmyQ8c3VgeSWjJaEXzuo+gYmCW+YyOKcTk2GxR0cwtGXv0c51wyR0/tf9VSlwJ+8a IrDZCDgMnDWH73cs9haNPXS/FFS5RfRKVUe9r54W3Ar9lAGetuWXghpbdWRPU+l7Qx3H 2caZb6HBWm5ahUKGlTbnUJdZERfVem6SwGK0hsfAEnCLdiJmQMJ21u+Rq/vIXwWPM9CS JS9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=j3R+p+oPOnq5dTGx6JZ3a+KhuWMx0dZxBbJW+mMpSTo=; b=bxk0zi0jxegj/9AEPP1QiD20fWS0B8dEaPXtZ/xBCvrjNMLIvfB4ZgzcKNDkMTgF/Z jmGvg946BpNqk1VnKWRz0BeKYCD09IdQOyDPuDypt0tEG9U6P8je5mpqziUByp5y4DvG ipKta2Qk+NhFfHW9sp+47gpJlhR9Pzw6Aq9agyso9L9lgI4DlmUmWXvXMgwSF3IJnn+X bjdZALDyo8ETPTUVPE4sHrYKsGiIdmMFxIrPLBL4uHySaExhyYrWksQoVroBdnW/06ph SGio/E+513cHuiopYBVfFP7A0ydjxAaCKEpTWWVXpSHo77LLtDfKPbZ4kleaYFocI1UC LrQw== X-Gm-Message-State: AIVw113fC9C1tYCib9xz9+fNvqgPjGiI6fShDSePHlXSRSpeFV5ZY3av eVb4FbVnQ+LG1PG7UCY= X-Received: by 10.84.128.76 with SMTP id 70mr20726200pla.229.1500111837798; Sat, 15 Jul 2017 02:43:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:43 -1000 Message-Id: <20170715094243.28371-35-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v14 34/34] target/arm: Perform per-insn cross-page check only for Thumb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.c | 57 +++++++++++++++++++++++++++++-----------------= ---- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d7c3c10..5b6368f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11850,6 +11850,13 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, max_insns =3D 1; } =20 + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound =3D (dc->next_page_start - dc->base.pc_first) / 4; + max_insns =3D MIN(max_insns, bound); + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11978,29 +11985,8 @@ static bool arm_pre_translate_insn(DisasContext *d= c) return false; } =20 -static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +static void arm_post_translate_insn(DisasContext *dc) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - * - * We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT - && (dc->pc >=3D dc->next_page_start - || (dc->pc >=3D dc->next_page_start - 3 - && insn_crosses_page(env, dc)))) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; @@ -12023,7 +12009,10 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) dc->pc +=3D 4; disas_arm_insn(dc, insn); =20 - arm_post_translate_insn(env, dc); + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ + + arm_post_translate_insn(dc); } =20 static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) @@ -12047,7 +12036,27 @@ static void thumb_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cpu) } } =20 - arm_post_translate_insn(env, dc); + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + arm_post_translate_insn(dc); } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) --=20 2.9.4