From nobody Sat May 4 06:10:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495240225910561.3484407135521; Fri, 19 May 2017 17:30:25 -0700 (PDT) Received: from localhost ([::1]:60731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsHo-0005ln-GE for importer@patchew.org; Fri, 19 May 2017 20:30:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsFQ-0004FB-Vh for qemu-devel@nongnu.org; Fri, 19 May 2017 20:27:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBsFP-0001ae-DJ for qemu-devel@nongnu.org; Fri, 19 May 2017 20:27:56 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39263) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBsFK-0001Zu-6b; Fri, 19 May 2017 20:27:50 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 6268520496; Fri, 19 May 2017 20:27:49 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Fri, 19 May 2017 20:27:49 -0400 Received: from keelia.au.ibm.com (unknown [202.90.207.97]) by mail.messagingengine.com (Postfix) with ESMTPA id 7D8CC241E3; Fri, 19 May 2017 20:27:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=YIMoUu e5kLhsKHBlkpl5uRzviDxg7m1sWa50vwojKuE=; b=UlKSnuhX3APkW9Q3ZCTqcF hnsUlS3LQC/G2YIZjZaAd75ImgGH9aug+mmbgVG1IOG1+0u7WWdFkDxYy3ReX8Ww 9GitJfbZg+wR50aDe8OYehY0AEvyslU45xuW4QtFGa3eycWeuGZMzobqRpW17eRb uf+zrFRsD3ca9T95BSxnAfqGiSytG56hS1YWoJi9G0OlRJTWYhbZvZlj/IwU7X6S cN8C40c7u+CqxpFGut8cK5gc9CQGlk0xDkXYad53zaqr6R4aeMhpOmmGKBlIIwxU mTNxb1Dmfpoh7rvM/k5s2KwKwrWpiHmnCed0nEYU/mkokk827OABB09PXjEX0g7g == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=YIMoUue5kLhsKHBlkpl5uRzviDxg7m1sWa50vwojK uE=; b=O6qiOH+Iu4FTdYqeNfL7CZjmxEiUIpdoI9IUExaIhZ74CQKYWBjgEQjnd nQs2unvlhHjnAt9eDq16EV3ATQSb0jSSimjW1rW6UC5vjeJxaB06WfFx83+ooLVT JFYZBCxQVIhBeb97wV4EafnObaFxCaw49KuMjibc/0eBg/P4fdS0GRCeLC97/xV9 J1hRW+rPlF/RHYKlFOARKhAbhxqdVxzJPGyWFW9QXyNULyeielIYoR/Sh+35sZtX cGaY4iqn+4nuSNg8JANmYD6Ps96cNhK7Bw1HY6S1bl4gyn1G9eA188EBwvcLgNrf crpdPsc4HLEcDAAJbH+8trlhLws3w== X-ME-Sender: X-Sasl-enc: tfrcbcDKwHnG3uRad3FOQe/73JxlS/TMi1mlTCPlvUDj 1495240068 From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Sat, 20 May 2017 08:26:52 +0800 Message-Id: <20170520002653.20213-2-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170520002653.20213-1-andrew@aj.id.au> References: <20170520002653.20213-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Ryan Chen , Andrew Jeffery , Alistair Francis , qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This model implements enough behaviour to do basic functionality tests such as device initialisation and read out of dummy sample values. The sample value generation strategy is similar to the STM ADC already in the tree. Signed-off-by: Andrew Jeffery --- hw/adc/Makefile.objs | 1 + hw/adc/aspeed_adc.c | 246 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/adc/aspeed_adc.h | 33 ++++++ 3 files changed, 280 insertions(+) create mode 100644 hw/adc/aspeed_adc.c create mode 100644 include/hw/adc/aspeed_adc.h diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs index 3f6dfdedaec7..2bf9362ba3c4 100644 --- a/hw/adc/Makefile.objs +++ b/hw/adc/Makefile.objs @@ -1 +1,2 @@ obj-$(CONFIG_STM32F2XX_ADC) +=3D stm32f2xx_adc.o +obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_adc.o diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c new file mode 100644 index 000000000000..d08f1684f7bc --- /dev/null +++ b/hw/adc/aspeed_adc.c @@ -0,0 +1,246 @@ +/* + * Aspeed ADC + * + * Andrew Jeffery + * + * Copyright 2017 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/adc/aspeed_adc.h" +#include "qapi/error.h" +#include "qemu/log.h" + +#define ASPEED_ADC_ENGINE_CTRL 0x00 +#define ASPEED_ADC_ENGINE_CH_EN_MASK 0xffff0000 +#define ASPEED_ADC_ENGINE_CH_EN(x) ((BIT(x)) << 16) +#define ASPEED_ADC_ENGINE_INIT BIT(8) +#define ASPEED_ADC_ENGINE_AUTO_COMP BIT(5) +#define ASPEED_ADC_ENGINE_COMP BIT(4) +#define ASPEED_ADC_ENGINE_MODE_MASK 0x0000000e +#define ASPEED_ADC_ENGINE_MODE_OFF (0b000 << 1) +#define ASPEED_ADC_ENGINE_MODE_STANDBY (0b001 << 1) +#define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1) +#define ASPEED_ADC_ENGINE_EN BIT(0) + +#define ASPEED_ADC_L_MASK ((1 << 10) - 1) +#define ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK) +#define ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK) +#define ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 | ASPEED_ADC_L_MA= SK) + +static inline uint32_t update_channels(uint32_t current) +{ + const uint32_t next =3D (current + 7) & 0x3ff; + + return (next << 16) | next; +} + +static bool breaks_threshold(AspeedADCState *s, int ch_off) +{ + const uint32_t a =3D ASPEED_ADC_L(s->channels[ch_off]); + const uint32_t a_lower =3D ASPEED_ADC_L(s->bounds[2 * ch_off]); + const uint32_t a_upper =3D ASPEED_ADC_H(s->bounds[2 * ch_off]); + const uint32_t b =3D ASPEED_ADC_H(s->channels[ch_off]); + const uint32_t b_lower =3D ASPEED_ADC_L(s->bounds[2 * ch_off + 1]); + const uint32_t b_upper =3D ASPEED_ADC_H(s->bounds[2 * ch_off + 1]); + + return ((a < a_lower || a > a_upper)) || + ((b < b_lower || b > b_upper)); +} + +static uint32_t read_channel_sample(AspeedADCState *s, int ch_off) +{ + uint32_t ret; + + /* Poor man's sampling */ + ret =3D s->channels[ch_off]; + s->channels[ch_off] =3D update_channels(s->channels[ch_off]); + + if (breaks_threshold(s, ch_off)) { + qemu_irq_raise(s->irq); + } + + return ret; +} + +#define TO_INDEX(addr, base) (((addr) - (base)) >> 2) + +static uint64_t aspeed_adc_read(void *opaque, hwaddr addr, + unsigned int size) +{ + AspeedADCState *s =3D ASPEED_ADC(opaque); + uint64_t ret; + + switch (addr) { + case 0x00: + ret =3D s->engine_ctrl; + break; + case 0x04: + ret =3D s->irq_ctrl; + break; + case 0x08: + ret =3D s->vga_detect_ctrl; + break; + case 0x0c: + ret =3D s->adc_clk_ctrl; + break; + case 0x10 ... 0x2e: + ret =3D read_channel_sample(s, TO_INDEX(addr, 0x10)); + break; + case 0x30 ... 0x6e: + ret =3D s->bounds[TO_INDEX(addr, 0x30)]; + break; + case 0x70 ... 0xae: + ret =3D s->hysteresis[TO_INDEX(addr, 0x70)]; + break; + case 0xc0: + ret =3D s->irq_src; + break; + case 0xc4: + ret =3D s->comp_trim; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: addr: 0x%lx, size: %u\n", __func__, = addr, + size); + ret =3D 0; + break; + } + + return ret; +} + +static void aspeed_adc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + AspeedADCState *s =3D ASPEED_ADC(opaque); + + switch (addr) { + case 0x00: + { + uint32_t init; + + init =3D !!(val & ASPEED_ADC_ENGINE_EN); + init *=3D ASPEED_ADC_ENGINE_INIT; + + val &=3D ~ASPEED_ADC_ENGINE_INIT; + val |=3D init; + } + + val &=3D ~ASPEED_ADC_ENGINE_AUTO_COMP; + s->engine_ctrl =3D val; + + break; + case 0x04: + s->irq_ctrl =3D val; + break; + case 0x08: + s->vga_detect_ctrl =3D val; + break; + case 0x0c: + s->adc_clk_ctrl =3D val; + break; + case 0x10 ... 0x2e: + s->channels[TO_INDEX(addr, 0x10)] =3D val; + break; + case 0x30 ... 0x6e: + s->bounds[TO_INDEX(addr, 0x30)] =3D (val & ASPEED_ADC_LH_MASK); + break; + case 0x70 ... 0xae: + s->hysteresis[TO_INDEX(addr, 0x70)] =3D + (val & (BIT(31) | ASPEED_ADC_LH_MASK)); + break; + case 0xc0: + s->irq_src =3D (val & 0xffff); + break; + case 0xc4: + s->comp_trim =3D (val & 0xf); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: %lu\n", __func__, addr); + break; + } +} + +static const MemoryRegionOps aspeed_adc_ops =3D { + .read =3D aspeed_adc_read, + .write =3D aspeed_adc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static void aspeed_adc_reset(DeviceState *dev) +{ + struct AspeedADCState *s =3D ASPEED_ADC(dev); + + s->engine_ctrl =3D 0; + s->irq_ctrl =3D 0; + s->vga_detect_ctrl =3D 0x0000000f; + s->adc_clk_ctrl =3D 0x0000000f; + memset(s->channels, 0, sizeof(s->channels)); + memset(s->bounds, 0, sizeof(s->bounds)); + memset(s->hysteresis, 0, sizeof(s->hysteresis)); + s->irq_src =3D 0; + s->comp_trim =3D 0; +} + +static void aspeed_adc_realize(DeviceState *dev, Error **errp) +{ + AspeedADCState *s =3D ASPEED_ADC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_adc_ops, s, + TYPE_ASPEED_ADC, 0x1000); + + sysbus_init_mmio(sbd, &s->mmio); +} + +static const VMStateDescription vmstate_aspeed_adc =3D { + .name =3D TYPE_ASPEED_ADC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(engine_ctrl, AspeedADCState), + VMSTATE_UINT32(irq_ctrl, AspeedADCState), + VMSTATE_UINT32(vga_detect_ctrl, AspeedADCState), + VMSTATE_UINT32(adc_clk_ctrl, AspeedADCState), + VMSTATE_UINT32_ARRAY(channels, AspeedADCState, + ASPEED_ADC_NR_CHANNELS / 2), + VMSTATE_UINT32_ARRAY(bounds, AspeedADCState, ASPEED_ADC_NR_CHANNEL= S), + VMSTATE_UINT32_ARRAY(hysteresis, AspeedADCState, + ASPEED_ADC_NR_CHANNELS), + VMSTATE_UINT32(irq_src, AspeedADCState), + VMSTATE_UINT32(comp_trim, AspeedADCState), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_adc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_adc_realize; + dc->reset =3D aspeed_adc_reset; + dc->desc =3D "Aspeed Analog-to-Digital Converter", + dc->vmsd =3D &vmstate_aspeed_adc; +} + +static const TypeInfo aspeed_adc_info =3D { + .name =3D TYPE_ASPEED_ADC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedADCState), + .class_init =3D aspeed_adc_class_init, +}; + +static void aspeed_adc_register_types(void) +{ + type_register_static(&aspeed_adc_info); +} + +type_init(aspeed_adc_register_types); diff --git a/include/hw/adc/aspeed_adc.h b/include/hw/adc/aspeed_adc.h new file mode 100644 index 000000000000..ae2089ac62ca --- /dev/null +++ b/include/hw/adc/aspeed_adc.h @@ -0,0 +1,33 @@ +#ifndef _ASPEED_ADC_H_ +#define _ASPEED_ADC_H_ + +#include + +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +#define TYPE_ASPEED_ADC "aspeed.adc" +#define ASPEED_ADC(obj) OBJECT_CHECK(AspeedADCState, (obj), TYPE_ASPEED_AD= C) + +#define ASPEED_ADC_NR_CHANNELS 16 + +typedef struct AspeedADCState { + /* */ + SysBusDevice parent; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t engine_ctrl; + uint32_t irq_ctrl; + uint32_t vga_detect_ctrl; + uint32_t adc_clk_ctrl; + uint32_t channels[ASPEED_ADC_NR_CHANNELS / 2]; + uint32_t bounds[ASPEED_ADC_NR_CHANNELS]; + uint32_t hysteresis[ASPEED_ADC_NR_CHANNELS]; + uint32_t irq_src; + uint32_t comp_trim; +} AspeedADCState; + +#endif /* _ASPEED_ADC_H_ */ --=20 2.9.3 From nobody Sat May 4 06:10:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495240159053796.3734496277989; Fri, 19 May 2017 17:29:19 -0700 (PDT) Received: from localhost ([::1]:60724 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsGj-00050X-IB for importer@patchew.org; Fri, 19 May 2017 20:29:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsFW-0004It-LS for qemu-devel@nongnu.org; Fri, 19 May 2017 20:28:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBsFT-0001bN-HM for qemu-devel@nongnu.org; Fri, 19 May 2017 20:28:02 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39673) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBsFQ-0001am-Pg; Fri, 19 May 2017 20:27:56 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 53738206CA; Fri, 19 May 2017 20:27:56 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Fri, 19 May 2017 20:27:56 -0400 Received: from keelia.au.ibm.com (unknown [202.90.207.97]) by mail.messagingengine.com (Postfix) with ESMTPA id 43391241E3; Fri, 19 May 2017 20:27:49 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=bEidNu Zadtg+gfp/qngfZt03GLwTKGxQo146dgMPOiI=; b=p02qc5tpoT6gpW3CwyA21y DvCkQdUOdjh+mzmHHYsallkL3a7d+xQDwm4DCFGBsND1OMEAkpMQVJXp6vaROjgz MMUXMyk/QyL744uUy2l/oERvecHrXn0CxWBT66//Y/8BYwE+Stkv6PwozC9SSKLu MFPBFUAXwrHfzckHxkKj6cbv3dCs/3TpdQikf0faMA7iDI3Hzr32v0eVbEC3unHX uaCKhq9S4aWoFZUDY41ZP0DusdyPHfH95IfxK8EJeA6lT0vslTlTfjHuTJLBhUVR hTGvSAMpVpHCAWxRdntJOZAIeV0b/kO7PSnIPCpqHAwCyZkX2uxsWdj+Env8uxnA == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=bEidNuZadtg+gfp/qngfZt03GLwTKGxQo146dgMPO iI=; b=YdAFJ9wsUflSbYbLS6TRbVDa2aVYupzjwlOlGLPP3/w9Q/ewWdC25XSPD iDezwcJVvN1xIcGcpHYjWsOkhZYj93Cg2ACEAssd2QQpsGcZXHT4qCPg+PmajQ7v mR6EQOOGxQzjQsSCt0SFJ8qarQ/1xeZKmhV6BcJOZnMcm7QxDPdNFaKtpjAg3ZHr qQU/LIZfKHw9ImnjXJ9KrR4o/Yu40g0t9sSmubLsRRODVyAGExN7mQMgFn/LVi4M 1rFfJHqHEWSaSkMns7yrYa42VE0eemaKpQc9Hqt2HiHiQ3O/bx07MD1N0Va1Lmow fMzpVtfNvnxXHfRIP1KLqQeYK2eag== X-ME-Sender: X-Sasl-enc: FmgCG6i+EeaDL5ia7NKH38wcyyCzgIj8bsQO6/STIBgO 1495240075 From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Sat, 20 May 2017 08:26:53 +0800 Message-Id: <20170520002653.20213-3-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170520002653.20213-1-andrew@aj.id.au> References: <20170520002653.20213-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 2/2] hw/arm: Integrate ADC model into Aspeed SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Ryan Chen , Andrew Jeffery , Alistair Francis , qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Andrew Jeffery Reviewed-by: Alistair Francis --- hw/arm/aspeed_soc.c | 15 +++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5c667d2c35b6..11f9588720d2 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -31,6 +31,7 @@ #define ASPEED_SOC_VIC_BASE 0x1E6C0000 #define ASPEED_SOC_SDMC_BASE 0x1E6E0000 #define ASPEED_SOC_SCU_BASE 0x1E6E2000 +#define ASPEED_SOC_ADC_BASE 0x1E6E9000 #define ASPEED_SOC_SRAM_BASE 0x1E720000 #define ASPEED_SOC_TIMER_BASE 0x1E782000 #define ASPEED_SOC_WDT_BASE 0x1E785000 @@ -157,6 +158,10 @@ static void aspeed_soc_init(Object *obj) object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); =20 + object_initialize(&s->adc, sizeof(s->adc), TYPE_ASPEED_ADC); + object_property_add_child(obj, "adc", OBJECT(&s->adc), NULL); + qdev_set_parent_bus(DEVICE(&s->adc), sysbus_get_default()); + object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); @@ -256,6 +261,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); =20 + /* ADC */ + object_property_set_bool(OBJECT(&s->adc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, ASPEED_SOC_ADC_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, + qdev_get_gpio_in(DEVICE(&s->vic), 31)); + /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hds[0]) { qemu_irq uart5 =3D qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index d16205c66b5f..3b4d66d30f08 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -15,6 +15,7 @@ #include "hw/arm/arm.h" #include "hw/intc/aspeed_vic.h" #include "hw/misc/aspeed_scu.h" +#include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_sdmc.h" #include "hw/timer/aspeed_timer.h" #include "hw/i2c/aspeed_i2c.h" @@ -37,6 +38,7 @@ typedef struct AspeedSoCState { AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; + AspeedADCState adc; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; --=20 2.9.3