From nobody Sat May 4 18:31:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494405312662880.3954516494531; Wed, 10 May 2017 01:35:12 -0700 (PDT) Received: from localhost ([::1]:41106 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d8N5Q-0001i2-KU for importer@patchew.org; Wed, 10 May 2017 04:35:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42839) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d8N3l-0000dq-2M for qemu-devel@nongnu.org; Wed, 10 May 2017 04:33:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d8N3i-0003hX-Lz for qemu-devel@nongnu.org; Wed, 10 May 2017 04:33:25 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:34517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d8N3i-0003hF-Fy for qemu-devel@nongnu.org; Wed, 10 May 2017 04:33:22 -0400 Received: by mail-pg0-x241.google.com with SMTP id u187so3229240pgb.1 for ; Wed, 10 May 2017 01:33:22 -0700 (PDT) Received: from eric.tencent.com ([203.205.141.37]) by smtp.gmail.com with ESMTPSA id z125sm3829043pfb.64.2017.05.10.01.33.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 May 2017 01:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s63d/d9Ct+4iwdhqUjdWr5K2eUVPHwTFpMV9Gkue+r4=; b=X6ToGPrQnFRTIX2YJZdtEzDQeY9GN7ZauapljXqb5mjJDd5WsEvh6eUHln+rIqEcmv Em1GjXUVQ6vE+F+OMGRcsCaZE7R19Hb9q9eV7Ek/DdKPAlMqN4WCVcTiLSYS9XUsi6wX jzWuJ3Z5zDK0uGnOpNwcndienc8KljYEFzdwM3MMXFR3cUpYqcoB3g4jMdyRPcGHkQvM 5yQqncZEhkwY9O9Z8cDqmdXf/EF62RS2R1n/ng0QRVK9jV1G2zvdj53Evy7yDk6AGO/j AZwhGcGojBgs1aSmkatkmyiVbJn4iEY1+fhSxcXt289EXqd3aMaOBfyOKW8Hw7HAFcYt Oa5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s63d/d9Ct+4iwdhqUjdWr5K2eUVPHwTFpMV9Gkue+r4=; b=btJP9ZR2JnOWEL+Tsri8UY8sufhncBBdcNqhxiwQjwqo55VTFpsDy4Wm18IiFf5CFW hohkpz9pjXD7RuntCs89rILBEBzik+Wz8AGrA1QtTRFcY5If5borBsQDmkDx8WASjgLI skFFtGWYLHX3JUO66WJ50X+OJ/KA9F7mLJlGiSa4xNLYih1Kn3G2fNhS4b6ktRU1LuFS H0eYRjfxArM+zVYzCgH1zBRDwjfCHUiBI3rSidxHdMp65UvMiTA3umSoOhFYKN81jYa4 FOUd6y1iKD34oCKZGQqA/AFJk1R8vyCjIsJtvNDB6Y04hnEHn138ZShvLU8488sYeg5V 6biA== X-Gm-Message-State: AODbwcCq5XHFnEtiASIMiEJ4eBa+3GcVuG07FjCyDgWu3DhyYuy04Q99 Ckrn38aWLSEFbg== X-Received: by 10.98.160.130 with SMTP id p2mr4939385pfl.184.1494405201495; Wed, 10 May 2017 01:33:21 -0700 (PDT) From: guangrong.xiao@gmail.com X-Google-Original-From: xiaoguangrong@tencent.com To: pbonzini@redhat.com, mst@redhat.com, mtosatti@redhat.com Date: Wed, 10 May 2017 16:32:55 +0800 Message-Id: <20170510083259.3900-2-xiaoguangrong@tencent.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170510083259.3900-1-xiaoguangrong@tencent.com> References: <20170510083259.3900-1-xiaoguangrong@tencent.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 1/5] mc146818rtc: update periodic timer only if it is needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , yunfangtai@tencent.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xiao Guangrong Currently, the timer is updated whenever RegA or RegB is written even if the periodic timer related configuration is not changed This patch optimizes it slightly to make the update happen only if its period or enable-status is changed, also later patches are depend on this optimization Signed-off-by: Xiao Guangrong --- hw/timer/mc146818rtc.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index 4165450..5cccb2a 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -391,6 +391,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { RTCState *s =3D opaque; + bool update_periodic_timer; =20 if ((addr & 1) =3D=3D 0) { s->cmos_index =3D data & 0x7f; @@ -423,6 +424,8 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, } break; case RTC_REG_A: + update_periodic_timer =3D (s->cmos_data[RTC_REG_A] ^ data) & 0= x0f; + if ((data & 0x60) =3D=3D 0x60) { if (rtc_running(s)) { rtc_update_time(s); @@ -445,10 +448,17 @@ static void cmos_ioport_write(void *opaque, hwaddr ad= dr, /* UIP bit is read only */ s->cmos_data[RTC_REG_A] =3D (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); - periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + + if (update_periodic_timer) { + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + } + check_update_timer(s); break; case RTC_REG_B: + update_periodic_timer =3D (s->cmos_data[RTC_REG_B] ^ data) + & REG_B_PIE; + if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ if (rtc_running(s)) { @@ -475,7 +485,11 @@ static void cmos_ioport_write(void *opaque, hwaddr add= r, qemu_irq_lower(s->irq); } s->cmos_data[RTC_REG_B] =3D data; - periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + + if (update_periodic_timer) { + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + } + check_update_timer(s); break; case RTC_REG_C: --=20 2.9.3 From nobody Sat May 4 18:31:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494405316486104.47966838455216; Wed, 10 May 2017 01:35:16 -0700 (PDT) Received: from localhost ([::1]:41107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d8N5X-0001p1-1B for importer@patchew.org; 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Wed, 10 May 2017 01:33:24 -0700 (PDT) From: guangrong.xiao@gmail.com X-Google-Original-From: xiaoguangrong@tencent.com To: pbonzini@redhat.com, mst@redhat.com, mtosatti@redhat.com Date: Wed, 10 May 2017 16:32:56 +0800 Message-Id: <20170510083259.3900-3-xiaoguangrong@tencent.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170510083259.3900-1-xiaoguangrong@tencent.com> References: <20170510083259.3900-1-xiaoguangrong@tencent.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 2/5] mc146818rtc: precisely count the clock for periodic timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , yunfangtai@tencent.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Tai Yunfang There are two issues in current code: 1) If the period is changed by re-configuring RegA, the coalesced irq will be scaled to reflect the new period, however, it calculates the new interrupt number like this: s->irq_coalesced =3D (s->irq_coalesced * s->period) / period; There are some clocks will be lost if they are not enough to be squeezed to a single new period that will cause the VM clock slower In order to fix the issue, we calculate the interrupt window based on the precise clock rather than period, then the clocks lost during period is scaled can be compensated properly 2) If periodic_timer_update() is called due to RegA reconfiguration, i.e, the period is updated, current time is not the start point for the next periodic timer, instead, which should start from the last interrupt, otherwise, the clock in VM will become slow This patch takes the clocks from last interrupt to current clock into account and compensates the clocks for the next interrupt, especially=EF=BC=8Cif a complete interrupt was lost in this window, the time can be caught up by LOST_TICK_POLICY_SLEW Signed-off-by: Tai Yunfang Signed-off-by: Xiao Guangrong --- hw/timer/mc146818rtc.c | 126 ++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 103 insertions(+), 23 deletions(-) diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index 5cccb2a..dac6744 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -146,31 +146,106 @@ static void rtc_coalesced_timer(void *opaque) } #endif =20 -/* handle periodic timer */ -static void periodic_timer_update(RTCState *s, int64_t current_time) +static uint32_t rtc_periodic_clock_ticks(RTCState *s) { - int period_code, period; - int64_t cur_clock, next_irq_clock; + int period_code; + + if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) { + return 0; + } =20 period_code =3D s->cmos_data[RTC_REG_A] & 0x0f; - if (period_code !=3D 0 - && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { - if (period_code <=3D 2) - period_code +=3D 7; - /* period in 32 Khz cycles */ - period =3D 1 << (period_code - 1); -#ifdef TARGET_I386 - if (period !=3D s->period) { - s->irq_coalesced =3D (s->irq_coalesced * s->period) / period; - DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coales= ced); - } - s->period =3D period; -#endif + if (!period_code) { + return 0; + } + + if (period_code <=3D 2) { + period_code +=3D 7; + } + + /* period in 32 Khz cycles */ + return 1 << (period_code - 1); +} + +/* + * handle periodic timer. @old_period indicates the periodic timer update + * is just due to period adjustment. + */ +static void +periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_peri= od) +{ + uint32_t period; + int64_t cur_clock, next_irq_clock, lost_clock =3D 0; + + period =3D rtc_periodic_clock_ticks(s); + + if (period) { /* compute 32 khz clock */ cur_clock =3D muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); =20 - next_irq_clock =3D (cur_clock & ~(period - 1)) + period; + /* + * if the periodic timer's update is due to period re-configuration, + * we should count the clock since last interrupt. + */ + if (old_period) { + int64_t last_periodic_clock, next_periodic_clock; + + next_periodic_clock =3D muldiv64(s->next_periodic_time, + RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND= ); + last_periodic_clock =3D next_periodic_clock - old_period; + lost_clock =3D cur_clock - last_periodic_clock; + assert(lost_clock >=3D 0); + } + +#ifdef TARGET_I386 + /* + * recalculate the coalesced irqs for two reasons: + * a) the lost_clock is more that a period, i,e. the timer + * interrupt has been lost, we should catch up the time. + * + * b) the period may be reconfigured, under this case, when + * switching from a shorter to a longer period, scale down + * the missing ticks since we expect the OS handler to + * treat the delayed ticks as longer. Any leftovers are + * put back into lost_clock. + * When switching to a shorter period, scale up the missing + * ticks since we expect the OS handler to treat the delayed + * ticks as shorter. + */ + if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { + uint32_t old_irq_coalesced =3D s->irq_coalesced; + + /* + * as the old QEMUs only used s->period for the case that + * LOST_TICK_POLICY_SLEW is used, in order to keep the + * compatible migration, we obey the rule as old QEMUs. + */ + s->period =3D period; + + lost_clock +=3D old_irq_coalesced * old_period; + s->irq_coalesced =3D lost_clock / s->period; + lost_clock %=3D s->period; + if (old_irq_coalesced !=3D s->irq_coalesced || + old_period !=3D s->period) { + DPRINTF_C("cmos: coalesced irqs scaled from %d to %d, " + "period scaled from %d to %d\n", old_irq_coalesc= ed, + s->irq_coalesced, old_period, s->period); + rtc_coalesced_timer_update(s); + } + } else +#endif + { + /* + * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW + * is not used, we should make the time progress anyway. + */ + lost_clock =3D MIN(lost_clock, period); + } + + assert(lost_clock >=3D 0 && lost_clock <=3D period); + + next_irq_clock =3D cur_clock + period - lost_clock; s->next_periodic_time =3D muldiv64(next_irq_clock, NANOSECONDS_PER= _SECOND, RTC_CLOCK_RATE) + 1; timer_mod(s->periodic_timer, s->next_periodic_time); @@ -186,7 +261,7 @@ static void rtc_periodic_timer(void *opaque) { RTCState *s =3D opaque; =20 - periodic_timer_update(s, s->next_periodic_time); + periodic_timer_update(s, s->next_periodic_time, 0); s->cmos_data[RTC_REG_C] |=3D REG_C_PF; if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { s->cmos_data[RTC_REG_C] |=3D REG_C_IRQF; @@ -391,6 +466,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { RTCState *s =3D opaque; + uint32_t old_period; bool update_periodic_timer; =20 if ((addr & 1) =3D=3D 0) { @@ -425,6 +501,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, break; case RTC_REG_A: update_periodic_timer =3D (s->cmos_data[RTC_REG_A] ^ data) & 0= x0f; + old_period =3D rtc_periodic_clock_ticks(s); =20 if ((data & 0x60) =3D=3D 0x60) { if (rtc_running(s)) { @@ -450,7 +527,8 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, (s->cmos_data[RTC_REG_A] & REG_A_UIP); =20 if (update_periodic_timer) { - periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), + old_period); } =20 check_update_timer(s); @@ -458,6 +536,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, case RTC_REG_B: update_periodic_timer =3D (s->cmos_data[RTC_REG_B] ^ data) & REG_B_PIE; + old_period =3D rtc_periodic_clock_ticks(s); =20 if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ @@ -487,7 +566,8 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, s->cmos_data[RTC_REG_B] =3D data; =20 if (update_periodic_timer) { - periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), + old_period); } =20 check_update_timer(s); @@ -757,7 +837,7 @@ static int rtc_post_load(void *opaque, int version_id) uint64_t now =3D qemu_clock_get_ns(rtc_clock); if (now < s->next_periodic_time || now > (s->next_periodic_time + get_max_clock_jump())) { - periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), 0); } } =20 @@ -822,7 +902,7 @@ static void rtc_notify_clock_reset(Notifier *notifier, = void *data) int64_t now =3D *(int64_t *)data; =20 rtc_set_date_from_host(ISA_DEVICE(s)); - periodic_timer_update(s, now); + periodic_timer_update(s, now, 0); check_update_timer(s); #ifdef TARGET_I386 if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { --=20 2.9.3 From nobody Sat May 4 18:31:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 3/5] mc146818rtc: ensure LOST_TICK_POLICY_SLEW is only enabled on TARGET_I386 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , yunfangtai@tencent.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xiao Guangrong Any tick policy specified on other platforms rather on TARGET_I386 will fall back to LOST_TICK_POLICY_DISCARD silently, this patch makes sure only TARGET_I386 can enable LOST_TICK_POLICY_SLEW After that, we can enable LOST_TICK_POLICY_SLEW in the common code which need not use '#ifdef TARGET_I386' to make these code be x86 specific anymore Signed-off-by: Xiao Guangrong Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/mc146818rtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index dac6744..9810bd5 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -980,19 +980,19 @@ static void rtc_realizefn(DeviceState *dev, Error **e= rrp) =20 rtc_set_date_from_host(isadev); =20 -#ifdef TARGET_I386 switch (s->lost_tick_policy) { +#ifdef TARGET_I386 case LOST_TICK_POLICY_SLEW: s->coalesced_timer =3D timer_new_ns(rtc_clock, rtc_coalesced_timer, s); break; +#endif case LOST_TICK_POLICY_DISCARD: break; default: error_setg(errp, "Invalid lost tick policy."); return; } -#endif =20 s->periodic_timer =3D timer_new_ns(rtc_clock, rtc_periodic_timer, s); s->update_timer =3D timer_new_ns(rtc_clock, rtc_update_timer, s); --=20 2.9.3 From nobody Sat May 4 18:31:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494405323339383.92352635733994; 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Wed, 10 May 2017 01:33:29 -0700 (PDT) From: guangrong.xiao@gmail.com X-Google-Original-From: xiaoguangrong@tencent.com To: pbonzini@redhat.com, mst@redhat.com, mtosatti@redhat.com Date: Wed, 10 May 2017 16:32:58 +0800 Message-Id: <20170510083259.3900-5-xiaoguangrong@tencent.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170510083259.3900-1-xiaoguangrong@tencent.com> References: <20170510083259.3900-1-xiaoguangrong@tencent.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 4/5] mc146818rtc: drop unnecessary '#ifdef TARGET_I386' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , yunfangtai@tencent.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xiao Guangrong If the code purely depends on LOST_TICK_POLICY_SLEW, we can simply drop '#ifdef TARGET_I386' as only x86 can enable this tick policy Signed-off-by: Xiao Guangrong Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/mc146818rtc.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index 9810bd5..104a26d 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -112,7 +112,6 @@ static uint64_t get_guest_rtc_ns(RTCState *s) guest_clock - s->last_update + s->offset; } =20 -#ifdef TARGET_I386 static void rtc_coalesced_timer_update(RTCState *s) { if (s->irq_coalesced =3D=3D 0) { @@ -126,6 +125,7 @@ static void rtc_coalesced_timer_update(RTCState *s) } } =20 +#ifdef TARGET_I386 static void rtc_coalesced_timer(void *opaque) { RTCState *s =3D opaque; @@ -198,7 +198,6 @@ periodic_timer_update(RTCState *s, int64_t current_time= , uint32_t old_period) assert(lost_clock >=3D 0); } =20 -#ifdef TARGET_I386 /* * recalculate the coalesced irqs for two reasons: * a) the lost_clock is more that a period, i,e. the timer @@ -233,9 +232,7 @@ periodic_timer_update(RTCState *s, int64_t current_time= , uint32_t old_period) s->irq_coalesced, old_period, s->period); rtc_coalesced_timer_update(s); } - } else -#endif - { + } else { /* * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW * is not used, we should make the time progress anyway. @@ -250,9 +247,7 @@ periodic_timer_update(RTCState *s, int64_t current_time= , uint32_t old_period) RTC_CLOCK_RATE) + 1; timer_mod(s->periodic_timer, s->next_periodic_time); } else { -#ifdef TARGET_I386 s->irq_coalesced =3D 0; -#endif timer_del(s->periodic_timer); } } @@ -841,13 +836,11 @@ static int rtc_post_load(void *opaque, int version_id) } } =20 -#ifdef TARGET_I386 if (version_id >=3D 2) { if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { rtc_coalesced_timer_update(s); } } -#endif return 0; } =20 @@ -904,11 +897,10 @@ static void rtc_notify_clock_reset(Notifier *notifier= , void *data) rtc_set_date_from_host(ISA_DEVICE(s)); periodic_timer_update(s, now, 0); check_update_timer(s); -#ifdef TARGET_I386 + if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { rtc_coalesced_timer_update(s); } -#endif } =20 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) @@ -929,12 +921,10 @@ static void rtc_reset(void *opaque) =20 qemu_irq_lower(s->irq); =20 -#ifdef TARGET_I386 if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { s->irq_coalesced =3D 0; s->irq_reinject_on_ack_count =3D 0; =09 } -#endif } =20 static const MemoryRegionOps cmos_ops =3D { --=20 2.9.3 From nobody Sat May 4 18:31:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 5/5] mc146818rtc: embrace all x86 specific code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , yunfangtai@tencent.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xiao Guangrong Introduce a function, rtc_policy_slew_deliver_irq(), which delivers irq if LOST_TICK_POLICY_SLEW is used, as which is only supported on x86, other platforms call it will trigger a assert After that, we can move the x86 specific code to the common place Signed-off-by: Xiao Guangrong --- hw/timer/mc146818rtc.c | 60 ++++++++++++++++++++++++++--------------------= ---- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index 104a26d..6d0a610 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -125,17 +125,34 @@ static void rtc_coalesced_timer_update(RTCState *s) } } =20 +static QLIST_HEAD(, RTCState) rtc_devices =3D + QLIST_HEAD_INITIALIZER(rtc_devices); + #ifdef TARGET_I386 +void qmp_rtc_reset_reinjection(Error **errp) +{ + RTCState *s; + + QLIST_FOREACH(s, &rtc_devices, link) { + s->irq_coalesced =3D 0; + } +} + +static bool rtc_policy_slew_deliver_irq(RTCState *s) +{ + apic_reset_irq_delivered(); + qemu_irq_raise(s->irq); + return apic_get_irq_delivered(); +} + static void rtc_coalesced_timer(void *opaque) { RTCState *s =3D opaque; =20 if (s->irq_coalesced !=3D 0) { - apic_reset_irq_delivered(); s->cmos_data[RTC_REG_C] |=3D 0xc0; DPRINTF_C("cmos: injecting from timer\n"); - qemu_irq_raise(s->irq); - if (apic_get_irq_delivered()) { + if (rtc_policy_slew_deliver_irq(s)) { s->irq_coalesced--; DPRINTF_C("cmos: coalesced irqs decreased to %d\n", s->irq_coalesced); @@ -144,6 +161,12 @@ static void rtc_coalesced_timer(void *opaque) =20 rtc_coalesced_timer_update(s); } +#else +static bool rtc_policy_slew_deliver_irq(RTCState *s) +{ + assert(0); + return false; +} #endif =20 static uint32_t rtc_periodic_clock_ticks(RTCState *s) @@ -260,21 +283,17 @@ static void rtc_periodic_timer(void *opaque) s->cmos_data[RTC_REG_C] |=3D REG_C_PF; if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { s->cmos_data[RTC_REG_C] |=3D REG_C_IRQF; -#ifdef TARGET_I386 if (s->lost_tick_policy =3D=3D LOST_TICK_POLICY_SLEW) { if (s->irq_reinject_on_ack_count >=3D RTC_REINJECT_ON_ACK_COUN= T) - s->irq_reinject_on_ack_count =3D 0; =09 - apic_reset_irq_delivered(); - qemu_irq_raise(s->irq); - if (!apic_get_irq_delivered()) { + s->irq_reinject_on_ack_count =3D 0; + if (!rtc_policy_slew_deliver_irq(s)) { s->irq_coalesced++; rtc_coalesced_timer_update(s); DPRINTF_C("cmos: coalesced irqs increased to %d\n", s->irq_coalesced); } } else -#endif - qemu_irq_raise(s->irq); + qemu_irq_raise(s->irq); } } =20 @@ -618,20 +637,6 @@ static void rtc_get_time(RTCState *s, struct tm *tm) rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; } =20 -static QLIST_HEAD(, RTCState) rtc_devices =3D - QLIST_HEAD_INITIALIZER(rtc_devices); - -#ifdef TARGET_I386 -void qmp_rtc_reset_reinjection(Error **errp) -{ - RTCState *s; - - QLIST_FOREACH(s, &rtc_devices, link) { - s->irq_coalesced =3D 0; - } -} -#endif - static void rtc_set_time(RTCState *s) { struct tm tm; @@ -751,22 +756,19 @@ static uint64_t cmos_ioport_read(void *opaque, hwaddr= addr, if (ret & (REG_C_UF | REG_C_AF)) { check_update_timer(s); } -#ifdef TARGET_I386 + if(s->irq_coalesced && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COU= NT) { s->irq_reinject_on_ack_count++; s->cmos_data[RTC_REG_C] |=3D REG_C_IRQF | REG_C_PF; - apic_reset_irq_delivered(); DPRINTF_C("cmos: injecting on ack\n"); - qemu_irq_raise(s->irq); - if (apic_get_irq_delivered()) { + if (rtc_policy_slew_deliver_irq(s)) { s->irq_coalesced--; DPRINTF_C("cmos: coalesced irqs decreased to %d\n", s->irq_coalesced); } } -#endif break; default: ret =3D s->cmos_data[s->cmos_index]; --=20 2.9.3