From nobody Fri May 3 12:24:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494353345519612.0107064906524; Tue, 9 May 2017 11:09:05 -0700 (PDT) Received: from localhost ([::1]:38763 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89ZG-0002MT-VS for importer@patchew.org; Tue, 09 May 2017 14:09:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89Xg-00012f-3e for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d89Xe-0002g7-Q2 for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:24 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:32859) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d89Xe-0002fb-LA for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:22 -0400 Received: by mail-qt0-x241.google.com with SMTP id a46so1002040qte.0 for ; Tue, 09 May 2017 11:07:22 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id w12sm213102qtc.20.2017.05.09.11.07.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 11:07:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=74Pvf32q5aNdiQFL+uFXMb1/k7BcTev+69cVO5MKEiE=; b=LoZZKUK5CeSBPKZYW6ETVosdr99FyNWR4QxoULjoIOdwGqNNQG+6yq4ouAtAivQEsn lbxQY/orKIssnjbIIzmnUl9kOiJhezp+JSqb+fGMVIFVk8I6gTw+5e566HYjUjd1gyly qAtEzNBzt8HBRyC+sR/C0kcjjnxIUdlSPvEhxxYKDYBjpma9PMasFwhl8ezz0y3gS2YO hL1MAPz/5JQg2Cpc1IEDSVPV15EmiAsR1V7EhEIp147RYjtbnc/xrM6ABmzNZELKYKwH TP/s4WEK+qKYlgpmtUJU+VBY3/zqOVX7dg8gfPQlK2wVq/9DzG4s8uRstOMo7h6IfAME r8GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=74Pvf32q5aNdiQFL+uFXMb1/k7BcTev+69cVO5MKEiE=; b=DhHGpr8XVEVVb7B1uWQa9mySqi2KjWNJVFSI0gI4HuHnaxVkGL0WQSDPcCFE1aGbgD ChDtwLfKSXlBhwxqsMVHGhruiJi0uN1dPoQQ+Ff6D2ZUIrNNbWOhb/HdEkTEHr9HLZk3 9VLq1VDgTIPDjqLpPlKQ1DeipQ+ZrA43hv4DPdZql0gtb1n4lS+b8MsmpMo7NywEietY AZ4jSXu3i3E7cFWSBXE7k9nuRhAI48uiJaw5/Ei5b7H8qKoqkFcVSfQa7lKS1w24t3Vg +jf59og07sZaWj+dR6t8UrhaACfZ96vKGJH5wm9ik7b9Pmlti2OH4kcxolh2yZNp9GCH QLuA== X-Gm-Message-State: AODbwcAfzVaOaLk/KkGbyqCXWjhNav5TahjK/E/0rMsgPZSl65QMT8cR LjbzlcwpTUxOu+Qnyp0= X-Received: by 10.200.35.110 with SMTP id b43mr1575043qtb.24.1494353241650; Tue, 09 May 2017 11:07:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 11:07:10 -0700 Message-Id: <20170509180715.22910-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170509180715.22910-1-rth@twiddle.net> References: <20170509180715.22910-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v3 1/6] target/s390x: Implement STORE FACILITIES LIST EXTENDED X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, improve STORE FACILITIES LIST so that we don't hard-code the list for all cpus. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/helper.h | 2 ++ target/s390x/insn-data.def | 2 ++ target/s390x/misc_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/s390x/translate.c | 17 ++++++------- 4 files changed, 72 insertions(+), 8 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 9102071..01adb50 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -83,6 +83,8 @@ DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env,= i32, i64, i64, i64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_RWG, void, env, i64) DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_2(stfle, i32, env, i64) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 075ff59..b6702da 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -747,6 +747,8 @@ C(0xe33e, STRV, RXY_a, Z, la2, r1_32u, new, m1_32, rev32, 0) C(0xe32f, STRVG, RXY_a, Z, la2, r1_o, new, m1_64, rev64, 0) =20 +/* STORE FACILITY LIST EXTENDED */ + C(0xb2b0, STFLE, S, SFLE, 0, a2, 0, 0, stfle, 0) /* STORE FPC */ C(0xb29c, STFPC, S, Z, 0, a2, new, m2_32, efpc, 0) =20 diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index eca8244..bd94242 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -678,3 +678,62 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t a= ddr) } } #endif + +/* The maximum bit defined at the moment is 129. */ +#define MAX_STFL_WORDS 3 + +/* Canonicalize the current cpu's features into the 64-bit words required + by STFLE. Return the index-1 of the max word that is non-zero. */ +static unsigned do_stfle(CPUS390XState *env, uint64_t words[MAX_STFL_WORDS= ]) +{ + S390CPU *cpu =3D s390_env_get_cpu(env); + const unsigned long *features =3D cpu->model->features; + unsigned max_bit =3D 0; + S390Feat feat; + + memset(words, 0, sizeof(uint64_t) * MAX_STFL_WORDS); + + if (test_bit(S390_FEAT_ZARCH, features)) { + /* z/Architecture is always active if around */ + words[0] =3D 1ull << (63 - 2); + } + + for (feat =3D find_first_bit(features, S390_FEAT_MAX); + feat < S390_FEAT_MAX; + feat =3D find_next_bit(features, S390_FEAT_MAX, feat + 1)) { + const S390FeatDef *def =3D s390_feat_def(feat); + if (def->type =3D=3D S390_FEAT_TYPE_STFL) { + unsigned bit =3D def->bit; + if (bit > max_bit) { + max_bit =3D bit; + } + assert(bit / 64 < MAX_STFL_WORDS); + words[bit / 64] |=3D 1ULL << (63 - bit % 64); + } + } + + return max_bit / 64; +} + +void HELPER(stfl)(CPUS390XState *env) +{ + uint64_t words[MAX_STFL_WORDS]; + + do_stfle(env, words); + cpu_stl_data(env, 200, words[0] >> 32); +} + +uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr) +{ + uint64_t words[MAX_STFL_WORDS]; + unsigned count_m1 =3D env->regs[0] & 0xff; + unsigned max_m1 =3D do_stfle(env, words); + unsigned i; + + for (i =3D 0; i <=3D count_m1; ++i) { + cpu_stq_data(env, addr + 8 * i, words[i]); + } + + env->regs[0] =3D deposit64(env->regs[0], 0, 8, max_m1); + return (count_m1 >=3D max_m1 ? 0 : 3); +} diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 01c6217..69940e3 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3628,15 +3628,8 @@ static ExitStatus op_spt(DisasContext *s, DisasOps *= o) =20 static ExitStatus op_stfl(DisasContext *s, DisasOps *o) { - TCGv_i64 f, a; - /* We really ought to have more complete indication of facilities - that we implement. Address this when STFLE is implemented. */ check_privileged(s); - f =3D tcg_const_i64(0xc0000000); - a =3D tcg_const_i64(200); - tcg_gen_qemu_st32(f, a, get_mem_index(s)); - tcg_temp_free_i64(f); - tcg_temp_free_i64(a); + gen_helper_stfl(cpu_env); return NO_EXIT; } =20 @@ -3802,6 +3795,14 @@ static ExitStatus op_sturg(DisasContext *s, DisasOps= *o) } #endif =20 +static ExitStatus op_stfle(DisasContext *s, DisasOps *o) +{ + potential_page_fault(s); + gen_helper_stfle(cc_op, cpu_env, o->in2); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_st8(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s)); --=20 2.9.3 From nobody Fri May 3 12:24:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494353473869675.0138521572186; Tue, 9 May 2017 11:11:13 -0700 (PDT) Received: from localhost ([::1]:38778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89bK-0004sK-IH for importer@patchew.org; Tue, 09 May 2017 14:11:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89Xg-00015F-UD for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d89Xf-0002hZ-PT for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:24 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:32860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d89Xf-0002h0-LT for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:23 -0400 Received: by mail-qt0-x241.google.com with SMTP id a46so1002074qte.0 for ; Tue, 09 May 2017 11:07:23 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id w12sm213102qtc.20.2017.05.09.11.07.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 11:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=qVQkIxN0sRGkzow83YmpumN2aQib2tJGseOAo4+y2ZQ=; b=kL6efUNZB/w8NWUEhuZUlwSa3tU/lk7SwqnEY0x4o7wkklfcihWUFM+v223Oi3FG3e Db9ZFv8AgfIbM2AfOKTFSrHOtFyOCG2cuVUqEwkLyWYCxKQSpXE0kRCnDqzFTqwKAmdT hj3+wFD/IAsujiC55LdJvYLwe2+xiTKaQZl3wGKx8Q3YGuZL3kEY0cBn0HnL+0fQKxBu G93UpAqXubgphdOeEg84DkBxUGA5o+RLHS+muzrV7VSfX2J/dgV1jFc5UyL4CSiszvQs Tpx2nN5Rjqn+FjDEG54YJUdfZ+k9tUFuvPapzDLjgtJbKWr3UdrkQ6YSwh/0FL9K+7Qq LF+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=qVQkIxN0sRGkzow83YmpumN2aQib2tJGseOAo4+y2ZQ=; b=E7ZIn+zkS0/4jqs4g0987qJIlYnktCqUaxNFHnnmIFedyYX0V9ZdalSr5X57yhReHu S2BXOl1TG7fQ+CQ1kMuvjo+UN1ObKxn+GPGttAS9qTgIwIhkIxhh2y/C5sKs3Zb62kEF Qit8dIxTPLKwNhwewhAsIbn0ieLiGT/26gMM/+YrvnnNIuel4dK/KI0FlZO6gfziH/vI UJNX+Lkzppw05oUdeIRaysZRIQOg0Wb+Cdvp/AQ8zXsmYf36R50nKZdppv1tNKS+F8gi 2dsMHpK/oclNymBg2RdY9BT/rel98IIxSG4OKFIQ0kndsWURbTg9q1qR+rWhPDhycJNg uv1w== X-Gm-Message-State: AODbwcBuV4uYTYaTfkoW0cGGt4ZbmaoJTdguUnZX7CihzO5gCD+usMl9 IPLyUQkixZTuQZl+gXg= X-Received: by 10.237.34.41 with SMTP id n38mr1525779qtc.29.1494353243009; Tue, 09 May 2017 11:07:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 11:07:11 -0700 Message-Id: <20170509180715.22910-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170509180715.22910-1-rth@twiddle.net> References: <20170509180715.22910-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v3 2/6] target/s390x: Implement LOAD PROGRAM PARAMETER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Miroslav Benes Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Miroslav Benes Linux arch/s390/kernel/head(64).S uses LPP instruction if it is available in facilities list provided by stfl/stfle instruction. This is the case of newer z/System generations and their qemu definition. The description of LPP is at http://www-01.ibm.com/support/docview.wss?uid=3Disg26fcd1cc32246f4c8852574c= e0044734a Reviewed-by: Aurelien Jarno Signed-off-by: Miroslav Benes Message-Id: <20170227085353.20787-1-mbenes@suse.cz> Signed-off-by: Richard Henderson --- target/s390x/insn-data.def | 2 ++ target/s390x/translate.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index b6702da..43c5707 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -845,6 +845,8 @@ /* LOAD CONTROL */ C(0xb700, LCTL, RS_a, Z, 0, a2, 0, 0, lctl, 0) C(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0) +/* LOAD PROGRAM PARAMETER */ + C(0xb280, LPP, S, LPP, 0, m2_64, 0, 0, lpp, 0) /* LOAD PSW */ C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0) /* LOAD PSW EXTENDED */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 69940e3..2b66a4e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1194,6 +1194,7 @@ typedef enum DisasFacility { FAC_SCF, /* store clock fast */ FAC_SFLE, /* store facility list extended */ FAC_ILA, /* interlocked access facility 1 */ + FAC_LPP, /* load-program-parameter */ } DisasFacility; =20 struct DisasInsn { @@ -2567,6 +2568,14 @@ static ExitStatus op_lra(DisasContext *s, DisasOps *= o) return NO_EXIT; } =20 +static ExitStatus op_lpp(DisasContext *s, DisasOps *o) +{ + check_privileged(s); + + tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp)); + return NO_EXIT; +} + static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) { TCGv_i64 t1, t2; --=20 2.9.3 From nobody Fri May 3 12:24:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494353347820959.8167591640384; Tue, 9 May 2017 11:09:07 -0700 (PDT) Received: from localhost ([::1]:38764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89ZJ-0002P0-Fl for importer@patchew.org; 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Tue, 09 May 2017 11:07:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 11:07:12 -0700 Message-Id: <20170509180715.22910-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170509180715.22910-1-rth@twiddle.net> References: <20170509180715.22910-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v3 3/6] target/s390x: Diagnose specification exception for atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All of the interlocked access facility instructions raise a specification exception for unaligned accesses. Do this by using the (previously unused) unaligned_access hook. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/cpu.c | 1 + target/s390x/cpu.h | 3 +++ target/s390x/helper.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 066dcd1..a1bf2ba 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -430,6 +430,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; + cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 058ddad..bbed320 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -480,6 +480,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, =20 #ifndef CONFIG_USER_ONLY void do_restart_interrupt(CPUS390XState *env); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb, uint8_t *ar) diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 68bd2f9..9978490 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -718,4 +718,20 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) cpu_loop_exit_noexc(cs); } } + +/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + this is only for the atomic operations, for which we want to raise a + specification exception. */ +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + + if (retaddr) { + cpu_restore_state(cs, retaddr); + } + program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER); +} #endif /* CONFIG_USER_ONLY */ --=20 2.9.3 From nobody Fri May 3 12:24:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494353477648860.1068250448117; Tue, 9 May 2017 11:11:17 -0700 (PDT) Received: from localhost ([::1]:38779 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89bQ-0004xF-9E for importer@patchew.org; Tue, 09 May 2017 14:11:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53924) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d89Xj-00017J-Hh for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d89Xi-0002nh-Do for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:27 -0400 Received: from mail-qk0-x229.google.com ([2607:f8b0:400d:c09::229]:33743) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d89Xi-0002mk-AK for qemu-devel@nongnu.org; Tue, 09 May 2017 14:07:26 -0400 Received: by mail-qk0-x229.google.com with SMTP id y201so8248647qka.0 for ; Tue, 09 May 2017 11:07:26 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id w12sm213102qtc.20.2017.05.09.11.07.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 11:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=aTkoRJifqfE+BmekeLe1hGpPsAC+St5Tr4vgFhwHdqY=; b=gMNbHJ5Y+/CEv0WupI4RoklcHaSlwa4Idm2cJHl+kxyY3E5XtTrQ55hc1hAOS0KWgY nRcBKupSRW1RnV9MNQnGnIH3b2pF0Wk27/Wk6O+9tARznn3Ll9InA6WQRMb8nDUvXHMj eCie+pzjl0ve0aYTU0JX7HKPRFnlMOalDZyXUTTXbNBlFho8wGB3u1q2DSh25ZY1azbp pyS7UaKjZfYSvzNqro7WFFwFQk6PZT9VD0dl25bDV0XWHVcO03/jz+V/HtP4DRJIa8hN 0gh7QoyYOZ8cLqvXP3gLb6TSIw1vumMaZy8AYbt1+MhRNPBxxm1fIGQi79DKtf4W4FPC vaEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=aTkoRJifqfE+BmekeLe1hGpPsAC+St5Tr4vgFhwHdqY=; b=ScxIpn1QRM323NKIviuetdJdrQwR1Tp2SrSHZEeLGExm2Sgo4dGNIlkmb4kbh1R06d nlMcsGdZUwJp6usNrpdKOZkblOxngwM0j3xBlXclvgZEKVpls4ODjV7hSEVLAqTsOdYB YihA/2XvqLeIFEETWIMZZVT7fdIqPhu/099q4L+k0tZjuWydS0MyH2QC0NXC0DqPCf2T FLPd22cUnU7CgoVEbCotPv+6+kON1N9uLvvTGisbswVhWcSXVzsyzfFWJivf5Sx8/hpC C+vcz9hS268SSoQhJAJpsCUHOBsqyl4RX+KbMnBf1yRGcSncw9h5/M7ReWNqk0/28KQB t8NQ== X-Gm-Message-State: AODbwcC2NMXGj2PwvvpBGfAp8c2FKM4JSelyASw5Djf1z644x78OaVbj JxCi8Lx0wO7HTJJ7cIE= X-Received: by 10.55.97.76 with SMTP id v73mr1425681qkb.241.1494353245531; Tue, 09 May 2017 11:07:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 11:07:13 -0700 Message-Id: <20170509180715.22910-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170509180715.22910-1-rth@twiddle.net> References: <20170509180715.22910-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::229 Subject: [Qemu-devel] [PATCH v3 4/6] target/s390x: Implement LOAD PAIR DISJOINT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Bischoff Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Bischoff Reviewed-by: Aurelien Jarno Signed-off-by: Eric Bischoff Message-Id: <20170228120134.7921-1-ebischoff@suse.com> [rth: Combine the two via insn->data; free the address temps.] Signed-off-by: Richard Henderson --- target/s390x/insn-data.def | 4 +++- target/s390x/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 43c5707..0909060 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -504,7 +504,9 @@ C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0) C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0) C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0) -/* LOAD PAIR DISJOINT TODO */ +/* LOAD PAIR DISJOINT */ + D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL) + D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ) /* LOAD POSITIVE */ C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32) C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 2b66a4e..8de0177 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2559,6 +2559,7 @@ static ExitStatus op_lctlg(DisasContext *s, DisasOps = *o) tcg_temp_free_i32(r3); return NO_EXIT; } + static ExitStatus op_lra(DisasContext *s, DisasOps *o) { check_privileged(s); @@ -2759,6 +2760,31 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps = *o) return NO_EXIT; } =20 +static ExitStatus op_lpd(DisasContext *s, DisasOps *o) +{ + TCGv_i64 a1, a2; + TCGMemOp mop =3D s->insn->data; + + /* In a parallel context, stop the world and single step. */ + if (parallel_cpus) { + potential_page_fault(s); + gen_helper_exit_atomic(cpu_env); + return EXIT_NORETURN; + } + + /* In a serial context, perform the two loads ... */ + a1 =3D get_address(s, 0, get_field(s->fields, b1), get_field(s->fields= , d1)); + a2 =3D get_address(s, 0, get_field(s->fields, b2), get_field(s->fields= , d2)); + tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN); + tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN); + tcg_temp_free_i64(a1); + tcg_temp_free_i64(a2); + + /* ... and indicate that we performed them while interlocked. */ + gen_op_movi_cc(s, 0); + return NO_EXIT; +} + #ifndef CONFIG_USER_ONLY static ExitStatus op_lura(DisasContext *s, DisasOps *o) { @@ -4430,6 +4456,22 @@ static void wout_r1_D32(DisasContext *s, DisasFields= *f, DisasOps *o) } #define SPEC_wout_r1_D32 SPEC_r1_even =20 +static void wout_r3_P32(DisasContext *s, DisasFields *f, DisasOps *o) +{ + int r3 =3D get_field(f, r3); + store_reg32_i64(r3, o->out); + store_reg32_i64(r3 + 1, o->out2); +} +#define SPEC_wout_r3_P32 SPEC_r3_even + +static void wout_r3_P64(DisasContext *s, DisasFields *f, DisasOps *o) +{ + int r3 =3D get_field(f, r3); + store_reg(r3, o->out); + store_reg(r3 + 1, o->out2); +} +#define SPEC_wout_r3_P64 SPEC_r3_even + static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o) { store_freg32_i64(get_field(f, r1), o->out); --=20 2.9.3 From nobody Fri May 3 12:24:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v3 5/6] target/s390x: Use atomic operations for COMPARE SWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 10 +++--- target/s390x/mem_helper.c | 39 ++++++++++++++++++++++ target/s390x/translate.c | 83 ++++++++----------------------------------= ---- 4 files changed, 59 insertions(+), 74 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 01adb50..0b70770 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -25,6 +25,7 @@ DEF_HELPER_3(cxgb, i64, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 0909060..5e5fcc5 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -239,12 +239,12 @@ D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1) =20 /* COMPARE AND SWAP */ - D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, 0) - D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, 0) - D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, 1) + D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_T= EUL) + D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_T= EUL) + D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_TEQ) /* COMPARE DOUBLE AND SWAP */ - D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, 1) - D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, 1) + D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEQ) + D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEQ) C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) =20 /* COMPARE AND TRAP */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 675aba2..c74ded3 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -844,6 +844,45 @@ uint32_t HELPER(trt)(CPUS390XState *env, uint32_t len,= uint64_t array, return cc; } =20 +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + uintptr_t ra =3D GETPC(); + Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); + Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + int mem_idx =3D cpu_mmu_index(env, false); + Int128 oldv; + bool fail; + + if (parallel_cpus) { +#ifndef CONFIG_ATOMIC128 + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); +#else + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); + fail =3D !int128_eq(oldv, cmpv); +#endif + } else { + uint64_t oldh, oldl; + + oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); + oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); + + oldv =3D int128_make128(oldl, oldh); + fail =3D !int128_eq(oldv, cmpv); + if (fail) { + newv =3D oldv; + } + + cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); + cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + } + + env->cc_op =3D fail; + env->regs[r1] =3D int128_gethi(oldv); + env->regs[r1 + 1] =3D int128_getlo(oldv); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 8de0177..ec250bb 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1943,102 +1943,47 @@ static ExitStatus op_cps(DisasContext *s, DisasOps= *o) =20 static ExitStatus op_cs(DisasContext *s, DisasOps *o) { - /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */ int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); - int is_64 =3D s->insn->data; - TCGv_i64 addr, mem, cc, z; + TCGv_i64 addr, cc; =20 /* Note that in1 =3D R3 (new value) and in2 =3D (zero-extended) R1 (expected value). */ =20 - /* Load the memory into the (temporary) output. While the PoO only ta= lks - about moving the memory to R1 on inequality, if we include equality= it - means that R1 is equal to the memory in all conditions. */ addr =3D get_address(s, 0, b2, d2); - if (is_64) { - tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s)); - } else { - tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s)); - } + tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, + get_mem_index(s), s->insn->data | MO_ALIGN); + tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? Note that this setco= nd produces the output CC value, thus the NE sense of the test. */ cc =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); - - /* If the memory and expected values are equal (CC=3D=3D0), copy R3 to= MEM. - Recall that we are allowed to unconditionally issue the store (and - thus any possible write trap), so (re-)store the original contents - of MEM in case of inequality. */ - z =3D tcg_const_i64(0); - mem =3D tcg_temp_new_i64(); - tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out); - if (is_64) { - tcg_gen_qemu_st64(mem, addr, get_mem_index(s)); - } else { - tcg_gen_qemu_st32(mem, addr, get_mem_index(s)); - } - tcg_temp_free_i64(z); - tcg_temp_free_i64(mem); - tcg_temp_free_i64(addr); - - /* Store CC back to cc_op. Wait until after the store so that any - exception gets the old cc_op value. */ tcg_gen_extrl_i64_i32(cc_op, cc); tcg_temp_free_i64(cc); set_cc_static(s); + return NO_EXIT; } =20 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o) { - /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */ int r1 =3D get_field(s->fields, r1); int r3 =3D get_field(s->fields, r3); int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); - TCGv_i64 addrh, addrl, memh, meml, outh, outl, cc, z; + TCGv_i64 addr; + TCGv_i32 t_r1, t_r3; =20 /* Note that R1:R1+1 =3D expected value and R3:R3+1 =3D new value. */ + addr =3D get_address(s, 0, b2, d2); + t_r1 =3D tcg_const_i32(r1); + t_r3 =3D tcg_const_i32(r3); + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + tcg_temp_free_i64(addr); + tcg_temp_free_i32(t_r1); + tcg_temp_free_i32(t_r3); =20 - addrh =3D get_address(s, 0, b2, d2); - addrl =3D get_address(s, 0, b2, d2 + 8); - outh =3D tcg_temp_new_i64(); - outl =3D tcg_temp_new_i64(); - - tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s)); - tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s)); - - /* Fold the double-word compare with arithmetic. */ - cc =3D tcg_temp_new_i64(); - z =3D tcg_temp_new_i64(); - tcg_gen_xor_i64(cc, outh, regs[r1]); - tcg_gen_xor_i64(z, outl, regs[r1 + 1]); - tcg_gen_or_i64(cc, cc, z); - tcg_gen_movi_i64(z, 0); - tcg_gen_setcond_i64(TCG_COND_NE, cc, cc, z); - - memh =3D tcg_temp_new_i64(); - meml =3D tcg_temp_new_i64(); - tcg_gen_movcond_i64(TCG_COND_EQ, memh, cc, z, regs[r3], outh); - tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl); - tcg_temp_free_i64(z); - - tcg_gen_qemu_st64(memh, addrh, get_mem_index(s)); - tcg_gen_qemu_st64(meml, addrl, get_mem_index(s)); - tcg_temp_free_i64(memh); - tcg_temp_free_i64(meml); - tcg_temp_free_i64(addrh); - tcg_temp_free_i64(addrl); - - /* Save back state now that we've passed all exceptions. */ - tcg_gen_mov_i64(regs[r1], outh); - tcg_gen_mov_i64(regs[r1 + 1], outl); - tcg_gen_extrl_i64_i32(cc_op, cc); - tcg_temp_free_i64(outh); - tcg_temp_free_i64(outl); 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Tue, 09 May 2017 11:07:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 11:07:15 -0700 Message-Id: <20170509180715.22910-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170509180715.22910-1-rth@twiddle.net> References: <20170509180715.22910-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v3 6/6] target/s390x: Use atomic operations for LOAD AND OP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/insn-data.def | 20 ++++++------ target/s390x/translate.c | 78 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 60 insertions(+), 38 deletions(-) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 5e5fcc5..55a7c52 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -390,20 +390,20 @@ /* LOAD ADDRESS RELATIVE LONG */ C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0) /* LOAD AND ADD */ - C(0xebf8, LAA, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_at= omic, add, adds32) - C(0xebe8, LAAG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic,= add, adds64) + D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32= , MO_TESL) + D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TE= Q) /* LOAD AND ADD LOGICAL */ - C(0xebfa, LAAL, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_at= omic, add, addu32) - C(0xebea, LAALG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic,= add, addu64) + D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32= , MO_TEUL) + D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa, addu64, MO_TE= Q) /* LOAD AND AND */ - C(0xebf4, LAN, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_at= omic, and, nz32) - C(0xebe4, LANG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic,= and, nz64) + D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, = MO_TESL) + D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEQ) /* LOAD AND EXCLUSIVE OR */ - C(0xebf7, LAX, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_at= omic, xor, nz32) - C(0xebe7, LAXG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic,= xor, nz64) + D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, = MO_TESL) + D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEQ) /* LOAD AND OR */ - C(0xebf6, LAO, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_at= omic, or, nz32) - C(0xebe6, LAOG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic,= or, nz64) + D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, = MO_TESL) + D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEQ) /* LOAD AND TEST */ C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32) C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index ec250bb..f738c7b 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2309,6 +2309,50 @@ static ExitStatus op_iske(DisasContext *s, DisasOps = *o) } #endif =20 +static ExitStatus op_laa(DisasContext *s, DisasOps *o) +{ + /* The real output is indeed the original value in memory; + recompute the addition for the computation of CC. */ + tcg_gen_atomic_fetch_add_i64(o->in2, o->in2, o->in1, get_mem_index(s), + s->insn->data | MO_ALIGN); + /* However, we need to recompute the addition for setting CC. */ + tcg_gen_add_i64(o->out, o->in1, o->in2); + return NO_EXIT; +} + +static ExitStatus op_lan(DisasContext *s, DisasOps *o) +{ + /* The real output is indeed the original value in memory; + recompute the addition for the computation of CC. */ + tcg_gen_atomic_fetch_and_i64(o->in2, o->in2, o->in1, get_mem_index(s), + s->insn->data | MO_ALIGN); + /* However, we need to recompute the operation for setting CC. */ + tcg_gen_and_i64(o->out, o->in1, o->in2); + return NO_EXIT; +} + +static ExitStatus op_lao(DisasContext *s, DisasOps *o) +{ + /* The real output is indeed the original value in memory; + recompute the addition for the computation of CC. */ + tcg_gen_atomic_fetch_or_i64(o->in2, o->in2, o->in1, get_mem_index(s), + s->insn->data | MO_ALIGN); + /* However, we need to recompute the operation for setting CC. */ + tcg_gen_or_i64(o->out, o->in1, o->in2); + return NO_EXIT; +} + +static ExitStatus op_lax(DisasContext *s, DisasOps *o) +{ + /* The real output is indeed the original value in memory; + recompute the addition for the computation of CC. */ + tcg_gen_atomic_fetch_xor_i64(o->in2, o->in2, o->in1, get_mem_index(s), + s->insn->data | MO_ALIGN); + /* However, we need to recompute the operation for setting CC. */ + tcg_gen_xor_i64(o->out, o->in1, o->in2); + return NO_EXIT; +} + static ExitStatus op_ldeb(DisasContext *s, DisasOps *o) { gen_helper_ldeb(o->out, cpu_env, o->in2); @@ -4483,21 +4527,17 @@ static void wout_m2_32(DisasContext *s, DisasFields= *f, DisasOps *o) } #define SPEC_wout_m2_32 0 =20 -static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, DisasOps= *o) +static void wout_in2_r1(DisasContext *s, DisasFields *f, DisasOps *o) { - /* XXX release reservation */ - tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); - store_reg32_i64(get_field(f, r1), o->in2); + store_reg(get_field(f, r1), o->in2); } -#define SPEC_wout_m2_32_r1_atomic 0 +#define SPEC_wout_in2_r1 0 =20 -static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, DisasOps= *o) +static void wout_in2_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) { - /* XXX release reservation */ - tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); - store_reg(get_field(f, r1), o->in2); + store_reg32_i64(get_field(f, r1), o->in2); } -#define SPEC_wout_m2_64_r1_atomic 0 +#define SPEC_wout_in2_r1_32 0 =20 /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* The "INput 1" generators. These load the first operand to an insn. */ @@ -4941,24 +4981,6 @@ static void in2_mri2_64(DisasContext *s, DisasFields= *f, DisasOps *o) } #define SPEC_in2_mri2_64 0 =20 -static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o) -{ - /* XXX should reserve the address */ - in1_la2(s, f, o); - o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s)); -} -#define SPEC_in2_m2_32s_atomic 0 - -static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o) -{ - /* XXX should reserve the address */ - in1_la2(s, f, o); - o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s)); -} -#define SPEC_in2_m2_64_atomic 0 - static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o) { o->in2 =3D tcg_const_i64(get_field(f, i2)); --=20 2.9.3