[Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage

P J P posted 4 patches 7 years, 1 month ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20170214185225.7994-1-ppandit@redhat.com
Test checkpatch passed
Test docker passed
Test s390x passed
hw/sd/sdhci.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
[Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage
Posted by P J P 7 years, 1 month ago
From: Prasad J Pandit <pjp@fedoraproject.org>

Hello,

In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
register is used to control 's->blkcnt' value. This bit is not relevant
in single block transfers. Also, Transfer Mode register value could be
set such that 's->blkcnt' would not see an update during multi block
transfers. Thus leading to an infinite loop.

This patch set attempts to correct 'Block Count Enable' bit usage.

This series incorporates changes suggested in patch set v3:
  -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02376.html
  -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02905.html

Thank you.
--
Prasad J Pandit (4):
  sd: sdhci: mask transfer mode register value
  sd: sdhci: check transfer mode register in multi block transfer
  sd: sdhci: conditionally invoke multi block transfer
  sd: sdhci: Remove block count enable check in single block transfers

 hw/sd/sdhci.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

-- 
2.9.3

Re: [Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage
Posted by Peter Maydell 7 years, 1 month ago
On 14 February 2017 at 18:52, P J P <ppandit@redhat.com> wrote:
> From: Prasad J Pandit <pjp@fedoraproject.org>
>
> Hello,
>
> In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
> register is used to control 's->blkcnt' value. This bit is not relevant
> in single block transfers. Also, Transfer Mode register value could be
> set such that 's->blkcnt' would not see an update during multi block
> transfers. Thus leading to an infinite loop.
>
> This patch set attempts to correct 'Block Count Enable' bit usage.
>
> This series incorporates changes suggested in patch set v3:
>   -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02376.html
>   -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02905.html

I've gone back through the mail archives for previous versions of
this series, and I think that we just need review for patch 4 now?

thanks
-- PMM

Re: [Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage
Posted by Alistair Francis 7 years, 1 month ago
On Fri, Feb 17, 2017 at 5:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 14 February 2017 at 18:52, P J P <ppandit@redhat.com> wrote:
>> From: Prasad J Pandit <pjp@fedoraproject.org>
>>
>> Hello,
>>
>> In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
>> register is used to control 's->blkcnt' value. This bit is not relevant
>> in single block transfers. Also, Transfer Mode register value could be
>> set such that 's->blkcnt' would not see an update during multi block
>> transfers. Thus leading to an infinite loop.
>>
>> This patch set attempts to correct 'Block Count Enable' bit usage.
>>
>> This series incorporates changes suggested in patch set v3:
>>   -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02376.html
>>   -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02905.html
>
> I've gone back through the mail archives for previous versions of
> this series, and I think that we just need review for patch 4 now?

Thanks Peter, I thought I had reviewed all of them.

I just reviewed patch 4, these should be good to go now then.

Thanks,

Alistair

>
> thanks
> -- PMM