Hi Richard/Peter,

This is a mostly ARM focused update to last weeks v9.

It has necessitated one change to the cputlb API. It was pointed out
that translators often have to special case a bunch of things if you
longjmp() out of a helper. As a result the cputlb _synched() calls are
no longer QEMU_NORETURN but do document the importance of the guest to
exit the block as soon as synchronisation is required. In ARM's case
this is already done as the TLB flushes are treated as CP write
operation which ends the block by default. This means I was able to
drop the two patches that dealt with ARM_CP_PC, simplifying the code.

The other moderate change was fixing up target-arm/powerctl to
properly model the ON_PENDING powerstate which is key to vCPUs
handling otherwise race-prone start-up sequences. The power off and
reset methods where also updated to update the CPUState structures in
the targets context.

Otherwise there is the usual array of review tags and a few minor
fixes documented as normal bellow the --- line.

A version of the tree can be found at:

  https://github.com/stsquad/qemu/tree/mttcg/base-patches-v10

Cheers,

Alex

Alex Bennée (17):
  docs: new design document multi-thread-tcg.txt
  tcg: move TCG_MO/BAR types into own file
  tcg: add kick timer for single-threaded vCPU emulation
  tcg: rename tcg_current_cpu to tcg_current_rr_cpu
  tcg: remove global exit_request
  tcg: enable tb_lock() for SoftMMU
  tcg: enable thread-per-vCPU
  cputlb: add assert_cpu_is_self checks
  cputlb: tweak qemu_ram_addr_from_host_nofail reporting
  cputlb and arm/sparc targets: convert mmuidx flushes from varg to
    bitmap
  cputlb: add tlb_flush_by_mmuidx async routines
  cputlb: atomically update tlb fields used by tlb_reset_dirty
  cputlb: introduce tlb_flush_*_all_cpus[_synced]
  target-arm/powerctl: defer cpu reset work to CPU context
  target-arm: don't generate WFE/YIELD calls for MTTCG
  target-arm: ensure all cross vCPUs TLB flushes complete
  tcg: enable MTTCG by default for ARM on x86 hosts

Jan Kiszka (1):
  tcg: drop global lock during TCG code execution

KONRAD Frederic (2):
  tcg: add options for enabling MTTCG
  cputlb: introduce tlb_flush_* async work.

Pranith Kumar (3):
  mttcg: translate-all: Enable locking debug in a debug build
  mttcg: Add missing tb_lock/unlock() in cpu_exec_step()
  tcg: handle EXCP_ATOMIC exception for system emulation

 configure                  |   6 +
 cpu-exec-common.c          |   3 -
 cpu-exec.c                 |  41 ++--
 cpus.c                     | 343 ++++++++++++++++++++++++++-------
 cputlb.c                   | 463 +++++++++++++++++++++++++++++++++++++--------
 docs/multi-thread-tcg.txt  | 350 ++++++++++++++++++++++++++++++++++
 exec.c                     |  12 +-
 hw/core/irq.c              |   1 +
 hw/i386/kvmvapic.c         |   4 +-
 hw/intc/arm_gicv3_cpuif.c  |   3 +
 hw/ppc/ppc.c               |  16 +-
 hw/ppc/spapr.c             |   3 +
 include/exec/cputlb.h      |   2 -
 include/exec/exec-all.h    | 132 +++++++++++--
 include/qom/cpu.h          |  16 ++
 include/sysemu/cpus.h      |   2 +
 memory.c                   |   2 +
 qemu-options.hx            |  20 ++
 qom/cpu.c                  |  10 +
 target/arm/arm-powerctl.c  | 192 ++++++++++++-------
 target/arm/arm-powerctl.h  |   2 +
 target/arm/cpu.h           |  13 +-
 target/arm/helper.c        | 219 ++++++++++-----------
 target/arm/op_helper.c     |  50 ++++-
 target/arm/translate-a64.c |   8 +-
 target/arm/translate.c     |  20 +-
 target/i386/smm_helper.c   |   7 +
 target/s390x/misc_helper.c |   5 +-
 target/sparc/ldst_helper.c |   8 +-
 tcg/i386/tcg-target.h      |  11 ++
 tcg/tcg-mo.h               |  48 +++++
 tcg/tcg.h                  |  27 +--
 translate-all.c            |  66 ++-----
 translate-common.c         |  21 +-
 vl.c                       |  49 ++++-
 35 files changed, 1730 insertions(+), 445 deletions(-)
 create mode 100644 docs/multi-thread-tcg.txt
 create mode 100644 tcg/tcg-mo.h

-- 
2.11.0

Hi Alex,

On Mon, Feb 6, 2017 at 10:30 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
> Hi Richard/Peter,
>
> This is a mostly ARM focused update to last weeks v9.
>
> It has necessitated one change to the cputlb API. It was pointed out
> that translators often have to special case a bunch of things if you
> longjmp() out of a helper. As a result the cputlb _synched() calls are
> no longer QEMU_NORETURN but do document the importance of the guest to
> exit the block as soon as synchronisation is required. In ARM's case
> this is already done as the TLB flushes are treated as CP write
> operation which ends the block by default. This means I was able to
> drop the two patches that dealt with ARM_CP_PC, simplifying the code.
>
> The other moderate change was fixing up target-arm/powerctl to
> properly model the ON_PENDING powerstate which is key to vCPUs
> handling otherwise race-prone start-up sequences. The power off and
> reset methods where also updated to update the CPUState structures in
> the targets context.
>
> Otherwise there is the usual array of review tags and a few minor
> fixes documented as normal bellow the --- line.
>
> A version of the tree can be found at:
>
>   https://github.com/stsquad/qemu/tree/mttcg/base-patches-v10
>

I've sent my Reviewed-by/tested-by for v9 but those seem to be lost.
I've tested v10 too.

So please add my tested and reviewed tags:

Tested-and-Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>

Thanks,
-- 
Pranith

On 02/06/2017 01:06 PM, Pranith Kumar wrote:

>> A version of the tree can be found at:
>>
>>   https://github.com/stsquad/qemu/tree/mttcg/base-patches-v10
>>
> 
> I've sent my Reviewed-by/tested-by for v9 but those seem to be lost.
> I've tested v10 too.
> 
> So please add my tested and reviewed tags:
> 
> Tested-and-Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>

I don't know if all the tools honor this spelling; but if it were me,
I'd assume it is better to split it into two lines, one for Tested-by:
and the other for Reviewed-by:

-- 
Eric Blake   eblake redhat com    +1-919-301-3266
Libvirt virtualization library http://libvirt.org

Pranith Kumar <bobby.prani@gmail.com> writes:

> Hi Alex,
>
> On Mon, Feb 6, 2017 at 10:30 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>> Hi Richard/Peter,
>>
>> This is a mostly ARM focused update to last weeks v9.
>>
>> It has necessitated one change to the cputlb API. It was pointed out
>> that translators often have to special case a bunch of things if you
>> longjmp() out of a helper. As a result the cputlb _synched() calls are
>> no longer QEMU_NORETURN but do document the importance of the guest to
>> exit the block as soon as synchronisation is required. In ARM's case
>> this is already done as the TLB flushes are treated as CP write
>> operation which ends the block by default. This means I was able to
>> drop the two patches that dealt with ARM_CP_PC, simplifying the code.
>>
>> The other moderate change was fixing up target-arm/powerctl to
>> properly model the ON_PENDING powerstate which is key to vCPUs
>> handling otherwise race-prone start-up sequences. The power off and
>> reset methods where also updated to update the CPUState structures in
>> the targets context.
>>
>> Otherwise there is the usual array of review tags and a few minor
>> fixes documented as normal bellow the --- line.
>>
>> A version of the tree can be found at:
>>
>>   https://github.com/stsquad/qemu/tree/mttcg/base-patches-v10
>>
>
> I've sent my Reviewed-by/tested-by for v9 but those seem to be lost.
> I've tested v10 too.
>
> So please add my tested and reviewed tags:
>
> Tested-and-Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>

Sorry I missed that as it was applied to the cover letter (everyone
keeps finding corner cases for my tooling ;-). I'll apply it to patch 23
where we default on.

>
> Thanks,


--
Alex Bennée