From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152969972963631.06961482266172; Fri, 22 Jun 2018 13:35:29 -0700 (PDT) Received: from localhost ([::1]:36076 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSmG-0003nA-OR for importer@patchew.org; Fri, 22 Jun 2018 16:35:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjb-00026f-82 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjZ-0005QJ-MJ for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45100) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjV-0005Ou-0V; Fri, 22 Jun 2018 16:32:37 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1B31060B13; Fri, 22 Jun 2018 20:32:36 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A16F76063F; Fri, 22 Jun 2018 20:32:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699556; bh=InCWDuIij7WtZxZkLbiWmWFvCgJSfZZgl3ZVKcb3qpg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JH5uLBgxPclpcqCdK+u869EGUZOlDNtOUGlbVdiTZptDf3Wa6XcrWQLX4kq8Pc6Iv deodsSPbs7DObckvCT0aToq4/fruWN/et68/8LjvQeQTG7qimdpYxRKMITuyFIVux5 PYRpQjfSu8AW0wbNRhsz2YF5vDvyJGAxHm7CpnqE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699555; bh=InCWDuIij7WtZxZkLbiWmWFvCgJSfZZgl3ZVKcb3qpg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NqBY7AZf/vaRlo4E6mGxdz3vcrtwrb3FgE8XctZGxfKVNHbCA02NKJEspVAiNALMz oiGK7GtjSVWyRlXrMolTXYl7DVRO9RfRUkL+Y7adV3gnqiqbi3bTGcEaAfUdR3kpr4 e4ssbzpIAYa5PwKwWK/2SsIDyMoY3ltA9MbQUdgE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A16F76063F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:15 -0400 Message-Id: <1529699547-17044-2-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensure time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 28 ++++++++++----- target/arm/helper.c | 100 ++++++++++++++++++++++++++++--------------------= ---- 2 files changed, 73 insertions(+), 55 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8488273..ba2c876 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -467,10 +467,20 @@ typedef struct CPUARMState { uint64_t oslsr_el1; /* OS Lock Status */ uint64_t mdcr_el2; uint64_t mdcr_el3; - /* If the counter is enabled, this stores the last time the counter - * was reset. Otherwise it stores the counter value + /* Stores the architectural value of the counter *the last time it= was + * updated* by pmccntr_op_start. Accesses should always be surroun= ded + * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest + * architecturally-corect value is being read/set. */ uint64_t c15_ccnt; + /* Stores the delta between the architectural value and the underl= ying + * cycle count during normal operation. It is used to update c15_c= cnt + * to be the correct architectural value before accesses. During + * accesses, c15_ccnt_delta contains the underlying count being us= ed + * for the access, after which it reverts to the delta value in + * pmccntr_op_finish. + */ + uint64_t c15_ccnt_delta; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ @@ -924,15 +934,17 @@ int cpu_arm_signal_handler(int host_signum, void *pin= fo, void *puc); =20 /** - * pmccntr_sync + * pmccntr_op_start/finish * @env: CPUARMState * - * Synchronises the counter in the PMCCNTR. This must always be called twi= ce, - * once before any action that might affect the timer and again afterwards. - * The function is used to swap the state of the register if required. - * This only happens when not in user mode (!CONFIG_USER_ONLY) + * Convert the counter in the PMCCNTR between its delta form (the typical = mode + * when it's enabled) and the guest-visible value. These two calls must al= ways + * surround any action which might affect the counter, and the return value + * from pmccntr_op_start must be supplied as the second argument to + * pmccntr_op_finish. */ -void pmccntr_sync(CPUARMState *env); +void pmccntr_op_start(CPUARMState *env); +void pmccntr_op_finish(CPUARMState *env); =20 /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants diff --git a/target/arm/helper.c b/target/arm/helper.c index 1248d84..23b3a16 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1044,28 +1044,53 @@ static inline bool arm_ccnt_enabled(CPUARMState *en= v) =20 return true; } - -void pmccntr_sync(CPUARMState *env) +/* + * Ensure c15_ccnt is the guest-visible count so that operations such as + * enabling/disabling the counter or filtering, modifying the count itself, + * etc. can be done logically. This is essentially a no-op if the counter = is + * not enabled at the time of the call. + */ +void pmccntr_op_start(CPUARMState *env) { - uint64_t temp_ticks; - - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + uint64_t cycles =3D 0; + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); =20 - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /=3D 64; - } - if (arm_ccnt_enabled(env)) { - env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; + uint64_t eff_cycles =3D cycles; + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + eff_cycles /=3D 64; + } + + env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; + } + env->cp15.c15_ccnt_delta =3D cycles; +} + +/* + * If PMCCNTR is enabled, recalculate the delta between the clock and the + * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to + * pmccntr_op_start. + */ +void pmccntr_op_finish(CPUARMState *env) +{ + if (arm_ccnt_enabled(env)) { + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + prev_cycles /=3D 64; + } + + env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } =20 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + pmccntr_op_start(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1076,26 +1101,16 @@ static void pmcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_sync(env); + pmccntr_op_finish(env); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, do not change value */ - return env->cp15.c15_ccnt; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - return total_ticks - env->cp15.c15_ccnt; + uint64_t ret; + pmccntr_op_start(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_op_finish(env); + return ret; } =20 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1112,22 +1127,9 @@ static void pmselr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, set the absolute value */ - env->cp15.c15_ccnt =3D value; - return; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - env->cp15.c15_ccnt =3D total_ticks - value; + pmccntr_op_start(env); + env->cp15.c15_ccnt =3D value; + pmccntr_op_finish(env); } =20 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1140,7 +1142,11 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, =20 #else /* CONFIG_USER_ONLY */ =20 -void pmccntr_sync(CPUARMState *env) +void pmccntr_op_start(CPUARMState *env) +{ +} + +void pmccntr_op_finish(CPUARMState *env) { } =20 @@ -1149,9 +1155,9 @@ void pmccntr_sync(CPUARMState *env) static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + pmccntr_op_start(env); env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; - pmccntr_sync(env); + pmccntr_op_finish(env); } =20 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529699870996440.46341625174375; Fri, 22 Jun 2018 13:37:50 -0700 (PDT) Received: from localhost ([::1]:36099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSoU-0005uk-5s for importer@patchew.org; Fri, 22 Jun 2018 16:37:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54278) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjb-00027O-US for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSja-0005Qk-Fx for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45212) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjW-0005PE-Qk; Fri, 22 Jun 2018 16:32:39 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E47DE60588; Fri, 22 Jun 2018 20:32:37 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C6EF760791; Fri, 22 Jun 2018 20:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699557; bh=kXuiWLwCGd8bfvAj9kqx2u3EggzImNyYC3Mp7UNH7PQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lk5nKgBSxcBEiYB7Wm4aRhhmJ8ajj+21FuX1JmIf12hPHoz1xVxkZwFJPSKm/EnQZ XEYjOXAqIIVYh9Or29ePT558dqkNvsNQDTi6b7Uk4xmv/nBix9Rt1zbCBZdB0aE1CA +EH/rXZ1j8Fy3LNJ5BS/v2BolS40e0hLUd3MyQd4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699556; bh=kXuiWLwCGd8bfvAj9kqx2u3EggzImNyYC3Mp7UNH7PQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pt31U8QuANhHUOAiTlHQlzxfyxtvPiyVZAGYBRx7hsRUrupoSbPu4wnjw8ZbhGmYI BjSKRzDseeziNhIcq8/XuoaFIH/ose/9aBLVWVsLek7ZT296d5t41oj4kDb+mWCZ4N DMptwO5+QdY6ShC8dFtG2t5NxwBrEgGnsj3IxgXs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C6EF760791 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:16 -0400 Message-Id: <1529699547-17044-3-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 02/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pmu_counter_enabled and pmu_op_start/finish functions are generic (as opposed to PMCCNTR-specific) to allow for the implementation of other events. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.c | 3 ++ target/arm/cpu.h | 22 +++++++++- target/arm/helper.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- 3 files changed, 129 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e1de45e..08ce1bc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -916,6 +916,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &=3D ~0xf00; + } else if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba2c876..800c4ec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -946,6 +946,24 @@ int cpu_arm_signal_handler(int host_signum, void *pinf= o, void pmccntr_op_start(CPUARMState *env); void pmccntr_op_finish(CPUARMState *env); =20 +/** + * pmu_op_start/finish + * @env: CPUARMState + * + * Convert all PMU counters between their delta form (the typical mode when + * they are enabled) and the guest-visible values. These two calls must + * surround any action which might affect the counters, and the return val= ue + * from pmu_op_start must be supplied as the second argument to pmu_op_fin= ish. + */ +void pmu_op_start(CPUARMState *env); +void pmu_op_finish(CPUARMState *env); + +/** + * Functions to register as EL change hooks for PMU mode filtering + */ +void pmu_pre_el_change(ARMCPU *cpu, void *ignored); +void pmu_post_el_change(ARMCPU *cpu, void *ignored); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those @@ -1007,7 +1025,8 @@ void pmccntr_op_finish(CPUARMState *env); =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) -#define MDCR_SPME (1U << 17) +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) #define MDCR_SPD (3U << 14) #define MDCR_TDRA (1U << 11) @@ -1017,6 +1036,7 @@ void pmccntr_op_finish(CPUARMState *env); #define MDCR_HPME (1U << 7) #define MDCR_TPM (1U << 6) #define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) =20 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) diff --git a/target/arm/helper.c b/target/arm/helper.c index 23b3a16..7c66977 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -935,10 +935,20 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRE 0x1 =20 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x000003ff + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1034,16 +1044,66 @@ static CPAccessResult pmreg_access_ccntr(CPUARMStat= e *env, return pmreg_access(env, ri, isread); } =20 -static inline bool arm_ccnt_enabled(CPUARMState *env) +/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing + * the current EL, security state, and register configuration. + */ +static inline bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { - /* This does not support checking PMCCFILTR_EL0 register */ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited, filtered; + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + uint8_t hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; =20 - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { - return false; + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter =3D=3D 31)) { + e =3D env->cp15.c9_pmcr & PMCRE; + } else { + e =3D env->cp15.mdcr_el2 & MDCR_HPME; + } + enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); + + if (!secure) { + if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { + prohibited =3D env->cp15.mdcr_el2 & MDCR_HPMD; + } else { + prohibited =3D false; + } + } else { + prohibited =3D arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.mdcr_el3 & MDCR_SPME); } =20 - return true; + if (prohibited && counter =3D=3D 31) { + prohibited =3D env->cp15.c9_pmcr & PMCRDP; + } + + /* TODO Remove assert, set filter to correct PMEVTYPER */ + assert(counter =3D=3D 31); + filter =3D env->cp15.pmccfiltr_el0; + + p =3D filter & PMXEVTYPER_P; + u =3D filter & PMXEVTYPER_U; + nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m =3D arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el =3D=3D 0) { + filtered =3D secure ? u : u !=3D nsu; + } else if (el =3D=3D 1) { + filtered =3D secure ? p : p !=3D nsk; + } else if (el =3D=3D 2) { + filtered =3D !nsh; + } else { /* EL3 */ + filtered =3D m !=3D p; + } + + return enabled && !prohibited && !filtered; } + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1056,7 +1116,7 @@ void pmccntr_op_start(CPUARMState *env) cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); =20 - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -1075,7 +1135,7 @@ void pmccntr_op_start(CPUARMState *env) */ void pmccntr_op_finish(CPUARMState *env) { - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; =20 if (env->cp15.c9_pmcr & PMCRD) { @@ -1087,10 +1147,30 @@ void pmccntr_op_finish(CPUARMState *env) } } =20 +void pmu_op_start(CPUARMState *env) +{ + pmccntr_op_start(env); +} + +void pmu_op_finish(CPUARMState *env) +{ + pmccntr_op_finish(env); +} + +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_op_start(env); + pmu_op_start(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1101,7 +1181,7 @@ static void pmcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_op_finish(env); + pmu_op_finish(env); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -1150,6 +1230,22 @@ void pmccntr_op_finish(CPUARMState *env) { } =20 +void pmu_op_start(CPUARMState *env) +{ +} + +void pmu_op_finish(CPUARMState *env) +{ +} + +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ +} + #endif =20 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529699718304133.9915759621607; Fri, 22 Jun 2018 13:35:18 -0700 (PDT) Received: from localhost ([::1]:36073 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSly-0003UD-2T for importer@patchew.org; Fri, 22 Jun 2018 16:35:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSja-00026M-Rp for qemu-devel@nongnu.org; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PdD7p+Er+a70X/0fiRJ6I7gCeJof/XPnsQBmtrNj47NVtBA8phqhDZoF4oi3SJxgO 06AzeDPJFaBlgPL2p3i69wyKLv+dnzTo6ziNMnONAMcZ8aClD869sugUg4Y77hTT2I syn2Ejjx/HKX823IB/hkB+e52xQoy5yqHq06zkuQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699558; bh=Kymi//lCrzBqEqszoUIytQdU3BjWSUg5+Pfc4iX+qCQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PdD7p+Er+a70X/0fiRJ6I7gCeJof/XPnsQBmtrNj47NVtBA8phqhDZoF4oi3SJxgO 06AzeDPJFaBlgPL2p3i69wyKLv+dnzTo6ziNMnONAMcZ8aClD869sugUg4Y77hTT2I syn2Ejjx/HKX823IB/hkB+e52xQoy5yqHq06zkuQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org ED818606FA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:17 -0400 Message-Id: <1529699547-17044-4-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 03/13] target/arm: Allow AArch32 access for PMCCFILTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c66977..7d63bb2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -949,6 +949,10 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMXEVTYPER_MT 0x02000000 #define PMXEVTYPER_EVTCOUNT 0x000003ff =20 +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1252,10 +1256,26 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, uint64_t value) { pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; + env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; pmccntr_op_finish(env); } =20 +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); + pmccntr_op_finish(env); +} + +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1474,6 +1494,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, #endif + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700002671807.2430504055883; Fri, 22 Jun 2018 13:40:02 -0700 (PDT) Received: from localhost ([::1]:36108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSqf-0007kn-RN for importer@patchew.org; Fri, 22 Jun 2018 16:40:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjd-00029F-Ei for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjc-0005Sk-De for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45352) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjZ-0005Pk-54; Fri, 22 Jun 2018 16:32:41 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3A34E60714; Fri, 22 Jun 2018 20:32:40 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 37B7A60B18; Fri, 22 Jun 2018 20:32:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699560; bh=XTmuX2iM+99Gb7/BTmleRvZIMQ5tShdo/3KBsIlV7Ec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WmJecBEgb38NWb9QNpvSDcZcOG/qrpp/LCRq3UvdTsKWcKqpSjSZnxcfawFMELGjU aFjhR6UU9i5bh1ZA2cBEkIg6WW0kl9kNVfR3FeK9LTgq5B5bXbEaERylmazxDBZOz+ RBZ40yqeir0NJt54896a6zykIKcIkEM+cxsKvvUw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699559; bh=XTmuX2iM+99Gb7/BTmleRvZIMQ5tShdo/3KBsIlV7Ec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QxI1KYTx+Tu5aDrC1LFgHsgtICcY+6JR6RP2zADhzQj/Buwj7rySpuaSq9plCV04V EWQ1p1yDeqhhwyNjXofMva2RnCQNn/F+JKxEEqMFH+G1AQjUzMucnr9mXEjuLhZI2J WMxLYzPWJ4Ot3L8m0TzlHabsHI5Kxo5DyAqIqcOE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 37B7A60B18 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:18 -0400 Message-Id: <1529699547-17044-5-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.c | 21 ++++++++++++++------- target/arm/cpu.h | 1 + target/arm/kvm32.c | 8 ++++---- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 08ce1bc..98790b1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -793,9 +793,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) =20 /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { - set_feature(env, ARM_FEATURE_V7); + set_feature(env, ARM_FEATURE_V7VE); + } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + /* v7 Virtualization Extensions. In real hardware this implies + * EL2 and also the presence of the Security Extensions. + * For QEMU, for backwards-compatibility we implement some + * CPUs or CPU configs which have no actual EL2 or EL3 but do + * include the various other features that V7VE implies. + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the + * Security Extensions is ARM_FEATURE_EL3. + */ set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_LPAE); + set_feature(env, ARM_FEATURE_V7); } if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); @@ -1509,15 +1520,13 @@ static void cortex_a7_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a7"; - set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_LPAE); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr =3D 0x410fc075; @@ -1554,15 +1563,13 @@ static void cortex_a15_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_LPAE); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr =3D 0x412fc0f1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 800c4ec..852743b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1474,6 +1474,7 @@ enum arm_features { ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ + ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 1740cda..fb9ea37 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -98,12 +98,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) /* Now we've retrieved all the register information we can * set the feature bits based on the ID register fields. * We can assume any KVM supporting CPU is at least a v7 - * with VFPv3, LPAE and the generic timers; this in turn implies - * most of the other feature bits, but a few must be tested. + * with VFPv3, virtualization extensions, and the generic + * timers; this in turn implies most of the other feature + * bits, but a few must be tested. */ - set_feature(&features, ARM_FEATURE_V7); + set_feature(&features, ARM_FEATURE_V7VE); set_feature(&features, ARM_FEATURE_VFP3); - set_feature(&features, ARM_FEATURE_LPAE); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 switch (extract32(id_isar0, 24, 4)) { --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529699718296365.42833029394967; Fri, 22 Jun 2018 13:35:18 -0700 (PDT) Received: from localhost ([::1]:36074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSm0-0003XL-0c for importer@patchew.org; Fri, 22 Jun 2018 16:35:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjd-000290-8T for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjc-0005Sc-Ba for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45422) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSja-0005Q3-1d; Fri, 22 Jun 2018 16:32:42 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 16C3A60B14; Fri, 22 Jun 2018 20:32:41 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7296A6081B; Fri, 22 Jun 2018 20:32:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699561; bh=KJ2hwWBPFbAMSD5tXendsVzPlgncIxTq0scY54lmlJU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BT5DXuQTqjQ1qBijXx9CIDIrsKERZ/WLZNV7Yx69uvGoMRot8LzWmW0jrnbc3zumF HCGjN5F9NYALT2RelrhufUIpgIkC2B0V/T8oKlRRuOIHZWA4bQ4kXku8byJZe6+WzM KHIxyf61W4Y9GzN50vTgUd0k4mWx0cgOJBfQ4Ce4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699560; bh=KJ2hwWBPFbAMSD5tXendsVzPlgncIxTq0scY54lmlJU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AZcy8odI1D550YZAVgjsc1NwqWpylzEo3a/QaB6L+8DFzjrkJH3IkY3fcQETLCdeq LAejTkAidX0o00bRRGzGRrq5blUqu5bcE8qroXDxgYsHnf7HldyYlTw4bvSa7Kfz21 EQ8tjuA93EOSCKN/77PKuoX+heicXIu7rGSfgHv4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7296A6081B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:19 -0400 Message-Id: <1529699547-17044-6-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" KVM implies V7VE, which implies ARM_DIV and THUMB_DIV. The conditional detection here is therefore unnecessary. Because V7VE is already unconditionally specified for all KVM hosts, ARM_DIV and THUMB_DIV are already indirectly specified and do not need to be included here at all. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/kvm32.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index fb9ea37..4e91c11 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -36,7 +36,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int i, ret, fdarray[3]; - uint32_t midr, id_pfr0, id_isar0, mvfr1; + uint32_t midr, id_pfr0, mvfr1; uint64_t features =3D 0; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, @@ -60,11 +60,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) }, { .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 2, 0, 0), - .addr =3D (uintptr_t)&id_isar0, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, .addr =3D (uintptr_t)&mvfr1, }, @@ -106,18 +101,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 - switch (extract32(id_isar0, 24, 4)) { - case 1: - set_feature(&features, ARM_FEATURE_THUMB_DIV); - break; - case 2: - set_feature(&features, ARM_FEATURE_ARM_DIV); - set_feature(&features, ARM_FEATURE_THUMB_DIV); - break; - default: - break; - } - if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700145005743.7609794067569; Fri, 22 Jun 2018 13:42:25 -0700 (PDT) Received: from localhost ([::1]:36128 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSsy-0001Fy-95 for importer@patchew.org; Fri, 22 Jun 2018 16:42:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54350) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjg-0002Cu-FQ for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjd-0005Tj-QV for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45514) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjb-0005Qq-A8; Fri, 22 Jun 2018 16:32:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 69B2D6063F; Fri, 22 Jun 2018 20:32:42 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A21A96063F; Fri, 22 Jun 2018 20:32:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699562; bh=V7ns7mI23uSH/jVaM05kg4BJ8DBXvvN00zcOc/fZ85k=; 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charset="utf-8" Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d63bb2..5d83446 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1293,9 +1293,17 @@ static void pmcntenclr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr &=3D ~value; } =20 +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr |=3D value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1645,6 +1653,23 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4996,6 +5021,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529699947699177.25902332542478; Fri, 22 Jun 2018 13:39:07 -0700 (PDT) Received: from localhost ([::1]:36105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSpm-0006tg-S4 for importer@patchew.org; Fri, 22 Jun 2018 16:39:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSji-0002GW-0o for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjg-0005Ui-NM for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:49 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45596) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjc-0005SM-I7; Fri, 22 Jun 2018 16:32:44 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A73F7606FA; Fri, 22 Jun 2018 20:32:43 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CB09F60B18; Fri, 22 Jun 2018 20:32:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699563; bh=FXb5Dui6GrdQJvFiV6FFqxpbehVwS4Gp9/FKTinrZuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F1fM8qNxxjOwYLO34TySbUboQE4eW/Y86kvYomgagoZ17lT76fsWAdu1njOGvxJij Nyg5ucYgknXzQnKr52rXqrXTNOVEyrnlVJRuVwCIjzcVc56YMT9X4mlucDtnhN8bKj mQfqy8KEsqiU+xx9P69cUWkYHtLFdQtbqNbOVTtY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699562; bh=FXb5Dui6GrdQJvFiV6FFqxpbehVwS4Gp9/FKTinrZuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m7XTMDyRFUY88IfJr8/G2hF+6wY9ogX7WnwhT0CJzHojoNKgFRNnTR+9xkEs9xZaB gKWgbQpBwZyJfaxY2rqRBuvGJhDhOagV2dqE1B7WJ9TRSc/7CFXgq05RcVuNwLs74s hftEqRNlojQRKzyUfYSE5c6WM/txVW2GGhnUTnRY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CB09F60B18 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:21 -0400 Message-Id: <1529699547-17044-8-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 20 +++++++++++++------- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu64.c | 2 -- target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 60 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 98790b1..2f5b16a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -927,9 +927,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &=3D ~0xf00; - } else if (!kvm_enabled()) { - arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); - arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + } + if (arm_feature(env, ARM_FEATURE_PMU)) { + uint64_t pmceid =3D get_pmceid(&cpu->env); + cpu->pmceid0 =3D pmceid & 0xffffffff; + cpu->pmceid1 =3D (pmceid >> 32) & 0xffffffff; + + if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + } + } else { + cpu->pmceid0 =3D 0x00000000; + cpu->pmceid1 =3D 0x00000000; } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -1538,8 +1548,6 @@ static void cortex_a7_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x00000000; - cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -1581,8 +1589,6 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x0000000; - cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x20000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 852743b..430b8d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -964,6 +964,16 @@ void pmu_op_finish(CPUARMState *env); void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters whi= ch + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c50dcd4..28482a0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,8 +141,6 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_isar5 =3D 0x00011121; cpu->id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; - cpu->pmceid0 =3D 0x00000000; - cpu->pmceid1 =3D 0x00000000; cpu->id_aa64isar0 =3D 0x00011120; cpu->id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d83446..9f81747 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -964,6 +964,43 @@ static inline uint64_t pmu_counter_mask(CPUARMState *e= nv) return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); } =20 +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function= */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +#define SUPPORTED_EVENT_SENTINEL UINT16_MAX +static const pm_event pm_events[] =3D { + { .number =3D SUPPORTED_EVENT_SENTINEL } +}; +static uint16_t supported_event_map[0x3f]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (= high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid =3D 0; + unsigned int i =3D 0; + while (pm_events[i].number !=3D SUPPORTED_EVENT_SENTINEL) { + const pm_event *cnt =3D &pm_events[i]; + if (cnt->number < 0x3f && cnt->supported(env)) { + pmceid |=3D (1 << cnt->number); + supported_event_map[cnt->number] =3D i; + } else { + supported_event_map[cnt->number] =3D SUPPORTED_EVENT_SENTINEL; + } + i++; + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700277864684.9662529745394; Fri, 22 Jun 2018 13:44:37 -0700 (PDT) Received: from localhost ([::1]:36139 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSv7-0002vi-2P for importer@patchew.org; Fri, 22 Jun 2018 16:44:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54454) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjk-0002JR-Qk for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSji-0005Vl-VM for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:52 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45654) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjd-0005TM-LX; Fri, 22 Jun 2018 16:32:45 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BFE9460AFF; Fri, 22 Jun 2018 20:32:44 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F1B626081B; Fri, 22 Jun 2018 20:32:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699564; bh=av9e1pjQzkvqgZprWPW2vEKn7V+b3aiZYArsRrsrk/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dm+p1sG86erERAij3CrT60iRZ2yVVZ9bhc8qD4Yo2T462TUb4bPcMnVpcTyd75JUU Qhy0yGD3fNsF/9vN7ewCKUjFkI0JunvToPRFu+CLb/vlMLEVUKbBMI4SN4W4HjakfF /LJT2B3SlQbAONd0wLP7XSf1px2diqgNNt/ZORd0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699563; bh=av9e1pjQzkvqgZprWPW2vEKn7V+b3aiZYArsRrsrk/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HBjtlEzSy1CLRUdBQt1YKSlzC5ja8u7qvHP94TmwSoc6K6JkiU1oOe2/3vuLqmP4c g9PemqJEOlNhYO32NFtgcAn1zAjEJtQHnjDople0vyFJ64+3IhhhlFzpXzzWibMMUZ 7NIbxDgyxVQ1yizHfat/tRdGnz4UbzJLcF+WjMFE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F1B626081B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:22 -0400 Message-Id: <1529699547-17044-9-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 3 + target/arm/helper.c | 224 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- 2 files changed, 209 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 430b8d5..c240b38 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -481,6 +481,9 @@ typedef struct CPUARMState { * pmccntr_op_finish. */ uint64_t c15_ccnt_delta; + uint64_t c14_pmevcntr[31]; + uint64_t c14_pmevcntr_delta[31]; + uint64_t c14_pmevtyper[31]; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 9f81747..f1fd21c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -938,6 +938,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 +#define PMCRP 0x2 #define PMCRE 0x1 =20 #define PMXEVTYPER_P 0x80000000 @@ -1120,9 +1121,11 @@ static inline bool pmu_counter_enabled(CPUARMState *= env, uint8_t counter) prohibited =3D env->cp15.c9_pmcr & PMCRDP; } =20 - /* TODO Remove assert, set filter to correct PMEVTYPER */ - assert(counter =3D=3D 31); - filter =3D env->cp15.pmccfiltr_el0; + if (counter =3D=3D 31) { + filter =3D env->cp15.pmccfiltr_el0; + } else { + filter =3D env->cp15.c14_pmevtyper[counter]; + } =20 p =3D filter & PMXEVTYPER_P; u =3D filter & PMXEVTYPER_U; @@ -1142,6 +1145,21 @@ static inline bool pmu_counter_enabled(CPUARMState *= env, uint8_t counter) filtered =3D m !=3D p; } =20 + if (counter !=3D 31) { + /* If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support */ + uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; + if (event > 0x3f) { + return false; /* We only support common architectural and + microarchitectural events */ + } + + uint16_t event_idx =3D supported_event_map[event]; + if (event_idx =3D=3D SUPPORTED_EVENT_SENTINEL) { + return false; + } + } + return enabled && !prohibited && !filtered; } =20 @@ -1188,14 +1206,44 @@ void pmccntr_op_finish(CPUARMState *env) } } =20 +static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) +{ + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t count =3D pm_events[event_idx].get_count(env); + + if (pmu_counter_enabled(env, counter)) { + env->cp15.c14_pmevcntr[counter] =3D + count - env->cp15.c14_pmevcntr_delta[counter]; + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; +} + +static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) +{ + if (pmu_counter_enabled(env, counter)) { + env->cp15.c14_pmevcntr_delta[counter] -=3D + env->cp15.c14_pmevcntr[counter]; + } +} + void pmu_op_start(CPUARMState *env) { + unsigned int i; pmccntr_op_start(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_start(env, i); + } } =20 void pmu_op_finish(CPUARMState *env) { + unsigned int i; pmccntr_op_finish(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_finish(env, i); + } } =20 void pmu_pre_el_change(ARMCPU *cpu, void *ignored) @@ -1218,6 +1266,13 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, env->cp15.c15_ccnt =3D 0; } =20 + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); @@ -1271,6 +1326,14 @@ void pmccntr_op_finish(CPUARMState *env) { } =20 +void pmevcntr_op_start(CPUARMState *env, uint8_t i) +{ +} + +void pmevcntr_op_finish(CPUARMState *env, uint8_t i) +{ +} + void pmu_op_start(CPUARMState *env) { } @@ -1341,30 +1404,113 @@ static void pmovsset_write(CPUARMState *env, const= ARMCPRegInfo *ri, env->cp15.c9_pmovsr |=3D value; } =20 -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) { + if (counter =3D=3D 0x1f) { + pmccfiltr_write(env, ri, value); + } else if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + env->cp15.c14_pmevtyper[counter] =3D value & 0xfe0003ff; + pmevcntr_op_finish(env, counter); + } /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - pmccfiltr_write(env, ri, value); +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 0x1f) { + return env->cp15.pmccfiltr_el0; + } else if (counter < pmu_num_counters(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; } } =20 +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). - */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - return env->cp15.pmccfiltr_el0; + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_op_finish(env, counter); + } + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + uint64_t ret; + pmevcntr_op_start(env, counter); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmevcntr_op_finish(env, counter); + return ret; } else { + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ return 0; } } =20 +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1552,16 +1698,23 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access_xevcntr }, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), @@ -4250,7 +4403,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { #endif /* The only field of MDCR_EL2 that has a defined architectural reset v= alue * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't impelment any PMU event counters, so using zero as a reset + * don't implement any PMU event counters, so using zero as a reset * value for MDCR_EL2 is okay */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -5062,6 +5215,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pmovsset_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { + unsigned int i; /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle * count register. @@ -5086,6 +5240,40 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < 31; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 15, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 8 | (3 &= (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 15, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 12 | (3 = & (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } #endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529699904966671.7849323008671; Fri, 22 Jun 2018 13:38:24 -0700 (PDT) Received: from localhost ([::1]:36102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSp6-0006PM-8c for importer@patchew.org; Fri, 22 Jun 2018 16:38:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjj-0002HA-17 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjh-0005VE-Rg for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45738) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSje-0005Ty-RM; Fri, 22 Jun 2018 16:32:47 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EC26760B18; Fri, 22 Jun 2018 20:32:45 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2804860B18; Fri, 22 Jun 2018 20:32:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699565; bh=kxTqBTIOZkPpnahXDZ6jA0/DUump16SXXMQLnyE9kUE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iG4fsrHJAmGPrA3N13IsrelhhjYWencFGC6pRz8vkSUf+ipLc6dU1V3frqE2EaDyp lx7szk3arnNCwvtvtn1y9Skrt4CtktEcBOCzi7kIT7sQUr2IStixSgtAhmdWVm9add bwW3oXbWiURO7pKX2RCCWcL9SOq0ZZXkEKjLXdbE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699565; bh=kxTqBTIOZkPpnahXDZ6jA0/DUump16SXXMQLnyE9kUE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iG4fsrHJAmGPrA3N13IsrelhhjYWencFGC6pRz8vkSUf+ipLc6dU1V3frqE2EaDyp lx7szk3arnNCwvtvtn1y9Skrt4CtktEcBOCzi7kIT7sQUr2IStixSgtAhmdWVm9add bwW3oXbWiURO7pKX2RCCWcL9SOq0ZZXkEKjLXdbE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2804860B18 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:23 -0400 Message-Id: <1529699547-17044-10-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 88 ++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 43 insertions(+), 45 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1fd21c..92ebd21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" =20 @@ -974,8 +975,49 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *); } pm_event; =20 +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t cycles_get_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return 0; +#endif +} + +#ifndef CONFIG_USER_ONLY +static bool instructions_supported(CPUARMState *env) +{ + return use_icount =3D=3D 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + return (uint64_t)cpu_get_icount_raw(); +} +#endif + #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count + }, + { .number =3D 0x011, /* CPU_CYCLES, Cycle */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count + }, +#endif { .number =3D SUPPORTED_EVENT_SENTINEL } }; static uint16_t supported_event_map[0x3f]; @@ -1055,8 +1097,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState = *env, return pmreg_access(env, ri, isread); } =20 -#ifndef CONFIG_USER_ONLY - static CPAccessResult pmreg_access_selr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1171,9 +1211,7 @@ static inline bool pmu_counter_enabled(CPUARMState *e= nv, uint8_t counter) */ void pmccntr_op_start(CPUARMState *env) { - uint64_t cycles =3D 0; - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + uint64_t cycles =3D cycles_get_count(env); =20 if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; @@ -1316,42 +1354,6 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); } =20 -#else /* CONFIG_USER_ONLY */ - -void pmccntr_op_start(CPUARMState *env) -{ -} - -void pmccntr_op_finish(CPUARMState *env) -{ -} - -void pmevcntr_op_start(CPUARMState *env, uint8_t i) -{ -} - -void pmevcntr_op_finish(CPUARMState *env, uint8_t i) -{ -} - -void pmu_op_start(CPUARMState *env) -{ -} - -void pmu_op_finish(CPUARMState *env) -{ -} - -void pmu_pre_el_change(ARMCPU *cpu, void *ignored) -{ -} - -void pmu_post_el_change(ARMCPU *cpu, void *ignored) -{ -} - -#endif - static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1664,7 +1666,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, -#ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), @@ -1684,7 +1685,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, -#endif { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, @@ -5220,7 +5220,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) * field as main ID register, and we implement only the cycle * count register. */ -#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5274,7 +5273,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } -#endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152970004783737.418150885133514; Fri, 22 Jun 2018 13:40:47 -0700 (PDT) Received: from localhost ([::1]:36117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSrH-0008Gf-Qq for importer@patchew.org; Fri, 22 Jun 2018 16:40:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjj-0002IC-Vw for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjj-0005Vq-11 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45846) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjg-0005UG-8J; Fri, 22 Jun 2018 16:32:48 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 30FEC60B1A; Fri, 22 Jun 2018 20:32:47 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 512A060B14; Fri, 22 Jun 2018 20:32:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699567; bh=8hIkBpvHzjiGfA5zv7NQ2//Yuxlrlreakg9D0D0zv+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=irHPA5wXa/boTuujz0Qhfz/lJjvsI5ifNdX480uCun63uKOyfUaVBZ7ZUa/njmCZS P9to+EeugYMuUhmoov6G+ElOgcghL6f/pxPPqnMHQHs3XUxNqu4OdwVV8zwfdKRyXn S4/GIAKcbiTuCaYf+NIRhPmecnZuMFj1yBQzmgAg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699566; bh=8hIkBpvHzjiGfA5zv7NQ2//Yuxlrlreakg9D0D0zv+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mmphuGvw0ACr9juwVgr50lDLUppE4voJVJ3b8bBILOEcB0hLh7u9Nsvh15PTU/jIq n2Hy1OohJ6Ci5ZjMIHVRx/ijZ1YGPlq3w0zQylaeae/yaieJqZs6BUFVUKbRuTylg+ 8vTdigMUDanS3EgXDO70KFE0C1q0Qyb9LThMaQDc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 512A060B14 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:24 -0400 Message-Id: <1529699547-17044-11-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92ebd21..3720239 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1618,7 +1618,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5234,7 +5234,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + /* 4 counters enabled */ + .resetvalue =3D (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT= ), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700079628714.4976415661466; Fri, 22 Jun 2018 13:41:19 -0700 (PDT) Received: from localhost ([::1]:36120 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSru-0000P8-Tv for importer@patchew.org; Fri, 22 Jun 2018 16:41:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjl-0002K2-6n for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjk-0005WC-1k for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45920) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjh-0005Un-L0; Fri, 22 Jun 2018 16:32:49 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8D69F606FA; Fri, 22 Jun 2018 20:32:48 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 921A560B19; Fri, 22 Jun 2018 20:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699568; bh=Z15p35WcXOWx43Sn/Hdq2etongdkPFFKKf+6JVt3BVs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T5n5Fd8ckpWsl2cPelk20IE6J02xhDLmZd0YGyuAZNtePRfF7kI2mxbOSPvIUEQjn oejhLjFsgxXW+Dmv8vzUH4b79rcyfJlTmg6PfL015IIaRnN29Fhczzn0ebH58H9iwg qKg8v0RVs7xHOE9jaW6FJtLd+IKybev0VuCqN6hQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699567; bh=Z15p35WcXOWx43Sn/Hdq2etongdkPFFKKf+6JVt3BVs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JOSlAEibwcGO5BY4UTLMz7kTc4ZsMaSl8vHLjX34Yf0FIkj4GCFcSHryJC265RhEs woQ0u6DoMJ2VUo3xphlzcY4nkRk3Tz/2mBi29lh/7J+Ei94sj6LMinCRBuXWGel8EX sX2B6tLGi97Lyz5pJ0ODo3oBx7vtl0KvNFVLcNEo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 921A560B19 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:25 -0400 Message-Id: <1529699547-17044-12-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 11/13] target/arm: Implement PMSWINC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3720239..96667e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -980,6 +980,15 @@ static bool event_always_supported(CPUARMState *env) return true; } =20 +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -1008,6 +1017,10 @@ static uint64_t instructions_get_count(CPUARMState *= env) =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count + }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, @@ -1318,6 +1331,24 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_op_finish(env); } =20 +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + pmevcntr_op_start(env, i); + env->cp15.c14_pmevcntr[i]++; + pmevcntr_op_finish(env, i); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1663,9 +1694,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700212465490.90964016287023; Fri, 22 Jun 2018 13:43:32 -0700 (PDT) Received: from localhost ([::1]:36132 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSu3-00027M-NG for importer@patchew.org; Fri, 22 Jun 2018 16:43:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjl-0002KG-AH for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjk-0005WP-Fg for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:32:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45986) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSji-0005VB-DT; Fri, 22 Jun 2018 16:32:50 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 844BC60B15; Fri, 22 Jun 2018 20:32:49 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id EB53360AD8; Fri, 22 Jun 2018 20:32:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699569; bh=VPE/xeceM58k5Qp2QWI5nMHZ/gBS9350bVqa2fM8oj4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HvHQjRCj/IXre3cUAJV1hLebAH8A4dao30y5KenYRJM9Xp738kQL0uWy0phzuyLFf H6/4n7kUdqpqbXE+DhOmdRweoKXfDbKSnz76bSWQpkzfTv1X+vMidJ5OAChC6OHDn/ B2qO6Q7N+/n6YOBHLQpd1qgaXgvqjt7IDdLblNPw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699568; bh=VPE/xeceM58k5Qp2QWI5nMHZ/gBS9350bVqa2fM8oj4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iAE5Qlr7X2g6puf+z5JbHEsg2rospc3/FKmSEv9Bn95+iP42OhZTFjKVtnqfTv9X8 FMmVz2+EiCi9zgSFb2kkpzpKYjR0ERxKJV3TG7UKRyEo6n8cM9AvQbGKH5kk3zSSmy jS+PX17/gVc5Dtqz+T1+s/FAj5L2SNVqfFLsoYY8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EB53360AD8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:26 -0400 Message-Id: <1529699547-17044-13-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This makes it match its AArch64 equivalent, PMINTENSET_EL1 Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 96667e6..38fb6a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1763,7 +1763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_ALIAS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), .resetvalue =3D 0, .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Fri May 3 13:58:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529700343588892.3204829852086; Fri, 22 Jun 2018 13:45:43 -0700 (PDT) Received: from localhost ([::1]:36145 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSwA-0003qa-K4 for importer@patchew.org; Fri, 22 Jun 2018 16:45:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWSjs-0002Oy-60 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:33:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWSjq-0005Xm-JU for qemu-devel@nongnu.org; Fri, 22 Jun 2018 16:33:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46088) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWSjl-0005WM-0N; Fri, 22 Jun 2018 16:32:53 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 23C366063F; Fri, 22 Jun 2018 20:32:52 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 34B5160AFF; Fri, 22 Jun 2018 20:32:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699572; bh=Icc0RJC3Dj+RKYu06P7IwGINJF0w5NHLTcYP5dVj3e8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KJMqIZmzBl1isqf3Swje2zaDqgQgi2CEYp7BMZ1DtsC7VfcKkcL3XscJ9w912zTuu +HrIYdso9PzLwdEdWiV57hDTqey2NRo6M4K84WgpBkFh4+EjBazhCK5YWk0UMLly4B nEjXB/2Piqj6epskhbY8ieboIdhFAgCOA/3wD+g0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529699570; bh=Icc0RJC3Dj+RKYu06P7IwGINJF0w5NHLTcYP5dVj3e8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RQI8WoCW5BDg3JF8h+ByrJWTF7f1rAzh8cKxxIXFm0mBGXiO1JGW7IAh1kXMQQY+q 5J34BXAumjrT4vAvK4RE4K1PDAziwQ7NRRiUUKzHoEE1aduGd+6JUidK7ittgDZRrP 83kk9ukgBLC4LG0NXMeF22MYJU1gEDVLLJk36OCE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 34B5160AFF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 22 Jun 2018 16:32:27 -0400 Message-Id: <1529699547-17044-14-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> References: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Setup a QEMUTimer to get a callback when we expect counters to next overflow and trigger an interrupt at that time. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 11 +++++ target/arm/cpu.h | 7 +++ target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++= ---- 3 files changed, 141 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2f5b16a..7b3c137 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -743,6 +743,12 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { + timer_deinit(cpu->pmu_timer); + timer_free(cpu->pmu_timer); + } +#endif } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) @@ -937,6 +943,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } + +#ifndef CONFIG_USER_ONLY + cpu->pmu_timer =3D timer_new(QEMU_CLOCK_VIRTUAL, 1, arm_pmu_timer_= cb, + cpu); +#endif } else { cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c240b38..583b008 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -720,6 +720,8 @@ struct ARMCPU { =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; + /* Timer used by the PMU */ + QEMUTimer *pmu_timer; /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; /* GPIO output for GICv3 maintenance interrupt signal */ @@ -962,6 +964,11 @@ void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); =20 /** + * Called when a PMU counter is due to overflow + */ +void arm_pmu_timer_cb(void *opaque); + +/** * Functions to register as EL change hooks for PMU mode filtering */ void pmu_pre_el_change(ARMCPU *cpu, void *ignored); diff --git a/target/arm/helper.c b/target/arm/helper.c index 38fb6a2..0ddbcac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -936,6 +936,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLC 0x40 #define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 @@ -951,6 +952,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMXEVTYPER_MT 0x02000000 #define PMXEVTYPER_EVTCOUNT 0x000003ff =20 +#define PMEVCNTR_OVERFLOW_MASK ((uint64_t)1 << 31) + #define PMCCFILTR 0xf8000000 #define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) @@ -973,6 +976,11 @@ typedef struct pm_event { /* Retrieve the current count of the underlying event. The programmed * counters hold a difference from the return value from this function= */ uint64_t (*get_count)(CPUARMState *); + /* Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. */ + int64_t (*ns_per_count)(uint64_t); } pm_event; =20 static bool event_always_supported(CPUARMState *env) @@ -989,6 +997,11 @@ static uint64_t swinc_get_count(CPUARMState *env) return 0; } =20 +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -1004,6 +1017,11 @@ static uint64_t cycles_get_count(CPUARMState *env) } =20 #ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; +} + static bool instructions_supported(CPUARMState *env) { return use_icount =3D=3D 1 /* Precise instruction counting */; @@ -1013,22 +1031,30 @@ static uint64_t instructions_get_count(CPUARMState = *env) { return (uint64_t)cpu_get_icount_raw(); } + +static int64_t instructions_ns_per(uint64_t icount) +{ + return cpu_icount_to_ns((int64_t)icount); +} #endif =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, - .get_count =3D swinc_get_count + .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, - .get_count =3D instructions_get_count + .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per }, { .number =3D 0x011, /* CPU_CYCLES, Cycle */ .supported =3D event_always_supported, - .get_count =3D cycles_get_count + .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per }, #endif { .number =3D SUPPORTED_EVENT_SENTINEL } @@ -1216,6 +1242,13 @@ static inline bool pmu_counter_enabled(CPUARMState *= env, uint8_t counter) return enabled && !prohibited && !filtered; } =20 +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1233,7 +1266,18 @@ void pmccntr_op_start(CPUARMState *env) eff_cycles /=3D 64; } =20 - env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + unsigned int overflow_bit =3D (env->cp15.c9_pmcr & PMCRLC) ? 63 : = 31; + uint64_t overflow_mask =3D (uint64_t)1 << overflow_bit; + if (!(new_pmccntr & overflow_mask) && + (env->cp15.c15_ccnt & overflow_mask)) { + env->cp15.c9_pmovsr |=3D (1 << 31); + new_pmccntr &=3D ~overflow_mask; + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; } env->cp15.c15_ccnt_delta =3D cycles; } @@ -1246,13 +1290,28 @@ void pmccntr_op_start(CPUARMState *env) void pmccntr_op_finish(CPUARMState *env) { if (pmu_counter_enabled(env, 31)) { - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; +#ifndef CONFIG_USER_ONLY + uint64_t delta; + if (env->cp15.c9_pmcr & PMCRLC) { + delta =3D UINT64_MAX - env->cp15.c15_ccnt + 1; + } else { + delta =3D UINT32_MAX - (uint32_t)env->cp15.c15_ccnt + 1; + } + int64_t overflow_in =3D cycles_ns_per(delta); =20 + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ prev_cycles /=3D 64; } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } @@ -1265,8 +1324,15 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) uint64_t count =3D pm_events[event_idx].get_count(env); =20 if (pmu_counter_enabled(env, counter)) { - env->cp15.c14_pmevcntr[counter] =3D - count - env->cp15.c14_pmevcntr_delta[counter]; + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + + if (!(new_pmevcntr & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[counter] & PMEVCNTR_OVERFLOW_MASK)= ) { + env->cp15.c9_pmovsr |=3D (1 << counter); + new_pmevcntr &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; } env->cp15.c14_pmevcntr_delta[counter] =3D count; } @@ -1274,6 +1340,21 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) { if (pmu_counter_enabled(env, counter)) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D UINT32_MAX - + (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; + int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + env->cp15.c14_pmevcntr_delta[counter] -=3D env->cp15.c14_pmevcntr[counter]; } @@ -1307,6 +1388,19 @@ void pmu_post_el_change(ARMCPU *cpu, void *ignored) pmu_op_finish(&cpu->env); } =20 +void arm_pmu_timer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1343,7 +1437,21 @@ static void pmswinc_write(CPUARMState *env, const AR= MCPRegInfo *ri, /* counter is SW_INCR */ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { pmevcntr_op_start(env, i); - env->cp15.c14_pmevcntr[i]++; + + /* Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + uint64_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + if (!(new_pmswinc & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[i] & PMEVCNTR_OVERFLOW_MASK)) { + env->cp15.c9_pmovsr |=3D (1 << i); + new_pmswinc &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + pmevcntr_op_finish(env, i); } } @@ -1414,6 +1522,7 @@ static void pmcntenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; + pmu_update_irq(env); } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1421,6 +1530,7 @@ static void pmcntenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1428,6 +1538,7 @@ static void pmovsr_write(CPUARMState *env, const ARMC= PRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1435,6 +1546,7 @@ static void pmovsset_write(CPUARMState *env, const AR= MCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); } =20 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1560,6 +1672,7 @@ static void pmintenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, /* We have no event counters so only the C bit can be changed */ value &=3D pmu_counter_mask(env); env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1567,6 +1680,7 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); } =20 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.