From nobody Thu May 2 07:45:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528451297399160.90865724148023; Fri, 8 Jun 2018 02:48:17 -0700 (PDT) Received: from localhost ([::1]:34398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRE0B-00052E-NQ for importer@patchew.org; Fri, 08 Jun 2018 05:48:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRDzD-0004kz-8m for qemu-devel@nongnu.org; Fri, 08 Jun 2018 05:47:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRDzA-0004YT-KV for qemu-devel@nongnu.org; Fri, 08 Jun 2018 05:47:11 -0400 Received: from 11.mo5.mail-out.ovh.net ([46.105.47.167]:45386) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fRDzA-0004Xr-Cq for qemu-devel@nongnu.org; Fri, 08 Jun 2018 05:47:08 -0400 Received: from player168.ha.ovh.net (unknown [10.109.108.82]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 7D78D1B9A9B for ; Fri, 8 Jun 2018 11:47:06 +0200 (CEST) Received: from bahia.lan (lns-bzn-46-82-253-208-248.adsl.proxad.net [82.253.208.248]) (Authenticated sender: groug@kaod.org) by player168.ha.ovh.net (Postfix) with ESMTPA id 1B1F94200C8; Fri, 8 Jun 2018 11:47:01 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Fri, 08 Jun 2018 11:46:55 +0200 Message-ID: <152845121577.13960.4480474870896921301.stgit@bahia.lan> User-Agent: StGit/0.17.1-46-g6855-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 5807954672481704325 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrjeelgdduiecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.47.167 Subject: [Qemu-devel] [PATCH v4] target/ppc: Allow PIR read in privileged mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leandro.lupori@gmail.com, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: luporl According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. PowerISA 3.0 - 4.3.3 Processor Identification Register "Read access to the PIR is privileged; write access is not provided." Figure 18 in section 4.4.4 explicitly confirms that mfspr PIR is privileged and doesn't require hypervisor state. Cc: David Gibson Cc: Alexander Graf Cc: qemu-ppc@nongnu.org Signed-off-by: Leandro Lupori Reviewed-by: Jose Ricardo Ziviani Reviewed-by: Greg Kurz Signed-off-by: Greg Kurz --- Changes in v2: - added my Signed-off-by, maintainers CC and Jose's Reviewed-by tags Changes in v3: - added subsystem name, version tag and summary of changes - added the section of PowerISA that describes PIR access privileges Changes in v4 (Greg): - rebased against ppc-for-3.0 (ie, file is now target/ppc/translate_init.in= c.c) - added some more context from PowerISA --- target/ppc/translate_init.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 1a89017ddea8..bb9296f5a3da 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7819,7 +7819,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env) /* Processor identification */ spr_register_hv(env, SPR_PIR, "PIR", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, &spr_read_generic, NULL, 0x00000000); spr_register_hv(env, SPR_HID0, "HID0",