From nobody Mon Apr 29 07:21:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524153506704104.52269442599095; Thu, 19 Apr 2018 08:58:26 -0700 (PDT) Received: from localhost ([::1]:57406 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9Bwz-0005ZD-9e for importer@patchew.org; Thu, 19 Apr 2018 11:58:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9BvZ-0004jl-QT for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9BvY-0005Vq-Vu for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:53 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:58206) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f9BvY-0005BP-EJ for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:52 -0400 Received: (qmail 22699 invoked by uid 484); 19 Apr 2018 15:56:35 -0000 Received: from unknown (HELO abo-VirtualBox.8.8.4.4) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 19 Apr 2018 15:56:34 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. 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Processed in 0.061551 secs); 19 Apr 2018 15:56:35 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Thu, 19 Apr 2018 16:56:24 +0100 Message-Id: <1524153386-3550-2-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v6 1/3] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from = the dynamic XML description. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 ++- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 19a0c03..436f675 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1815,10 +1815,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index dcb8476..799e322 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5664,7 +5664,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS; + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 /* Check that raw accesses are either forbidden or handled. Note that --=20 2.7.4 From nobody Mon Apr 29 07:21:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524153636745304.9177846663762; Thu, 19 Apr 2018 09:00:36 -0700 (PDT) Received: from localhost ([::1]:57510 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9Bz4-00076c-T4 for importer@patchew.org; Thu, 19 Apr 2018 12:00:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9Bvc-0004lu-Ng for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:57:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9Bvb-0005YQ-K2 for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:56 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:37273) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f9Bvb-0005DT-7i for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:55 -0400 Received: (qmail 22740 invoked by uid 484); 19 Apr 2018 15:56:38 -0000 Received: from unknown (HELO abo-VirtualBox.8.8.4.4) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 19 Apr 2018 15:56:37 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. 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Processed in 0.052325 secs); 19 Apr 2018 15:56:38 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Thu, 19 Apr 2018 16:56:25 +0100 Message-Id: <1524153386-3550-3-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v6 2/3] target/arm: Add "_S" suffix to the secure version of a sysreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. Add "_S" suffix to the secure version of sysregs that have both S and NS vi= ews Replace (S) and (NS) by _S and _NS for the register that are manually defin= ed, so all the registers follow the same convention. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 799e322..858bda2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -695,12 +695,12 @@ static const ARMCPRegInfo cp_reginfo[] =3D { * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. */ - { .name =3D "FCSEIDR(NS)", + { .name =3D "FCSEIDR", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR(S)", + { .name =3D "FCSEIDR_S", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), @@ -716,7 +716,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, + { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), @@ -1967,7 +1967,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { cp15.c14_timer[GTIMER_PHYS].ctl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CTL(S)", + { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, @@ -2006,7 +2006,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, - { .name =3D "CNTP_TVAL(S)", + { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, @@ -2060,7 +2060,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, .access =3D PL1_RW | PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, @@ -5563,7 +5563,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Err= or **errp) =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, int state, int secstate, - int crm, int opc1, int opc2) + int crm, int opc1, int opc2, + const char *name) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. @@ -5573,6 +5574,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; =20 + r2->name =3D g_strdup(name); /* Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ @@ -5804,19 +5806,24 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ + char *name; + switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2); + r->secure, crm, opc1, o= pc2, + r->name); break; default: + name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, - crm, opc1, opc2); + crm, opc1, opc2, name); + g_free(name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->nam= e); break; } } else { @@ -5824,7 +5831,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * of AArch32 */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->name); } } } --=20 2.7.4 From nobody Mon Apr 29 07:21:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524153836449332.0582854695689; Thu, 19 Apr 2018 09:03:56 -0700 (PDT) Received: from localhost ([::1]:57626 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9C2K-0001ZK-1B for importer@patchew.org; Thu, 19 Apr 2018 12:03:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9Bvf-0004oB-K8 for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:57:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9Bve-0005Zd-9q for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:59 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:37203) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f9Bvd-0005Fi-PP for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:58 -0400 Received: (qmail 22774 invoked by uid 484); 19 Apr 2018 15:56:40 -0000 Received: from unknown (HELO abo-VirtualBox.8.8.4.4) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 19 Apr 2018 15:56:39 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. 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Processed in 0.052078 secs); 19 Apr 2018 15:56:40 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Thu, 19 Apr 2018 16:56:26 +0100 Message-Id: <1524153386-3550-4-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v6 3/3] target/arm: Add the XML dynamic generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Generate an XML description for the cp-regs. Register these regs with the gdb_register_coprocessor(). Add arm_gdb_get_sysreg() to use it as a callback to read those regs. Add a dummy arm_gdb_set_sysreg(). Signed-off-by: Abdallah Bouassida Tested-by: Alex Benn=C3=A9e --- gdbstub.c | 10 +++++++ include/qom/cpu.h | 5 +++- target/arm/cpu.c | 1 + target/arm/cpu.h | 26 ++++++++++++++++++ target/arm/gdbstub.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/helper.c | 26 ++++++++++++++++++ 6 files changed, 143 insertions(+), 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index a76b2fa..4b56a43 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -674,6 +674,16 @@ static const char *get_feature_xml(const char *p, cons= t char **newp, } return target_xml; } + if (cc->gdb_get_dynamic_xml) { + CPUState *cpu =3D first_cpu; + char *xmlname =3D g_strndup(p, len); + const char *xml =3D cc->gdb_get_dynamic_xml(cpu, xmlname); + + g_free(xmlname); + if (xml) { + return xml; + } + } for (i =3D 0; ; i++) { name =3D xml_builtin[i][0]; if (!name || (strncmp(name, p, len) =3D=3D 0 && strlen(name) =3D= =3D len)) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 14e45c4..9d3afc6 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -132,6 +132,9 @@ struct TranslationBlock; * before the insn which triggers a watchpoint rather than after= it. * @gdb_arch_name: Optional callback that returns the architecture name kn= own * to GDB. The caller must free the returned string with g_free. + * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for = the + * gdb stub. Returns a pointer to the XML contents for the specified XML= file + * or NULL if the CPU doesn't have a dynamically generated content for i= t. * @cpu_exec_enter: Callback for cpu_exec preparation. * @cpu_exec_exit: Callback for cpu_exec cleanup. * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. @@ -198,7 +201,7 @@ typedef struct CPUClass { const struct VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); - + const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); void (*cpu_exec_enter)(CPUState *cpu); void (*cpu_exec_exit)(CPUState *cpu); bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5..38b8b1c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1879,6 +1879,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; cc->gdb_arch_name =3D arm_gdb_arch_name; + cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 436f675..9544043 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -133,6 +133,19 @@ enum { s<2n+1> maps to the most significant half of d */ =20 +/** + * DynamicGDBXMLInfo: + * @desc: Contains the XML descriptions. + * @num_cpregs: Number of the Coprocessor registers seen by GDB. + * @cpregs_keys: Array that contains the corresponding Key of + * a given cpreg with the same order of the cpreg in the XML description. + */ +typedef struct DynamicGDBXMLInfo { + char *desc; + int num_cpregs; + uint32_t *cpregs_keys; +} DynamicGDBXMLInfo; + /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { uint64_t cval; /* Timer CompareValue register */ @@ -682,6 +695,8 @@ struct ARMCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 + DynamicGDBXMLInfo dyn_xml; + /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; /* GPIO outputs for generic timer */ @@ -863,6 +878,17 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu= , vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 +/* Dynamically generates for gdb stub an XML description of the sysregs fr= om + * the cp_regs hashtable. Returns the registered sysregs number. + */ +int arm_gen_dynamic_xml(CPUState *cpu); + +/* Returns the dynamically generated XML for the gdb stub. + * Returns a pointer to the XML contents for the specified XML file or NULL + * if the XML name doesn't match the predefined one. + */ +const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); + int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 04c1208..e80cfb4 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -22,6 +22,11 @@ #include "cpu.h" #include "exec/gdbstub.h" =20 +typedef struct RegisterSysregXmlParam { + CPUState *cs; + GString *s; +} RegisterSysregXmlParam; + /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect whatever the target description contains. Due to a historical mishap the FPA registers appear in between core integer regs and the CPSR. @@ -101,3 +106,74 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) /* Unknown register. */ return 0; } + +static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, + ARMCPRegInfo *ri, uint32_t ri_key, + int bitsize) +{ + g_string_append_printf(s, "name); + g_string_append_printf(s, " bitsize=3D\"%d\"", bitsize); + g_string_append_printf(s, " group=3D\"cp_regs\"/>"); + dyn_xml->num_cpregs++; + dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] =3D ri_key; +} + +static void arm_register_sysreg_for_xml(gpointer key, gpointer value, + gpointer p) +{ + uint32_t ri_key =3D *(uint32_t *)key; + ARMCPRegInfo *ri =3D value; + RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; + GString *s =3D param->s; + ARMCPU *cpu =3D ARM_CPU(param->cs); + CPUARMState *env =3D &cpu->env; + DynamicGDBXMLInfo *dyn_xml =3D &cpu->dyn_xml; + + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + if (ri->state =3D=3D ARM_CP_STATE_AA64) { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + } + } else { + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + if (!arm_feature(env, ARM_FEATURE_EL3) && + (ri->secure & ARM_CP_SECSTATE_S)) { + return; + } + if (ri->type & ARM_CP_64BIT) { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + } else { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 32); + } + } + } + } +} + +int arm_gen_dynamic_xml(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GString *s =3D g_string_new(NULL); + RegisterSysregXmlParam param =3D {cs, s}; + + cpu->dyn_xml.num_cpregs =3D 0; + cpu->dyn_xml.cpregs_keys =3D g_malloc(sizeof(uint32_t *) * + g_hash_table_size(cpu->cp_regs)); + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m= ); + g_string_append_printf(s, ""); + cpu->dyn_xml.desc =3D g_string_free(s, false); + return cpu->dyn_xml.num_cpregs; +} + +const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + + if (strcmp(xmlname, "system-registers.xml") =3D=3D 0) { + return cpu->dyn_xml.desc; + } + return NULL; +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 858bda2..db77662 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -220,6 +220,29 @@ static void write_raw_cp_reg(CPUARMState *env, const A= RMCPRegInfo *ri, } } =20 +static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + + key =3D cpu->dyn_xml.cpregs_keys[reg]; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); + if (ri) { + if (cpreg_field_is_64bit(ri)) { + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + } else { + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + } + } + return 0; +} + +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; +} + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -5474,6 +5497,9 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, + arm_gen_dynamic_xml(cs), + "system-registers.xml", 0); } =20 /* Sort alphabetically by type name, except for "any". */ --=20 2.7.4