From nobody Sun May 5 03:23:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15222698626141023.7156890465421; Wed, 28 Mar 2018 13:44:22 -0700 (PDT) Received: from localhost ([::1]:40923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f1Hvh-0006FD-Nj for importer@patchew.org; Wed, 28 Mar 2018 16:44:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f1Hsa-000446-46 for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f1HsY-0000Wc-1P for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:08 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34609) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f1HsX-0000Vm-P5 for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:05 -0400 Received: by mail-pg0-x242.google.com with SMTP id y16so1015364pgv.1 for ; Wed, 28 Mar 2018 13:41:05 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c15sm9934513pfm.114.2018.03.28.13.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Mar 2018 13:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kL07N7ONPctwZA+39cdww0jP+t9ILensL5acctBsp5k=; b=iwK7tiKQBDrloewVm9OQHPemuD93BDgi61kDOvVOV1oXaSgMYbmsi3W0KSNEYER4ir Z5zYP651N4zZ3icjc5sBFlKxhZn7HrJny08NvvtmoLXHQBZ+6aCv8flVWHc8z3BJU6Tt d44ZHq/0qAUSuJ2IkdMGZo7L5xwrpt9tFJq91gJV3Z39wnPaP2Sol9qFc69s5h4Tav4/ OIUtcnfGvuTjj/UqI7lO/vNkC/oa96gLJ0GcXuwql5zyaWpcEQIsuCglNgnsApqQP2+U dQDpjNaDPGjIH36RpdOsuigInOHAxT5dqU5ModTwAAQph6J1SekEFcty/HBkO1Jieuy7 N70A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kL07N7ONPctwZA+39cdww0jP+t9ILensL5acctBsp5k=; b=hemomBfIrxoy4JAdDdYSqrB47QqTXbET8guahg3cQBazr6gdnZNhab7GOFCMTCsb/Q 499P7noRBLoqbw1ScY2WDqH55EizLDSsBCwhYd2BMXDIdtYfbzmACaqYbxjWCttpTd8u +EptJdtTUG1Rmxn+xSdZo90gh1nmUO6MXBalU/frEPbYJFsvieW2HtAXzO3H4oEOjmBA KZxeBzfU1G9E0b4YZLXhbKeo2H03wsz4PHKb7My/hcwdB9AnBGh7qI30kXAw2ctU40F0 GJ8DcacHjw327kWWJTEMeOplqYbq8CJLC/RPdruaQu7e4JSn1AVvh94E5eDG2jvqWG6Q 3c8g== X-Gm-Message-State: AElRT7HfjCFipCtMli6HA3OVQ4vMMA6lkH0sS83qjXMe8S+HZeXtwCOE BR9TkIpVJ7dEzFYzl9etPnKIw/YGl5o= X-Google-Smtp-Source: AIpwx48/3xfy2pm1y+YUtkwyn4QbCvzZbgGImN8fYsdQVonvmodpOyMqE3LUdHxydfT0e/4jGGSE0g== X-Received: by 2002:a17:902:57d2:: with SMTP id g18-v6mr5216857plj.381.1522269664634; Wed, 28 Mar 2018 13:41:04 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 28 Mar 2018 13:40:18 -0700 Message-Id: <1522269619-48636-2-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1522269619-48636-1-git-send-email-mjc@sifive.com> References: <1522269619-48636-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 1/2] RISC-V: Convert cpu definition to future model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Igor Mammedov , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 - Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract - Fixes -cpu list Cc: Igor Mammedov Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Igor Mammedov --- target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 69 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9de34d7..5a527fb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#if defined(TARGET_RISCV32) + static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#elif defined(TARGET_RISCV64) + static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 -static const RISCVCPUInfo riscv_cpus[] =3D { - { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init }, - { 0, NULL, NULL } -}; +#endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { @@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_riscv_cpu; } =20 -static void cpu_register(const RISCVCPUInfo *info) -{ - TypeInfo type_info =3D { - .name =3D info->name, - .parent =3D TYPE_RISCV_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D info->initfn, - }; - - type_register(&type_info); -} - -static const TypeInfo riscv_cpu_type_info =3D { - .name =3D TYPE_RISCV_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D riscv_cpu_init, - .abstract =3D false, - .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, -}; - char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_str; } =20 -void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) { - const RISCVCPUInfo *info =3D riscv_cpus; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - (*cpu_fprintf)(f, "%s\n", info->name); - } - info++; - } + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); } =20 -static void riscv_cpu_register_types(void) +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) { - const RISCVCPUInfo *info =3D riscv_cpus; + RISCVCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); =20 - type_register_static(&riscv_cpu_type_info); + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - cpu_register(info); - } - info++; - } +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RISCVCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_RISCV_CPU, false); + list =3D g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list); } =20 -type_init(riscv_cpu_register_types) +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RISCVCPU), + .instance_init =3D riscv_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RISCVCPUClass), + .class_init =3D riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it) +#endif +}; + +DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.7.0 From nobody Sun May 5 03:23:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522269759284139.05153932651; Wed, 28 Mar 2018 13:42:39 -0700 (PDT) Received: from localhost ([::1]:40916 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f1Hu2-0004eE-DP for importer@patchew.org; Wed, 28 Mar 2018 16:42:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f1Hsa-000445-3s for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 2/2] RISC-V: Fix incorrect disassembly for addiw X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3c17501..74ad16e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] =3D { rvc_imm_eq_= zero, rvc_end }; static const rvc_constraint rvcc_not[] =3D { rvc_imm_eq_n1, rvc_end }; static const rvc_constraint rvcc_neg[] =3D { rvc_rs1_eq_x0, rvc_end }; static const rvc_constraint rvcc_negw[] =3D { rvc_rs1_eq_x0, rvc_end }; -static const rvc_constraint rvcc_sext_w[] =3D { rvc_rs2_eq_x0, rvc_end }; +static const rvc_constraint rvcc_sext_w[] =3D { rvc_imm_eq_zero, rvc_end }; static const rvc_constraint rvcc_seqz[] =3D { rvc_imm_eq_p1, rvc_end }; static const rvc_constraint rvcc_snez[] =3D { rvc_rs1_eq_x0, rvc_end }; static const rvc_constraint rvcc_sltz[] =3D { rvc_rs2_eq_x0, rvc_end }; --=20 2.7.0