From nobody Mon Apr 29 02:30:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518555489478513.7037963403276; Tue, 13 Feb 2018 12:58:09 -0800 (PST) Received: from localhost ([::1]:49234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1elheS-000190-JS for importer@patchew.org; Tue, 13 Feb 2018 15:58:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1elhaq-0006bK-QP for qemu-devel@nongnu.org; Tue, 13 Feb 2018 15:54:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1elhap-0003OU-Nz for qemu-devel@nongnu.org; Tue, 13 Feb 2018 15:54:24 -0500 Received: from shattrath.sceen.net ([2001:41d0:c:ada::1]:53105 helo=mail.sceen.net) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1elhap-0003Gh-HB for qemu-devel@nongnu.org; Tue, 13 Feb 2018 15:54:23 -0500 Received: by mail.sceen.net (Postfix, from userid 1000) id 6A89840BE1; Tue, 13 Feb 2018 21:54:19 +0100 (CET) From: Richard Braun To: qemu-devel@nongnu.org Date: Tue, 13 Feb 2018 21:54:19 +0100 Message-Id: <1518555259-26463-1-git-send-email-rbraun@sceen.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <20180209093643.GC27456@shattrath> References: <20180209093643.GC27456@shattrath> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:41d0:c:ada::1 Subject: [Qemu-devel] [PATCH v2] hw/char/stm32f2xx_usart: fix TXE/TC bit handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" I/O currently being synchronous, there is no reason to ever clear the SR_TXE bit. However the SR_TC bit may be cleared by software writing to the SR register, so set it on each write. In addition, fix the reset value of the USART status register. Signed-off-by: Richard Braun Reviewed-by: Alistair Francis --- hw/char/stm32f2xx_usart.c | 12 ++++++++---- include/hw/char/stm32f2xx_usart.h | 7 ++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 07b462d4b6..032b5fda13 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -96,12 +96,10 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwad= dr addr, switch (addr) { case USART_SR: retvalue =3D s->usart_sr; - s->usart_sr &=3D ~USART_SR_TC; qemu_chr_fe_accept_input(&s->chr); return retvalue; case USART_DR: DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usar= t_dr); - s->usart_sr |=3D USART_SR_TXE; s->usart_sr &=3D ~USART_SR_RXNE; qemu_chr_fe_accept_input(&s->chr); qemu_set_irq(s->irq, 0); @@ -137,7 +135,9 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr = addr, switch (addr) { case USART_SR: if (value <=3D 0x3FF) { - s->usart_sr =3D value; + /* I/O being synchronous, TXE is always set. In addition, it m= ay + only be set by hardware, so keep it set here. */ + s->usart_sr =3D value | USART_SR_TXE; } else { s->usart_sr &=3D value; } @@ -151,8 +151,12 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr= addr, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); + /* XXX I/O are currently synchronous, making it impossible for + software to observe transient states where TXE or TC aren't + set. Unlike TXE however, which is read-only, software may + clear TC by writing 0 to the SR register, so set it again + on each write. */ s->usart_sr |=3D USART_SR_TC; - s->usart_sr &=3D ~USART_SR_TXE; } return; case USART_BRR: diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_= usart.h index 9d03a7527c..7ea7448813 100644 --- a/include/hw/char/stm32f2xx_usart.h +++ b/include/hw/char/stm32f2xx_usart.h @@ -37,7 +37,12 @@ #define USART_CR3 0x14 #define USART_GTPR 0x18 =20 -#define USART_SR_RESET 0x00C00000 +/* + * XXX The reset value mentioned in "24.6.1 Status register" seems bogus. + * Looking at "Table 98 USART register map and reset values", it seems it + * should be 0xc0, and that's how real hardware behaves. + */ +#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC) =20 #define USART_SR_TXE (1 << 7) #define USART_SR_TC (1 << 6) --=20 2.11.0